* [PATCH v3 0/4] PCI: brcmstb: Some minor fixes/features
@ 2020-05-07 20:15 ` Jim Quinlan
0 siblings, 0 replies; 16+ messages in thread
From: Jim Quinlan @ 2020-05-07 20:15 UTC (permalink / raw)
To: james.quinlan
Cc: Andrew Murray,
open list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Jeremy Linton,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
open list, open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
Lorenzo Pieralisi, Nicolas Saenz Julienne, Rob Herring
v3 -- A change was submitted to [1] to make 'aspm-no-l0s' a general
property for PCIe devices. As such, the STB PCIe YAML file
merely notes that it may be used.
v2 -- Dropped commit concerning CRS.
-- Chanded new prop 'brcm,aspm-en-l0s' to 'aspm-no-l0s'.
-- Capitalize first letter in commit subject line; spelling.
v1 -- original
[1] https://github.com/devicetree-org/dt-schema/blob/master/schemas/pci/pci-bus.yaml
Jim Quinlan (4):
PCI: brcmstb: Don't clk_put() a managed clock
PCI: brcmstb: Fix window register offset from 4 to 8
dt-bindings: PCI: brcmstb: New prop 'aspm-no-l0s'
PCI: brcmstb: Disable L0s component of ASPM if requested
.../bindings/pci/brcm,stb-pcie.yaml | 2 ++
drivers/pci/controller/pcie-brcmstb.c | 19 +++++++++++++++----
2 files changed, 17 insertions(+), 4 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 0/4] PCI: brcmstb: Some minor fixes/features
@ 2020-05-07 20:15 ` Jim Quinlan
0 siblings, 0 replies; 16+ messages in thread
From: Jim Quinlan @ 2020-05-07 20:15 UTC (permalink / raw)
To: james.quinlan
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Lorenzo Pieralisi, Rob Herring,
open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS, open list,
Jeremy Linton, Nicolas Saenz Julienne,
open list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
Andrew Murray
v3 -- A change was submitted to [1] to make 'aspm-no-l0s' a general
property for PCIe devices. As such, the STB PCIe YAML file
merely notes that it may be used.
v2 -- Dropped commit concerning CRS.
-- Chanded new prop 'brcm,aspm-en-l0s' to 'aspm-no-l0s'.
-- Capitalize first letter in commit subject line; spelling.
v1 -- original
[1] https://github.com/devicetree-org/dt-schema/blob/master/schemas/pci/pci-bus.yaml
Jim Quinlan (4):
PCI: brcmstb: Don't clk_put() a managed clock
PCI: brcmstb: Fix window register offset from 4 to 8
dt-bindings: PCI: brcmstb: New prop 'aspm-no-l0s'
PCI: brcmstb: Disable L0s component of ASPM if requested
.../bindings/pci/brcm,stb-pcie.yaml | 2 ++
drivers/pci/controller/pcie-brcmstb.c | 19 +++++++++++++++----
2 files changed, 17 insertions(+), 4 deletions(-)
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 1/4] PCI: brcmstb: Don't clk_put() a managed clock
2020-05-07 20:15 ` Jim Quinlan
@ 2020-05-07 20:15 ` Jim Quinlan
-1 siblings, 0 replies; 16+ messages in thread
From: Jim Quinlan @ 2020-05-07 20:15 UTC (permalink / raw)
To: james.quinlan
Cc: Jim Quinlan, Nicolas Saenz Julienne, Lorenzo Pieralisi,
Rob Herring, Bjorn Helgaas, Florian Fainelli,
maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS, open list
From: Jim Quinlan <jquinlan@broadcom.com>
clk_put() was being invoked on a clock obtained by
devm_clk_get_optional().
Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
---
drivers/pci/controller/pcie-brcmstb.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 6d79d14527a6..454917ee9241 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -899,7 +899,6 @@ static void __brcm_pcie_remove(struct brcm_pcie *pcie)
brcm_msi_remove(pcie);
brcm_pcie_turn_off(pcie);
clk_disable_unprepare(pcie->clk);
- clk_put(pcie->clk);
}
static int brcm_pcie_remove(struct platform_device *pdev)
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 1/4] PCI: brcmstb: Don't clk_put() a managed clock
@ 2020-05-07 20:15 ` Jim Quinlan
0 siblings, 0 replies; 16+ messages in thread
From: Jim Quinlan @ 2020-05-07 20:15 UTC (permalink / raw)
To: james.quinlan
Cc: moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
Rob Herring, Florian Fainelli,
open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS, open list,
Lorenzo Pieralisi, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
Jim Quinlan, Bjorn Helgaas, Nicolas Saenz Julienne
From: Jim Quinlan <jquinlan@broadcom.com>
clk_put() was being invoked on a clock obtained by
devm_clk_get_optional().
Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
---
drivers/pci/controller/pcie-brcmstb.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 6d79d14527a6..454917ee9241 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -899,7 +899,6 @@ static void __brcm_pcie_remove(struct brcm_pcie *pcie)
brcm_msi_remove(pcie);
brcm_pcie_turn_off(pcie);
clk_disable_unprepare(pcie->clk);
- clk_put(pcie->clk);
}
static int brcm_pcie_remove(struct platform_device *pdev)
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 2/4] PCI: brcmstb: Fix window register offset from 4 to 8
2020-05-07 20:15 ` Jim Quinlan
@ 2020-05-07 20:15 ` Jim Quinlan
-1 siblings, 0 replies; 16+ messages in thread
From: Jim Quinlan @ 2020-05-07 20:15 UTC (permalink / raw)
To: james.quinlan
Cc: Jim Quinlan, Nicolas Saenz Julienne, Lorenzo Pieralisi,
Rob Herring, Bjorn Helgaas, Florian Fainelli,
maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE, Andrew Murray,
Jeremy Linton,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS, open list
From: Jim Quinlan <jquinlan@broadcom.com>
The outbound memory window registers were being referenced
with an incorrect stride offset. This probably wasn't noticed
previously as there was likely only one such window employed.
Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Fixes: c0452137034b ("PCI: brcmstb: Add Broadcom STB PCIe host controller driver")
---
drivers/pci/controller/pcie-brcmstb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 454917ee9241..5b0dec5971b8 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -54,11 +54,11 @@
#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
#define PCIE_MEM_WIN0_LO(win) \
- PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 8)
#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
#define PCIE_MEM_WIN0_HI(win) \
- PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8)
#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 2/4] PCI: brcmstb: Fix window register offset from 4 to 8
@ 2020-05-07 20:15 ` Jim Quinlan
0 siblings, 0 replies; 16+ messages in thread
From: Jim Quinlan @ 2020-05-07 20:15 UTC (permalink / raw)
To: james.quinlan
Cc: moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
Rob Herring, Florian Fainelli,
open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS, open list,
Jeremy Linton, Lorenzo Pieralisi,
maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
Jim Quinlan, Bjorn Helgaas, Nicolas Saenz Julienne,
Andrew Murray
From: Jim Quinlan <jquinlan@broadcom.com>
The outbound memory window registers were being referenced
with an incorrect stride offset. This probably wasn't noticed
previously as there was likely only one such window employed.
Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Fixes: c0452137034b ("PCI: brcmstb: Add Broadcom STB PCIe host controller driver")
---
drivers/pci/controller/pcie-brcmstb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 454917ee9241..5b0dec5971b8 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -54,11 +54,11 @@
#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
#define PCIE_MEM_WIN0_LO(win) \
- PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 8)
#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
#define PCIE_MEM_WIN0_HI(win) \
- PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8)
#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 3/4] dt-bindings: PCI: brcmstb: New prop 'aspm-no-l0s'
2020-05-07 20:15 ` Jim Quinlan
@ 2020-05-07 20:15 ` Jim Quinlan
-1 siblings, 0 replies; 16+ messages in thread
From: Jim Quinlan @ 2020-05-07 20:15 UTC (permalink / raw)
To: james.quinlan
Cc: Jim Quinlan, Nicolas Saenz Julienne, Florian Fainelli,
maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE, Bjorn Helgaas,
Rob Herring,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
open list:PCI SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
From: Jim Quinlan <jquinlan@broadcom.com>
For various reasons, one may want to disable the ASPM L0s
capability.
Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
---
Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
index 77d3e81a437b..8680a0f86c5a 100644
--- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
@@ -56,6 +56,8 @@ properties:
description: Indicates usage of spread-spectrum clocking.
type: boolean
+ aspm-no-l0s: true
+
required:
- reg
- dma-ranges
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 3/4] dt-bindings: PCI: brcmstb: New prop 'aspm-no-l0s'
@ 2020-05-07 20:15 ` Jim Quinlan
0 siblings, 0 replies; 16+ messages in thread
From: Jim Quinlan @ 2020-05-07 20:15 UTC (permalink / raw)
To: james.quinlan
Cc: moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Florian Fainelli, open list:PCI SUBSYSTEM, open list,
Rob Herring, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
Jim Quinlan, Bjorn Helgaas, Nicolas Saenz Julienne
From: Jim Quinlan <jquinlan@broadcom.com>
For various reasons, one may want to disable the ASPM L0s
capability.
Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
---
Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
index 77d3e81a437b..8680a0f86c5a 100644
--- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
@@ -56,6 +56,8 @@ properties:
description: Indicates usage of spread-spectrum clocking.
type: boolean
+ aspm-no-l0s: true
+
required:
- reg
- dma-ranges
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 4/4] PCI: brcmstb: Disable L0s component of ASPM if requested
2020-05-07 20:15 ` Jim Quinlan
@ 2020-05-07 20:15 ` Jim Quinlan
-1 siblings, 0 replies; 16+ messages in thread
From: Jim Quinlan @ 2020-05-07 20:15 UTC (permalink / raw)
To: james.quinlan
Cc: Jim Quinlan, Nicolas Saenz Julienne, Lorenzo Pieralisi,
Rob Herring, Bjorn Helgaas, Florian Fainelli,
maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS, open list
From: Jim Quinlan <jquinlan@broadcom.com>
Some informal internal experiments has shown that the BrcmSTB ASPM L0s
savings may introduce an undesirable noise signal on some customers'
boards. In addition, L0s was found lacking in realized power savings,
especially relative to the L1 ASPM component. This is BrcmSTB's
experience and may not hold for others. At any rate, if the
'aspm-no-l0s' property is present L0s will be disabled.
Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
---
drivers/pci/controller/pcie-brcmstb.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 5b0dec5971b8..73020b4ff090 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -41,6 +41,9 @@
#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
+#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
+#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
+
#define PCIE_RC_DL_MDIO_ADDR 0x1100
#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
@@ -693,7 +696,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
int num_out_wins = 0;
u16 nlw, cls, lnksta;
int i, ret;
- u32 tmp;
+ u32 tmp, aspm_support;
/* Reset the bridge */
brcm_pcie_bridge_sw_init_set(pcie, 1);
@@ -803,6 +806,15 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
num_out_wins++;
}
+ /* Don't advertise L0s capability if 'aspm-no-l0s' */
+ aspm_support = PCIE_LINK_STATE_L1;
+ if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
+ aspm_support |= PCIE_LINK_STATE_L0S;
+ tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
+ u32p_replace_bits(&tmp, aspm_support,
+ PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
+ writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
+
/*
* For config space accesses on the RC, show the right class for
* a PCIe-PCIe bridge (the default setting is to be EP mode).
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 4/4] PCI: brcmstb: Disable L0s component of ASPM if requested
@ 2020-05-07 20:15 ` Jim Quinlan
0 siblings, 0 replies; 16+ messages in thread
From: Jim Quinlan @ 2020-05-07 20:15 UTC (permalink / raw)
To: james.quinlan
Cc: moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
Rob Herring, Florian Fainelli,
open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS, open list,
Lorenzo Pieralisi, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
Jim Quinlan, Bjorn Helgaas, Nicolas Saenz Julienne
From: Jim Quinlan <jquinlan@broadcom.com>
Some informal internal experiments has shown that the BrcmSTB ASPM L0s
savings may introduce an undesirable noise signal on some customers'
boards. In addition, L0s was found lacking in realized power savings,
especially relative to the L1 ASPM component. This is BrcmSTB's
experience and may not hold for others. At any rate, if the
'aspm-no-l0s' property is present L0s will be disabled.
Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
---
drivers/pci/controller/pcie-brcmstb.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 5b0dec5971b8..73020b4ff090 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -41,6 +41,9 @@
#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
+#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
+#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
+
#define PCIE_RC_DL_MDIO_ADDR 0x1100
#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
@@ -693,7 +696,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
int num_out_wins = 0;
u16 nlw, cls, lnksta;
int i, ret;
- u32 tmp;
+ u32 tmp, aspm_support;
/* Reset the bridge */
brcm_pcie_bridge_sw_init_set(pcie, 1);
@@ -803,6 +806,15 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
num_out_wins++;
}
+ /* Don't advertise L0s capability if 'aspm-no-l0s' */
+ aspm_support = PCIE_LINK_STATE_L1;
+ if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
+ aspm_support |= PCIE_LINK_STATE_L0S;
+ tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
+ u32p_replace_bits(&tmp, aspm_support,
+ PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
+ writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
+
/*
* For config space accesses on the RC, show the right class for
* a PCIe-PCIe bridge (the default setting is to be EP mode).
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v3 1/4] PCI: brcmstb: Don't clk_put() a managed clock
2020-05-07 20:15 ` Jim Quinlan
@ 2020-05-07 20:17 ` Florian Fainelli
-1 siblings, 0 replies; 16+ messages in thread
From: Florian Fainelli @ 2020-05-07 20:17 UTC (permalink / raw)
To: Jim Quinlan
Cc: Nicolas Saenz Julienne, Lorenzo Pieralisi, Rob Herring,
Bjorn Helgaas, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS, open list
On 5/7/2020 1:15 PM, Jim Quinlan wrote:
> From: Jim Quinlan <jquinlan@broadcom.com>
>
> clk_put() was being invoked on a clock obtained by
> devm_clk_get_optional().
>
> Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
> Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
This one should also have:
Fixes: c0452137034b ("PCI: brcmstb: Add Broadcom STB PCIe host
controller driver")
not sure if Bjorn can add it while applying.
--
Florian
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 1/4] PCI: brcmstb: Don't clk_put() a managed clock
@ 2020-05-07 20:17 ` Florian Fainelli
0 siblings, 0 replies; 16+ messages in thread
From: Florian Fainelli @ 2020-05-07 20:17 UTC (permalink / raw)
To: Jim Quinlan
Cc: moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
Rob Herring, Lorenzo Pieralisi,
open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS, open list,
maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
Bjorn Helgaas, Nicolas Saenz Julienne
On 5/7/2020 1:15 PM, Jim Quinlan wrote:
> From: Jim Quinlan <jquinlan@broadcom.com>
>
> clk_put() was being invoked on a clock obtained by
> devm_clk_get_optional().
>
> Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
> Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
This one should also have:
Fixes: c0452137034b ("PCI: brcmstb: Add Broadcom STB PCIe host
controller driver")
not sure if Bjorn can add it while applying.
--
Florian
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 3/4] dt-bindings: PCI: brcmstb: New prop 'aspm-no-l0s'
2020-05-07 20:15 ` Jim Quinlan
@ 2020-05-08 1:11 ` Rob Herring
-1 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2020-05-08 1:11 UTC (permalink / raw)
To: Jim Quinlan
Cc: Nicolas Saenz Julienne, Florian Fainelli,
maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE, Bjorn Helgaas,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
open list:PCI SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
On Thu, May 7, 2020 at 3:16 PM Jim Quinlan <james.quinlan@broadcom.com> wrote:
>
> From: Jim Quinlan <jquinlan@broadcom.com>
>
> For various reasons, one may want to disable the ASPM L0s
> capability.
>
> Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
> ---
> Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 2 ++
> 1 file changed, 2 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 3/4] dt-bindings: PCI: brcmstb: New prop 'aspm-no-l0s'
@ 2020-05-08 1:11 ` Rob Herring
0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2020-05-08 1:11 UTC (permalink / raw)
To: Jim Quinlan
Cc: moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Florian Fainelli, open list:PCI SUBSYSTEM, open list,
maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
Bjorn Helgaas, Nicolas Saenz Julienne
On Thu, May 7, 2020 at 3:16 PM Jim Quinlan <james.quinlan@broadcom.com> wrote:
>
> From: Jim Quinlan <jquinlan@broadcom.com>
>
> For various reasons, one may want to disable the ASPM L0s
> capability.
>
> Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
> ---
> Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 2 ++
> 1 file changed, 2 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/4] PCI: brcmstb: Some minor fixes/features
2020-05-07 20:15 ` Jim Quinlan
@ 2020-05-11 10:52 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 16+ messages in thread
From: Lorenzo Pieralisi @ 2020-05-11 10:52 UTC (permalink / raw)
To: Jim Quinlan
Cc: Andrew Murray,
open list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Jeremy Linton,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
open list, open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
Nicolas Saenz Julienne, Rob Herring
On Thu, May 07, 2020 at 04:15:39PM -0400, Jim Quinlan wrote:
> v3 -- A change was submitted to [1] to make 'aspm-no-l0s' a general
> property for PCIe devices. As such, the STB PCIe YAML file
> merely notes that it may be used.
>
> v2 -- Dropped commit concerning CRS.
> -- Chanded new prop 'brcm,aspm-en-l0s' to 'aspm-no-l0s'.
> -- Capitalize first letter in commit subject line; spelling.
>
> v1 -- original
>
> [1] https://github.com/devicetree-org/dt-schema/blob/master/schemas/pci/pci-bus.yaml
>
> Jim Quinlan (4):
> PCI: brcmstb: Don't clk_put() a managed clock
> PCI: brcmstb: Fix window register offset from 4 to 8
> dt-bindings: PCI: brcmstb: New prop 'aspm-no-l0s'
> PCI: brcmstb: Disable L0s component of ASPM if requested
>
> .../bindings/pci/brcm,stb-pcie.yaml | 2 ++
> drivers/pci/controller/pcie-brcmstb.c | 19 +++++++++++++++----
> 2 files changed, 17 insertions(+), 4 deletions(-)
Applied to pci/brcmstb, thanks !
Lorenzo
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/4] PCI: brcmstb: Some minor fixes/features
@ 2020-05-11 10:52 ` Lorenzo Pieralisi
0 siblings, 0 replies; 16+ messages in thread
From: Lorenzo Pieralisi @ 2020-05-11 10:52 UTC (permalink / raw)
To: Jim Quinlan
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Rob Herring,
open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS, open list,
Jeremy Linton, Nicolas Saenz Julienne,
open list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
Andrew Murray
On Thu, May 07, 2020 at 04:15:39PM -0400, Jim Quinlan wrote:
> v3 -- A change was submitted to [1] to make 'aspm-no-l0s' a general
> property for PCIe devices. As such, the STB PCIe YAML file
> merely notes that it may be used.
>
> v2 -- Dropped commit concerning CRS.
> -- Chanded new prop 'brcm,aspm-en-l0s' to 'aspm-no-l0s'.
> -- Capitalize first letter in commit subject line; spelling.
>
> v1 -- original
>
> [1] https://github.com/devicetree-org/dt-schema/blob/master/schemas/pci/pci-bus.yaml
>
> Jim Quinlan (4):
> PCI: brcmstb: Don't clk_put() a managed clock
> PCI: brcmstb: Fix window register offset from 4 to 8
> dt-bindings: PCI: brcmstb: New prop 'aspm-no-l0s'
> PCI: brcmstb: Disable L0s component of ASPM if requested
>
> .../bindings/pci/brcm,stb-pcie.yaml | 2 ++
> drivers/pci/controller/pcie-brcmstb.c | 19 +++++++++++++++----
> 2 files changed, 17 insertions(+), 4 deletions(-)
Applied to pci/brcmstb, thanks !
Lorenzo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2020-05-11 10:53 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-07 20:15 [PATCH v3 0/4] PCI: brcmstb: Some minor fixes/features Jim Quinlan
2020-05-07 20:15 ` Jim Quinlan
2020-05-07 20:15 ` [PATCH v3 1/4] PCI: brcmstb: Don't clk_put() a managed clock Jim Quinlan
2020-05-07 20:15 ` Jim Quinlan
2020-05-07 20:17 ` Florian Fainelli
2020-05-07 20:17 ` Florian Fainelli
2020-05-07 20:15 ` [PATCH v3 2/4] PCI: brcmstb: Fix window register offset from 4 to 8 Jim Quinlan
2020-05-07 20:15 ` Jim Quinlan
2020-05-07 20:15 ` [PATCH v3 3/4] dt-bindings: PCI: brcmstb: New prop 'aspm-no-l0s' Jim Quinlan
2020-05-07 20:15 ` Jim Quinlan
2020-05-08 1:11 ` Rob Herring
2020-05-08 1:11 ` Rob Herring
2020-05-07 20:15 ` [PATCH v3 4/4] PCI: brcmstb: Disable L0s component of ASPM if requested Jim Quinlan
2020-05-07 20:15 ` Jim Quinlan
2020-05-11 10:52 ` [PATCH v3 0/4] PCI: brcmstb: Some minor fixes/features Lorenzo Pieralisi
2020-05-11 10:52 ` Lorenzo Pieralisi
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