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* [PATCH v1 1/3] gpio: mpc8xxx: support fsl-layerscape platform.
@ 2020-05-09 10:35 ` Hui Song
  0 siblings, 0 replies; 12+ messages in thread
From: Hui Song @ 2020-05-09 10:35 UTC (permalink / raw)
  To: jagdish.gediya, priyanka.jain, pramod.kumar_1
  Cc: linux-arm-kernel, devicetree, linux-kernel, linux-gpio, hui.song

From: "hui.song" <hui.song_1@nxp.com>

Make the MPC8XXX gpio driver to support the fsl-layerscape.

Signed-off-by: hui.song <hui.song_1@nxp.com>
---
 drivers/gpio/mpc8xxx_gpio.c | 59 +++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c
index 1dfd22522c..466f5f50cf 100644
--- a/drivers/gpio/mpc8xxx_gpio.c
+++ b/drivers/gpio/mpc8xxx_gpio.c
@@ -12,6 +12,8 @@
 #include <dm.h>
 #include <mapmem.h>
 #include <asm/gpio.h>
+#include <asm/io.h>
+#include <dm/of_access.h>
 
 struct ccsr_gpio {
 	u32	gpdir;
@@ -20,6 +22,7 @@ struct ccsr_gpio {
 	u32	gpier;
 	u32	gpimr;
 	u32	gpicr;
+	u32	gpibe;
 };
 
 struct mpc8xxx_gpio_data {
@@ -49,31 +52,51 @@ inline u32 gpio_mask(uint gpio)
 
 static inline u32 mpc8xxx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
 {
+#if CONFIG_ARM
+	return in_le32(&base->gpdat) & mask;
+#else
 	return in_be32(&base->gpdat) & mask;
+#endif
 }
 
 static inline u32 mpc8xxx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
 {
+#if CONFIG_ARM
+	return in_le32(&base->gpdir) & mask;
+#else
 	return in_be32(&base->gpdir) & mask;
+#endif
 }
 
 static inline int mpc8xxx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
 {
+#if CONFIG_ARM
+	return in_le32(&base->gpodr) & mask;
+#else
 	return in_be32(&base->gpodr) & mask;
+#endif
 }
 
 static inline void mpc8xxx_gpio_open_drain_on(struct ccsr_gpio *base, u32
 					      gpios)
 {
+#if CONFIG_ARM
+	setbits_le32(&base->gpodr, gpios);
+#else
 	/* GPODR register 1 -> open drain on */
 	setbits_be32(&base->gpodr, gpios);
+#endif
 }
 
 static inline void mpc8xxx_gpio_open_drain_off(struct ccsr_gpio *base,
 					       u32 gpios)
 {
+#if CONFIG_ARM
+	clrbits_le32(&base->gpodr, gpios);
+#else
 	/* GPODR register 0 -> open drain off (actively driven) */
 	clrbits_be32(&base->gpodr, gpios);
+#endif
 }
 
 static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio)
@@ -81,9 +104,13 @@ static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio)
 	struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
 	u32 mask = gpio_mask(gpio);
 
+#if CONFIG_ARM
+	clrbits_le32(&data->base->gpdir, mask);
+#else
 	/* GPDIR register 0 -> input */
 	clrbits_be32(&data->base->gpdir, mask);
 
+#endif
 	return 0;
 }
 
@@ -100,10 +127,19 @@ static int mpc8xxx_gpio_set_value(struct udevice *dev, uint gpio, int value)
 		data->dat_shadow &= ~mask;
 	}
 
+#if CONFIG_ARM
+	gpdir = in_le32(&base->gpdir);
+#else
 	gpdir = in_be32(&base->gpdir);
+#endif
 	gpdir |= gpio_mask(gpio);
+#if CONFIG_ARM
+	out_le32(&base->gpdat, gpdir & data->dat_shadow);
+	out_le32(&base->gpdir, gpdir);
+#else
 	out_be32(&base->gpdat, gpdir & data->dat_shadow);
 	out_be32(&base->gpdir, gpdir);
+#endif
 
 	return 0;
 }
@@ -147,13 +183,29 @@ static int mpc8xxx_gpio_ofdata_to_platdata(struct udevice *dev)
 {
 	struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
 	fdt_addr_t addr;
+	u32 i;
+#if CONFIG_ARM
+	u32 reg[4];
+
+	dev_read_u32_array(dev, "reg", reg, 4);
+#else
 	u32 reg[2];
 
 	dev_read_u32_array(dev, "reg", reg, 2);
+#endif
+
+#if CONFIG_ARM
+	for (i = 0; i < 2; i++)
+		reg[i] = be32_to_cpu(reg[i]);
+#endif
 	addr = dev_translate_address(dev, reg);
 
 	plat->addr = addr;
+#if CONFIG_ARM
+	plat->size = reg[3];
+#else
 	plat->size = reg[1];
+#endif
 	plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);
 
 	return 0;
@@ -187,6 +239,7 @@ static int mpc8xxx_gpio_platdata_to_priv(struct udevice *dev)
 static int mpc8xxx_gpio_probe(struct udevice *dev)
 {
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct device_node const  *np = dev->node.np;
 	struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
 	char name[32], *str;
 
@@ -198,6 +251,12 @@ static int mpc8xxx_gpio_probe(struct udevice *dev)
 	if (!str)
 		return -ENOMEM;
 
+	if (of_device_is_compatible(np, "fsl,qoriq-gpio", NULL, NULL)) {
+		unsigned long gpibe = data->addr + sizeof(struct ccsr_gpio);
+
+		out_be32(gpibe, 0xffffffff);
+	}
+
 	uc_priv->bank_name = str;
 	uc_priv->gpio_count = data->gpio_count;
 
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v1 1/3] gpio: mpc8xxx: support fsl-layerscape platform.
@ 2020-05-09 10:35 ` Hui Song
  0 siblings, 0 replies; 12+ messages in thread
From: Hui Song @ 2020-05-09 10:35 UTC (permalink / raw)
  To: jagdish.gediya, priyanka.jain, pramod.kumar_1
  Cc: devicetree, hui.song, linux-kernel, linux-arm-kernel, linux-gpio

From: "hui.song" <hui.song_1@nxp.com>

Make the MPC8XXX gpio driver to support the fsl-layerscape.

Signed-off-by: hui.song <hui.song_1@nxp.com>
---
 drivers/gpio/mpc8xxx_gpio.c | 59 +++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c
index 1dfd22522c..466f5f50cf 100644
--- a/drivers/gpio/mpc8xxx_gpio.c
+++ b/drivers/gpio/mpc8xxx_gpio.c
@@ -12,6 +12,8 @@
 #include <dm.h>
 #include <mapmem.h>
 #include <asm/gpio.h>
+#include <asm/io.h>
+#include <dm/of_access.h>
 
 struct ccsr_gpio {
 	u32	gpdir;
@@ -20,6 +22,7 @@ struct ccsr_gpio {
 	u32	gpier;
 	u32	gpimr;
 	u32	gpicr;
+	u32	gpibe;
 };
 
 struct mpc8xxx_gpio_data {
@@ -49,31 +52,51 @@ inline u32 gpio_mask(uint gpio)
 
 static inline u32 mpc8xxx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
 {
+#if CONFIG_ARM
+	return in_le32(&base->gpdat) & mask;
+#else
 	return in_be32(&base->gpdat) & mask;
+#endif
 }
 
 static inline u32 mpc8xxx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
 {
+#if CONFIG_ARM
+	return in_le32(&base->gpdir) & mask;
+#else
 	return in_be32(&base->gpdir) & mask;
+#endif
 }
 
 static inline int mpc8xxx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
 {
+#if CONFIG_ARM
+	return in_le32(&base->gpodr) & mask;
+#else
 	return in_be32(&base->gpodr) & mask;
+#endif
 }
 
 static inline void mpc8xxx_gpio_open_drain_on(struct ccsr_gpio *base, u32
 					      gpios)
 {
+#if CONFIG_ARM
+	setbits_le32(&base->gpodr, gpios);
+#else
 	/* GPODR register 1 -> open drain on */
 	setbits_be32(&base->gpodr, gpios);
+#endif
 }
 
 static inline void mpc8xxx_gpio_open_drain_off(struct ccsr_gpio *base,
 					       u32 gpios)
 {
+#if CONFIG_ARM
+	clrbits_le32(&base->gpodr, gpios);
+#else
 	/* GPODR register 0 -> open drain off (actively driven) */
 	clrbits_be32(&base->gpodr, gpios);
+#endif
 }
 
 static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio)
@@ -81,9 +104,13 @@ static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio)
 	struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
 	u32 mask = gpio_mask(gpio);
 
+#if CONFIG_ARM
+	clrbits_le32(&data->base->gpdir, mask);
+#else
 	/* GPDIR register 0 -> input */
 	clrbits_be32(&data->base->gpdir, mask);
 
+#endif
 	return 0;
 }
 
@@ -100,10 +127,19 @@ static int mpc8xxx_gpio_set_value(struct udevice *dev, uint gpio, int value)
 		data->dat_shadow &= ~mask;
 	}
 
+#if CONFIG_ARM
+	gpdir = in_le32(&base->gpdir);
+#else
 	gpdir = in_be32(&base->gpdir);
+#endif
 	gpdir |= gpio_mask(gpio);
+#if CONFIG_ARM
+	out_le32(&base->gpdat, gpdir & data->dat_shadow);
+	out_le32(&base->gpdir, gpdir);
+#else
 	out_be32(&base->gpdat, gpdir & data->dat_shadow);
 	out_be32(&base->gpdir, gpdir);
+#endif
 
 	return 0;
 }
@@ -147,13 +183,29 @@ static int mpc8xxx_gpio_ofdata_to_platdata(struct udevice *dev)
 {
 	struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
 	fdt_addr_t addr;
+	u32 i;
+#if CONFIG_ARM
+	u32 reg[4];
+
+	dev_read_u32_array(dev, "reg", reg, 4);
+#else
 	u32 reg[2];
 
 	dev_read_u32_array(dev, "reg", reg, 2);
+#endif
+
+#if CONFIG_ARM
+	for (i = 0; i < 2; i++)
+		reg[i] = be32_to_cpu(reg[i]);
+#endif
 	addr = dev_translate_address(dev, reg);
 
 	plat->addr = addr;
+#if CONFIG_ARM
+	plat->size = reg[3];
+#else
 	plat->size = reg[1];
+#endif
 	plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);
 
 	return 0;
@@ -187,6 +239,7 @@ static int mpc8xxx_gpio_platdata_to_priv(struct udevice *dev)
 static int mpc8xxx_gpio_probe(struct udevice *dev)
 {
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct device_node const  *np = dev->node.np;
 	struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
 	char name[32], *str;
 
@@ -198,6 +251,12 @@ static int mpc8xxx_gpio_probe(struct udevice *dev)
 	if (!str)
 		return -ENOMEM;
 
+	if (of_device_is_compatible(np, "fsl,qoriq-gpio", NULL, NULL)) {
+		unsigned long gpibe = data->addr + sizeof(struct ccsr_gpio);
+
+		out_be32(gpibe, 0xffffffff);
+	}
+
 	uc_priv->bank_name = str;
 	uc_priv->gpio_count = data->gpio_count;
 
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v1 2/3] armv8: gpio: add gpio feature
  2020-05-09 10:35 ` Hui Song
@ 2020-05-09 10:35   ` Hui Song
  -1 siblings, 0 replies; 12+ messages in thread
From: Hui Song @ 2020-05-09 10:35 UTC (permalink / raw)
  To: jagdish.gediya, priyanka.jain, pramod.kumar_1
  Cc: linux-arm-kernel, devicetree, linux-kernel, linux-gpio, hui.song

From: "hui.song" <hui.song_1@nxp.com>

add one struct mpc8xxx_gpio_plat to enable gpio feature.

Signed-off-by: hui.song <hui.song_1@nxp.com>
---
 .../include/asm/arch-fsl-layerscape/gpio.h    | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/gpio.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/gpio.h b/arch/arm/include/asm/arch-fsl-layerscape/gpio.h
new file mode 100644
index 0000000000..d8dd750a72
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/gpio.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * Dummy header file to enable CONFIG_OF_CONTROL.
+ * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
+ * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
+ * OF_CONTROL must have arch/gpio.h.
+ */
+
+#ifndef __ASM_ARCH_MX85XX_GPIO_H
+#define __ASM_ARCH_MX85XX_GPIO_H
+
+struct mpc8xxx_gpio_plat {
+	ulong addr;
+	unsigned long size;
+	uint ngpios;
+};
+
+#endif
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v1 2/3] armv8: gpio: add gpio feature
@ 2020-05-09 10:35   ` Hui Song
  0 siblings, 0 replies; 12+ messages in thread
From: Hui Song @ 2020-05-09 10:35 UTC (permalink / raw)
  To: jagdish.gediya, priyanka.jain, pramod.kumar_1
  Cc: devicetree, hui.song, linux-kernel, linux-arm-kernel, linux-gpio

From: "hui.song" <hui.song_1@nxp.com>

add one struct mpc8xxx_gpio_plat to enable gpio feature.

Signed-off-by: hui.song <hui.song_1@nxp.com>
---
 .../include/asm/arch-fsl-layerscape/gpio.h    | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/gpio.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/gpio.h b/arch/arm/include/asm/arch-fsl-layerscape/gpio.h
new file mode 100644
index 0000000000..d8dd750a72
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/gpio.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * Dummy header file to enable CONFIG_OF_CONTROL.
+ * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
+ * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
+ * OF_CONTROL must have arch/gpio.h.
+ */
+
+#ifndef __ASM_ARCH_MX85XX_GPIO_H
+#define __ASM_ARCH_MX85XX_GPIO_H
+
+struct mpc8xxx_gpio_plat {
+	ulong addr;
+	unsigned long size;
+	uint ngpios;
+};
+
+#endif
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v1 3/3] dm: armv8: gpio: include <asm/arch/gpio.h> for fsl-layerscape
  2020-05-09 10:35 ` Hui Song
@ 2020-05-09 10:35   ` Hui Song
  -1 siblings, 0 replies; 12+ messages in thread
From: Hui Song @ 2020-05-09 10:35 UTC (permalink / raw)
  To: jagdish.gediya, priyanka.jain, pramod.kumar_1
  Cc: linux-arm-kernel, devicetree, linux-kernel, linux-gpio, hui.song

From: "hui.song" <hui.song_1@nxp.com>

Enable the gpio feature on fsl-layerscape platform.

Signed-off-by: hui.song <hui.song_1@nxp.com>
---
 arch/arm/include/asm/gpio.h | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
index 333e407b66..7715a01706 100644
--- a/arch/arm/include/asm/gpio.h
+++ b/arch/arm/include/asm/gpio.h
@@ -1,12 +1,8 @@
 #if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \
 	!defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM68360) && \
 	!defined(CONFIG_ARCH_BCM6858) && !defined(CONFIG_ARCH_BCM63158) && \
-	!defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_LX2160A) && \
-	!defined(CONFIG_ARCH_LS1028A) && !defined(CONFIG_ARCH_LS2080A) && \
-	!defined(CONFIG_ARCH_LS1088A) && !defined(CONFIG_ARCH_ASPEED) && \
-	!defined(CONFIG_ARCH_LS1012A) && !defined(CONFIG_ARCH_LS1043A) && \
-	!defined(CONFIG_ARCH_LS1046A) && !defined(CONFIG_ARCH_U8500) && \
-	!defined(CONFIG_CORTINA_PLATFORM)
+	!defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_ASPEED) && \
+	!defined(CONFIG_ARCH_U8500) && !defined(CONFIG_CORTINA_PLATFORM)
 #include <asm/arch/gpio.h>
 #endif
 #include <asm-generic/gpio.h>
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v1 3/3] dm: armv8: gpio: include <asm/arch/gpio.h> for fsl-layerscape
@ 2020-05-09 10:35   ` Hui Song
  0 siblings, 0 replies; 12+ messages in thread
From: Hui Song @ 2020-05-09 10:35 UTC (permalink / raw)
  To: jagdish.gediya, priyanka.jain, pramod.kumar_1
  Cc: devicetree, hui.song, linux-kernel, linux-arm-kernel, linux-gpio

From: "hui.song" <hui.song_1@nxp.com>

Enable the gpio feature on fsl-layerscape platform.

Signed-off-by: hui.song <hui.song_1@nxp.com>
---
 arch/arm/include/asm/gpio.h | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
index 333e407b66..7715a01706 100644
--- a/arch/arm/include/asm/gpio.h
+++ b/arch/arm/include/asm/gpio.h
@@ -1,12 +1,8 @@
 #if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \
 	!defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM68360) && \
 	!defined(CONFIG_ARCH_BCM6858) && !defined(CONFIG_ARCH_BCM63158) && \
-	!defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_LX2160A) && \
-	!defined(CONFIG_ARCH_LS1028A) && !defined(CONFIG_ARCH_LS2080A) && \
-	!defined(CONFIG_ARCH_LS1088A) && !defined(CONFIG_ARCH_ASPEED) && \
-	!defined(CONFIG_ARCH_LS1012A) && !defined(CONFIG_ARCH_LS1043A) && \
-	!defined(CONFIG_ARCH_LS1046A) && !defined(CONFIG_ARCH_U8500) && \
-	!defined(CONFIG_CORTINA_PLATFORM)
+	!defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_ASPEED) && \
+	!defined(CONFIG_ARCH_U8500) && !defined(CONFIG_CORTINA_PLATFORM)
 #include <asm/arch/gpio.h>
 #endif
 #include <asm-generic/gpio.h>
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* Re: [PATCH v1 1/3] gpio: mpc8xxx: support fsl-layerscape platform.
  2020-05-09 10:35 ` Hui Song
@ 2020-05-09 11:27   ` Russell King - ARM Linux admin
  -1 siblings, 0 replies; 12+ messages in thread
From: Russell King - ARM Linux admin @ 2020-05-09 11:27 UTC (permalink / raw)
  To: Hui Song
  Cc: jagdish.gediya, priyanka.jain, pramod.kumar_1, devicetree,
	linux-kernel, linux-arm-kernel, linux-gpio

On Sat, May 09, 2020 at 06:35:35PM +0800, Hui Song wrote:
> From: "hui.song" <hui.song_1@nxp.com>
> 
> Make the MPC8XXX gpio driver to support the fsl-layerscape.
> 
> Signed-off-by: hui.song <hui.song_1@nxp.com>
> ---
>  drivers/gpio/mpc8xxx_gpio.c | 59 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 59 insertions(+)

What project are these for?  There is no such file in the kernel tree.

I think you've sent these patches to the wrong people and mailing lists.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 10.2Mbps down 587kbps up

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH v1 1/3] gpio: mpc8xxx: support fsl-layerscape platform.
@ 2020-05-09 11:27   ` Russell King - ARM Linux admin
  0 siblings, 0 replies; 12+ messages in thread
From: Russell King - ARM Linux admin @ 2020-05-09 11:27 UTC (permalink / raw)
  To: Hui Song
  Cc: devicetree, jagdish.gediya, priyanka.jain, linux-kernel,
	linux-gpio, pramod.kumar_1, linux-arm-kernel

On Sat, May 09, 2020 at 06:35:35PM +0800, Hui Song wrote:
> From: "hui.song" <hui.song_1@nxp.com>
> 
> Make the MPC8XXX gpio driver to support the fsl-layerscape.
> 
> Signed-off-by: hui.song <hui.song_1@nxp.com>
> ---
>  drivers/gpio/mpc8xxx_gpio.c | 59 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 59 insertions(+)

What project are these for?  There is no such file in the kernel tree.

I think you've sent these patches to the wrong people and mailing lists.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 10.2Mbps down 587kbps up

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH v1 1/3] gpio: mpc8xxx: support fsl-layerscape platform.
  2020-05-09 10:39 ` Hui Song
@ 2020-05-09 15:24   ` Andrew Lunn
  -1 siblings, 0 replies; 12+ messages in thread
From: Andrew Lunn @ 2020-05-09 15:24 UTC (permalink / raw)
  To: Hui Song
  Cc: u-boot, jiafei.pan, devicetree, linux-kernel, linux-arm-kernel,
	linux-gpio

On Sat, May 09, 2020 at 06:39:54PM +0800, Hui Song wrote:
> From: "hui.song" <hui.song_1@nxp.com>
> 
> Make the MPC8XXX gpio driver to support the fsl-layerscape.
> 
> Signed-off-by: hui.song <hui.song_1@nxp.com>
> ---
>  drivers/gpio/mpc8xxx_gpio.c | 59 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 59 insertions(+)
> 
> diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c
> index 1dfd22522c..466f5f50cf 100644
> --- a/drivers/gpio/mpc8xxx_gpio.c
> +++ b/drivers/gpio/mpc8xxx_gpio.c
> @@ -12,6 +12,8 @@
>  #include <dm.h>
>  #include <mapmem.h>
>  #include <asm/gpio.h>
> +#include <asm/io.h>
> +#include <dm/of_access.h>
>  
>  struct ccsr_gpio {
>  	u32	gpdir;
> @@ -20,6 +22,7 @@ struct ccsr_gpio {
>  	u32	gpier;
>  	u32	gpimr;
>  	u32	gpicr;
> +	u32	gpibe;
>  };
>  
>  struct mpc8xxx_gpio_data {
> @@ -49,31 +52,51 @@ inline u32 gpio_mask(uint gpio)
>  
>  static inline u32 mpc8xxx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
>  {
> +#if CONFIG_ARM
> +	return in_le32(&base->gpdat) & mask;
> +#else
>  	return in_be32(&base->gpdat) & mask;
> +#endif
>  }

Hi Hui

Did the hardware engineers really change the endinness of the
register? Forget about the CPU here, did the register change
endinness? In general, you should not need to use #if like this, so
long as the register itself is still the same. There are functions
which will do the correct thing depending on if the CPU is big or
little endian.

> @@ -147,13 +183,29 @@ static int mpc8xxx_gpio_ofdata_to_platdata(struct udevice *dev)
>  {
>  	struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
>  	fdt_addr_t addr;
> +	u32 i;
> +#if CONFIG_ARM
> +	u32 reg[4];
> +
> +	dev_read_u32_array(dev, "reg", reg, 4);
> +#else
>  	u32 reg[2];
>  
>  	dev_read_u32_array(dev, "reg", reg, 2);
> +#endif
> +
> +#if CONFIG_ARM
> +	for (i = 0; i < 2; i++)
> +		reg[i] = be32_to_cpu(reg[i]);
> +#endif
>  	addr = dev_translate_address(dev, reg);
>  
>  	plat->addr = addr;
> +#if CONFIG_ARM
> +	plat->size = reg[3];
> +#else
>  	plat->size = reg[1];
> +#endif
>  	plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);

So you are extending the DT binding. You need to document this. And it
should really have a different compatible string, since the binding is
not compatible between the two variants.
>  
>  	return 0;
> @@ -187,6 +239,7 @@ static int mpc8xxx_gpio_platdata_to_priv(struct udevice *dev)
>  static int mpc8xxx_gpio_probe(struct udevice *dev)
>  {
>  	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> +	struct device_node const  *np = dev->node.np;
>  	struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
>  	char name[32], *str;
>  
> @@ -198,6 +251,12 @@ static int mpc8xxx_gpio_probe(struct udevice *dev)
>  	if (!str)
>  		return -ENOMEM;
>  
> +	if (of_device_is_compatible(np, "fsl,qoriq-gpio", NULL, NULL)) {
> +		unsigned long gpibe = data->addr + sizeof(struct ccsr_gpio);
> +
> +		out_be32(gpibe, 0xffffffff);

That is an odd way to determine the address of a register.

     Andrew

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH v1 1/3] gpio: mpc8xxx: support fsl-layerscape platform.
@ 2020-05-09 15:24   ` Andrew Lunn
  0 siblings, 0 replies; 12+ messages in thread
From: Andrew Lunn @ 2020-05-09 15:24 UTC (permalink / raw)
  To: Hui Song
  Cc: u-boot, devicetree, linux-kernel, linux-gpio, jiafei.pan,
	linux-arm-kernel

On Sat, May 09, 2020 at 06:39:54PM +0800, Hui Song wrote:
> From: "hui.song" <hui.song_1@nxp.com>
> 
> Make the MPC8XXX gpio driver to support the fsl-layerscape.
> 
> Signed-off-by: hui.song <hui.song_1@nxp.com>
> ---
>  drivers/gpio/mpc8xxx_gpio.c | 59 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 59 insertions(+)
> 
> diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c
> index 1dfd22522c..466f5f50cf 100644
> --- a/drivers/gpio/mpc8xxx_gpio.c
> +++ b/drivers/gpio/mpc8xxx_gpio.c
> @@ -12,6 +12,8 @@
>  #include <dm.h>
>  #include <mapmem.h>
>  #include <asm/gpio.h>
> +#include <asm/io.h>
> +#include <dm/of_access.h>
>  
>  struct ccsr_gpio {
>  	u32	gpdir;
> @@ -20,6 +22,7 @@ struct ccsr_gpio {
>  	u32	gpier;
>  	u32	gpimr;
>  	u32	gpicr;
> +	u32	gpibe;
>  };
>  
>  struct mpc8xxx_gpio_data {
> @@ -49,31 +52,51 @@ inline u32 gpio_mask(uint gpio)
>  
>  static inline u32 mpc8xxx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
>  {
> +#if CONFIG_ARM
> +	return in_le32(&base->gpdat) & mask;
> +#else
>  	return in_be32(&base->gpdat) & mask;
> +#endif
>  }

Hi Hui

Did the hardware engineers really change the endinness of the
register? Forget about the CPU here, did the register change
endinness? In general, you should not need to use #if like this, so
long as the register itself is still the same. There are functions
which will do the correct thing depending on if the CPU is big or
little endian.

> @@ -147,13 +183,29 @@ static int mpc8xxx_gpio_ofdata_to_platdata(struct udevice *dev)
>  {
>  	struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
>  	fdt_addr_t addr;
> +	u32 i;
> +#if CONFIG_ARM
> +	u32 reg[4];
> +
> +	dev_read_u32_array(dev, "reg", reg, 4);
> +#else
>  	u32 reg[2];
>  
>  	dev_read_u32_array(dev, "reg", reg, 2);
> +#endif
> +
> +#if CONFIG_ARM
> +	for (i = 0; i < 2; i++)
> +		reg[i] = be32_to_cpu(reg[i]);
> +#endif
>  	addr = dev_translate_address(dev, reg);
>  
>  	plat->addr = addr;
> +#if CONFIG_ARM
> +	plat->size = reg[3];
> +#else
>  	plat->size = reg[1];
> +#endif
>  	plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);

So you are extending the DT binding. You need to document this. And it
should really have a different compatible string, since the binding is
not compatible between the two variants.
>  
>  	return 0;
> @@ -187,6 +239,7 @@ static int mpc8xxx_gpio_platdata_to_priv(struct udevice *dev)
>  static int mpc8xxx_gpio_probe(struct udevice *dev)
>  {
>  	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> +	struct device_node const  *np = dev->node.np;
>  	struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
>  	char name[32], *str;
>  
> @@ -198,6 +251,12 @@ static int mpc8xxx_gpio_probe(struct udevice *dev)
>  	if (!str)
>  		return -ENOMEM;
>  
> +	if (of_device_is_compatible(np, "fsl,qoriq-gpio", NULL, NULL)) {
> +		unsigned long gpibe = data->addr + sizeof(struct ccsr_gpio);
> +
> +		out_be32(gpibe, 0xffffffff);

That is an odd way to determine the address of a register.

     Andrew

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 12+ messages in thread

* [PATCH v1 1/3] gpio: mpc8xxx: support fsl-layerscape platform.
@ 2020-05-09 10:39 ` Hui Song
  0 siblings, 0 replies; 12+ messages in thread
From: Hui Song @ 2020-05-09 10:39 UTC (permalink / raw)
  To: u-boot, jiafei.pan
  Cc: linux-arm-kernel, devicetree, linux-kernel, linux-gpio, hui.song

From: "hui.song" <hui.song_1@nxp.com>

Make the MPC8XXX gpio driver to support the fsl-layerscape.

Signed-off-by: hui.song <hui.song_1@nxp.com>
---
 drivers/gpio/mpc8xxx_gpio.c | 59 +++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c
index 1dfd22522c..466f5f50cf 100644
--- a/drivers/gpio/mpc8xxx_gpio.c
+++ b/drivers/gpio/mpc8xxx_gpio.c
@@ -12,6 +12,8 @@
 #include <dm.h>
 #include <mapmem.h>
 #include <asm/gpio.h>
+#include <asm/io.h>
+#include <dm/of_access.h>
 
 struct ccsr_gpio {
 	u32	gpdir;
@@ -20,6 +22,7 @@ struct ccsr_gpio {
 	u32	gpier;
 	u32	gpimr;
 	u32	gpicr;
+	u32	gpibe;
 };
 
 struct mpc8xxx_gpio_data {
@@ -49,31 +52,51 @@ inline u32 gpio_mask(uint gpio)
 
 static inline u32 mpc8xxx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
 {
+#if CONFIG_ARM
+	return in_le32(&base->gpdat) & mask;
+#else
 	return in_be32(&base->gpdat) & mask;
+#endif
 }
 
 static inline u32 mpc8xxx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
 {
+#if CONFIG_ARM
+	return in_le32(&base->gpdir) & mask;
+#else
 	return in_be32(&base->gpdir) & mask;
+#endif
 }
 
 static inline int mpc8xxx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
 {
+#if CONFIG_ARM
+	return in_le32(&base->gpodr) & mask;
+#else
 	return in_be32(&base->gpodr) & mask;
+#endif
 }
 
 static inline void mpc8xxx_gpio_open_drain_on(struct ccsr_gpio *base, u32
 					      gpios)
 {
+#if CONFIG_ARM
+	setbits_le32(&base->gpodr, gpios);
+#else
 	/* GPODR register 1 -> open drain on */
 	setbits_be32(&base->gpodr, gpios);
+#endif
 }
 
 static inline void mpc8xxx_gpio_open_drain_off(struct ccsr_gpio *base,
 					       u32 gpios)
 {
+#if CONFIG_ARM
+	clrbits_le32(&base->gpodr, gpios);
+#else
 	/* GPODR register 0 -> open drain off (actively driven) */
 	clrbits_be32(&base->gpodr, gpios);
+#endif
 }
 
 static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio)
@@ -81,9 +104,13 @@ static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio)
 	struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
 	u32 mask = gpio_mask(gpio);
 
+#if CONFIG_ARM
+	clrbits_le32(&data->base->gpdir, mask);
+#else
 	/* GPDIR register 0 -> input */
 	clrbits_be32(&data->base->gpdir, mask);
 
+#endif
 	return 0;
 }
 
@@ -100,10 +127,19 @@ static int mpc8xxx_gpio_set_value(struct udevice *dev, uint gpio, int value)
 		data->dat_shadow &= ~mask;
 	}
 
+#if CONFIG_ARM
+	gpdir = in_le32(&base->gpdir);
+#else
 	gpdir = in_be32(&base->gpdir);
+#endif
 	gpdir |= gpio_mask(gpio);
+#if CONFIG_ARM
+	out_le32(&base->gpdat, gpdir & data->dat_shadow);
+	out_le32(&base->gpdir, gpdir);
+#else
 	out_be32(&base->gpdat, gpdir & data->dat_shadow);
 	out_be32(&base->gpdir, gpdir);
+#endif
 
 	return 0;
 }
@@ -147,13 +183,29 @@ static int mpc8xxx_gpio_ofdata_to_platdata(struct udevice *dev)
 {
 	struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
 	fdt_addr_t addr;
+	u32 i;
+#if CONFIG_ARM
+	u32 reg[4];
+
+	dev_read_u32_array(dev, "reg", reg, 4);
+#else
 	u32 reg[2];
 
 	dev_read_u32_array(dev, "reg", reg, 2);
+#endif
+
+#if CONFIG_ARM
+	for (i = 0; i < 2; i++)
+		reg[i] = be32_to_cpu(reg[i]);
+#endif
 	addr = dev_translate_address(dev, reg);
 
 	plat->addr = addr;
+#if CONFIG_ARM
+	plat->size = reg[3];
+#else
 	plat->size = reg[1];
+#endif
 	plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);
 
 	return 0;
@@ -187,6 +239,7 @@ static int mpc8xxx_gpio_platdata_to_priv(struct udevice *dev)
 static int mpc8xxx_gpio_probe(struct udevice *dev)
 {
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct device_node const  *np = dev->node.np;
 	struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
 	char name[32], *str;
 
@@ -198,6 +251,12 @@ static int mpc8xxx_gpio_probe(struct udevice *dev)
 	if (!str)
 		return -ENOMEM;
 
+	if (of_device_is_compatible(np, "fsl,qoriq-gpio", NULL, NULL)) {
+		unsigned long gpibe = data->addr + sizeof(struct ccsr_gpio);
+
+		out_be32(gpibe, 0xffffffff);
+	}
+
 	uc_priv->bank_name = str;
 	uc_priv->gpio_count = data->gpio_count;
 
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v1 1/3] gpio: mpc8xxx: support fsl-layerscape platform.
@ 2020-05-09 10:39 ` Hui Song
  0 siblings, 0 replies; 12+ messages in thread
From: Hui Song @ 2020-05-09 10:39 UTC (permalink / raw)
  To: u-boot, jiafei.pan
  Cc: devicetree, hui.song, linux-kernel, linux-arm-kernel, linux-gpio

From: "hui.song" <hui.song_1@nxp.com>

Make the MPC8XXX gpio driver to support the fsl-layerscape.

Signed-off-by: hui.song <hui.song_1@nxp.com>
---
 drivers/gpio/mpc8xxx_gpio.c | 59 +++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c
index 1dfd22522c..466f5f50cf 100644
--- a/drivers/gpio/mpc8xxx_gpio.c
+++ b/drivers/gpio/mpc8xxx_gpio.c
@@ -12,6 +12,8 @@
 #include <dm.h>
 #include <mapmem.h>
 #include <asm/gpio.h>
+#include <asm/io.h>
+#include <dm/of_access.h>
 
 struct ccsr_gpio {
 	u32	gpdir;
@@ -20,6 +22,7 @@ struct ccsr_gpio {
 	u32	gpier;
 	u32	gpimr;
 	u32	gpicr;
+	u32	gpibe;
 };
 
 struct mpc8xxx_gpio_data {
@@ -49,31 +52,51 @@ inline u32 gpio_mask(uint gpio)
 
 static inline u32 mpc8xxx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
 {
+#if CONFIG_ARM
+	return in_le32(&base->gpdat) & mask;
+#else
 	return in_be32(&base->gpdat) & mask;
+#endif
 }
 
 static inline u32 mpc8xxx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
 {
+#if CONFIG_ARM
+	return in_le32(&base->gpdir) & mask;
+#else
 	return in_be32(&base->gpdir) & mask;
+#endif
 }
 
 static inline int mpc8xxx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
 {
+#if CONFIG_ARM
+	return in_le32(&base->gpodr) & mask;
+#else
 	return in_be32(&base->gpodr) & mask;
+#endif
 }
 
 static inline void mpc8xxx_gpio_open_drain_on(struct ccsr_gpio *base, u32
 					      gpios)
 {
+#if CONFIG_ARM
+	setbits_le32(&base->gpodr, gpios);
+#else
 	/* GPODR register 1 -> open drain on */
 	setbits_be32(&base->gpodr, gpios);
+#endif
 }
 
 static inline void mpc8xxx_gpio_open_drain_off(struct ccsr_gpio *base,
 					       u32 gpios)
 {
+#if CONFIG_ARM
+	clrbits_le32(&base->gpodr, gpios);
+#else
 	/* GPODR register 0 -> open drain off (actively driven) */
 	clrbits_be32(&base->gpodr, gpios);
+#endif
 }
 
 static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio)
@@ -81,9 +104,13 @@ static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio)
 	struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
 	u32 mask = gpio_mask(gpio);
 
+#if CONFIG_ARM
+	clrbits_le32(&data->base->gpdir, mask);
+#else
 	/* GPDIR register 0 -> input */
 	clrbits_be32(&data->base->gpdir, mask);
 
+#endif
 	return 0;
 }
 
@@ -100,10 +127,19 @@ static int mpc8xxx_gpio_set_value(struct udevice *dev, uint gpio, int value)
 		data->dat_shadow &= ~mask;
 	}
 
+#if CONFIG_ARM
+	gpdir = in_le32(&base->gpdir);
+#else
 	gpdir = in_be32(&base->gpdir);
+#endif
 	gpdir |= gpio_mask(gpio);
+#if CONFIG_ARM
+	out_le32(&base->gpdat, gpdir & data->dat_shadow);
+	out_le32(&base->gpdir, gpdir);
+#else
 	out_be32(&base->gpdat, gpdir & data->dat_shadow);
 	out_be32(&base->gpdir, gpdir);
+#endif
 
 	return 0;
 }
@@ -147,13 +183,29 @@ static int mpc8xxx_gpio_ofdata_to_platdata(struct udevice *dev)
 {
 	struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
 	fdt_addr_t addr;
+	u32 i;
+#if CONFIG_ARM
+	u32 reg[4];
+
+	dev_read_u32_array(dev, "reg", reg, 4);
+#else
 	u32 reg[2];
 
 	dev_read_u32_array(dev, "reg", reg, 2);
+#endif
+
+#if CONFIG_ARM
+	for (i = 0; i < 2; i++)
+		reg[i] = be32_to_cpu(reg[i]);
+#endif
 	addr = dev_translate_address(dev, reg);
 
 	plat->addr = addr;
+#if CONFIG_ARM
+	plat->size = reg[3];
+#else
 	plat->size = reg[1];
+#endif
 	plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);
 
 	return 0;
@@ -187,6 +239,7 @@ static int mpc8xxx_gpio_platdata_to_priv(struct udevice *dev)
 static int mpc8xxx_gpio_probe(struct udevice *dev)
 {
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct device_node const  *np = dev->node.np;
 	struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
 	char name[32], *str;
 
@@ -198,6 +251,12 @@ static int mpc8xxx_gpio_probe(struct udevice *dev)
 	if (!str)
 		return -ENOMEM;
 
+	if (of_device_is_compatible(np, "fsl,qoriq-gpio", NULL, NULL)) {
+		unsigned long gpibe = data->addr + sizeof(struct ccsr_gpio);
+
+		out_be32(gpibe, 0xffffffff);
+	}
+
 	uc_priv->bank_name = str;
 	uc_priv->gpio_count = data->gpio_count;
 
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 12+ messages in thread

end of thread, other threads:[~2020-05-09 15:24 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-09 10:35 [PATCH v1 1/3] gpio: mpc8xxx: support fsl-layerscape platform Hui Song
2020-05-09 10:35 ` Hui Song
2020-05-09 10:35 ` [PATCH v1 2/3] armv8: gpio: add gpio feature Hui Song
2020-05-09 10:35   ` Hui Song
2020-05-09 10:35 ` [PATCH v1 3/3] dm: armv8: gpio: include <asm/arch/gpio.h> for fsl-layerscape Hui Song
2020-05-09 10:35   ` Hui Song
2020-05-09 11:27 ` [PATCH v1 1/3] gpio: mpc8xxx: support fsl-layerscape platform Russell King - ARM Linux admin
2020-05-09 11:27   ` Russell King - ARM Linux admin
2020-05-09 10:39 Hui Song
2020-05-09 10:39 ` Hui Song
2020-05-09 15:24 ` Andrew Lunn
2020-05-09 15:24   ` Andrew Lunn

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