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From: Pragnesh Patel <pragnesh.patel@sifive.com>
To: u-boot@lists.denx.de
Subject: [PATCH v8 12/21] riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux
Date: Sat,  9 May 2020 20:00:27 +0530	[thread overview]
Message-ID: <20200509143037.26009-13-pragnesh.patel@sifive.com> (raw)
In-Reply-To: <20200509143037.26009-1-pragnesh.patel@sifive.com>

This sync has changes required to use GPIO in U-Boot and
U-Boot SPL.

Sync dts from linux v5.7-rc2 commit:
"riscv: dts: Add GPIO reboot method to HiFive Unleashed DTS file"
(sha1: 0a91330b2af9f71ceeeed483f92774182b58f6d9)

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 arch/riscv/dts/fu540-c000.dtsi          | 37 ++++++++++++++++++++++++-
 arch/riscv/dts/hifive-unleashed-a00.dts |  9 ++++++
 2 files changed, 45 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/dts/fu540-c000.dtsi b/arch/riscv/dts/fu540-c000.dtsi
index afa43c7ea3..7db8610534 100644
--- a/arch/riscv/dts/fu540-c000.dtsi
+++ b/arch/riscv/dts/fu540-c000.dtsi
@@ -54,6 +54,7 @@
 			reg = <1>;
 			riscv,isa = "rv64imafdc";
 			tlb-split;
+			next-level-cache = <&l2cache>;
 			cpu1_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				compatible = "riscv,cpu-intc";
@@ -77,6 +78,7 @@
 			reg = <2>;
 			riscv,isa = "rv64imafdc";
 			tlb-split;
+			next-level-cache = <&l2cache>;
 			cpu2_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				compatible = "riscv,cpu-intc";
@@ -100,6 +102,7 @@
 			reg = <3>;
 			riscv,isa = "rv64imafdc";
 			tlb-split;
+			next-level-cache = <&l2cache>;
 			cpu3_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				compatible = "riscv,cpu-intc";
@@ -123,6 +126,7 @@
 			reg = <4>;
 			riscv,isa = "rv64imafdc";
 			tlb-split;
+			next-level-cache = <&l2cache>;
 			cpu4_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				compatible = "riscv,cpu-intc";
@@ -162,6 +166,13 @@
 			clocks = <&prci PRCI_CLK_TLCLK>;
 			status = "disabled";
 		};
+		dma: dma at 3000000 {
+			compatible = "sifive,fu540-c000-pdma";
+			reg = <0x0 0x3000000 0x0 0x8000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <23 24 25 26 27 28 29 30>;
+			#dma-cells = <1>;
+		};
 		uart1: serial at 10011000 {
 			compatible = "sifive,fu540-c000-uart", "sifive,uart0";
 			reg = <0x0 0x10011000 0x0 0x1000>;
@@ -246,6 +257,30 @@
 			#pwm-cells = <3>;
 			status = "disabled";
 		};
-
+		l2cache: cache-controller at 2010000 {
+			compatible = "sifive,fu540-c000-ccache", "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <1024>;
+			cache-size = <2097152>;
+			cache-unified;
+			interrupt-parent = <&plic0>;
+			interrupts = <1 2 3>;
+			reg = <0x0 0x2010000 0x0 0x1000>;
+		};
+		gpio: gpio at 10060000 {
+			compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
+			interrupt-parent = <&plic0>;
+			interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>,
+				     <14>, <15>, <16>, <17>, <18>, <19>, <20>,
+				     <21>, <22>;
+			reg = <0x0 0x10060000 0x0 0x1000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&prci PRCI_CLK_TLCLK>;
+			status = "disabled";
+		};
 	};
 };
diff --git a/arch/riscv/dts/hifive-unleashed-a00.dts b/arch/riscv/dts/hifive-unleashed-a00.dts
index 88cfcb96bf..4a2729f5ca 100644
--- a/arch/riscv/dts/hifive-unleashed-a00.dts
+++ b/arch/riscv/dts/hifive-unleashed-a00.dts
@@ -2,6 +2,7 @@
 /* Copyright (c) 2018-2019 SiFive, Inc */
 
 #include "fu540-c000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 /* Clock frequency (in Hz) of the PCB crystal for rtcclk */
 #define RTCCLK_FREQ		1000000
@@ -41,6 +42,10 @@
 		clock-frequency = <RTCCLK_FREQ>;
 		clock-output-names = "rtcclk";
 	};
+	gpio-restart {
+		compatible = "gpio-restart";
+		gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+	};
 };
 
 &uart0 {
@@ -94,3 +99,7 @@
 &pwm1 {
 	status = "okay";
 };
+
+&gpio {
+	status = "okay";
+};
-- 
2.17.1

  parent reply	other threads:[~2020-05-09 14:30 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 01/21] misc: add driver for the SiFive otp controller Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 02/21] riscv: sifive: fu540: Use OTP DM driver for serial environment variable Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 03/21] riscv: Add _image_binary_end for SPL Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 04/21] lib: Makefile: build crc7.c when CONFIG_MMC_SPI Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 05/21] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 06/21] sifive: fu540: add ddr driver Pragnesh Patel
2020-05-09 19:47   ` Giulio Benetti
2020-05-10  6:18     ` Pragnesh Patel
2020-05-10  6:35     ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 07/21] sifive: dts: fu540: Add DDR controller and phy register settings Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 08/21] riscv: sifive: dts: fu540: add U-Boot dmc node Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 09/21] clk: sifive: fu540-prci: Add clock enable and disable ops Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 10/21] clk: sifive: fu540-prci: Add ddr clock initialization in SPL Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 11/21] clk: sifive: fu540-prci: Add ehternet " Pragnesh Patel
2020-05-09 14:30 ` Pragnesh Patel [this message]
2020-05-09 14:30 ` [PATCH v8 13/21] riscv: cpu: fu540: Add support for cpu fu540 Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 14/21] riscv: Add place-holder for driver compilation Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 15/21] riscv: sifive: fu540: add SPL configuration Pragnesh Patel
2020-05-11  9:00   ` Jagan Teki
2020-05-11  9:44     ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 16/21] sifive: fu540: Add sample SD gpt partition layout Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 17/21] sifive: fu540: Add U-Boot proper sector start Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 18/21] configs: fu540: Add config options for U-Boot SPL Pragnesh Patel
2020-05-10  9:20   ` Jagan Teki
2020-05-11  5:59     ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 19/21] sifive: dts: fu540: Enable L2 Cache in U-Boot Pragnesh Patel
2020-05-10 15:14   ` Jagan Teki
2020-05-11  6:06     ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 20/21] riscv: sifive: fu540: enable all cache ways from U-Boot proper Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 21/21] doc: sifive: fu540: Add description for OpenSBI generic platform Pragnesh Patel

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