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From: Pragnesh Patel <pragnesh.patel@sifive.com>
To: u-boot@lists.denx.de
Subject: [PATCH v8 11/21] clk: sifive: fu540-prci: Add ehternet clock initialization in SPL
Date: Sat,  9 May 2020 20:00:26 +0530	[thread overview]
Message-ID: <20200509143037.26009-12-pragnesh.patel@sifive.com> (raw)
In-Reply-To: <20200509143037.26009-1-pragnesh.patel@sifive.com>

Add ehternet clock initialization for SPL

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
---
 drivers/clk/sifive/fu540-prci.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index 033562274e..e7ceda0dcf 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -41,6 +41,8 @@
 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
 #include <dt-bindings/clock/sifive-fu540-prci.h>
 
+#define MHz		1000000
+
 /*
  * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
  *     hfclk and rtcclk
@@ -709,6 +711,29 @@ static int sifive_fu540_prci_disable(struct clk *clk)
 	return ret;
 }
 
+#ifdef CONFIG_SPL_BUILD
+static void ethernet_init(struct udevice *dev)
+{
+	u32 v;
+	struct clk clock;
+	struct __prci_data *pd = dev_get_priv(dev);
+
+	/* GEMGXL init */
+	clock.id = PRCI_CLK_GEMGXLPLL;
+	sifive_fu540_prci_set_rate(&clock, 125UL * MHz);
+	sifive_fu540_prci_clock_enable(&__prci_init_clocks[clock.id], 1);
+
+	/* Release GEMGXL reset */
+	v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
+	v |= PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK;
+	__prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
+
+	/* Procmon => core clock */
+	__prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET,
+			pd);
+}
+#endif
+
 static int sifive_fu540_prci_probe(struct udevice *dev)
 {
 	int i, err;
@@ -734,6 +759,10 @@ static int sifive_fu540_prci_probe(struct udevice *dev)
 			__prci_wrpll_read_cfg0(pd, pc->pwd);
 	}
 
+#ifdef CONFIG_SPL_BUILD
+	ethernet_init(dev);
+#endif
+
 	return 0;
 }
 
-- 
2.17.1

  parent reply	other threads:[~2020-05-09 14:30 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 01/21] misc: add driver for the SiFive otp controller Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 02/21] riscv: sifive: fu540: Use OTP DM driver for serial environment variable Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 03/21] riscv: Add _image_binary_end for SPL Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 04/21] lib: Makefile: build crc7.c when CONFIG_MMC_SPI Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 05/21] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 06/21] sifive: fu540: add ddr driver Pragnesh Patel
2020-05-09 19:47   ` Giulio Benetti
2020-05-10  6:18     ` Pragnesh Patel
2020-05-10  6:35     ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 07/21] sifive: dts: fu540: Add DDR controller and phy register settings Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 08/21] riscv: sifive: dts: fu540: add U-Boot dmc node Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 09/21] clk: sifive: fu540-prci: Add clock enable and disable ops Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 10/21] clk: sifive: fu540-prci: Add ddr clock initialization in SPL Pragnesh Patel
2020-05-09 14:30 ` Pragnesh Patel [this message]
2020-05-09 14:30 ` [PATCH v8 12/21] riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 13/21] riscv: cpu: fu540: Add support for cpu fu540 Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 14/21] riscv: Add place-holder for driver compilation Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 15/21] riscv: sifive: fu540: add SPL configuration Pragnesh Patel
2020-05-11  9:00   ` Jagan Teki
2020-05-11  9:44     ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 16/21] sifive: fu540: Add sample SD gpt partition layout Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 17/21] sifive: fu540: Add U-Boot proper sector start Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 18/21] configs: fu540: Add config options for U-Boot SPL Pragnesh Patel
2020-05-10  9:20   ` Jagan Teki
2020-05-11  5:59     ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 19/21] sifive: dts: fu540: Enable L2 Cache in U-Boot Pragnesh Patel
2020-05-10 15:14   ` Jagan Teki
2020-05-11  6:06     ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 20/21] riscv: sifive: fu540: enable all cache ways from U-Boot proper Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 21/21] doc: sifive: fu540: Add description for OpenSBI generic platform Pragnesh Patel

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