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From: Lyude Paul <lyude@redhat.com>
To: nouveau@lists.freedesktop.org
Cc: "Alex Deucher" <alexander.deucher@amd.com>,
	"Pankaj Bharadiya" <pankaj.laxminarayan.bharadiya@intel.com>,
	"Daniel Vetter" <daniel@ffwll.ch>,
	"David Airlie" <airlied@linux.ie>, "Takashi Iwai" <tiwai@suse.de>,
	"Sean Paul" <seanpaul@chromium.org>,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	"Ben Skeggs" <bskeggs@redhat.com>,
	"Lyude Paul" <lyude@redhat.com>,
	"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
	"Jani Nikula" <jani.nikula@intel.com>,
	"Ilia Mirkin" <imirkin@alum.mit.edu>
Subject: [PATCH v3 0/5] drm/nouveau: DP interlace fixes
Date: Mon, 11 May 2020 18:41:22 -0400	[thread overview]
Message-ID: <20200511224148.598468-1-lyude@redhat.com> (raw)

Currently, nouveau doesn't actually bother to try probing whether or not
it can actually handle interlaced modes over DisplayPort. As a result,
on volta and later we'll end up trying to set an interlaced mode even
when it's not supported and cause the front end for the display engine
to hang.

So, let's teach nouveau to reject interlaced modes on hardware that
can't actually handle it. Additionally for MST, since we accomplish this
by simply reusing more of the SST mode validation we also get (some)
basic bw validation for modes we detect on MST connectors completely for
free.

Lyude Paul (5):
  drm/nouveau/kms/nv50-: Initialize core channel in
    nouveau_display_create()
  drm/nouveau/kms/nv50-: Probe SOR and PIOR caps for DP interlacing
    support
  drm/nouveau/kms/gv100-: Add support for interlaced modes
  drm/nouveau/kms/nv50-: Move 8BPC limit for MST into
    nv50_mstc_get_modes()
  drm/nouveau/kms/nv50-: Share DP SST mode_valid() handling with MST

 drivers/gpu/drm/nouveau/dispnv50/core.h     |  7 +++
 drivers/gpu/drm/nouveau/dispnv50/core507d.c | 15 ++++++
 drivers/gpu/drm/nouveau/dispnv50/core827d.c |  1 +
 drivers/gpu/drm/nouveau/dispnv50/core907d.c |  1 +
 drivers/gpu/drm/nouveau/dispnv50/core917d.c |  1 +
 drivers/gpu/drm/nouveau/dispnv50/corec37d.c | 26 +++++++++
 drivers/gpu/drm/nouveau/dispnv50/corec57d.c |  1 +
 drivers/gpu/drm/nouveau/dispnv50/disp.c     | 58 +++++++++++++++------
 drivers/gpu/drm/nouveau/dispnv50/disp.h     |  1 +
 drivers/gpu/drm/nouveau/dispnv50/headc37d.c |  5 +-
 drivers/gpu/drm/nouveau/dispnv50/headc57d.c |  5 +-
 drivers/gpu/drm/nouveau/dispnv50/pior507d.c |  8 +++
 drivers/gpu/drm/nouveau/dispnv50/sor507d.c  |  7 +++
 drivers/gpu/drm/nouveau/dispnv50/sor907d.c  | 11 ++++
 drivers/gpu/drm/nouveau/dispnv50/sorc37d.c  |  9 ++++
 drivers/gpu/drm/nouveau/nouveau_connector.c | 48 +++++++++++------
 drivers/gpu/drm/nouveau/nouveau_connector.h |  5 ++
 drivers/gpu/drm/nouveau/nouveau_dp.c        | 31 +++++++++++
 drivers/gpu/drm/nouveau/nouveau_encoder.h   |  8 +++
 19 files changed, 213 insertions(+), 35 deletions(-)

-- 
2.26.2


WARNING: multiple messages have this Message-ID (diff)
From: Lyude Paul <lyude-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: "Jani Nikula"
	<jani.nikula-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
	"David Airlie" <airlied-cv59FeDIM0c@public.gmane.org>,
	"Pankaj Bharadiya"
	<pankaj.laxminarayan.bharadiya-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
	"Takashi Iwai" <tiwai-l3A5Bk7waGM@public.gmane.org>,
	"Sean Paul" <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
	"Ben Skeggs" <bskeggs-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
	"Daniel Vetter" <daniel-/w4YWyX8dFk@public.gmane.org>,
	"Alex Deucher" <alexander.deucher-5C7GfCeVMHo@public.gmane.org>,
	"Ville Syrjälä"
	<ville.syrjala-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
Subject: [PATCH v3 0/5] drm/nouveau: DP interlace fixes
Date: Mon, 11 May 2020 18:41:22 -0400	[thread overview]
Message-ID: <20200511224148.598468-1-lyude@redhat.com> (raw)

Currently, nouveau doesn't actually bother to try probing whether or not
it can actually handle interlaced modes over DisplayPort. As a result,
on volta and later we'll end up trying to set an interlaced mode even
when it's not supported and cause the front end for the display engine
to hang.

So, let's teach nouveau to reject interlaced modes on hardware that
can't actually handle it. Additionally for MST, since we accomplish this
by simply reusing more of the SST mode validation we also get (some)
basic bw validation for modes we detect on MST connectors completely for
free.

Lyude Paul (5):
  drm/nouveau/kms/nv50-: Initialize core channel in
    nouveau_display_create()
  drm/nouveau/kms/nv50-: Probe SOR and PIOR caps for DP interlacing
    support
  drm/nouveau/kms/gv100-: Add support for interlaced modes
  drm/nouveau/kms/nv50-: Move 8BPC limit for MST into
    nv50_mstc_get_modes()
  drm/nouveau/kms/nv50-: Share DP SST mode_valid() handling with MST

 drivers/gpu/drm/nouveau/dispnv50/core.h     |  7 +++
 drivers/gpu/drm/nouveau/dispnv50/core507d.c | 15 ++++++
 drivers/gpu/drm/nouveau/dispnv50/core827d.c |  1 +
 drivers/gpu/drm/nouveau/dispnv50/core907d.c |  1 +
 drivers/gpu/drm/nouveau/dispnv50/core917d.c |  1 +
 drivers/gpu/drm/nouveau/dispnv50/corec37d.c | 26 +++++++++
 drivers/gpu/drm/nouveau/dispnv50/corec57d.c |  1 +
 drivers/gpu/drm/nouveau/dispnv50/disp.c     | 58 +++++++++++++++------
 drivers/gpu/drm/nouveau/dispnv50/disp.h     |  1 +
 drivers/gpu/drm/nouveau/dispnv50/headc37d.c |  5 +-
 drivers/gpu/drm/nouveau/dispnv50/headc57d.c |  5 +-
 drivers/gpu/drm/nouveau/dispnv50/pior507d.c |  8 +++
 drivers/gpu/drm/nouveau/dispnv50/sor507d.c  |  7 +++
 drivers/gpu/drm/nouveau/dispnv50/sor907d.c  | 11 ++++
 drivers/gpu/drm/nouveau/dispnv50/sorc37d.c  |  9 ++++
 drivers/gpu/drm/nouveau/nouveau_connector.c | 48 +++++++++++------
 drivers/gpu/drm/nouveau/nouveau_connector.h |  5 ++
 drivers/gpu/drm/nouveau/nouveau_dp.c        | 31 +++++++++++
 drivers/gpu/drm/nouveau/nouveau_encoder.h   |  8 +++
 19 files changed, 213 insertions(+), 35 deletions(-)

-- 
2.26.2

WARNING: multiple messages have this Message-ID (diff)
From: Lyude Paul <lyude@redhat.com>
To: nouveau@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>,
	David Airlie <airlied@linux.ie>,
	Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	Sean Paul <seanpaul@chromium.org>,
	Ben Skeggs <bskeggs@redhat.com>,
	Alex Deucher <alexander.deucher@amd.com>
Subject: [PATCH v3 0/5] drm/nouveau: DP interlace fixes
Date: Mon, 11 May 2020 18:41:22 -0400	[thread overview]
Message-ID: <20200511224148.598468-1-lyude@redhat.com> (raw)

Currently, nouveau doesn't actually bother to try probing whether or not
it can actually handle interlaced modes over DisplayPort. As a result,
on volta and later we'll end up trying to set an interlaced mode even
when it's not supported and cause the front end for the display engine
to hang.

So, let's teach nouveau to reject interlaced modes on hardware that
can't actually handle it. Additionally for MST, since we accomplish this
by simply reusing more of the SST mode validation we also get (some)
basic bw validation for modes we detect on MST connectors completely for
free.

Lyude Paul (5):
  drm/nouveau/kms/nv50-: Initialize core channel in
    nouveau_display_create()
  drm/nouveau/kms/nv50-: Probe SOR and PIOR caps for DP interlacing
    support
  drm/nouveau/kms/gv100-: Add support for interlaced modes
  drm/nouveau/kms/nv50-: Move 8BPC limit for MST into
    nv50_mstc_get_modes()
  drm/nouveau/kms/nv50-: Share DP SST mode_valid() handling with MST

 drivers/gpu/drm/nouveau/dispnv50/core.h     |  7 +++
 drivers/gpu/drm/nouveau/dispnv50/core507d.c | 15 ++++++
 drivers/gpu/drm/nouveau/dispnv50/core827d.c |  1 +
 drivers/gpu/drm/nouveau/dispnv50/core907d.c |  1 +
 drivers/gpu/drm/nouveau/dispnv50/core917d.c |  1 +
 drivers/gpu/drm/nouveau/dispnv50/corec37d.c | 26 +++++++++
 drivers/gpu/drm/nouveau/dispnv50/corec57d.c |  1 +
 drivers/gpu/drm/nouveau/dispnv50/disp.c     | 58 +++++++++++++++------
 drivers/gpu/drm/nouveau/dispnv50/disp.h     |  1 +
 drivers/gpu/drm/nouveau/dispnv50/headc37d.c |  5 +-
 drivers/gpu/drm/nouveau/dispnv50/headc57d.c |  5 +-
 drivers/gpu/drm/nouveau/dispnv50/pior507d.c |  8 +++
 drivers/gpu/drm/nouveau/dispnv50/sor507d.c  |  7 +++
 drivers/gpu/drm/nouveau/dispnv50/sor907d.c  | 11 ++++
 drivers/gpu/drm/nouveau/dispnv50/sorc37d.c  |  9 ++++
 drivers/gpu/drm/nouveau/nouveau_connector.c | 48 +++++++++++------
 drivers/gpu/drm/nouveau/nouveau_connector.h |  5 ++
 drivers/gpu/drm/nouveau/nouveau_dp.c        | 31 +++++++++++
 drivers/gpu/drm/nouveau/nouveau_encoder.h   |  8 +++
 19 files changed, 213 insertions(+), 35 deletions(-)

-- 
2.26.2

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             reply	other threads:[~2020-05-11 22:42 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-11 22:41 Lyude Paul [this message]
2020-05-11 22:41 ` [PATCH v3 0/5] drm/nouveau: DP interlace fixes Lyude Paul
2020-05-11 22:41 ` Lyude Paul
2020-05-11 22:41 ` [PATCH v3 1/5] drm/nouveau/kms/nv50-: Initialize core channel in nouveau_display_create() Lyude Paul
2020-05-11 22:41   ` Lyude Paul
2020-05-11 22:41 ` [PATCH v3 2/5] drm/nouveau/kms/nv50-: Probe SOR and PIOR caps for DP interlacing support Lyude Paul
2020-05-11 22:41   ` Lyude Paul
2020-05-11 22:41 ` [PATCH v3 3/5] drm/nouveau/kms/gv100-: Add support for interlaced modes Lyude Paul
2020-05-11 22:41   ` Lyude Paul
2020-05-11 23:05   ` Ilia Mirkin
2020-05-11 23:05     ` Ilia Mirkin
2020-05-12  2:10     ` Ben Skeggs
2020-05-12  2:10       ` Ben Skeggs
2020-05-12  2:10       ` Ben Skeggs
2020-05-11 22:41 ` [PATCH v3 4/5] drm/nouveau/kms/nv50-: Move 8BPC limit for MST into nv50_mstc_get_modes() Lyude Paul
2020-05-11 22:41   ` Lyude Paul
2020-05-11 22:41 ` [PATCH v3 5/5] drm/nouveau/kms/nv50-: Share DP SST mode_valid() handling with MST Lyude Paul
2020-05-11 22:41   ` Lyude Paul

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