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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v28 2/6] drm/i915: Extract skl SAGV checking
Date: Tue, 12 May 2020 14:47:45 +0300	[thread overview]
Message-ID: <20200512114745.GN6112@intel.com> (raw)
In-Reply-To: <20200507144503.15506-3-stanislav.lisovskiy@intel.com>

On Thu, May 07, 2020 at 05:44:59PM +0300, Stanislav Lisovskiy wrote:
> Introduce platform dependent SAGV checking in
> combination with bandwidth state pipe SAGV mask.
> 
> This is preparation to adding TGL support, which
> requires different way of SAGV checking.
> 
> v2, v3, v4, v5, v6: Fix rebase conflict
> 
> v7: - Nuke icl specific function, use skl
>       for icl as well, gen specific active_pipes
>       check to be added in the next patch(Ville)
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8a86298962dc..3dc1ad66beb3 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3804,7 +3804,7 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
>  		intel_enable_sagv(dev_priv);
>  }
>  
> -static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> +static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -3865,7 +3865,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
>  {
>  	int ret;
>  	struct intel_crtc *crtc;
> -	struct intel_crtc_state *new_crtc_state;
> +	const struct intel_crtc_state *new_crtc_state;
>  	struct intel_bw_state *new_bw_state = NULL;
>  	const struct intel_bw_state *old_bw_state = NULL;
>  	int i;
> @@ -3878,7 +3878,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
>  
>  		old_bw_state = intel_atomic_get_old_bw_state(state);
>  
> -		if (intel_crtc_can_enable_sagv(new_crtc_state))
> +		if (skl_crtc_can_enable_sagv(new_crtc_state))

I'd leave this behing as a trivial wrapper 
intel_crtc_can_enable_sagv()
{
	return skl_crtc_cna_enable_sagv();
}

so we won't need that ugly 'can_sagv' boolean when introducing the tgl
counterpart. Otherwise lgtm.

>  			new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
>  		else
>  			new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> @@ -3889,6 +3889,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
>  
>  	new_bw_state->active_pipes =
>  		intel_calc_active_pipes(state, old_bw_state->active_pipes);
> +
>  	if (new_bw_state->active_pipes != old_bw_state->active_pipes) {
>  		ret = intel_atomic_lock_global_state(&new_bw_state->base);
>  		if (ret)
> -- 
> 2.24.1.485.gad05a3d8e5

-- 
Ville Syrjälä
Intel
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  reply	other threads:[~2020-05-12 11:47 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-07 14:44 [Intel-gfx] [PATCH v28 0/6] SAGV support for Gen12+ Stanislav Lisovskiy
2020-05-07 14:44 ` [Intel-gfx] [PATCH v28 1/6] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
2020-05-12 11:35   ` Ville Syrjälä
2020-05-07 14:44 ` [Intel-gfx] [PATCH v28 2/6] drm/i915: Extract skl SAGV checking Stanislav Lisovskiy
2020-05-12 11:47   ` Ville Syrjälä [this message]
2020-05-07 14:45 ` [Intel-gfx] [PATCH v28 3/6] drm/i915: Make active_pipes check skl specific Stanislav Lisovskiy
2020-05-12 11:39   ` Ville Syrjälä
2020-05-12 12:44     ` Lisovskiy, Stanislav
2020-05-12 13:03       ` Ville Syrjälä
2020-05-12 13:14       ` Ville Syrjälä
2020-05-12 13:26         ` Lisovskiy, Stanislav
2020-05-12 15:32           ` Ville Syrjälä
2020-05-12 20:36             ` Lisovskiy, Stanislav
2020-05-07 14:45 ` [Intel-gfx] [PATCH v28 4/6] drm/i915: Add TGL+ SAGV support Stanislav Lisovskiy
2020-05-12 12:03   ` Ville Syrjälä
2020-05-12 12:52     ` Lisovskiy, Stanislav
2020-05-12 13:10       ` Ville Syrjälä
2020-05-12 13:17         ` Lisovskiy, Stanislav
2020-05-12 13:38           ` Ville Syrjälä
2020-05-12 13:41             ` Lisovskiy, Stanislav
2020-05-12 13:50               ` Ville Syrjälä
2020-05-12 13:59                 ` Lisovskiy, Stanislav
2020-05-12 14:32                   ` Ville Syrjälä
2020-05-12 15:04                     ` Lisovskiy, Stanislav
2020-05-12 15:14                       ` Ville Syrjälä
2020-05-07 14:45 ` [Intel-gfx] [PATCH v28 5/6] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
2020-05-12 16:02   ` Ville Syrjälä
2020-05-07 14:45 ` [Intel-gfx] [PATCH v28 6/6] drm/i915: Enable SAGV support for Gen12 Stanislav Lisovskiy
2020-05-07 16:04 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for SAGV support for Gen12+ (rev36) Patchwork
2020-05-07 16:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-07 20:39 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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