[PATCH v9 11/18] clk: sifive: fu540-prci: release ethernet clock reset

From: Pragnesh Patel <pragnesh.patel@sifive.com>
To: u-boot@lists.denx.de
Subject: [PATCH v9 11/18] clk: sifive: fu540-prci: release ethernet clock reset
Date: Wed, 13 May 2020 11:56:08 +0530	[thread overview]
Message-ID: <20200513062617.19988-12-pragnesh.patel@sifive.com> (raw)
In-Reply-To: <20200513062617.19988-1-pragnesh.patel@sifive.com>

Release ethernet clock reset

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
---
 drivers/clk/sifive/fu540-prci.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index f26a370a64..45491a77d5 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -559,6 +559,25 @@ static void __prci_ddr_release_reset(struct __prci_data *pd)
 		asm volatile ("nop");
 }
 
+/**
+ * __prci_ethernet_release_reset() - Release ethernet reset
+ * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg
+ *
+ */
+static void __prci_ethernet_release_reset(struct __prci_data *pd)
+{
+	u32 v;
+
+	/* Release GEMGXL reset */
+	v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
+	v |= PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK;
+	__prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
+
+	/* Procmon => core clock */
+	__prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET,
+		      pd);
+}
+
 /*
  * PRCI integration data for each WRPLL instance
  */
@@ -579,6 +598,7 @@ static struct __prci_wrpll_data __prci_ddrpll_data = {
 static struct __prci_wrpll_data __prci_gemgxlpll_data = {
 	.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
 	.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
+	.release_reset = __prci_ethernet_release_reset,
 };
 
 /*
-- 
2.17.1
