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From: Pragnesh Patel <pragnesh.patel@sifive.com>
To: u-boot@lists.denx.de
Subject: [PATCH v9 11/18] clk: sifive: fu540-prci: release ethernet clock reset
Date: Wed, 13 May 2020 08:02:43 +0000	[thread overview]
Message-ID: <MWHPR13MB0944CFB53D6874B8A3443144E5BF0@MWHPR13MB0944.namprd13.prod.outlook.com> (raw)
In-Reply-To: <CAMty3ZC1v2F7QjOge9omEt5yg6JZVL2Au0CdAdsoRA0wcvb7-w@mail.gmail.com>

>-----Original Message-----
>From: Jagan Teki <jagan@amarulasolutions.com>
>Sent: 13 May 2020 13:30
>To: Pragnesh Patel <pragnesh.patel@sifive.com>
>Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra
><atish.patra@wdc.com>; Palmer Dabbelt <palmerdabbelt@google.com>; Bin
>Meng <bmeng.cn@gmail.com>; Paul Walmsley <paul.walmsley@sifive.com>;
>Anup Patel <anup.patel@wdc.com>; Sagar Kadam
><sagar.kadam@sifive.com>; Rick Chen <rick@andestech.com>; Lukasz
>Majewski <lukma@denx.de>; Anatolij Gustschin <agust@denx.de>; Simon
>Glass <sjg@chromium.org>
>Subject: Re: [PATCH v9 11/18] clk: sifive: fu540-prci: release ethernet clock
>reset
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>On Wed, May 13, 2020 at 12:48 PM Pragnesh Patel
><pragnesh.patel@sifive.com> wrote:
>>
>> Hi Jagan,
>>
>> >-----Original Message-----
>> >From: Jagan Teki <jagan@amarulasolutions.com>
>> >Sent: 13 May 2020 12:21
>> >To: Pragnesh Patel <pragnesh.patel@sifive.com>
>> >Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra
>> ><atish.patra@wdc.com>; Palmer Dabbelt <palmerdabbelt@google.com>;
>Bin
>> >Meng <bmeng.cn@gmail.com>; Paul Walmsley
><paul.walmsley@sifive.com>;
>> >Anup Patel <anup.patel@wdc.com>; Sagar Kadam
>> ><sagar.kadam@sifive.com>; Rick Chen <rick@andestech.com>; Lukasz
>> >Majewski <lukma@denx.de>; Anatolij Gustschin <agust@denx.de>; Simon
>> >Glass <sjg@chromium.org>
>> >Subject: Re: [PATCH v9 11/18] clk: sifive: fu540-prci: release
>> >ethernet clock reset
>> >
>> >[External Email] Do not click links or attachments unless you
>> >recognize the sender and know the content is safe
>> >
>> >On Wed, May 13, 2020 at 11:57 AM Pragnesh Patel
>> ><pragnesh.patel@sifive.com> wrote:
>> >>
>> >> Release ethernet clock reset
>> >
>> >Please add a detailed commit message of why the ethernet clock is
>> >resetting in SPL code since ethernet won't need for SPL at all?
>>
>> Once the ethernet clock has been initialized ( set_rate() and
>> clk_enable() ), we need to take ethernet clock out of reset.
>>
>> This patch is necessary in this series otherwise U-Boot cannot use
>> ethernet and not able To boot.
>>
>> This ethernet reset __prci_ethernet_release_reset() is not depend on SPL or
>U-Boot proper.
>> Right now, U-Boot proper is using ethernet so this gets called only
>> for U-Boot proper and if SPL wants to use ethernet then function helps to
>take clock out of reset.
>
>But will __prci_ethernet_release_reset is called in SPL?

Right now no but if SPL wants to use ethernet in future then this function gets called.

  reply	other threads:[~2020-05-13  8:02 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-13  6:25 [PATCH v9 00/18] RISC-V SiFive FU540 support SPL Pragnesh Patel
2020-05-13  6:25 ` [PATCH v9 01/18] misc: add driver for the SiFive otp controller Pragnesh Patel
2020-05-13  6:25 ` [PATCH v9 02/18] riscv: sifive: fu540: Use OTP DM driver for serial environment variable Pragnesh Patel
2020-05-13  6:26 ` [PATCH v9 03/18] riscv: Add _image_binary_end for SPL Pragnesh Patel
2020-05-13  6:26 ` [PATCH v9 04/18] lib: Makefile: build crc7.c when CONFIG_MMC_SPI Pragnesh Patel
2020-05-13  9:08   ` Heinrich Schuchardt
2020-05-17 12:02   ` Bin Meng
2020-05-17 14:27     ` Heinrich Schuchardt
2020-05-17 14:30       ` Bin Meng
2020-05-13  6:26 ` [PATCH v9 05/18] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files Pragnesh Patel
2020-05-13  6:26 ` [PATCH v9 06/18] sifive: fu540: add ddr driver Pragnesh Patel
2020-05-13  6:26 ` [PATCH v9 07/18] sifive: dts: fu540: Add DDR controller and phy register settings Pragnesh Patel
2020-05-13  6:26 ` [PATCH v9 08/18] riscv: sifive: dts: fu540: add U-Boot dmc node Pragnesh Patel
2020-05-13  6:26 ` [PATCH v9 09/18] clk: sifive: fu540-prci: Add clock enable and disable ops Pragnesh Patel
2020-05-13  6:26 ` [PATCH v9 10/18] clk: sifive: fu540-prci: Add ddr clock initialization Pragnesh Patel
2020-05-13  6:26 ` [PATCH v9 11/18] clk: sifive: fu540-prci: release ethernet clock reset Pragnesh Patel
2020-05-13  6:50   ` Jagan Teki
2020-05-13  7:18     ` Pragnesh Patel
2020-05-13  7:59       ` Jagan Teki
2020-05-13  8:02         ` Pragnesh Patel [this message]
2020-05-13  6:26 ` [PATCH v9 12/18] riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux Pragnesh Patel
2020-05-13  6:26 ` [PATCH v9 13/18] riscv: cpu: fu540: Add support for cpu fu540 Pragnesh Patel
2020-05-13  6:26 ` [PATCH v9 14/18] riscv: sifive: fu540: add SPL configuration Pragnesh Patel
2020-05-13  6:26 ` [PATCH v9 15/18] sifive: fu540: Add sample SD gpt partition layout Pragnesh Patel
2020-05-13  6:26 ` [PATCH v9 16/18] sifive: fu540: Add U-Boot proper sector start Pragnesh Patel
2020-05-13  6:26 ` [PATCH v9 17/18] configs: fu540: Add config options for U-Boot SPL Pragnesh Patel
2020-05-13  6:26 ` [PATCH v9 18/18] doc: sifive: fu540: Add description for OpenSBI generic platform Pragnesh Patel

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