From: Stefan Roese <sr@denx.de>
To: u-boot@lists.denx.de
Subject: [PATCH v2 12/12] mips: octeon: Add minimal Octeon 3 EBB7304 EVK support
Date: Thu, 14 May 2020 11:59:12 +0200 [thread overview]
Message-ID: <20200514095912.14428-13-sr@denx.de> (raw)
In-Reply-To: <20200514095912.14428-1-sr@denx.de>
This patch adds very basic minimal support for the Marvell Octeon 3
CN73xx based EBB7304 EVK. Please note that the basic Octeon port does
not support DDR3/4 initialization yet. To still use U-Boot on with this
port, the L2 cache (4MiB) is used as RAM. This way, U-Boot can boot
to the prompt on this board.
Supported devices:
- UART
- reset
- CFI parallel NOR flash
Signed-off-by: Stefan Roese <sr@denx.de>
---
Changes in v2:
- Removed CONFIG_SYS_MIPS_TIMER_FREQ
arch/mips/dts/Makefile | 1 +
arch/mips/dts/mrvl,octeon-ebb7304.dts | 96 ++++++++++++++++++++++++
arch/mips/mach-octeon/Kconfig | 14 ++++
board/Marvell/octeon_ebb7304/Kconfig | 19 +++++
board/Marvell/octeon_ebb7304/MAINTAINERS | 7 ++
board/Marvell/octeon_ebb7304/Makefile | 8 ++
board/Marvell/octeon_ebb7304/board.c | 12 +++
configs/octeon_ebb7304_defconfig | 34 +++++++++
include/configs/octeon_common.h | 25 ++++++
include/configs/octeon_ebb7304.h | 20 +++++
10 files changed, 236 insertions(+)
create mode 100644 arch/mips/dts/mrvl,octeon-ebb7304.dts
create mode 100644 board/Marvell/octeon_ebb7304/Kconfig
create mode 100644 board/Marvell/octeon_ebb7304/MAINTAINERS
create mode 100644 board/Marvell/octeon_ebb7304/Makefile
create mode 100644 board/Marvell/octeon_ebb7304/board.c
create mode 100644 configs/octeon_ebb7304_defconfig
create mode 100644 include/configs/octeon_common.h
create mode 100644 include/configs/octeon_ebb7304.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index f711e9fb59..dc85901dca 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -18,6 +18,7 @@ dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb
dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb
+dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += mrvl,octeon-ebb7304.dtb
dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f at st1704.dtb
diff --git a/arch/mips/dts/mrvl,octeon-ebb7304.dts b/arch/mips/dts/mrvl,octeon-ebb7304.dts
new file mode 100644
index 0000000000..4e9c2de7d4
--- /dev/null
+++ b/arch/mips/dts/mrvl,octeon-ebb7304.dts
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Marvell / Cavium Inc. EVB CN7300
+ */
+
+/dts-v1/;
+
+/include/ "mrvl,cn73xx.dtsi"
+
+/ {
+ model = "cavium,ebb7304";
+ compatible = "cavium,ebb7304";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&bootbus {
+ /*
+ * bootbus CS0 for CFI flash is remapped (0x1fc0.0000 -> 1f40.0000)
+ * as the initial size is too small for the 8MiB flash device
+ */
+ ranges = <0 0 0 0x1f400000 0xc00000>,
+ <1 0 0x10000 0x10000000 0>,
+ <2 0 0x10000 0x20000000 0>,
+ <3 0 0x10000 0x30000000 0>,
+ <4 0 0 0x1d020000 0x10000>,
+ <5 0 0x10000 0x50000000 0>,
+ <6 0 0x10000 0x60000000 0>,
+ <7 0 0x10000 0x70000000 0>;
+
+ cavium,cs-config at 0 {
+ compatible = "cavium,octeon-3860-bootbus-config";
+ cavium,cs-index = <0>;
+ cavium,t-adr = <10>;
+ cavium,t-ce = <50>;
+ cavium,t-oe = <50>;
+ cavium,t-we = <35>;
+ cavium,t-rd-hld = <25>;
+ cavium,t-wr-hld = <35>;
+ cavium,t-pause = <0>;
+ cavium,t-wait = <50>;
+ cavium,t-page = <30>;
+ cavium,t-rd-dly = <0>;
+ cavium,page-mode = <1>;
+ cavium,pages = <8>;
+ cavium,bus-width = <8>;
+ };
+
+ cavium,cs-config at 4 {
+ compatible = "cavium,octeon-3860-bootbus-config";
+ cavium,cs-index = <4>;
+ cavium,t-adr = <10>;
+ cavium,t-ce = <10>;
+ cavium,t-oe = <160>;
+ cavium,t-we = <100>;
+ cavium,t-rd-hld = <10>;
+ cavium,t-wr-hld = <0>;
+ cavium,t-pause = <50>;
+ cavium,t-wait = <50>;
+ cavium,t-page = <10>;
+ cavium,t-rd-dly = <10>;
+ cavium,pages = <0>;
+ cavium,bus-width = <8>;
+ };
+
+ flash0: nor at 0,0 {
+ compatible = "cfi-flash";
+ reg = <0 0 0x800000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition at 0 {
+ label = "bootloader";
+ reg = <0 0x340000>;
+ read-only;
+ };
+ partition at 300000 {
+ label = "storage";
+ reg = <0x340000 0x4be000>;
+ };
+ partition at 7fe000 {
+ label = "environment";
+ reg = <0x7fe000 0x2000>;
+ read-only;
+ };
+ };
+};
+
+&uart0 {
+ clock-frequency = <1200000000>;
+};
diff --git a/arch/mips/mach-octeon/Kconfig b/arch/mips/mach-octeon/Kconfig
index 9fd4c6cb0a..4fc89dc97e 100644
--- a/arch/mips/mach-octeon/Kconfig
+++ b/arch/mips/mach-octeon/Kconfig
@@ -31,6 +31,18 @@ config SOC_OCTEON3
endchoice
+choice
+ prompt "Octeon 3 board select"
+ default TARGET_OCTEON_EBB7304
+
+config TARGET_OCTEON_EBB7304
+ bool "Marvell Octeon EBB7304"
+ select OCTEON_CN73XX
+ help
+ Choose this for the Octeon EBB7304 board
+
+endchoice
+
config SYS_DCACHE_SIZE
default 32768
@@ -50,4 +62,6 @@ config MIPS_INIT_JUMP_OFFSET
This specifies the address where U-Boot starts exceution.
In this case its the flash base address of the bootbus.
+source "board/Marvell/octeon_ebb7304/Kconfig"
+
endmenu
diff --git a/board/Marvell/octeon_ebb7304/Kconfig b/board/Marvell/octeon_ebb7304/Kconfig
new file mode 100644
index 0000000000..ab54e6dbbc
--- /dev/null
+++ b/board/Marvell/octeon_ebb7304/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_OCTEON_EBB7304
+
+config SYS_BOARD
+ string
+ default "octeon_ebb7304"
+
+config SYS_VENDOR
+ string
+ default "Marvell"
+
+config SYS_CONFIG_NAME
+ string
+ default "octeon_ebb7304"
+
+config DEFAULT_DEVICE_TREE
+ string
+ default "mrvl,octeon-ebb7304"
+
+endif
diff --git a/board/Marvell/octeon_ebb7304/MAINTAINERS b/board/Marvell/octeon_ebb7304/MAINTAINERS
new file mode 100644
index 0000000000..f52beacbac
--- /dev/null
+++ b/board/Marvell/octeon_ebb7304/MAINTAINERS
@@ -0,0 +1,7 @@
+OCTEON_EBB7304 BOARD
+M: Aaron Williams <awilliams@marvell.com>
+S: Maintained
+F: board/Marvell/octeon_ebb7304
+F: configs/octeon_ebb7304_defconfig
+F: include/configs/octeon_ebb7304.h
+F: arch/mips/dts/mrvl,octeon-ebb7304.dts
diff --git a/board/Marvell/octeon_ebb7304/Makefile b/board/Marvell/octeon_ebb7304/Makefile
new file mode 100644
index 0000000000..8c6ffb9328
--- /dev/null
+++ b/board/Marvell/octeon_ebb7304/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2016 Stefan Roese <sr@denx.de>
+# Copyright (C) 2019 Marvell International Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := board.o
diff --git a/board/Marvell/octeon_ebb7304/board.c b/board/Marvell/octeon_ebb7304/board.c
new file mode 100644
index 0000000000..41ac18b952
--- /dev/null
+++ b/board/Marvell/octeon_ebb7304/board.c
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <dm.h>
+
+/*
+ * Nothing included right now. Code will be added in follow-up
+ * patches.
+ */
diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig
new file mode 100644
index 0000000000..e4f3526ff6
--- /dev/null
+++ b/configs/octeon_ebb7304_defconfig
@@ -0,0 +1,34 @@
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0xffffffff80000000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEBUG_UART_BASE=0x8001180000000800
+CONFIG_DEBUG_UART_CLOCK=1200000000
+CONFIG_ARCH_OCTEON=y
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_ADDR=0x1FBFE000
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_DEBUG_UART_SHIFT=3
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_OCTEON=y
+CONFIG_HEXDUMP=y
diff --git a/include/configs/octeon_common.h b/include/configs/octeon_common.h
new file mode 100644
index 0000000000..5d1e74cb76
--- /dev/null
+++ b/include/configs/octeon_common.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019-2020
+ * Marvell <www.marvell.com>
+ */
+
+#ifndef __OCTEON_COMMON_H__
+#define __OCTEON_COMMON_H__
+
+/* No DDR init yet -> run in L2 cache with limited resources */
+#define CONFIG_SYS_MALLOC_LEN (256 << 10)
+#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (1 << 20))
+
+/*
+ * Set a max image size for the image (incl. DTB), so that a growing
+ * image will not exceed this maximum size
+ */
+#define CONFIG_BOARD_SIZE_LIMIT 0x100000 /* 1MiB */
+
+#define CONFIG_SYS_INIT_SP_OFFSET 0x180000
+
+#endif /* __OCTEON_COMMON_H__ */
diff --git a/include/configs/octeon_ebb7304.h b/include/configs/octeon_ebb7304.h
new file mode 100644
index 0000000000..04fe4dfe22
--- /dev/null
+++ b/include/configs/octeon_ebb7304.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019-2020
+ * Marvell <www.marvell.com>
+ */
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+#include "octeon_common.h"
+
+/*
+ * CFI flash
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
+
+#endif /* __CONFIG_H__ */
--
2.26.2
next prev parent reply other threads:[~2020-05-14 9:59 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-14 9:59 [PATCH v2 00/12] mips: Add initial Octeon MIPS64 base support Stefan Roese
2020-05-14 9:59 ` [PATCH v2 01/12] mips: start.S: Add CONFIG_MIPS_INIT_JUMP_OFFSET Stefan Roese
2020-05-14 9:59 ` [PATCH v2 02/12] mips: start.S: Don't call mips_cache_reset() on ARCH_OCTEON Stefan Roese
2020-05-14 9:59 ` [PATCH v2 03/12] mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM Stefan Roese
2020-06-05 15:29 ` Daniel Schwierzeck
2020-05-14 9:59 ` [PATCH v2 04/12] mips: cache: Make flush_cache() weak to enable overwrite Stefan Roese
2020-06-05 15:29 ` Daniel Schwierzeck
2020-05-14 9:59 ` [PATCH v2 05/12] mips: time: Only compile the weak get_tbclk() when needed Stefan Roese
2020-06-05 15:29 ` Daniel Schwierzeck
2020-05-14 9:59 ` [PATCH v2 06/12] mips: traps: Set WG bit in EBase register on Octeon Stefan Roese
2020-06-05 15:30 ` Daniel Schwierzeck
2020-05-14 9:59 ` [PATCH v2 07/12] mips: mipsregs.h: Add more register macros for Octeon port Stefan Roese
2020-05-14 9:59 ` [PATCH v2 08/12] mips: mipsregs.h: Sync with linux v5.7.0-rc3 version Stefan Roese
2020-05-14 9:59 ` [PATCH v2 09/12] sysreset: Add Octeon sysreset driver Stefan Roese
2020-05-14 9:59 ` [PATCH v2 10/12] mips: octeon: Initial minimal support for the Marvell Octeon SoC Stefan Roese
2020-06-16 17:42 ` Daniel Schwierzeck
2020-06-19 8:08 ` Stefan Roese
2020-05-14 9:59 ` [PATCH v2 11/12] mips: octeon: dts: Add Octeon 3 cn73xx base dtsi file Stefan Roese
2020-05-14 9:59 ` Stefan Roese [this message]
2020-06-16 17:35 ` [PATCH v2 12/12] mips: octeon: Add minimal Octeon 3 EBB7304 EVK support Daniel Schwierzeck
2020-06-19 8:06 ` Stefan Roese
2020-05-26 12:23 ` [PATCH v2 00/12] mips: Add initial Octeon MIPS64 base support Stefan Roese
2020-06-02 10:59 ` Stefan Roese
2020-06-05 15:40 ` Daniel Schwierzeck
2020-06-06 5:25 ` Stefan Roese
2020-06-15 7:49 ` Stefan Roese
2020-06-16 17:27 ` Daniel Schwierzeck
2020-06-19 7:51 ` Stefan Roese
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