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From: Christoph Hellwig <hch@lst.de>
To: Andrew Morton <akpm@linux-foundation.org>,
	Arnd Bergmann <arnd@arndb.de>,
	Roman Zippel <zippel@linux-m68k.org>
Cc: Jessica Yu <jeyu@kernel.org>, Michal Simek <monstr@monstr.eu>,
	x86@kernel.org, linux-alpha@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-c6x-dev@linux-c6x.org, linux-hexagon@vger.kernel.org,
	linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org,
	linux-mips@vger.kernel.org, openrisc@lists.librecores.org,
	linuxppc-dev@lists.ozlabs.org, linux-riscv@lists.infradead.org,
	linux-sh@vger.kernel.org, sparclinux@vger.kernel.org,
	linux-arch@vger.kernel.org, linux-mm@kvack.org,
	linux-um@lists.infradead.org, linux-xtensa@linux-xtensa.org,
	linux-fsdevel@vger.kernel.org
Subject: [PATCH 11/29] hexagon: use asm-generic/cacheflush.h
Date: Fri, 15 May 2020 14:36:28 +0000	[thread overview]
Message-ID: <20200515143646.3857579-12-hch@lst.de> (raw)
In-Reply-To: <20200515143646.3857579-1-hch@lst.de>

Hexagon needs almost no cache flushing routines of its own.  Rely on
asm-generic/cacheflush.h for the defaults.

Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 arch/hexagon/include/asm/cacheflush.h | 19 +++++--------------
 1 file changed, 5 insertions(+), 14 deletions(-)

diff --git a/arch/hexagon/include/asm/cacheflush.h b/arch/hexagon/include/asm/cacheflush.h
index fb447de45d54c..6eff0730e6efd 100644
--- a/arch/hexagon/include/asm/cacheflush.h
+++ b/arch/hexagon/include/asm/cacheflush.h
@@ -25,29 +25,17 @@
 #define LINESIZE	32
 #define LINEBITS	5
 
-#define flush_cache_all()			do { } while (0)
-#define flush_cache_mm(mm)			do { } while (0)
-#define flush_cache_dup_mm(mm)			do { } while (0)
-#define flush_cache_range(vma, start, end)	do { } while (0)
-#define flush_cache_page(vma, vmaddr, pfn)	do { } while (0)
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-#define flush_dcache_page(page)			do { } while (0)
-#define flush_dcache_mmap_lock(mapping)		do { } while (0)
-#define flush_dcache_mmap_unlock(mapping)	do { } while (0)
-#define flush_icache_page(vma, pg)		do { } while (0)
-#define flush_icache_user_range(vma, pg, adr, len)	do { } while (0)
-#define flush_cache_vmap(start, end)		do { } while (0)
-#define flush_cache_vunmap(start, end)		do { } while (0)
-
 /*
  * Flush Dcache range through current map.
  */
 extern void flush_dcache_range(unsigned long start, unsigned long end);
+#define flush_dcache_range flush_dcache_range
 
 /*
  * Flush Icache range through current map.
  */
 extern void flush_icache_range(unsigned long start, unsigned long end);
+#define flush_icache_range flush_icache_range
 
 /*
  * Memory-management related flushes are there to ensure in non-physically
@@ -78,6 +66,7 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
 
 void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
 		       unsigned long vaddr, void *dst, void *src, int len);
+#define copy_to_user_page copy_to_user_page
 
 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
 	memcpy(dst, src, len)
@@ -85,4 +74,6 @@ void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
 extern void hexagon_inv_dcache_range(unsigned long start, unsigned long end);
 extern void hexagon_clean_dcache_range(unsigned long start, unsigned long end);
 
+#include <asm-generic/cacheflush.h>
+
 #endif
-- 
2.26.2

WARNING: multiple messages have this Message-ID
From: Christoph Hellwig <hch@lst.de>
To: Andrew Morton <akpm@linux-foundation.org>,
	Arnd Bergmann <arnd@arndb.de>,
	Roman Zippel <zippel@linux-m68k.org>
Cc: Jessica Yu <jeyu@kernel.org>, Michal Simek <monstr@monstr.eu>,
	x86@kernel.org, linux-alpha@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-c6x-dev@linux-c6x.org, linux-hexagon@vger.kernel.org,
	linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org,
	linux-mips@vger.kernel.org, openrisc@lists.librecores.org,
	linuxppc-dev@lists.ozlabs.org, linux-riscv@lists.infradead.org,
	linux-sh@vger.kernel.org, sparclinux@vger.kernel.org,
	linux-arch@vger.kernel.org, linux-mm@kvack.org,
	linux-um@lists.infradead.org, linux-xtensa@linux-xtensa.org,
	linux-fsdevel@vger.kernel.org
Subject: [PATCH 11/29] hexagon: use asm-generic/cacheflush.h
Date: Fri, 15 May 2020 16:36:28 +0200	[thread overview]
Message-ID: <20200515143646.3857579-12-hch@lst.de> (raw)
In-Reply-To: <20200515143646.3857579-1-hch@lst.de>

Hexagon needs almost no cache flushing routines of its own.  Rely on
asm-generic/cacheflush.h for the defaults.

Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 arch/hexagon/include/asm/cacheflush.h | 19 +++++--------------
 1 file changed, 5 insertions(+), 14 deletions(-)

diff --git a/arch/hexagon/include/asm/cacheflush.h b/arch/hexagon/include/asm/cacheflush.h
index fb447de45d54c..6eff0730e6efd 100644
--- a/arch/hexagon/include/asm/cacheflush.h
+++ b/arch/hexagon/include/asm/cacheflush.h
@@ -25,29 +25,17 @@
 #define LINESIZE	32
 #define LINEBITS	5
 
-#define flush_cache_all()			do { } while (0)
-#define flush_cache_mm(mm)			do { } while (0)
-#define flush_cache_dup_mm(mm)			do { } while (0)
-#define flush_cache_range(vma, start, end)	do { } while (0)
-#define flush_cache_page(vma, vmaddr, pfn)	do { } while (0)
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-#define flush_dcache_page(page)			do { } while (0)
-#define flush_dcache_mmap_lock(mapping)		do { } while (0)
-#define flush_dcache_mmap_unlock(mapping)	do { } while (0)
-#define flush_icache_page(vma, pg)		do { } while (0)
-#define flush_icache_user_range(vma, pg, adr, len)	do { } while (0)
-#define flush_cache_vmap(start, end)		do { } while (0)
-#define flush_cache_vunmap(start, end)		do { } while (0)
-
 /*
  * Flush Dcache range through current map.
  */
 extern void flush_dcache_range(unsigned long start, unsigned long end);
+#define flush_dcache_range flush_dcache_range
 
 /*
  * Flush Icache range through current map.
  */
 extern void flush_icache_range(unsigned long start, unsigned long end);
+#define flush_icache_range flush_icache_range
 
 /*
  * Memory-management related flushes are there to ensure in non-physically
@@ -78,6 +66,7 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
 
 void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
 		       unsigned long vaddr, void *dst, void *src, int len);
+#define copy_to_user_page copy_to_user_page
 
 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
 	memcpy(dst, src, len)
@@ -85,4 +74,6 @@ void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
 extern void hexagon_inv_dcache_range(unsigned long start, unsigned long end);
 extern void hexagon_clean_dcache_range(unsigned long start, unsigned long end);
 
+#include <asm-generic/cacheflush.h>
+
 #endif
-- 
2.26.2


WARNING: multiple messages have this Message-ID
From: Christoph Hellwig <hch@lst.de>
To: Andrew Morton <akpm@linux-foundation.org>,
	Arnd Bergmann <arnd@arndb.de>,
	Roman Zippel <zippel@linux-m68k.org>
Cc: linux-arch@vger.kernel.org, linux-xtensa@linux-xtensa.org,
	Michal Simek <monstr@monstr.eu>, Jessica Yu <jeyu@kernel.org>,
	linux-ia64@vger.kernel.org, linux-c6x-dev@linux-c6x.org,
	linux-sh@vger.kernel.org, linux-hexagon@vger.kernel.org,
	x86@kernel.org, linux-um@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org,
	linux-mm@kvack.org, linux-m68k@lists.linux-m68k.org,
	openrisc@lists.librecores.org, linux-alpha@vger.kernel.org,
	sparclinux@vger.kernel.org, linux-fsdevel@vger.kernel.org,
	linux-riscv@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 11/29] hexagon: use asm-generic/cacheflush.h
Date: Fri, 15 May 2020 16:36:28 +0200	[thread overview]
Message-ID: <20200515143646.3857579-12-hch@lst.de> (raw)
In-Reply-To: <20200515143646.3857579-1-hch@lst.de>

Hexagon needs almost no cache flushing routines of its own.  Rely on
asm-generic/cacheflush.h for the defaults.

Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 arch/hexagon/include/asm/cacheflush.h | 19 +++++--------------
 1 file changed, 5 insertions(+), 14 deletions(-)

diff --git a/arch/hexagon/include/asm/cacheflush.h b/arch/hexagon/include/asm/cacheflush.h
index fb447de45d54c..6eff0730e6efd 100644
--- a/arch/hexagon/include/asm/cacheflush.h
+++ b/arch/hexagon/include/asm/cacheflush.h
@@ -25,29 +25,17 @@
 #define LINESIZE	32
 #define LINEBITS	5
 
-#define flush_cache_all()			do { } while (0)
-#define flush_cache_mm(mm)			do { } while (0)
-#define flush_cache_dup_mm(mm)			do { } while (0)
-#define flush_cache_range(vma, start, end)	do { } while (0)
-#define flush_cache_page(vma, vmaddr, pfn)	do { } while (0)
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-#define flush_dcache_page(page)			do { } while (0)
-#define flush_dcache_mmap_lock(mapping)		do { } while (0)
-#define flush_dcache_mmap_unlock(mapping)	do { } while (0)
-#define flush_icache_page(vma, pg)		do { } while (0)
-#define flush_icache_user_range(vma, pg, adr, len)	do { } while (0)
-#define flush_cache_vmap(start, end)		do { } while (0)
-#define flush_cache_vunmap(start, end)		do { } while (0)
-
 /*
  * Flush Dcache range through current map.
  */
 extern void flush_dcache_range(unsigned long start, unsigned long end);
+#define flush_dcache_range flush_dcache_range
 
 /*
  * Flush Icache range through current map.
  */
 extern void flush_icache_range(unsigned long start, unsigned long end);
+#define flush_icache_range flush_icache_range
 
 /*
  * Memory-management related flushes are there to ensure in non-physically
@@ -78,6 +66,7 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
 
 void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
 		       unsigned long vaddr, void *dst, void *src, int len);
+#define copy_to_user_page copy_to_user_page
 
 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
 	memcpy(dst, src, len)
@@ -85,4 +74,6 @@ void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
 extern void hexagon_inv_dcache_range(unsigned long start, unsigned long end);
 extern void hexagon_clean_dcache_range(unsigned long start, unsigned long end);
 
+#include <asm-generic/cacheflush.h>
+
 #endif
-- 
2.26.2



WARNING: multiple messages have this Message-ID
From: Christoph Hellwig <hch@lst.de>
To: Andrew Morton <akpm@linux-foundation.org>,
	Arnd Bergmann <arnd@arndb.de>,
	Roman Zippel <zippel@linux-m68k.org>
Cc: linux-arch@vger.kernel.org, linux-xtensa@linux-xtensa.org,
	Michal Simek <monstr@monstr.eu>, Jessica Yu <jeyu@kernel.org>,
	linux-ia64@vger.kernel.org, linux-c6x-dev@linux-c6x.org,
	linux-sh@vger.kernel.org, linux-hexagon@vger.kernel.org,
	x86@kernel.org, linux-um@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org,
	linux-mm@kvack.org, linux-m68k@lists.linux-m68k.org,
	openrisc@lists.librecores.org, linux-alpha@vger.kernel.org,
	sparclinux@vger.kernel.org, linux-fsdevel@vger.kernel.org,
	linux-riscv@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 11/29] hexagon: use asm-generic/cacheflush.h
Date: Fri, 15 May 2020 16:36:28 +0200	[thread overview]
Message-ID: <20200515143646.3857579-12-hch@lst.de> (raw)
In-Reply-To: <20200515143646.3857579-1-hch@lst.de>

Hexagon needs almost no cache flushing routines of its own.  Rely on
asm-generic/cacheflush.h for the defaults.

Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 arch/hexagon/include/asm/cacheflush.h | 19 +++++--------------
 1 file changed, 5 insertions(+), 14 deletions(-)

diff --git a/arch/hexagon/include/asm/cacheflush.h b/arch/hexagon/include/asm/cacheflush.h
index fb447de45d54c..6eff0730e6efd 100644
--- a/arch/hexagon/include/asm/cacheflush.h
+++ b/arch/hexagon/include/asm/cacheflush.h
@@ -25,29 +25,17 @@
 #define LINESIZE	32
 #define LINEBITS	5
 
-#define flush_cache_all()			do { } while (0)
-#define flush_cache_mm(mm)			do { } while (0)
-#define flush_cache_dup_mm(mm)			do { } while (0)
-#define flush_cache_range(vma, start, end)	do { } while (0)
-#define flush_cache_page(vma, vmaddr, pfn)	do { } while (0)
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-#define flush_dcache_page(page)			do { } while (0)
-#define flush_dcache_mmap_lock(mapping)		do { } while (0)
-#define flush_dcache_mmap_unlock(mapping)	do { } while (0)
-#define flush_icache_page(vma, pg)		do { } while (0)
-#define flush_icache_user_range(vma, pg, adr, len)	do { } while (0)
-#define flush_cache_vmap(start, end)		do { } while (0)
-#define flush_cache_vunmap(start, end)		do { } while (0)
-
 /*
  * Flush Dcache range through current map.
  */
 extern void flush_dcache_range(unsigned long start, unsigned long end);
+#define flush_dcache_range flush_dcache_range
 
 /*
  * Flush Icache range through current map.
  */
 extern void flush_icache_range(unsigned long start, unsigned long end);
+#define flush_icache_range flush_icache_range
 
 /*
  * Memory-management related flushes are there to ensure in non-physically
@@ -78,6 +66,7 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
 
 void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
 		       unsigned long vaddr, void *dst, void *src, int len);
+#define copy_to_user_page copy_to_user_page
 
 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
 	memcpy(dst, src, len)
@@ -85,4 +74,6 @@ void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
 extern void hexagon_inv_dcache_range(unsigned long start, unsigned long end);
 extern void hexagon_clean_dcache_range(unsigned long start, unsigned long end);
 
+#include <asm-generic/cacheflush.h>
+
 #endif
-- 
2.26.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID
From: Christoph Hellwig <hch@lst.de>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] [PATCH 11/29] hexagon: use asm-generic/cacheflush.h
Date: Fri, 15 May 2020 16:36:28 +0200	[thread overview]
Message-ID: <20200515143646.3857579-12-hch@lst.de> (raw)
In-Reply-To: <20200515143646.3857579-1-hch@lst.de>

Hexagon needs almost no cache flushing routines of its own.  Rely on
asm-generic/cacheflush.h for the defaults.

Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 arch/hexagon/include/asm/cacheflush.h | 19 +++++--------------
 1 file changed, 5 insertions(+), 14 deletions(-)

diff --git a/arch/hexagon/include/asm/cacheflush.h b/arch/hexagon/include/asm/cacheflush.h
index fb447de45d54c..6eff0730e6efd 100644
--- a/arch/hexagon/include/asm/cacheflush.h
+++ b/arch/hexagon/include/asm/cacheflush.h
@@ -25,29 +25,17 @@
 #define LINESIZE	32
 #define LINEBITS	5
 
-#define flush_cache_all()			do { } while (0)
-#define flush_cache_mm(mm)			do { } while (0)
-#define flush_cache_dup_mm(mm)			do { } while (0)
-#define flush_cache_range(vma, start, end)	do { } while (0)
-#define flush_cache_page(vma, vmaddr, pfn)	do { } while (0)
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-#define flush_dcache_page(page)			do { } while (0)
-#define flush_dcache_mmap_lock(mapping)		do { } while (0)
-#define flush_dcache_mmap_unlock(mapping)	do { } while (0)
-#define flush_icache_page(vma, pg)		do { } while (0)
-#define flush_icache_user_range(vma, pg, adr, len)	do { } while (0)
-#define flush_cache_vmap(start, end)		do { } while (0)
-#define flush_cache_vunmap(start, end)		do { } while (0)
-
 /*
  * Flush Dcache range through current map.
  */
 extern void flush_dcache_range(unsigned long start, unsigned long end);
+#define flush_dcache_range flush_dcache_range
 
 /*
  * Flush Icache range through current map.
  */
 extern void flush_icache_range(unsigned long start, unsigned long end);
+#define flush_icache_range flush_icache_range
 
 /*
  * Memory-management related flushes are there to ensure in non-physically
@@ -78,6 +66,7 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
 
 void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
 		       unsigned long vaddr, void *dst, void *src, int len);
+#define copy_to_user_page copy_to_user_page
 
 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
 	memcpy(dst, src, len)
@@ -85,4 +74,6 @@ void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
 extern void hexagon_inv_dcache_range(unsigned long start, unsigned long end);
 extern void hexagon_clean_dcache_range(unsigned long start, unsigned long end);
 
+#include <asm-generic/cacheflush.h>
+
 #endif
-- 
2.26.2


  parent reply	other threads:[~2020-05-15 14:36 UTC|newest]

Thread overview: 200+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-15 14:36 sort out the flush_icache_range mess v2 Christoph Hellwig
2020-05-15 14:36 ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36 ` Christoph Hellwig
2020-05-15 14:36 ` Christoph Hellwig
2020-05-15 14:36 ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 01/29] arm: fix the flush_icache_range arguments in set_fiq_handler Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 02/29] nds32: unexport flush_icache_page Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 03/29] powerpc: unexport flush_icache_user_range Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 04/29] unicore32: remove flush_cache_user_range Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 05/29] asm-generic: fix the inclusion guards for cacheflush.h Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 06/29] asm-generic: don't include <linux/mm.h> in cacheflush.h Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-27  4:34   ` [PATCH] media: omap3isp: Shuffle cacheflush.h and include mm.h Nathan Chancellor
2020-05-27  4:34     ` [OpenRISC] " Nathan Chancellor
2020-05-27  4:34     ` Nathan Chancellor
2020-05-27  4:34     ` Nathan Chancellor
2020-05-27  4:34     ` Nathan Chancellor
2020-05-27  5:10     ` Christoph Hellwig
2020-05-27  5:10       ` [OpenRISC] " Christoph Hellwig
2020-05-27  5:10       ` Christoph Hellwig
2020-05-27  5:10       ` Christoph Hellwig
2020-05-27  5:10       ` Christoph Hellwig
2020-05-27  7:02     ` Geert Uytterhoeven
2020-05-27  7:02       ` [OpenRISC] " Geert Uytterhoeven
2020-05-27  7:02       ` Geert Uytterhoeven
2020-05-27  7:02       ` Geert Uytterhoeven
2020-05-27  7:02       ` Geert Uytterhoeven
2020-05-27  7:02       ` Geert Uytterhoeven
2020-05-27  7:02       ` Geert Uytterhoeven
2020-05-27  7:02       ` Geert Uytterhoeven
2020-05-27  8:13       ` Nathan Chancellor
2020-05-27  8:13         ` [OpenRISC] " Nathan Chancellor
2020-05-27  8:13         ` Nathan Chancellor
2020-05-27  8:13         ` Nathan Chancellor
2020-05-27  8:13         ` Nathan Chancellor
2020-05-27  8:13         ` Nathan Chancellor
2020-05-27  8:13         ` Nathan Chancellor
2020-05-27 13:45         ` Laurent Pinchart
2020-05-27 13:45           ` [OpenRISC] " Laurent Pinchart
2020-05-27 13:45           ` Laurent Pinchart
2020-05-27 13:45           ` Laurent Pinchart
2020-05-27 13:45           ` Laurent Pinchart
2020-05-27 13:45           ` Laurent Pinchart
2020-05-27 13:45           ` Laurent Pinchart
2020-05-15 14:36 ` [PATCH 07/29] asm-generic: improve the flush_dcache_page stub Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 08/29] alpha: use asm-generic/cacheflush.h Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 09/29] arm64: " Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-22 15:54   ` Catalin Marinas
2020-05-22 15:54     ` [OpenRISC] " Catalin Marinas
2020-05-22 15:54     ` Catalin Marinas
2020-05-22 15:54     ` Catalin Marinas
2020-05-22 15:54     ` Catalin Marinas
2020-05-15 14:36 ` [PATCH 10/29] c6x: " Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-18 18:20   ` Mark Salter
2020-05-18 18:20     ` [OpenRISC] " Mark Salter
2020-05-18 18:20     ` Mark Salter
2020-05-18 18:20     ` Mark Salter
2020-05-18 18:20     ` Mark Salter
2020-05-18 18:20     ` Mark Salter
2020-05-15 14:36 ` Christoph Hellwig [this message]
2020-05-15 14:36   ` [OpenRISC] [PATCH 11/29] hexagon: " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 12/29] ia64: " Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 13/29] microblaze: " Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 14/29] m68knommu: " Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 15/29] openrisc: " Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 16/29] powerpc: " Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 17/29] riscv: " Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 18/29] arm,sparc,unicore32: remove flush_icache_user_range Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] [PATCH 18/29] arm, sparc, unicore32: " Christoph Hellwig
2020-05-15 14:36   ` [PATCH 18/29] arm,sparc,unicore32: " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 19/29] mm: rename flush_icache_user_range to flush_icache_user_page Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 20/29] asm-generic: add a flush_icache_user_range stub Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 21/29] sh: implement flush_icache_user_range Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 22/29] xtensa: " Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 23/29] arm: rename flush_cache_user_range to flush_icache_user_range Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 24/29] m68k: implement flush_icache_user_range Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 25/29] exec: only build read_code when needed Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 26/29] exec: use flush_icache_user_range in read_code Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 27/29] binfmt_flat: use flush_icache_user_range Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 28/29] nommu: use flush_icache_user_range in brk and mmap Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36 ` [PATCH 29/29] module: move the set_fs hack for flush_icache_range to m68k Christoph Hellwig
2020-05-15 14:36   ` [OpenRISC] " Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-15 14:36   ` Christoph Hellwig
2020-05-18 13:04   ` Jessica Yu
2020-05-18 13:04     ` [OpenRISC] " Jessica Yu
2020-05-18 13:04     ` Jessica Yu
2020-05-18 13:04     ` Jessica Yu
2020-05-18 13:04     ` Jessica Yu

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