[igt-dev] [PATCH i-g-t v3 0/7] Make gpgpu fill tests libdrm independent

[igt-dev] [PATCH i-g-t v3 0/7] Make gpgpu fill tests libdrm independent

[Zbigniew Kempczyński]

I've introduced intel_bb which is very simplified version of libdrm
powered intel_batchbuffer. Currently it supports simple relocation
but it is enough to cover all gpgpu fill needs. Other (fenced) 
relocation will be added when I will have to face with such pipelines /
batchbuffers.

As commands created in gpu_cmds.c are coupled more than I thought on 
the beginning (media fill also use them) "_v2" suffix was introduced.
When all tests will be rewritten to "_v2" old functions can be removed
and "_v2" can be deleted.

v2: changes according to the review:
    - make intel_bb api more consistent and universal
    - add intel_bb api documentation
    - add alignment field in buf_ops buffer initalization for linear
      buffers
v3: changes:
    - add all gens pipelines
    - fix compiling issues on non-x86 archs
    - add ctx (suggested by knr)

Zbigniew Kempczyński (7):
  lib/intel_bufops: Add bufops reference and relaxate stride requirement
  lib/rendercopy_bufmgr: Pass alignment during buffer initialization
  lib/intel_batchbuffer: Introduce intel_bb
  lib/gpu_cmds: Add gpgpu pipeline functions based on intel_bb
  lib/gpgpu_fill: libdrm-free gpgpu pipeline creation
  lib/intel_batchbuffer: Introduce temporary igt_fillfunc_v2_t
  tests/gem_gpgpu_fill: Remove libdrm dependency

 lib/gpgpu_fill.c            | 181 ++++++++++++
 lib/gpgpu_fill.h            |  34 +++
 lib/gpu_cmds.c              | 559 ++++++++++++++++++++++++++++++++++++
 lib/gpu_cmds.h              |  54 ++++
 lib/intel_batchbuffer.c     | 412 ++++++++++++++++++++++++++
 lib/intel_batchbuffer.h     |  97 +++++++
 lib/intel_bufops.c          |  41 ++-
 lib/intel_bufops.h          |   7 +-
 lib/rendercopy_bufmgr.c     |   4 +-
 tests/i915/gem_gpgpu_fill.c | 126 ++++++--
 10 files changed, 1474 insertions(+), 41 deletions(-)

-- 
2.26.0

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[igt-dev] [PATCH i-g-t v3 1/7] lib/intel_bufops: Add bufops reference and relaxate stride requirement

[Zbigniew Kempczyński]

Add bufops reference to intel_buf to allow acquire drm fd against which
buffer was created.

Relax stride limitation for intel_buf for non-tiled buffers.

v2: add alignment and ensure it is dword sized for linear buffers

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/intel_bufops.c | 41 +++++++++++++++++++++++++++++++----------
 lib/intel_bufops.h |  7 +++++--
 2 files changed, 36 insertions(+), 12 deletions(-)

diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
index 804b2a0a..ef36c9cc 100644
--- a/lib/intel_bufops.c
+++ b/lib/intel_bufops.c
@@ -52,7 +52,7 @@
  * struct intel_buf ibuf;
  * ...
  * bops = buf_ops_create(fd);
- * intel_buf_init(bops, &ibuf, 512, 512, 32, I915_TILING_X, false);
+ * intel_buf_init(bops, &ibuf, 512, 512, 32, 64, I915_TILING_X, false);
  * ...
  * linear_to_intel_buf(bops, &ibuf, linear);
  * ...
@@ -673,7 +673,7 @@ void linear_to_intel_buf(struct buf_ops *bops, struct intel_buf *buf,
 static void __intel_buf_init(struct buf_ops *bops,
 			     uint32_t handle,
 			     struct intel_buf *buf,
-			     int width, int height, int bpp,
+			     int width, int height, int bpp, int alignment,
 			     uint32_t req_tiling, uint32_t compression)
 {
 	uint32_t tiling = req_tiling;
@@ -683,9 +683,12 @@ static void __intel_buf_init(struct buf_ops *bops,
 	igt_assert(buf);
 	igt_assert(width > 0 && height > 0);
 	igt_assert(bpp == 8 || bpp == 16 || bpp == 32);
+	igt_assert(alignment % 4 == 0);
 
 	memset(buf, 0, sizeof(*buf));
 
+	buf->bops = bops;
+
 	if (compression) {
 		int aux_width, aux_height;
 
@@ -721,7 +724,10 @@ static void __intel_buf_init(struct buf_ops *bops,
 		size = buf->aux.offset + aux_width * aux_height;
 
 	} else {
-		buf->stride = ALIGN(width * (bpp / 8), 128);
+		if (buf->tiling)
+			buf->stride = ALIGN(width * (bpp / 8), 128);
+		else
+			buf->stride = ALIGN(width * (bpp / 8), alignment ?: 4);
 		buf->size = buf->stride * height;
 		buf->tiling = tiling;
 		buf->bpp = bpp;
@@ -744,6 +750,7 @@ static void __intel_buf_init(struct buf_ops *bops,
  * @width: surface width
  * @height: surface height
  * @bpp: bits-per-pixel (8 / 16 / 32)
+ * @alignment: alignment of the stride for linear surfaces
  * @tiling: surface tiling
  * @compression: surface compression type
  *
@@ -754,11 +761,11 @@ static void __intel_buf_init(struct buf_ops *bops,
  */
 void intel_buf_init(struct buf_ops *bops,
 		    struct intel_buf *buf,
-		    int width, int height, int bpp,
+		    int width, int height, int bpp, int alignment,
 		    uint32_t tiling, uint32_t compression)
 {
-	__intel_buf_init(bops, 0, buf, width, height, bpp, tiling,
-			 compression);
+	__intel_buf_init(bops, 0, buf, width, height, bpp, alignment,
+			 tiling, compression);
 }
 
 /**
@@ -784,6 +791,7 @@ void intel_buf_close(struct buf_ops *bops, struct intel_buf *buf)
  * @width: surface width
  * @height: surface height
  * @bpp: bits-per-pixel (8 / 16 / 32)
+ * @alignment: alignment of the stride for linear surfaces
  * @tiling: surface tiling
  * @compression: surface compression type
  *
@@ -797,11 +805,11 @@ void intel_buf_close(struct buf_ops *bops, struct intel_buf *buf)
 void intel_buf_init_using_handle(struct buf_ops *bops,
 				 uint32_t handle,
 				 struct intel_buf *buf,
-				 int width, int height, int bpp,
+				 int width, int height, int bpp, int alignment,
 				 uint32_t req_tiling, uint32_t compression)
 {
-	__intel_buf_init(bops, handle, buf, width, height, bpp, req_tiling,
-			 compression);
+	__intel_buf_init(bops, handle, buf, width, height, bpp, alignment,
+			 req_tiling, compression);
 }
 
 #define DEFAULT_BUFOPS(__gen_start, __gen_end) \
@@ -908,7 +916,7 @@ static void idempotency_selftest(struct buf_ops *bops, uint32_t tiling)
 			  bool_str(software_tiling),
 			  bool_str(!software_tiling),
 			  tiling_str(tiling));
-		intel_buf_init(bops, &buf, width, height, bpp, tiling, false);
+		intel_buf_init(bops, &buf, width, height, bpp, 0, tiling, false);
 		buf_ops_set_software_tiling(bops, tiling, software_tiling);
 
 		linear_to_intel_buf(bops, &buf, (uint32_t *) linear_in);
@@ -1038,6 +1046,19 @@ void buf_ops_destroy(struct buf_ops *bops)
 	free(bops);
 }
 
+/**
+ * buf_ops_getfd
+ * @bops: pointer to buf_ops
+ *
+ * Returns: drm fd
+ */
+int buf_ops_getfd(struct buf_ops *bops)
+{
+	igt_assert(bops);
+
+	return bops->fd;
+}
+
 /**
  * buf_ops_set_software_tiling
  * @bops: pointer to buf_ops
diff --git a/lib/intel_bufops.h b/lib/intel_bufops.h
index f3d6aed8..3a4fae4e 100644
--- a/lib/intel_bufops.h
+++ b/lib/intel_bufops.h
@@ -2,10 +2,12 @@
 #define __INTEL_BUFOPS_H__
 
 #include <stdint.h>
+#include "igt_aux.h"
 
 struct buf_ops;
 
 struct intel_buf {
+	struct buf_ops *bops;
 	uint32_t handle;
 	uint32_t stride;
 	uint32_t tiling;
@@ -58,6 +60,7 @@ intel_buf_aux_height(int gen, const struct intel_buf *buf)
 
 struct buf_ops *buf_ops_create(int fd);
 void buf_ops_destroy(struct buf_ops *bops);
+int buf_ops_getfd(struct buf_ops *bops);
 
 bool buf_ops_set_software_tiling(struct buf_ops *bops,
 				 uint32_t tiling,
@@ -73,14 +76,14 @@ bool buf_ops_has_hw_fence(struct buf_ops *bops, uint32_t tiling);
 bool buf_ops_has_tiling_support(struct buf_ops *bops, uint32_t tiling);
 
 void intel_buf_init(struct buf_ops *bops, struct intel_buf *buf,
-		    int width, int height, int bpp,
+		    int width, int height, int bpp, int alignment,
 		    uint32_t tiling, uint32_t compression);
 void intel_buf_close(struct buf_ops *bops, struct intel_buf *buf);
 
 void intel_buf_init_using_handle(struct buf_ops *bops,
 				 uint32_t handle,
 				 struct intel_buf *buf,
-				 int width, int height, int bpp,
+				 int width, int height, int bpp, int alignment,
 				 uint32_t req_tiling, uint32_t compression);
 
 #endif
-- 
2.26.0

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Re: [igt-dev] [PATCH i-g-t v3 1/7] lib/intel_bufops: Add bufops reference and relaxate stride requirement

[Chris Wilson]

Quoting Zbigniew Kempczyński (2020-05-18 10:09:13)
> @@ -721,7 +724,10 @@ static void __intel_buf_init(struct buf_ops *bops,
>                 size = buf->aux.offset + aux_width * aux_height;
>  
>         } else {
> -               buf->stride = ALIGN(width * (bpp / 8), 128);
> +               if (buf->tiling)
> +                       buf->stride = ALIGN(width * (bpp / 8), 128);

128 is for y-tiling, 512 for x-tiling; and of course older gen varies.

if (tiling) {
	if (gen < 3)
		tile_width = 128;
	else if (IS_ALV || IS_GDG || tiling == X)
		tile_width = 512;
	else
		tile_width = 128;
}

So if you need a work anywhere value, 512.
-Chris
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[igt-dev] [PATCH i-g-t v3 2/7] lib/rendercopy_bufmgr: Pass alignment during buffer initialization

[Zbigniew Kempczyński]

For linear buffer buf_ops currently was extended to align the stride
so we need to update the call.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/rendercopy_bufmgr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/rendercopy_bufmgr.c b/lib/rendercopy_bufmgr.c
index 96603229..dc38d530 100644
--- a/lib/rendercopy_bufmgr.c
+++ b/lib/rendercopy_bufmgr.c
@@ -163,8 +163,8 @@ void igt_buf_init(struct rendercopy_bufmgr *bmgr, struct igt_buf *buf,
 	intel_buf_init_using_handle(bmgr->bops,
 				    buf->bo->handle,
 				    &ibuf,
-				    width, height, bpp, tiling,
-				    compression);
+				    width, height, bpp, 0,
+				    tiling, compression);
 
 	buf->ccs[0].offset = ibuf.aux.offset;
 	buf->ccs[0].stride = ibuf.aux.stride;
-- 
2.26.0

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[igt-dev] [PATCH i-g-t v3 3/7] lib/intel_batchbuffer: Introduce intel_bb

[Zbigniew Kempczyński]

Simple batchbuffer facility which gathers and outputs relocations.

v2: make bb api more consistent and universal
v3: fix compiling issues on non-x86 arch

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/intel_batchbuffer.c | 385 ++++++++++++++++++++++++++++++++++++++++
 lib/intel_batchbuffer.h |  89 ++++++++++
 2 files changed, 474 insertions(+)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index f1a45b47..580feabb 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -41,6 +41,7 @@
 #include "rendercopy.h"
 #include "media_fill.h"
 #include "ioctl_wrappers.h"
+#include "i915/gem_mman.h"
 #include "media_spin.h"
 #include "gpgpu_fill.h"
 #include "igt_aux.h"
@@ -1171,3 +1172,387 @@ igt_media_spinfunc_t igt_get_media_spinfunc(int devid)
 
 	return spin;
 }
+
+/* Intel batchbuffer v2 */
+
+/*
+ * __intel_bb_create:
+ * @i915: drm fd
+ * @size: size of the batchbuffer
+ *
+ * Returns:
+ *
+ * Pointer the intel_bb, asserts on failure.
+ */
+struct intel_bb *intel_bb_create(int i915, uint32_t size)
+{
+	struct intel_bb *ibb = calloc(1, sizeof(*ibb));
+
+	igt_assert(ibb);
+
+	ibb->i915 = i915;
+	ibb->devid = intel_get_drm_devid(i915);
+	ibb->gen = intel_gen(ibb->devid);
+	ibb->handle = gem_create(i915, size);
+	ibb->size = size;
+	ibb->batch = calloc(1, size);
+	igt_assert(ibb->batch);
+	ibb->ptr = ibb->batch;
+	ibb->objects = NULL;
+
+	return ibb;
+}
+
+/**
+ * intel_bb_destroy:
+ * @ibb: pointer to intel_bb
+ *
+ * Frees all relocations / objects allocated during filling the batch.
+ */
+void intel_bb_destroy(struct intel_bb *ibb)
+{
+	uint32_t i;
+	void *ptr;
+
+	igt_assert(ibb);
+
+	/* Free relocations */
+	for (i = 0; i < ibb->num_objects; i++) {
+		ptr = from_user_pointer(ibb->objects[i].relocs_ptr);
+		if (ptr)
+			free(ptr);
+	}
+
+	free(ibb->objects);
+
+	munmap(ibb->batch, ibb->size);
+	gem_close(ibb->i915, ibb->handle);
+
+	free(ibb);
+}
+
+/**
+ * intel_bb_set_debug:
+ * @ibb: pointer to intel_bb
+ * @debug: true / false
+ *
+ * Sets debug to true / false. Execbuf is then called synchronously and
+ * object/reloc arrays are printed after execution.
+ */
+void intel_bb_set_debug(struct intel_bb *ibb, bool debug)
+{
+	ibb->debug = debug;
+}
+
+/*
+ * intel_bb_add_handle:
+ * @ibb: pointer to intel_bb
+ * @handle: which handle to add to objects array
+ * @offset: presumed offset of the object when I915_EXEC_NO_RELOC flag is
+ * used in execbuf call
+ *
+ * Function allocates additional execobj slot in object array for a handle.
+ * For batchbuffer only presumed address is saved.
+ */
+static void intel_bb_add_handle(struct intel_bb *ibb,
+				uint32_t handle,
+				uint64_t offset)
+{
+	uint32_t i;
+
+	/* Skip bb as object, it will be added before exec */
+	if (ibb->handle == handle) {
+		igt_assert(ibb->batch_offset == 0 ||
+			   ibb->batch_offset == offset);
+		ibb->batch_offset = offset;
+		return;
+	}
+
+	for (i = 0; i < ibb->num_objects; i++)
+		if (ibb->objects[i].handle == handle)
+			return;
+
+	i = ibb->num_objects++;
+	ibb->objects = realloc(ibb->objects,
+			       sizeof(*ibb->objects) * (i + 1));
+	igt_assert(ibb->objects);
+
+	memset(&ibb->objects[i], 0, sizeof(*ibb->objects));
+	ibb->objects[i].handle = handle;
+	ibb->objects[i].offset = offset;
+}
+
+/*
+ * intel_bb_add_reloc:
+ * @ibb: pointer to intel_bb
+ * @handle: object handle which address will be taken to patch the bb
+ * @read_domains: gem domain bits for the relocation
+ * @write_domain: gem domain bit for the relocation
+ * @delta: delta value to add to @buffer's gpu address
+ * @offset: offset within bb to be patched
+ * @presumed_offset: address of the object in address space, important for
+ * I915_EXEC_NO_RELOC flag
+ *
+ * Function allocates additional relocation slot in reloc array for a handle.
+ */
+static void intel_bb_add_reloc(struct intel_bb *ibb,
+			       uint32_t handle,
+			       uint32_t read_domains,
+			       uint32_t write_domain,
+			       uint64_t delta,
+			       uint64_t offset,
+			       uint64_t presumed_offset)
+{
+	struct drm_i915_gem_relocation_entry *relocs;
+	uint32_t i;
+
+	intel_bb_add_handle(ibb, handle, presumed_offset);
+
+	relocs = ibb->relocs;
+	if (ibb->num_relocs == ibb->allocated_relocs) {
+		ibb->allocated_relocs += 4096 / sizeof(*relocs);
+		relocs = realloc(relocs, sizeof(*relocs) * ibb->allocated_relocs);
+		igt_assert(relocs);
+		ibb->relocs = relocs;
+	}
+
+	i = ibb->num_relocs++;
+	memset(&relocs[i], 0, sizeof(*relocs));
+	relocs[i].target_handle = handle;
+	relocs[i].read_domains = read_domains;
+	relocs[i].write_domain = write_domain;
+	relocs[i].delta = delta;
+	relocs[i].offset = offset;
+	relocs[i].presumed_offset = presumed_offset;
+
+	igt_debug("add reloc: handle: %u, r/w: 0x%x/0x%x, "
+		  "delta: 0x%" PRIx64 ", "
+		  "offset: 0x%" PRIx64 ", "
+		  "poffset: 0x%" PRIx64 "\n",
+		  handle, read_domains, write_domain,
+		  delta, offset, presumed_offset);
+}
+
+/**
+ * intel_bb_emit_reloc:
+ * @ibb: pointer to intel_bb
+ * @handle: object handle which address will be taken to patch the bb
+ * @read_domains: gem domain bits for the relocation
+ * @write_domain: gem domain bit for the relocation
+ * @delta: delta value to add to @buffer's gpu address
+ * @presumed_offset: address of the object in address space, important for
+ * I915_EXEC_NO_RELOC flag
+ *
+ * Function prepares relocation (execobj if required + reloc) and emits
+ * offset in bb. For I915_EXEC_NO_RELOC presumed_offset is a hint we already
+ * have object in valid place and relocation step can be skipped in this case.
+ *
+ * Note: delta is value added to address, mostly used when some instructions
+ * require modify-bit set to apply change. Which delta is valid depends
+ * on instruction (see instruction specification).
+ */
+void intel_bb_emit_reloc(struct intel_bb *ibb,
+			 uint32_t handle,
+			 uint32_t read_domains,
+			 uint32_t write_domain,
+			 uint64_t delta,
+			 uint64_t presumed_offset)
+{
+	igt_assert(ibb);
+
+	intel_bb_add_reloc(ibb, handle, read_domains, write_domain,
+			   delta, intel_bb_offset(ibb), presumed_offset);
+
+	intel_bb_out(ibb, delta + presumed_offset);
+	if (ibb->gen >= 8)
+		intel_bb_out(ibb, presumed_offset >> 32);
+}
+
+/**
+ * intel_bb_offset_reloc:
+ * @ibb: pointer to intel_bb
+ * @handle: object handle which address will be taken to patch the bb
+ * @read_domains: gem domain bits for the relocation
+ * @write_domain: gem domain bit for the relocation
+ * @offset: offset within bb to be patched
+ * @presumed_offset: address of the object in address space, important for
+ * I915_EXEC_NO_RELOC flag
+ *
+ * Function prepares relocation (execobj if required + reloc). It it used
+ * for editing batchbuffer via modifying structures. It means when we're
+ * preparing batchbuffer it is more descriptive to edit the structure
+ * than emitting dwords. But it require for some fields to point the
+ * relocation. For that case @offset is passed by the user and it points
+ * to the offset in bb where the relocation will be applied.
+ */
+void intel_bb_offset_reloc(struct intel_bb *ibb,
+			   uint32_t handle,
+			   uint32_t read_domains,
+			   uint32_t write_domain,
+			   uint32_t offset,
+			   uint64_t presumed_offset)
+{
+	igt_assert(ibb);
+
+	intel_bb_add_reloc(ibb, handle, read_domains, write_domain,
+			   0, offset, presumed_offset);
+}
+
+static void intel_bb_dump_execbuf(struct drm_i915_gem_execbuffer2 *execbuf)
+{
+	struct drm_i915_gem_exec_object2 *objects;
+	struct drm_i915_gem_relocation_entry *relocs, *reloc;
+	int i, j;
+
+	igt_info("execbuf batch len: %u, start offset: 0x%x, "
+		 "DR1: 0x%x, DR4: 0x%x, "
+		 "num clip: %u, clipptr: 0x%llx, "
+		 "flags: 0x%llx, rsvd1: 0x%llx, rsvd2: 0x%llx\n",
+		 execbuf->batch_len, execbuf->batch_start_offset,
+		 execbuf->DR1, execbuf->DR4,
+		 execbuf->num_cliprects, execbuf->cliprects_ptr,
+		 execbuf->flags, execbuf->rsvd1, execbuf->rsvd2);
+
+	igt_info("execbuf buffer_count: %d\n", execbuf->buffer_count);
+	for (i = 0; i < execbuf->buffer_count; i++) {
+		objects = &((struct drm_i915_gem_exec_object2 *)
+			    from_user_pointer(execbuf->buffers_ptr))[i];
+		relocs = from_user_pointer(objects->relocs_ptr);
+		igt_info(" [%d] <handle: %u, reloc_count: %d, reloc_ptr: %p, "
+			 "align: 0x%llx, offset: 0x%llx, flags: 0x%llx, "
+			 "rsvd1: 0x%llx, rsvd2: 0x%llx\n",
+			 i, objects->handle, objects->relocation_count,
+			 relocs,
+			 objects->alignment,
+			 objects->offset, objects->flags,
+			 objects->rsvd1, objects->rsvd2);
+		if (objects->relocation_count) {
+			igt_info("execbuf relocs:\n");
+			for (j = 0; j < objects->relocation_count; j++) {
+				reloc = &relocs[j];
+				igt_info(" [%d] <target handle: %u, "
+					 "offset: 0x%llx, delta: 0x%x, "
+					 "presumed_offset: 0x%llx, "
+					 "read_domains: 0x%x, "
+					 "write_domain: 0x%x\n",
+					 j, reloc->target_handle,
+					 reloc->offset, reloc->delta,
+					 reloc->presumed_offset,
+					 reloc->read_domains,
+					 reloc->write_domain);
+			}
+		}
+	}
+}
+
+/*
+ * @__intel_bb_exec:
+ * @ibb: pointer to intel_bb
+ * @end_offset: offset of the last instruction in the bb
+ * @flags: flags passed directly to execbuf
+ * @ctx: context
+ * @sync: if true wait for execbuf completion, otherwise caller is responsible
+ * to wait for completion
+ *
+ * Returns: 0 on success, otherwise errno.
+ *
+ * Note: In this step execobj for bb is allocated and inserted to the objects
+ * array.
+*/
+int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
+		    uint32_t ctx, uint64_t flags, bool sync)
+{
+	struct drm_i915_gem_execbuffer2 execbuf;
+	uint32_t i;
+	int ret;
+
+	i = ibb->num_objects;
+
+	if (i == 0 || ibb->objects[i - 1].handle != ibb->handle) {
+		ibb->objects = realloc(ibb->objects, sizeof(*ibb->objects) * (i + 1));
+		igt_assert(ibb->objects);
+
+		gem_write(ibb->i915, ibb->handle, 0, ibb->batch, ibb->size);
+
+		memset(&ibb->objects[i], 0, sizeof(*ibb->objects));
+		ibb->objects[i].relocs_ptr = to_user_pointer(ibb->relocs);
+		ibb->objects[i].relocation_count = ibb->num_relocs;
+		ibb->objects[i].handle = ibb->handle;
+		ibb->objects[i].offset = ibb->batch_offset;
+		ibb->num_objects++;
+	}
+
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffers_ptr = (uintptr_t) ibb->objects;
+	execbuf.buffer_count = ibb->num_objects;
+	execbuf.batch_len = end_offset;
+	execbuf.rsvd1 = ctx;
+	execbuf.flags = flags;
+
+	ret = __gem_execbuf(ibb->i915, &execbuf);
+	if (ret)
+		return ret;
+
+	if (sync || ibb->debug)
+		gem_sync(ibb->i915, ibb->handle);
+
+	if (ibb->debug)
+		intel_bb_dump_execbuf(&execbuf);
+
+	return 0;
+}
+
+/**
+ * intel_bb_exec:
+ * @ibb: pointer to intel_bb
+ * @end_offset: offset of the last instruction in the bb
+ * @flags: flags passed directly to execbuf
+ * @sync: if true wait for execbuf completion, otherwise caller is responsible
+ * to wait for completion
+ *
+ * Do execbuf with default context. Asserts on failure.
+*/
+void intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
+		   uint64_t flags, bool sync)
+{
+	igt_assert_eq(__intel_bb_exec(ibb, end_offset, 0, flags, sync), 0);
+}
+
+/*
+ * intel_bb_exec_with_context:
+ * @ibb: pointer to intel_bb
+ * @end_offset: offset of the last instruction in the bb
+ * @flags: flags passed directly to execbuf
+ * @ctx: context
+ * @sync: if true wait for execbuf completion, otherwise caller is responsible
+ * to wait for completion
+ *
+ * Do execbuf with context @context.
+*/
+void intel_bb_exec_with_context(struct intel_bb *ibb, uint32_t end_offset,
+				uint32_t ctx, uint64_t flags, bool sync)
+{
+	igt_assert_eq(__intel_bb_exec(ibb, end_offset, ctx, flags, sync), 0);
+}
+
+/**
+ * intel_bb_get_presumed_address:
+ * @ibb: pointer to intel_bb
+ * @handle: object handle
+ *
+ * When objects addresses are previously pinned and we don't want to relocate
+ * we need to acquire them from previous execbuf. Function checks previous
+ * relocation entry for @handle and returns presumed_offset field.
+ */
+uint64_t intel_bb_get_presumed_offset(struct intel_bb *ibb, uint32_t handle)
+{
+	uint32_t i;
+
+	igt_assert(ibb);
+
+	for (i = 0; i < ibb->num_relocs; i++)
+		if (ibb->relocs[i].target_handle == handle)
+			return ibb->relocs[i].presumed_offset;
+
+	return 0;
+}
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 442f3a18..5f3bd974 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -7,6 +7,7 @@
 
 #include "igt_core.h"
 #include "intel_reg.h"
+#include "drmtest.h"
 
 #define BATCH_SZ 4096
 #define BATCH_RESERVED 16
@@ -422,4 +423,92 @@ typedef void (*igt_media_spinfunc_t)(struct intel_batchbuffer *batch,
 
 igt_media_spinfunc_t igt_get_media_spinfunc(int devid);
 
+
+/*
+ * Batchbuffer without libdrm dependency
+ */
+struct intel_bb {
+	int i915;
+	int gen;
+	bool debug;
+	uint32_t devid;
+	uint32_t handle;
+	uint32_t size;
+	uint32_t *batch;
+	uint32_t *ptr;
+
+	struct drm_i915_gem_exec_object2 *objects;
+	uint32_t num_objects;
+	uint64_t batch_offset;
+
+	struct drm_i915_gem_relocation_entry *relocs;
+	uint32_t num_relocs;
+	uint32_t allocated_relocs;
+};
+
+struct intel_bb *intel_bb_create(int i915, uint32_t size);
+
+void intel_bb_destroy(struct intel_bb *ibb);
+void intel_bb_set_debug(struct intel_bb *ibb, bool debug);
+
+inline uint32_t intel_bb_offset(struct intel_bb *ibb)
+{
+	return (uint32_t) ((uint8_t *) ibb->ptr - (uint8_t *) ibb->batch);
+}
+
+inline void intel_bb_ptr_set(struct intel_bb *ibb, uint32_t offset)
+{
+	ibb->ptr = (void *) ((uint8_t *) ibb->batch + offset);
+
+	igt_assert(intel_bb_offset(ibb) < ibb->size);
+}
+
+inline void intel_bb_ptr_add(struct intel_bb *ibb, uint32_t offset)
+{
+	intel_bb_ptr_set(ibb, intel_bb_offset(ibb) + offset);
+}
+
+inline void intel_bb_ptr_align(struct intel_bb *ibb, uint32_t alignment)
+{
+	intel_bb_ptr_set(ibb, ALIGN(intel_bb_offset(ibb), alignment));
+}
+
+inline void *intel_bb_ptr(struct intel_bb *ibb)
+{
+	return (void *) ibb->ptr;
+}
+
+inline void intel_bb_out(struct intel_bb *ibb, uint32_t dword)
+{
+	*ibb->ptr = dword;
+	ibb->ptr++;
+
+	igt_assert(intel_bb_offset(ibb) < ibb->size);
+}
+
+void intel_bb_emit_reloc(struct intel_bb *ibb,
+			 uint32_t handle,
+			 uint32_t read_domains,
+			 uint32_t write_domain,
+			 uint64_t delta,
+			 uint64_t presumed_offset);
+
+void intel_bb_offset_reloc(struct intel_bb *ibb,
+			   uint32_t handle,
+			   uint32_t read_domains,
+			   uint32_t write_domain,
+			   uint32_t offset,
+			   uint64_t presumed_offset);
+
+int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
+		    uint32_t ctx, uint64_t flags, bool sync);
+
+void intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
+		   uint64_t flags, bool sync);
+
+void intel_bb_exec_with_context(struct intel_bb *ibb, uint32_t end_offset,
+				uint32_t ctx, uint64_t flags, bool sync);
+
+uint64_t intel_bb_get_presumed_offset(struct intel_bb *ibb, uint32_t handle);
+
 #endif
-- 
2.26.0

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Re: [igt-dev] [PATCH i-g-t v3 3/7] lib/intel_batchbuffer: Introduce intel_bb

[Chris Wilson]

Quoting Zbigniew Kempczyński (2020-05-18 10:09:15)
> +       /* Free relocations */
> +       for (i = 0; i < ibb->num_objects; i++) {
> +               ptr = from_user_pointer(ibb->objects[i].relocs_ptr);
> +               if (ptr)
> +                       free(ptr);

free(NULL) is safe.
-Chris
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Re: [igt-dev] [PATCH i-g-t v3 3/7] lib/intel_batchbuffer: Introduce intel_bb

[Chris Wilson]

Quoting Zbigniew Kempczyński (2020-05-18 10:09:15)
> +/*
> + * intel_bb_add_handle:
> + * @ibb: pointer to intel_bb
> + * @handle: which handle to add to objects array
> + * @offset: presumed offset of the object when I915_EXEC_NO_RELOC flag is
> + * used in execbuf call
> + *
> + * Function allocates additional execobj slot in object array for a handle.
> + * For batchbuffer only presumed address is saved.
> + */
> +static void intel_bb_add_handle(struct intel_bb *ibb,
> +                               uint32_t handle,
> +                               uint64_t offset)

If you get into the CCS directory management (which we will for
rendercopy), we will need to take note of EXEC_OBJECT_PINNED. And you
may as well pass the EXEC_OBJECT_WRITE flag at this time. In short, you
might as well start off by passing flags.
-Chris
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Re: [igt-dev] [PATCH i-g-t v3 3/7] lib/intel_batchbuffer: Introduce intel_bb

[Chris Wilson]

Quoting Zbigniew Kempczyński (2020-05-18 10:09:15)
> +uint64_t intel_bb_get_presumed_offset(struct intel_bb *ibb, uint32_t handle)
> +{
> +       uint32_t i;
> +
> +       igt_assert(ibb);
> +
> +       for (i = 0; i < ibb->num_relocs; i++)
> +               if (ibb->relocs[i].target_handle == handle)
> +                       return ibb->relocs[i].presumed_offset;

The canonical source is execobj[].offset. The kernel always updates the
returned execobj[] with the correct information, but the reloc[] array
may be told a lie to force a relocation on the next pass.

The rule is address in batch matches that of reloc[].presumed_offset
that matches execobj[].offset. The latter being the linchpin.
-Chris
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Re: [igt-dev] [PATCH i-g-t v3 3/7] lib/intel_batchbuffer: Introduce intel_bb

[Chris Wilson]

Quoting Zbigniew Kempczyński (2020-05-18 10:09:15)
> +static void intel_bb_add_handle(struct intel_bb *ibb,
> +                               uint32_t handle,
> +                               uint64_t offset)
> +{
> +       uint32_t i;
> +
> +       /* Skip bb as object, it will be added before exec */

So what we tend to end up doing is just adding the batch whenever it
makes sense then swapping it at the end. You could insist upon having
I915_EXEC_BATCH_FIRST so that you can put into the execobj[] at creation
time, but doing a swap() at submit is easy as well.

> +       if (ibb->handle == handle) {
> +               igt_assert(ibb->batch_offset == 0 ||
> +                          ibb->batch_offset == offset);
> +               ibb->batch_offset = offset;
> +               return;
> +       }
> +
> +       for (i = 0; i < ibb->num_objects; i++)
> +               if (ibb->objects[i].handle == handle)
> +                       return;

Really tempted to say insertion sort and bsearch. I wonder if we have
enough objects for that to be worthwhile. Brb, off to try that idea out
in iris....
-Chris
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[igt-dev] [PATCH i-g-t v3 4/7] lib/gpu_cmds: Add gpgpu pipeline functions based on intel_bb

[Zbigniew Kempczyński]

Add no-libdrm functions which will replace libdrm version in the
final version.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/gpu_cmds.c | 559 +++++++++++++++++++++++++++++++++++++++++++++++++
 lib/gpu_cmds.h |  54 +++++
 2 files changed, 613 insertions(+)

diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index dc0ae96c..db1a5f70 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -768,3 +768,562 @@ gen9_emit_state_base_address(struct intel_batchbuffer *batch)
 	OUT_BATCH(0);
 	OUT_BATCH(0xfffff000);
 }
+
+/*
+ * Here we start version of the gpgpu fill pipeline creation which is based
+ * on intel_bb.
+ */
+uint32_t
+gen7_fill_curbe_buffer_data_v2(struct intel_bb *ibb, uint8_t color)
+{
+	uint32_t *curbe_buffer;
+	uint32_t offset;
+
+	intel_bb_ptr_align(ibb, 64);
+	curbe_buffer = intel_bb_ptr(ibb);
+	offset = intel_bb_offset(ibb);
+
+	*curbe_buffer = color;
+	intel_bb_ptr_add(ibb, 32);
+
+	return offset;
+}
+
+static uint32_t
+gen7_fill_kernel_v2(struct intel_bb *ibb,
+		    const uint32_t kernel[][4],
+		    size_t size)
+{
+	uint32_t *kernel_dst;
+	uint32_t offset;
+
+	intel_bb_ptr_align(ibb, 64);
+	kernel_dst = intel_bb_ptr(ibb);
+	offset = intel_bb_offset(ibb);
+
+	memcpy(kernel_dst, kernel, size);
+
+	intel_bb_ptr_add(ibb, size);
+
+	return offset;
+}
+
+static uint32_t
+gen7_fill_surface_state_v2(struct intel_bb *ibb,
+			   struct intel_buf *buf,
+			   uint32_t format,
+			   int is_dst)
+{
+	struct gen7_surface_state *ss;
+	uint32_t write_domain, read_domain, offset;
+
+	if (is_dst) {
+		write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
+	} else {
+		write_domain = 0;
+		read_domain = I915_GEM_DOMAIN_SAMPLER;
+	}
+
+	intel_bb_ptr_align(ibb, 64);
+	offset = intel_bb_offset(ibb);
+	ss = intel_bb_ptr(ibb);
+	intel_bb_ptr_add(ibb, 64);
+
+	ss->ss0.surface_type = SURFACE_2D;
+	ss->ss0.surface_format = format;
+	ss->ss0.render_cache_read_write = 1;
+
+	if (buf->tiling == I915_TILING_X)
+		ss->ss0.tiled_mode = 2;
+	else if (buf->tiling == I915_TILING_Y)
+		ss->ss0.tiled_mode = 3;
+
+	ss->ss1.base_addr = 0;
+
+	intel_bb_offset_reloc(ibb, buf->handle,
+			      read_domain, write_domain,
+			      offset + 4, 0x0);
+
+	ss->ss2.height = intel_buf_height(buf) - 1;
+	ss->ss2.width  = intel_buf_width(buf) - 1;
+	ss->ss3.pitch  = buf->stride - 1;
+
+	ss->ss7.shader_chanel_select_r = 4;
+	ss->ss7.shader_chanel_select_g = 5;
+	ss->ss7.shader_chanel_select_b = 6;
+	ss->ss7.shader_chanel_select_a = 7;
+
+	return offset;
+}
+
+static uint32_t
+gen8_fill_surface_state_v2(struct intel_bb *ibb,
+			   struct intel_buf *buf,
+			   uint32_t format,
+			   int is_dst)
+{
+	struct gen8_surface_state *ss;
+	uint32_t write_domain, read_domain, offset;
+
+	if (is_dst) {
+		write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
+	} else {
+		write_domain = 0;
+		read_domain = I915_GEM_DOMAIN_SAMPLER;
+	}
+
+	intel_bb_ptr_align(ibb, 64);
+	offset = intel_bb_offset(ibb);
+	ss = intel_bb_ptr(ibb);
+	intel_bb_ptr_add(ibb, 64);
+
+	ss->ss0.surface_type = SURFACE_2D;
+	ss->ss0.surface_format = format;
+	ss->ss0.render_cache_read_write = 1;
+	ss->ss0.vertical_alignment = 1; /* align 4 */
+	ss->ss0.horizontal_alignment = 1; /* align 4 */
+
+	if (buf->tiling == I915_TILING_X)
+		ss->ss0.tiled_mode = 2;
+	else if (buf->tiling == I915_TILING_Y)
+		ss->ss0.tiled_mode = 3;
+
+	ss->ss8.base_addr = 0;
+
+	intel_bb_offset_reloc(ibb, buf->handle,
+			      read_domain, write_domain,
+			      offset + 4, 0x0);
+
+	ss->ss2.height = intel_buf_height(buf) - 1;
+	ss->ss2.width  = intel_buf_width(buf) - 1;
+	ss->ss3.pitch  = buf->stride - 1;
+
+	ss->ss7.shader_chanel_select_r = 4;
+	ss->ss7.shader_chanel_select_g = 5;
+	ss->ss7.shader_chanel_select_b = 6;
+	ss->ss7.shader_chanel_select_a = 7;
+
+	return offset;
+}
+
+static uint32_t
+gen7_fill_binding_table_v2(struct intel_bb *ibb,
+			   struct intel_buf *buf)
+{
+	uint32_t binding_table_offset;
+	uint32_t *binding_table;
+	uint32_t devid = intel_get_drm_devid(ibb->i915);
+
+	intel_bb_ptr_align(ibb, 64);
+	binding_table_offset = intel_bb_offset(ibb);
+	binding_table = intel_bb_ptr(ibb);
+	intel_bb_ptr_add(ibb, 64);
+
+	if (IS_GEN7(devid))
+		binding_table[0] = gen7_fill_surface_state_v2(ibb, buf,
+							      SURFACEFORMAT_R8_UNORM, 1);
+
+	else
+		binding_table[0] = gen8_fill_surface_state_v2(ibb, buf,
+							      SURFACEFORMAT_R8_UNORM, 1);
+
+	return binding_table_offset;
+}
+
+uint32_t
+gen7_fill_interface_descriptor_v2(struct intel_bb *ibb,
+				  struct intel_buf *buf,
+				  const uint32_t kernel[][4],
+				  size_t size)
+{
+	struct gen7_interface_descriptor_data *idd;
+	uint32_t offset;
+	uint32_t binding_table_offset, kernel_offset;
+
+	binding_table_offset = gen7_fill_binding_table_v2(ibb, buf);
+	kernel_offset = gen7_fill_kernel_v2(ibb, kernel, size);
+
+	intel_bb_ptr_align(ibb, 64);
+	idd = intel_bb_ptr(ibb);
+	offset = intel_bb_offset(ibb);
+
+	idd->desc0.kernel_start_pointer = (kernel_offset >> 6);
+
+	idd->desc1.single_program_flow = 1;
+	idd->desc1.floating_point_mode = GEN7_FLOATING_POINT_IEEE_754;
+
+	idd->desc2.sampler_count = 0;      /* 0 samplers used */
+	idd->desc2.sampler_state_pointer = 0;
+
+	idd->desc3.binding_table_entry_count = 0;
+	idd->desc3.binding_table_pointer = (binding_table_offset >> 5);
+
+	idd->desc4.constant_urb_entry_read_offset = 0;
+	idd->desc4.constant_urb_entry_read_length = 1; /* grf 1 */
+
+	intel_bb_ptr_add(ibb, sizeof(*idd));
+
+	return offset;
+}
+
+uint32_t
+gen8_fill_interface_descriptor_v2(struct intel_bb *ibb,
+				  struct intel_buf *buf,
+				  const uint32_t kernel[][4],
+				  size_t size)
+{
+	struct gen8_interface_descriptor_data *idd;
+	uint32_t offset;
+	uint32_t binding_table_offset, kernel_offset;
+
+	binding_table_offset = gen7_fill_binding_table_v2(ibb, buf);
+	kernel_offset = gen7_fill_kernel_v2(ibb, kernel, size);
+
+	intel_bb_ptr_align(ibb, 64);
+	idd = intel_bb_ptr(ibb);
+	offset = intel_bb_offset(ibb);
+
+	idd->desc0.kernel_start_pointer = (kernel_offset >> 6);
+
+	idd->desc2.single_program_flow = 1;
+	idd->desc2.floating_point_mode = GEN8_FLOATING_POINT_IEEE_754;
+
+	idd->desc3.sampler_count = 0;      /* 0 samplers used */
+	idd->desc3.sampler_state_pointer = 0;
+
+	idd->desc4.binding_table_entry_count = 0;
+	idd->desc4.binding_table_pointer = (binding_table_offset >> 5);
+
+	idd->desc5.constant_urb_entry_read_offset = 0;
+	idd->desc5.constant_urb_entry_read_length = 1; /* grf 1 */
+
+	idd->desc6.num_threads_in_tg = 1;
+
+	return offset;
+}
+
+void
+gen7_emit_state_base_address_v2(struct intel_bb *ibb)
+{
+	intel_bb_out(ibb, GEN7_STATE_BASE_ADDRESS | (10 - 2));
+
+	/* general */
+	intel_bb_out(ibb, 0);
+
+	/* surface */
+	intel_bb_emit_reloc(ibb, ibb->handle,
+			    I915_GEM_DOMAIN_INSTRUCTION, 0,
+			    BASE_ADDRESS_MODIFY, 0x0);
+
+	/* dynamic */
+	intel_bb_emit_reloc(ibb, ibb->handle,
+			    I915_GEM_DOMAIN_INSTRUCTION, 0,
+			    BASE_ADDRESS_MODIFY, 0x0);
+
+	/* indirect */
+	intel_bb_out(ibb, 0);
+
+	/* instruction */
+	intel_bb_emit_reloc(ibb, ibb->handle,
+			    I915_GEM_DOMAIN_INSTRUCTION, 0,
+			    BASE_ADDRESS_MODIFY, 0x0);
+
+	/* general/dynamic/indirect/instruction access Bound */
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, 0 | BASE_ADDRESS_MODIFY);
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, 0 | BASE_ADDRESS_MODIFY);
+}
+
+void
+gen8_emit_state_base_address_v2(struct intel_bb *ibb)
+{
+	intel_bb_out(ibb, GEN8_STATE_BASE_ADDRESS | (16 - 2));
+
+	/* general */
+	intel_bb_out(ibb, 0 | BASE_ADDRESS_MODIFY);
+	intel_bb_out(ibb, 0);
+
+	/* stateless data port */
+	intel_bb_out(ibb, 0 | BASE_ADDRESS_MODIFY);
+
+	/* surface */
+	intel_bb_emit_reloc(ibb, ibb->handle,
+			    I915_GEM_DOMAIN_SAMPLER, 0,
+			    BASE_ADDRESS_MODIFY, 0x0);
+
+	/* dynamic */
+	intel_bb_emit_reloc(ibb, ibb->handle,
+			    I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION,
+			    0,
+			    BASE_ADDRESS_MODIFY, 0x0);
+
+	/* indirect */
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, 0);
+
+	/* instruction */
+	intel_bb_emit_reloc(ibb, ibb->handle,
+			    I915_GEM_DOMAIN_INSTRUCTION,
+			    0,
+			    BASE_ADDRESS_MODIFY, 0x0);
+
+
+	/* general state buffer size */
+	intel_bb_out(ibb, 0xfffff000 | 1);
+	/* dynamic state buffer size */
+	intel_bb_out(ibb, 1 << 12 | 1);
+	/* indirect object buffer size */
+	intel_bb_out(ibb, 0xfffff000 | 1);
+	/* instruction buffer size, must set modify enable bit, otherwise it may
+	 * result in GPU hang
+	 */
+	intel_bb_out(ibb, 1 << 12 | 1);
+}
+
+
+void
+gen9_emit_state_base_address_v2(struct intel_bb *ibb)
+{
+	intel_bb_out(ibb, GEN8_STATE_BASE_ADDRESS | (19 - 2));
+
+	/* general */
+	intel_bb_out(ibb, 0 | BASE_ADDRESS_MODIFY);
+	intel_bb_out(ibb, 0);
+
+	/* stateless data port */
+	intel_bb_out(ibb, 0 | BASE_ADDRESS_MODIFY);
+
+	/* surface */
+	intel_bb_emit_reloc(ibb, ibb->handle,
+			    I915_GEM_DOMAIN_SAMPLER, 0,
+			    BASE_ADDRESS_MODIFY, 0x0);
+
+	/* dynamic */
+	intel_bb_emit_reloc(ibb, ibb->handle,
+			    I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION,
+			    0,
+			    BASE_ADDRESS_MODIFY, 0x0);
+
+	/* indirect */
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, 0);
+
+	/* instruction */
+	intel_bb_emit_reloc(ibb, ibb->handle,
+			    I915_GEM_DOMAIN_INSTRUCTION, 0,
+			    BASE_ADDRESS_MODIFY, 0x0);
+
+	/* general state buffer size */
+	intel_bb_out(ibb, 0xfffff000 | 1);
+	/* dynamic state buffer size */
+	intel_bb_out(ibb, 1 << 12 | 1);
+	/* indirect object buffer size */
+	intel_bb_out(ibb, 0xfffff000 | 1);
+	/* intruction buffer size, must set modify enable bit, otherwise it may
+	 * result in GPU hang
+	 */
+	intel_bb_out(ibb, 1 << 12 | 1);
+
+	/* Bindless surface state base address */
+	intel_bb_out(ibb, 0 | BASE_ADDRESS_MODIFY);
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, 0xfffff000);
+}
+
+void
+gen7_emit_vfe_state_v2(struct intel_bb *ibb, uint32_t threads,
+		       uint32_t urb_entries, uint32_t urb_size,
+		       uint32_t curbe_size, uint32_t mode)
+{
+	intel_bb_out(ibb, GEN7_MEDIA_VFE_STATE | (8 - 2));
+
+	/* scratch buffer */
+	intel_bb_out(ibb, 0);
+
+	/* number of threads & urb entries */
+	intel_bb_out(ibb, threads << 16 |
+		     urb_entries << 8 |
+		     mode << 2); /* GPGPU vs media mode */
+
+	intel_bb_out(ibb, 0);
+
+	/* urb entry size & curbe size */
+	intel_bb_out(ibb, urb_size << 16 |	/* in 256 bits unit */
+		     curbe_size);		/* in 256 bits unit */
+
+	/* scoreboard */
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, 0);
+}
+
+void
+gen8_emit_vfe_state_v2(struct intel_bb *ibb, uint32_t threads,
+		       uint32_t urb_entries, uint32_t urb_size,
+		       uint32_t curbe_size)
+{
+	intel_bb_out(ibb, GEN7_MEDIA_VFE_STATE | (9 - 2));
+
+	/* scratch buffer */
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, 0);
+
+	/* number of threads & urb entries */
+	intel_bb_out(ibb, threads << 16 | urb_entries << 8);
+
+	intel_bb_out(ibb, 0);
+
+	/* urb entry size & curbe size */
+	intel_bb_out(ibb, urb_size << 16 | curbe_size);
+
+	/* scoreboard */
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, 0);
+}
+
+void
+gen7_emit_curbe_load_v2(struct intel_bb *ibb, uint32_t curbe_buffer)
+{
+	intel_bb_out(ibb, GEN7_MEDIA_CURBE_LOAD | (4 - 2));
+	intel_bb_out(ibb, 0);
+	/* curbe total data length */
+	intel_bb_out(ibb, 64);
+	/* curbe data start address, is relative to the dynamics base address */
+	intel_bb_out(ibb, curbe_buffer);
+}
+
+void
+gen7_emit_interface_descriptor_load_v2(struct intel_bb *ibb,
+				       uint32_t interface_descriptor)
+{
+	intel_bb_out(ibb, GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
+	intel_bb_out(ibb, 0);
+	/* interface descriptor data length */
+	if (ibb->gen == 7)
+		intel_bb_out(ibb, sizeof(struct gen7_interface_descriptor_data));
+	else
+		intel_bb_out(ibb, sizeof(struct gen8_interface_descriptor_data));
+	/* interface descriptor address, is relative to the dynamics base
+	 * address
+	 */
+	intel_bb_out(ibb, interface_descriptor);
+}
+
+void
+gen7_emit_gpgpu_walk_v2(struct intel_bb *ibb,
+			unsigned int x, unsigned int y,
+			unsigned int width, unsigned int height)
+{
+	uint32_t x_dim, y_dim, tmp, right_mask;
+
+	/*
+	 * Simply do SIMD16 based dispatch, so every thread uses
+	 * SIMD16 channels.
+	 *
+	 * Define our own thread group size, e.g 16x1 for every group, then
+	 * will have 1 thread each group in SIMD16 dispatch. So thread
+	 * width/height/depth are all 1.
+	 *
+	 * Then thread group X = width / 16 (aligned to 16)
+	 * thread group Y = height;
+	 */
+	x_dim = (width + 15) / 16;
+	y_dim = height;
+
+	tmp = width & 15;
+	if (tmp == 0)
+		right_mask = (1 << 16) - 1;
+	else
+		right_mask = (1 << tmp) - 1;
+
+	intel_bb_out(ibb, GEN7_GPGPU_WALKER | 9);
+
+	/* interface descriptor offset */
+	intel_bb_out(ibb, 0);
+
+	/* SIMD size, thread w/h/d */
+	intel_bb_out(ibb, 1 << 30 | /* SIMD16 */
+		  0 << 16 | /* depth:1 */
+		  0 << 8 | /* height:1 */
+		  0); /* width:1 */
+
+	/* thread group X */
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, x_dim);
+
+	/* thread group Y */
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, y_dim);
+
+	/* thread group Z */
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, 1);
+
+	/* right mask */
+	intel_bb_out(ibb, right_mask);
+
+	/* bottom mask, height 1, always 0xffffffff */
+	intel_bb_out(ibb, 0xffffffff);
+}
+
+void
+gen8_emit_gpgpu_walk_v2(struct intel_bb *ibb,
+			unsigned int x, unsigned int y,
+			unsigned int width, unsigned int height)
+{
+	uint32_t x_dim, y_dim, tmp, right_mask;
+
+	/*
+	 * Simply do SIMD16 based dispatch, so every thread uses
+	 * SIMD16 channels.
+	 *
+	 * Define our own thread group size, e.g 16x1 for every group, then
+	 * will have 1 thread each group in SIMD16 dispatch. So thread
+	 * width/height/depth are all 1.
+	 *
+	 * Then thread group X = width / 16 (aligned to 16)
+	 * thread group Y = height;
+	 */
+	x_dim = (width + 15) / 16;
+	y_dim = height;
+
+	tmp = width & 15;
+	if (tmp == 0)
+		right_mask = (1 << 16) - 1;
+	else
+		right_mask = (1 << tmp) - 1;
+
+	intel_bb_out(ibb, GEN7_GPGPU_WALKER | 13);
+
+	intel_bb_out(ibb, 0); /* kernel offset */
+	intel_bb_out(ibb, 0); /* indirect data length */
+	intel_bb_out(ibb, 0); /* indirect data offset */
+
+	/* SIMD size, thread w/h/d */
+	intel_bb_out(ibb, 1 << 30 | /* SIMD16 */
+		     0 << 16 | /* depth:1 */
+		     0 << 8 | /* height:1 */
+		     0); /* width:1 */
+
+	/* thread group X */
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, x_dim);
+
+	/* thread group Y */
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, y_dim);
+
+	/* thread group Z */
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, 1);
+
+	/* right mask */
+	intel_bb_out(ibb, right_mask);
+
+	/* bottom mask, height 1, always 0xffffffff */
+	intel_bb_out(ibb, 0xffffffff);
+}
diff --git a/lib/gpu_cmds.h b/lib/gpu_cmds.h
index 1321af44..61aff153 100644
--- a/lib/gpu_cmds.h
+++ b/lib/gpu_cmds.h
@@ -35,6 +35,7 @@
 #include "drmtest.h"
 #include "intel_batchbuffer.h"
 #include "intel_chipset.h"
+#include "intel_bufops.h"
 #include <assert.h>
 
 void
@@ -148,4 +149,57 @@ gen_emit_media_object(struct intel_batchbuffer *batch, unsigned int xoffset,
 void
 gen9_emit_state_base_address(struct intel_batchbuffer *batch);
 
+
+/* No libdrm */
+uint32_t
+gen7_fill_curbe_buffer_data_v2(struct intel_bb *ibb,
+			       uint8_t color);
+
+uint32_t
+gen7_fill_interface_descriptor_v2(struct intel_bb *ibb,
+				  struct intel_buf *buf,
+				  const uint32_t kernel[][4],
+				  size_t size);
+
+uint32_t
+gen8_fill_interface_descriptor_v2(struct intel_bb *ibb,
+				  struct intel_buf *buf,
+				  const uint32_t kernel[][4],
+				  size_t size);
+
+void
+gen7_emit_state_base_address_v2(struct intel_bb *ibb);
+
+void
+gen8_emit_state_base_address_v2(struct intel_bb *ibb);
+
+void
+gen9_emit_state_base_address_v2(struct intel_bb *ibb);
+
+void
+gen7_emit_vfe_state_v2(struct intel_bb *ibb, uint32_t threads,
+		       uint32_t urb_entries, uint32_t urb_size,
+		       uint32_t curbe_size, uint32_t mode);
+
+void
+gen8_emit_vfe_state_v2(struct intel_bb *ibb, uint32_t threads,
+		       uint32_t urb_entries, uint32_t urb_size,
+		       uint32_t curbe_size);
+void
+gen7_emit_curbe_load_v2(struct intel_bb *ibb, uint32_t curbe_buffer);
+
+void
+gen7_emit_interface_descriptor_load_v2(struct intel_bb *ibb,
+				       uint32_t interface_descriptor);
+
+void
+gen7_emit_gpgpu_walk_v2(struct intel_bb *ibb,
+			unsigned int x, unsigned int y,
+			unsigned int width, unsigned int height);
+
+void
+gen8_emit_gpgpu_walk_v2(struct intel_bb *ibb,
+			unsigned int x, unsigned int y,
+			unsigned int width, unsigned int height);
+
 #endif /* GPU_CMDS_H */
-- 
2.26.0

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[igt-dev] [PATCH i-g-t v3 5/7] lib/gpgpu_fill: libdrm-free gpgpu pipeline creation

[Zbigniew Kempczyński]

Provide "v2" pipeline for gpgpu fill for all gens.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/gpgpu_fill.c | 181 +++++++++++++++++++++++++++++++++++++++++++++++
 lib/gpgpu_fill.h |  34 +++++++++
 2 files changed, 215 insertions(+)

diff --git a/lib/gpgpu_fill.c b/lib/gpgpu_fill.c
index 5660d4c0..a0dc97c3 100644
--- a/lib/gpgpu_fill.c
+++ b/lib/gpgpu_fill.c
@@ -120,6 +120,7 @@ static const uint32_t gen12_gpgpu_kernel[][4] = {
  *
  */
 
+#define PAGE_SIZE 4096
 #define BATCH_STATE_SPLIT 2048
 /* VFE STATE params */
 #define THREADS 1
@@ -178,6 +179,54 @@ gen7_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 	intel_batchbuffer_reset(batch);
 }
 
+void
+gen7_gpgpu_fillfunc_v2(int i915,
+		       struct intel_buf *buf,
+		       unsigned x, unsigned y,
+		       unsigned width, unsigned height,
+		       uint8_t color)
+{
+	struct intel_bb *ibb;
+	uint32_t curbe_buffer, interface_descriptor;
+
+	ibb = intel_bb_create(i915, PAGE_SIZE);
+	intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT);
+
+	/* Fill curbe buffer data */
+	curbe_buffer = gen7_fill_curbe_buffer_data_v2(ibb, color);
+
+	/*
+	 * const buffer needs to fill for every thread, but as we have just 1
+	 * thread per every group, so need only one curbe data.
+	 * For each thread, just use thread group ID for buffer offset.
+	 */
+	interface_descriptor =
+			gen7_fill_interface_descriptor_v2(ibb, buf,
+							  gen7_gpgpu_kernel,
+							  sizeof(gen7_gpgpu_kernel));
+
+	intel_bb_ptr_set(ibb, 0);
+
+	/* GPGPU pipeline */
+	intel_bb_out(ibb, GEN7_PIPELINE_SELECT | PIPELINE_SELECT_GPGPU);
+
+	gen7_emit_state_base_address_v2(ibb);
+	gen7_emit_vfe_state_v2(ibb, THREADS, GEN7_GPGPU_URB_ENTRIES,
+			       GPGPU_URB_SIZE, GPGPU_CURBE_SIZE,
+			       GEN7_VFE_STATE_GPGPU_MODE);
+	gen7_emit_curbe_load_v2(ibb, curbe_buffer);
+	gen7_emit_interface_descriptor_load_v2(ibb, interface_descriptor);
+	gen7_emit_gpgpu_walk_v2(ibb, x, y, width, height);
+
+	intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+	intel_bb_ptr_align(ibb, 32);
+
+	intel_bb_exec(ibb, intel_bb_offset(ibb),
+		      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+
+	intel_bb_destroy(ibb);
+}
+
 void
 gen8_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 		    const struct igt_buf *dst,
@@ -226,6 +275,52 @@ gen8_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 	intel_batchbuffer_reset(batch);
 }
 
+void
+gen8_gpgpu_fillfunc_v2(int i915,
+		       struct intel_buf *buf,
+		       unsigned x, unsigned y,
+		       unsigned width, unsigned height,
+		       uint8_t color)
+{
+	struct intel_bb *ibb;
+	uint32_t curbe_buffer, interface_descriptor;
+
+	ibb = intel_bb_create(i915, PAGE_SIZE);
+	intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT);
+
+	/*
+	 * const buffer needs to fill for every thread, but as we have just 1
+	 * thread per every group, so need only one curbe data.
+	 * For each thread, just use thread group ID for buffer offset.
+	 */
+	curbe_buffer = gen7_fill_curbe_buffer_data_v2(ibb, color);
+
+	interface_descriptor = gen8_fill_interface_descriptor_v2(ibb, buf,
+				gen8_gpgpu_kernel, sizeof(gen8_gpgpu_kernel));
+
+	intel_bb_ptr_set(ibb, 0);
+
+	/* GPGPU pipeline */
+	intel_bb_out(ibb, GEN7_PIPELINE_SELECT | PIPELINE_SELECT_GPGPU);
+
+	gen8_emit_state_base_address_v2(ibb);
+	gen8_emit_vfe_state_v2(ibb, THREADS, GEN8_GPGPU_URB_ENTRIES,
+			       GPGPU_URB_SIZE, GPGPU_CURBE_SIZE);
+
+	gen7_emit_curbe_load_v2(ibb, curbe_buffer);
+	gen7_emit_interface_descriptor_load_v2(ibb, interface_descriptor);
+
+	gen8_emit_gpgpu_walk_v2(ibb, x, y, width, height);
+
+	intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+	intel_bb_ptr_align(ibb, 32);
+
+	intel_bb_exec(ibb, intel_bb_offset(ibb),
+		      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+
+	intel_bb_destroy(ibb);
+}
+
 static void
 __gen9_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 		      const struct igt_buf *dst,
@@ -276,6 +371,58 @@ __gen9_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 	intel_batchbuffer_reset(batch);
 }
 
+
+static void
+__gen9_gpgpu_fillfunc_v2(int i915,
+			 struct intel_buf *buf,
+			 unsigned x, unsigned y,
+			 unsigned width, unsigned height,
+			 uint8_t color,
+			 const uint32_t kernel[][4], size_t kernel_size)
+{
+	struct intel_bb *ibb;
+	uint32_t curbe_buffer, interface_descriptor;
+
+	ibb = intel_bb_create(i915, PAGE_SIZE);
+	intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT);
+
+	/*
+	 * const buffer needs to fill for every thread, but as we have just 1
+	 * thread per every group, so need only one curbe data.
+	 * For each thread, just use thread group ID for buffer offset.
+	 */
+	/* Fill curbe buffer data */
+	curbe_buffer = gen7_fill_curbe_buffer_data_v2(ibb, color);
+
+	interface_descriptor = gen8_fill_interface_descriptor_v2(ibb, buf,
+								 kernel,
+								 kernel_size);
+
+	intel_bb_ptr_set(ibb, 0);
+
+	/* GPGPU pipeline */
+	intel_bb_out(ibb, GEN7_PIPELINE_SELECT | GEN9_PIPELINE_SELECTION_MASK |
+		     PIPELINE_SELECT_GPGPU);
+
+	gen9_emit_state_base_address_v2(ibb);
+
+	gen8_emit_vfe_state_v2(ibb, THREADS, GEN8_GPGPU_URB_ENTRIES,
+			       GPGPU_URB_SIZE, GPGPU_CURBE_SIZE);
+
+	gen7_emit_curbe_load_v2(ibb, curbe_buffer);
+	gen7_emit_interface_descriptor_load_v2(ibb, interface_descriptor);
+
+	gen8_emit_gpgpu_walk_v2(ibb, x, y, width, height);
+
+	intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+	intel_bb_ptr_align(ibb, 32);
+
+	intel_bb_exec(ibb, intel_bb_offset(ibb),
+		      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+
+	intel_bb_destroy(ibb);
+}
+
 void gen9_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 			 const struct igt_buf *dst,
 			 unsigned int x, unsigned int y,
@@ -286,6 +433,18 @@ void gen9_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 			      gen9_gpgpu_kernel, sizeof(gen9_gpgpu_kernel));
 }
 
+void gen9_gpgpu_fillfunc_v2(int i915,
+			    struct intel_buf *buf,
+			    unsigned x, unsigned y,
+			    unsigned width, unsigned height,
+			    uint8_t color)
+{
+	__gen9_gpgpu_fillfunc_v2(i915, buf, x, y, width, height, color,
+				 gen9_gpgpu_kernel,
+				 sizeof(gen9_gpgpu_kernel));
+}
+
+
 void gen11_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 			  const struct igt_buf *dst,
 			  unsigned int x, unsigned int y,
@@ -296,6 +455,17 @@ void gen11_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 			      gen11_gpgpu_kernel, sizeof(gen11_gpgpu_kernel));
 }
 
+void gen11_gpgpu_fillfunc_v2(int i915,
+			     struct intel_buf *buf,
+			     unsigned x, unsigned y,
+			     unsigned width, unsigned height,
+			     uint8_t color)
+{
+	__gen9_gpgpu_fillfunc_v2(i915, buf, x, y, width, height, color,
+				 gen11_gpgpu_kernel,
+				 sizeof(gen11_gpgpu_kernel));
+}
+
 void gen12_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 			  const struct igt_buf *dst,
 			  unsigned int x, unsigned int y,
@@ -305,3 +475,14 @@ void gen12_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 	__gen9_gpgpu_fillfunc(batch, dst, x, y, width, height, color,
 			      gen12_gpgpu_kernel, sizeof(gen12_gpgpu_kernel));
 }
+
+void gen12_gpgpu_fillfunc_v2(int i915,
+			     struct intel_buf *buf,
+			     unsigned x, unsigned y,
+			     unsigned width, unsigned height,
+			     uint8_t color)
+{
+	__gen9_gpgpu_fillfunc_v2(i915, buf, x, y, width, height, color,
+				 gen12_gpgpu_kernel,
+				 sizeof(gen12_gpgpu_kernel));
+}
diff --git a/lib/gpgpu_fill.h b/lib/gpgpu_fill.h
index da7d646f..a387732b 100644
--- a/lib/gpgpu_fill.h
+++ b/lib/gpgpu_fill.h
@@ -28,6 +28,7 @@
 #define GPGPU_FILL_H
 
 #include "intel_batchbuffer.h"
+#include "intel_bufops.h"
 
 void
 gen7_gpgpu_fillfunc(struct intel_batchbuffer *batch,
@@ -36,6 +37,13 @@ gen7_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 		    unsigned int width, unsigned int height,
 		    uint8_t color);
 
+void
+gen7_gpgpu_fillfunc_v2(int i915,
+		       struct intel_buf *buf,
+		       unsigned x, unsigned y,
+		       unsigned width, unsigned height,
+		       uint8_t color);
+
 void
 gen8_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 		    const struct igt_buf *dst,
@@ -43,6 +51,13 @@ gen8_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 		    unsigned int width, unsigned int height,
 		    uint8_t color);
 
+void
+gen8_gpgpu_fillfunc_v2(int i915,
+		       struct intel_buf *buf,
+		       unsigned x, unsigned y,
+		       unsigned width, unsigned height,
+		       uint8_t color);
+
 void
 gen9_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 		    const struct igt_buf *dst,
@@ -50,6 +65,12 @@ gen9_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 		    unsigned int width, unsigned int height,
 		    uint8_t color);
 
+void gen9_gpgpu_fillfunc_v2(int i915,
+			    struct intel_buf *buf,
+			    unsigned x, unsigned y,
+			    unsigned width, unsigned height,
+			    uint8_t color);
+
 void
 gen11_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 		     const struct igt_buf *dst,
@@ -57,6 +78,12 @@ gen11_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 		     unsigned int width, unsigned int height,
 		     uint8_t color);
 
+void gen11_gpgpu_fillfunc_v2(int i915,
+			     struct intel_buf *buf,
+			     unsigned x, unsigned y,
+			     unsigned width, unsigned height,
+			     uint8_t color);
+
 void
 gen12_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 		     const struct igt_buf *dst,
@@ -64,4 +91,11 @@ gen12_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 		     unsigned int width, unsigned int height,
 		     uint8_t color);
 
+void
+gen12_gpgpu_fillfunc_v2(int i915,
+			struct intel_buf *buf,
+			unsigned x, unsigned y,
+			unsigned width, unsigned height,
+			uint8_t color);
+
 #endif /* GPGPU_FILL_H */
-- 
2.26.0

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[igt-dev] [PATCH i-g-t v3 6/7] lib/intel_batchbuffer: Introduce temporary igt_fillfunc_v2_t

[Zbigniew Kempczyński]

gem_gpgpu_fill test is spread over different generations (gen >= 7)
so some transitional state is required until all gens will be
rewritten to new intel_bb code without libdrm dependency.

So, let's define new igt_fillfunc_v2_t to be new fill function.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/intel_batchbuffer.c | 27 +++++++++++++++++++++++++++
 lib/intel_batchbuffer.h |  8 ++++++++
 2 files changed, 35 insertions(+)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 580feabb..3787bea8 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -1152,6 +1152,33 @@ igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid)
 	return fill;
 }
 
+/**
+ * igt_get_gpgpu_fillfunc_v2:
+ * @devid: pci device id
+ *
+ * Returns:
+ *
+ * The platform-specific gpgpu fill function pointer for the device specified
+ * with @devid. Will return NULL when no gpgpu fill function is implemented.
+ */
+igt_fillfunc_v2_t igt_get_gpgpu_fillfunc_v2(int devid)
+{
+	igt_fillfunc_v2_t fill = NULL;
+
+	if (IS_GEN7(devid))
+		fill = gen7_gpgpu_fillfunc_v2;
+	else if (IS_BROADWELL(devid))
+		fill = gen8_gpgpu_fillfunc_v2;
+	else if (IS_GEN9(devid) || IS_GEN10(devid))
+		fill = gen9_gpgpu_fillfunc_v2;
+	else if (IS_GEN11(devid))
+		fill = gen11_gpgpu_fillfunc_v2;
+	else if (IS_GEN12(devid))
+		fill = gen12_gpgpu_fillfunc_v2;
+
+	return fill;
+}
+
 /**
  * igt_get_media_spinfunc:
  * @devid: pci device id
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 5f3bd974..4427f254 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -391,8 +391,16 @@ typedef void (*igt_fillfunc_t)(struct intel_batchbuffer *batch,
 			       unsigned width, unsigned height,
 			       uint8_t color);
 
+struct intel_buf;
+typedef void (*igt_fillfunc_v2_t)(int i915,
+				  struct intel_buf *buf,
+				  unsigned x, unsigned y,
+				  unsigned width, unsigned height,
+				  uint8_t color);
+
 igt_fillfunc_t igt_get_media_fillfunc(int devid);
 igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid);
+igt_fillfunc_v2_t igt_get_gpgpu_fillfunc_v2(int devid);
 
 typedef void (*igt_vme_func_t)(struct intel_batchbuffer *batch,
 			       const struct igt_buf *src,
-- 
2.26.0

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[igt-dev] [PATCH i-g-t v3 7/7] tests/gem_gpgpu_fill: Remove libdrm dependency

[Zbigniew Kempczyński]

Gpgpu pipeline creation is a little bit coupled (some functions
are used in other gens) so providing "v2" version of the same
functions is necessary unless former will have full replacement
(media fill also uses same functions).

So gpgpu fill prefers now "newer" version of the same pipeline
creation which is libdrm-free.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/i915/gem_gpgpu_fill.c | 126 ++++++++++++++++++++++++++++--------
 1 file changed, 99 insertions(+), 27 deletions(-)

diff --git a/tests/i915/gem_gpgpu_fill.c b/tests/i915/gem_gpgpu_fill.c
index fb1758bd..24a2c834 100644
--- a/tests/i915/gem_gpgpu_fill.c
+++ b/tests/i915/gem_gpgpu_fill.c
@@ -46,6 +46,7 @@
 #include "i915/gem.h"
 #include "igt.h"
 #include "intel_bufmgr.h"
+#include "intel_bufops.h"
 
 #define WIDTH 64
 #define HEIGHT 64
@@ -60,6 +61,7 @@ typedef struct {
 	uint32_t devid;
 	drm_intel_bufmgr *bufmgr;
 	uint8_t linear[WIDTH * HEIGHT];
+	struct buf_ops *bops;
 } data_t;
 
 static void scratch_buf_init(data_t *data, struct igt_buf *buf,
@@ -83,6 +85,34 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf,
 	buf->bpp = 32;
 }
 
+static struct intel_buf *
+create_buf(data_t *data, int width, int height, uint8_t color)
+{
+	struct intel_buf *buf;
+	uint8_t *ptr;
+	int i;
+
+	buf = calloc(1, sizeof(*buf));
+	igt_assert(buf);
+
+	/*
+	 * Legacy code uses 32 bpp after buffer creation.
+	 * Let's do the same due to keep shader intact.
+	 */
+	intel_buf_init(data->bops, buf, width/4, height, 32, 0,
+		       I915_TILING_NONE, 0);
+
+	ptr = gem_mmap__cpu_coherent(data->drm_fd,
+				     buf->handle, 0, buf->size, PROT_WRITE);
+
+	for (i = 0; i < buf->size; i++)
+		ptr[i] = color;
+
+	munmap(ptr, buf->size);
+
+	return buf;
+}
+
 static void
 scratch_buf_check(data_t *data, struct igt_buf *buf, int x, int y,
 		uint8_t color)
@@ -97,47 +127,89 @@ scratch_buf_check(data_t *data, struct igt_buf *buf, int x, int y,
 		     color, val, x, y);
 }
 
-igt_simple_main
+static void buf_check(uint8_t *ptr, int x, int y, uint8_t color)
+{
+	uint8_t val;
+
+	val = ptr[y * WIDTH + x];
+	igt_assert_f(val == color,
+		     "Expected 0x%02x, found 0x%02x at (%d,%d)\n",
+		     color, val, x, y);
+}
+
+static void no_libdrm(data_t *data, igt_fillfunc_v2_t fill)
+{
+	struct intel_buf *buf;
+	uint8_t *ptr;
+	int i, j;
+
+	buf = create_buf(data, WIDTH, HEIGHT, COLOR_C4);
+	ptr = gem_mmap__cpu_coherent(data->drm_fd, buf->handle,
+				     0, buf->size, PROT_READ);
+	for (i = 0; i < WIDTH; i++)
+		for (j = 0; j < HEIGHT; j++)
+			buf_check(ptr, i, j, COLOR_C4);
+
+	fill(data->drm_fd, buf, 0, 0, WIDTH / 2, HEIGHT / 2, COLOR_4C);
+
+	for (i = 0; i < WIDTH; i++)
+		for (j = 0; j < HEIGHT; j++)
+			if (i < WIDTH / 2 && j < HEIGHT / 2)
+				buf_check(ptr, i, j, COLOR_4C);
+			else
+				buf_check(ptr, i, j, COLOR_C4);
+
+	munmap(ptr, buf->size);
+}
+
+static void with_libdrm(data_t *data, igt_fillfunc_t fill)
 {
-	data_t data = {0, };
 	struct intel_batchbuffer *batch = NULL;
 	struct igt_buf dst;
-	igt_fillfunc_t gpgpu_fill = NULL;
 	int i, j;
 
+	batch = intel_batchbuffer_alloc(data->bufmgr, data->devid);
+	igt_assert(batch);
+
+	scratch_buf_init(data, &dst, WIDTH, HEIGHT, STRIDE, COLOR_C4);
+
+	for (i = 0; i < WIDTH; i++)
+		for (j = 0; j < HEIGHT; j++)
+			scratch_buf_check(data, &dst, i, j, COLOR_C4);
+
+	fill(batch, &dst, 0, 0, WIDTH / 2, HEIGHT / 2, COLOR_4C);
+
+	for (i = 0; i < WIDTH; i++)
+		for (j = 0; j < HEIGHT; j++)
+			if (i < WIDTH / 2 && j < HEIGHT / 2)
+				scratch_buf_check(data, &dst, i, j, COLOR_4C);
+			else
+				scratch_buf_check(data, &dst, i, j, COLOR_C4);
+
+}
+
+igt_simple_main
+{
+	data_t data = {0, };
+	igt_fillfunc_t gpgpu_fill = NULL;
+	igt_fillfunc_v2_t gpgpu_fill_v2 = NULL;
+
 	data.drm_fd = drm_open_driver_render(DRIVER_INTEL);
 	data.devid = intel_get_drm_devid(data.drm_fd);
 	igt_require_gem(data.drm_fd);
+	data.bops = buf_ops_create(data.drm_fd);
 
 	data.bufmgr = drm_intel_bufmgr_gem_init(data.drm_fd, 4096);
 	igt_assert(data.bufmgr);
 
 	gpgpu_fill = igt_get_gpgpu_fillfunc(data.devid);
+	gpgpu_fill_v2 = igt_get_gpgpu_fillfunc_v2(data.devid);
 
-	igt_require_f(gpgpu_fill,
+	igt_require_f(gpgpu_fill || gpgpu_fill_v2,
 		      "no gpgpu-fill function\n");
 
-	batch = intel_batchbuffer_alloc(data.bufmgr, data.devid);
-	igt_assert(batch);
-
-	scratch_buf_init(&data, &dst, WIDTH, HEIGHT, STRIDE, COLOR_C4);
-
-	for (i = 0; i < WIDTH; i++) {
-		for (j = 0; j < HEIGHT; j++) {
-			scratch_buf_check(&data, &dst, i, j, COLOR_C4);
-		}
-	}
-
-	gpgpu_fill(batch,
-		   &dst, 0, 0, WIDTH / 2, HEIGHT / 2,
-		   COLOR_4C);
-
-	for (i = 0; i < WIDTH; i++) {
-		for (j = 0; j < HEIGHT; j++) {
-			if (i < WIDTH / 2 && j < HEIGHT / 2)
-				scratch_buf_check(&data, &dst, i, j, COLOR_4C);
-			else
-				scratch_buf_check(&data, &dst, i, j, COLOR_C4);
-		}
-	}
+	if (gpgpu_fill_v2)
+		no_libdrm(&data, gpgpu_fill_v2);
+	else
+		with_libdrm(&data, gpgpu_fill);
 }
-- 
2.26.0

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[igt-dev] ✓ Fi.CI.BAT: success for Make gpgpu fill tests libdrm independent (rev3)

[Patchwork]

== Series Details ==

Series: Make gpgpu fill tests libdrm independent (rev3)
URL   : https://patchwork.freedesktop.org/series/77175/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8493 -> IGTPW_4575
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/index.html

Known issues
------------

  Here are the changes found in IGTPW_4575 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@i915_selftest@live@execlists:
    - fi-tgl-y:           [INCOMPLETE][1] ([i915#1803]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/fi-tgl-y/igt@i915_selftest@live@execlists.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/fi-tgl-y/igt@i915_selftest@live@execlists.html

  
  [i915#1803]: https://gitlab.freedesktop.org/drm/intel/issues/1803


Participating hosts (51 -> 43)
------------------------------

  Additional (1): fi-kbl-7560u 
  Missing    (9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-hsw-4770 fi-byt-clapper fi-bsw-nick fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5657 -> IGTPW_4575

  CI-20190529: 20190529
  CI_DRM_8493: 47e0097b33017be45f6826ef82a1f535b81ab9a3 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_4575: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/index.html
  IGT_5657: 649eae5c905a7460b44305800f95db83a6dd47cb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/index.html
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[igt-dev] ✗ Fi.CI.IGT: failure for Make gpgpu fill tests libdrm independent (rev3)

[Patchwork]

== Series Details ==

Series: Make gpgpu fill tests libdrm independent (rev3)
URL   : https://patchwork.freedesktop.org/series/77175/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_8493_full -> IGTPW_4575_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_4575_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_4575_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_4575_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_gpgpu_fill:
    - shard-glk:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-glk8/igt@gem_gpgpu_fill.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-glk5/igt@gem_gpgpu_fill.html
    - shard-apl:          [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-apl1/igt@gem_gpgpu_fill.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-apl2/igt@gem_gpgpu_fill.html

  * igt@kms_cursor_edge_walk@pipe-d-64x64-right-edge:
    - shard-tglb:         [PASS][5] -> [FAIL][6] +42 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb2/igt@kms_cursor_edge_walk@pipe-d-64x64-right-edge.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb6/igt@kms_cursor_edge_walk@pipe-d-64x64-right-edge.html

  * igt@kms_draw_crc@draw-method-xrgb2101010-blt-ytiled:
    - shard-tglb:         NOTRUN -> [FAIL][7]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb2/igt@kms_draw_crc@draw-method-xrgb2101010-blt-ytiled.html

  
#### Warnings ####

  * igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge:
    - shard-tglb:         [FAIL][8] ([i915#402]) -> [FAIL][9] +4 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb7/igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb3/igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-tglb:         [SKIP][10] ([i915#668]) -> [FAIL][11] +2 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html

  
Known issues
------------

  Here are the changes found in IGTPW_4575_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_workarounds@suspend-resume-context:
    - shard-kbl:          [PASS][12] -> [DMESG-WARN][13] ([i915#165])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-kbl6/igt@gem_workarounds@suspend-resume-context.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-kbl3/igt@gem_workarounds@suspend-resume-context.html

  * igt@i915_suspend@fence-restore-untiled:
    - shard-apl:          [PASS][14] -> [DMESG-WARN][15] ([i915#180])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-apl6/igt@i915_suspend@fence-restore-untiled.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-apl4/igt@i915_suspend@fence-restore-untiled.html

  * igt@kms_big_fb@linear-32bpp-rotate-0:
    - shard-apl:          [PASS][16] -> [FAIL][17] ([i915#1119] / [i915#95])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-apl2/igt@kms_big_fb@linear-32bpp-rotate-0.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-apl3/igt@kms_big_fb@linear-32bpp-rotate-0.html

  * igt@kms_big_fb@linear-8bpp-rotate-180:
    - shard-tglb:         [PASS][18] -> [FAIL][19] ([i915#1172]) +2 similar issues
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb5/igt@kms_big_fb@linear-8bpp-rotate-180.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb8/igt@kms_big_fb@linear-8bpp-rotate-180.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-270:
    - shard-tglb:         [PASS][20] -> [FAIL][21] ([i915#1172] / [i915#402]) +3 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb2/igt@kms_big_fb@y-tiled-16bpp-rotate-270.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb6/igt@kms_big_fb@y-tiled-16bpp-rotate-270.html

  * igt@kms_color@pipe-a-ctm-0-5:
    - shard-tglb:         [PASS][22] -> [FAIL][23] ([i915#1149] / [i915#402]) +1 similar issue
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb8/igt@kms_color@pipe-a-ctm-0-5.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb7/igt@kms_color@pipe-a-ctm-0-5.html

  * igt@kms_color@pipe-b-ctm-max:
    - shard-tglb:         [PASS][24] -> [FAIL][25] ([i915#1149]) +2 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb3/igt@kms_color@pipe-b-ctm-max.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb5/igt@kms_color@pipe-b-ctm-max.html

  * igt@kms_color@pipe-d-ctm-0-5:
    - shard-tglb:         [PASS][26] -> [FAIL][27] ([i915#1149] / [i915#315])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb7/igt@kms_color@pipe-d-ctm-0-5.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb1/igt@kms_color@pipe-d-ctm-0-5.html

  * igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen:
    - shard-kbl:          [PASS][28] -> [FAIL][29] ([i915#54] / [i915#93] / [i915#95]) +1 similar issue
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen.html

  * igt@kms_cursor_edge_walk@pipe-a-256x256-right-edge:
    - shard-tglb:         [PASS][30] -> [FAIL][31] ([i915#1897] / [i915#402]) +9 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb6/igt@kms_cursor_edge_walk@pipe-a-256x256-right-edge.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb7/igt@kms_cursor_edge_walk@pipe-a-256x256-right-edge.html

  * igt@kms_flip_tiling@flip-x-tiled:
    - shard-tglb:         [PASS][32] -> [FAIL][33] ([i915#402] / [i915#699])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb3/igt@kms_flip_tiling@flip-x-tiled.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb6/igt@kms_flip_tiling@flip-x-tiled.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-kbl:          [PASS][34] -> [FAIL][35] ([i915#49] / [i915#93] / [i915#95])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
    - shard-glk:          [PASS][36] -> [FAIL][37] ([i915#49]) +1 similar issue
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-glk7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-glk2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-kbl:          [PASS][38] -> [FAIL][39] ([i915#49])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html
    - shard-apl:          [PASS][40] -> [FAIL][41] ([i915#49] / [i915#95]) +1 similar issue
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-apl1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-apl2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render:
    - shard-tglb:         [PASS][42] -> [SKIP][43] ([i915#668]) +8 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [PASS][44] -> [FAIL][45] ([i915#53] / [i915#93] / [i915#95])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-kbl:          [PASS][46] -> [FAIL][47] ([fdo#108145] / [i915#265] / [i915#93] / [i915#95])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-kbl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-kbl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
    - shard-apl:          [PASS][48] -> [FAIL][49] ([fdo#108145] / [i915#265] / [i915#95])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-vs-premult-vs-constant:
    - shard-tglb:         [PASS][50] -> [FAIL][51] ([i915#1897]) +27 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb2/igt@kms_plane_alpha_blend@pipe-c-coverage-vs-premult-vs-constant.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb3/igt@kms_plane_alpha_blend@pipe-c-coverage-vs-premult-vs-constant.html

  * igt@kms_plane_cursor@pipe-b-viewport-size-128:
    - shard-tglb:         [PASS][52] -> [FAIL][53] ([i915#402]) +55 similar issues
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb8/igt@kms_plane_cursor@pipe-b-viewport-size-128.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb6/igt@kms_plane_cursor@pipe-b-viewport-size-128.html

  * igt@kms_plane_lowres@pipe-a-tiling-y:
    - shard-tglb:         [PASS][54] -> [FAIL][55] ([i915#402] / [i915#899])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb3/igt@kms_plane_lowres@pipe-a-tiling-y.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb6/igt@kms_plane_lowres@pipe-a-tiling-y.html

  * igt@kms_plane_lowres@pipe-b-tiling-y:
    - shard-tglb:         [PASS][56] -> [FAIL][57] ([i915#899])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb6/igt@kms_plane_lowres@pipe-b-tiling-y.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb1/igt@kms_plane_lowres@pipe-b-tiling-y.html

  * igt@kms_psr@psr2_suspend:
    - shard-iclb:         [PASS][58] -> [SKIP][59] ([fdo#109441]) +1 similar issue
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-iclb2/igt@kms_psr@psr2_suspend.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-iclb7/igt@kms_psr@psr2_suspend.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-kbl:          [PASS][60] -> [DMESG-WARN][61] ([i915#180]) +1 similar issue
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-kbl2/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-kbl2/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

  
#### Possible fixes ####

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [FAIL][62] ([i915#1899]) -> [PASS][63]
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-iclb1/igt@i915_pm_dc@dc6-psr.html

  * igt@kms_available_modes_crc@available_mode_test_crc:
    - shard-tglb:         [FAIL][64] ([i915#1537]) -> [PASS][65]
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb2/igt@kms_available_modes_crc@available_mode_test_crc.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb5/igt@kms_available_modes_crc@available_mode_test_crc.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-180:
    - shard-tglb:         [FAIL][66] ([i915#1172] / [i915#402]) -> [PASS][67] +3 similar issues
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb2/igt@kms_big_fb@x-tiled-16bpp-rotate-180.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb1/igt@kms_big_fb@x-tiled-16bpp-rotate-180.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-0:
    - shard-tglb:         [FAIL][68] ([i915#1172]) -> [PASS][69] +1 similar issue
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb8/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb5/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html

  * igt@kms_ccs@pipe-a-crc-primary-basic:
    - shard-tglb:         [FAIL][70] ([i915#1483] / [i915#402]) -> [PASS][71]
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb3/igt@kms_ccs@pipe-a-crc-primary-basic.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb7/igt@kms_ccs@pipe-a-crc-primary-basic.html

  * igt@kms_color@pipe-b-gamma:
    - shard-tglb:         [FAIL][72] ([i915#1149] / [i915#402]) -> [PASS][73] +3 similar issues
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb7/igt@kms_color@pipe-b-gamma.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb3/igt@kms_color@pipe-b-gamma.html

  * igt@kms_color@pipe-d-ctm-blue-to-red:
    - shard-tglb:         [FAIL][74] ([i915#1149]) -> [PASS][75] +3 similar issues
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb6/igt@kms_color@pipe-d-ctm-blue-to-red.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb2/igt@kms_color@pipe-d-ctm-blue-to-red.html

  * igt@kms_cursor_crc@pipe-a-cursor-64x21-random:
    - shard-kbl:          [FAIL][76] ([i915#54] / [i915#93] / [i915#95]) -> [PASS][77] +1 similar issue
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-64x21-random.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-64x21-random.html

  * igt@kms_cursor_crc@pipe-b-cursor-suspend:
    - shard-apl:          [DMESG-WARN][78] ([i915#180]) -> [PASS][79] +3 similar issues
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-apl8/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-apl1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-d-cursor-64x21-offscreen:
    - shard-tglb:         [FAIL][80] ([i915#1897] / [i915#402]) -> [PASS][81] +3 similar issues
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-64x21-offscreen.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb2/igt@kms_cursor_crc@pipe-d-cursor-64x21-offscreen.html

  * igt@kms_cursor_crc@pipe-d-cursor-alpha-opaque:
    - shard-tglb:         [FAIL][82] ([i915#1897]) -> [PASS][83] +66 similar issues
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb3/igt@kms_cursor_crc@pipe-d-cursor-alpha-opaque.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb3/igt@kms_cursor_crc@pipe-d-cursor-alpha-opaque.html

  * igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
    - shard-tglb:         [FAIL][84] ([IGT#5] / [i915#402]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb7/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb1/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html

  * igt@kms_draw_crc@draw-method-rgb565-render-xtiled:
    - shard-snb:          [SKIP][86] ([fdo#109271]) -> [PASS][87] +3 similar issues
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-snb4/igt@kms_draw_crc@draw-method-rgb565-render-xtiled.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-snb1/igt@kms_draw_crc@draw-method-rgb565-render-xtiled.html

  * igt@kms_draw_crc@fill-fb:
    - shard-apl:          [FAIL][88] ([i915#95]) -> [PASS][89]
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-apl6/igt@kms_draw_crc@fill-fb.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-apl8/igt@kms_draw_crc@fill-fb.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-tglb:         [FAIL][90] ([i915#64]) -> [PASS][91]
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb6/igt@kms_fbcon_fbt@fbc-suspend.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb8/igt@kms_fbcon_fbt@fbc-suspend.html

  * {igt@kms_flip@flip-vs-suspend@a-dp1}:
    - shard-kbl:          [DMESG-WARN][92] ([i915#180]) -> [PASS][93] +5 similar issues
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-kbl7/igt@kms_flip@flip-vs-suspend@a-dp1.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-kbl1/igt@kms_flip@flip-vs-suspend@a-dp1.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
    - shard-tglb:         [FAIL][94] ([i915#402]) -> [PASS][95] +69 similar issues
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-farfromfence:
    - shard-tglb:         [SKIP][96] ([i915#668]) -> [PASS][97] +18 similar issues
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb6/igt@kms_frontbuffer_tracking@psr-farfromfence.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb7/igt@kms_frontbuffer_tracking@psr-farfromfence.html

  * igt@kms_mmap_write_crc@main:
    - shard-tglb:         [FAIL][98] ([i915#1180] / [i915#402]) -> [PASS][99]
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb5/igt@kms_mmap_write_crc@main.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb6/igt@kms_mmap_write_crc@main.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-iclb:         [FAIL][100] ([i915#1757]) -> [PASS][101]
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-iclb3/igt@kms_panel_fitting@atomic-fastset.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-iclb5/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - shard-kbl:          [INCOMPLETE][102] ([i915#155]) -> [PASS][103]
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-tglb:         [FAIL][104] -> [PASS][105]
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-apl:          [FAIL][106] ([fdo#108145] / [i915#265] / [i915#95]) -> [PASS][107]
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-apl8/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html

  * igt@kms_plane_cursor@pipe-a-overlay-size-256:
    - shard-kbl:          [FAIL][108] ([i915#1559] / [i915#93] / [i915#95]) -> [PASS][109]
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-kbl3/igt@kms_plane_cursor@pipe-a-overlay-size-256.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-kbl7/igt@kms_plane_cursor@pipe-a-overlay-size-256.html
    - shard-apl:          [FAIL][110] ([i915#1559] / [i915#95]) -> [PASS][111]
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-apl1/igt@kms_plane_cursor@pipe-a-overlay-size-256.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-apl7/igt@kms_plane_cursor@pipe-a-overlay-size-256.html

  * igt@kms_plane_cursor@pipe-a-primary-size-256:
    - shard-glk:          [FAIL][112] ([i915#1559]) -> [PASS][113]
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-glk9/igt@kms_plane_cursor@pipe-a-primary-size-256.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-glk4/igt@kms_plane_cursor@pipe-a-primary-size-256.html

  * igt@kms_plane_lowres@pipe-c-tiling-none:
    - shard-tglb:         [FAIL][114] ([i915#899]) -> [PASS][115] +2 similar issues
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb7/igt@kms_plane_lowres@pipe-c-tiling-none.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb5/igt@kms_plane_lowres@pipe-c-tiling-none.html

  * igt@kms_psr@psr2_cursor_plane_move:
    - shard-iclb:         [SKIP][116] ([fdo#109441]) -> [PASS][117]
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-iclb7/igt@kms_psr@psr2_cursor_plane_move.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html

  
#### Warnings ####

  * igt@i915_pm_dc@dc6-psr:
    - shard-tglb:         [SKIP][118] ([i915#468]) -> [SKIP][119] ([i915#668])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb2/igt@i915_pm_dc@dc6-psr.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb6/igt@i915_pm_dc@dc6-psr.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-180:
    - shard-tglb:         [FAIL][120] ([i915#1172]) -> [FAIL][121] ([i915#1172] / [i915#402])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb8/igt@kms_big_fb@x-tiled-8bpp-rotate-180.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb8/igt@kms_big_fb@x-tiled-8bpp-rotate-180.html

  * igt@kms_color@pipe-a-degamma:
    - shard-tglb:         [FAIL][122] ([i915#1149]) -> [FAIL][123] ([i915#1149] / [i915#402]) +1 similar issue
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb1/igt@kms_color@pipe-a-degamma.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb3/igt@kms_color@pipe-a-degamma.html

  * igt@kms_color@pipe-b-ctm-blue-to-red:
    - shard-tglb:         [FAIL][124] ([i915#1149] / [i915#402]) -> [FAIL][125] ([i915#1149]) +1 similar issue
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb8/igt@kms_color@pipe-b-ctm-blue-to-red.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb3/igt@kms_color@pipe-b-ctm-blue-to-red.html

  * igt@kms_content_protection@atomic:
    - shard-apl:          [TIMEOUT][126] ([i915#1319]) -> [DMESG-FAIL][127] ([fdo#110321])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-apl3/igt@kms_content_protection@atomic.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-apl8/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-apl:          [FAIL][128] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][129] ([i915#1319])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-apl8/igt@kms_content_protection@atomic-dpms.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-apl3/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@legacy:
    - shard-apl:          [TIMEOUT][130] ([i915#1319]) -> [FAIL][131] ([fdo#110321] / [fdo#110336])
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-apl1/igt@kms_content_protection@legacy.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-apl7/igt@kms_content_protection@legacy.html

  * igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque:
    - shard-tglb:         [FAIL][132] ([i915#1897]) -> [FAIL][133] ([i915#1897] / [i915#402]) +11 similar issues
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb8/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb1/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-apl:          [FAIL][134] ([i915#1121] / [i915#95]) -> [DMESG-FAIL][135] ([i915#180] / [i915#95])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-apl4/igt@kms_fbcon_fbt@fbc-suspend.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-apl4/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-tglb:         [SKIP][136] ([i915#668]) -> [FAIL][137] ([i915#402]) +3 similar issues
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
    - shard-tglb:         [FAIL][138] ([i915#402]) -> [SKIP][139] ([i915#668]) +2 similar issues
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt:
    - shard-tglb:         [SKIP][140] ([i915#668]) -> [FAIL][141] ([i915#1897])
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-suspend:
    - shard-tglb:         [FAIL][142] ([i915#1897]) -> [SKIP][143] ([i915#668])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb3/igt@kms_frontbuffer_tracking@psr-suspend.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb5/igt@kms_frontbuffer_tracking@psr-suspend.html

  * igt@kms_plane@plane-position-hole-dpms-pipe-d-planes:
    - shard-tglb:         [FAIL][144] ([i915#1897] / [i915#402]) -> [FAIL][145] ([i915#1897]) +3 similar issues
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb7/igt@kms_plane@plane-position-hole-dpms-pipe-d-planes.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb8/igt@kms_plane@plane-position-hole-dpms-pipe-d-planes.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
    - shard-apl:          [FAIL][146] ([fdo#108145] / [i915#265]) -> [FAIL][147] ([fdo#108145] / [i915#265] / [i915#95])
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-apl2/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
    - shard-kbl:          [FAIL][148] ([fdo#108145] / [i915#265] / [i915#93] / [i915#95]) -> [FAIL][149] ([fdo#108145] / [i915#265])
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-kbl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-kbl3/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
    - shard-apl:          [FAIL][150] ([fdo#108145] / [i915#265] / [i915#95]) -> [FAIL][151] ([fdo#108145] / [i915#265])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-apl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-apl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html

  * igt@kms_plane_lowres@pipe-b-tiling-x:
    - shard-tglb:         [FAIL][152] ([i915#899]) -> [FAIL][153] ([i915#402] / [i915#899])
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb8/igt@kms_plane_lowres@pipe-b-tiling-x.html
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/shard-tglb6/igt@kms_plane_lowres@pipe-b-tiling-x.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://b

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4575/index.html
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