From: Anup Patel <anup.patel@wdc.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>, Marc Zyngier <maz@kernel.org> Cc: Atish Patra <atish.patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel <anup.patel@wdc.com>, stable@vger.kernel.org Subject: [PATCH v2 1/3] irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map() Date: Mon, 18 May 2020 14:44:39 +0530 [thread overview] Message-ID: <20200518091441.94843-2-anup.patel@wdc.com> (raw) In-Reply-To: <20200518091441.94843-1-anup.patel@wdc.com> For multiple PLIC instances, each PLIC can only target a subset of CPUs which is represented by "lmask" in the "struct plic_priv". Currently, the default irq affinity for each PLIC interrupt is all online CPUs which is illegal value for default irq affinity when we have multiple PLIC instances. To fix this, we now set "lmask" as the default irq affinity in for each interrupt in plic_irqdomain_map(). Fixes: f1ad1133b18f ("irqchip/sifive-plic: Add support for multiple PLICs") Cc: stable@vger.kernel.org Signed-off-by: Anup Patel <anup.patel@wdc.com> --- drivers/irqchip/irq-sifive-plic.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 822e074c0600..9f7f8ce88c00 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -176,9 +176,12 @@ static struct irq_chip plic_chip = { static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) { + struct plic_priv *priv = d->host_data; + irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data, handle_fasteoi_irq, NULL, NULL); irq_set_noprobe(irq); + irq_set_affinity(irq, &priv->lmask); return 0; } -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup.patel@wdc.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>, Marc Zyngier <maz@kernel.org> Cc: Anup Patel <anup@brainfault.org>, Anup Patel <anup.patel@wdc.com>, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Atish Patra <atish.patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, linux-riscv@lists.infradead.org Subject: [PATCH v2 1/3] irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map() Date: Mon, 18 May 2020 14:44:39 +0530 [thread overview] Message-ID: <20200518091441.94843-2-anup.patel@wdc.com> (raw) In-Reply-To: <20200518091441.94843-1-anup.patel@wdc.com> For multiple PLIC instances, each PLIC can only target a subset of CPUs which is represented by "lmask" in the "struct plic_priv". Currently, the default irq affinity for each PLIC interrupt is all online CPUs which is illegal value for default irq affinity when we have multiple PLIC instances. To fix this, we now set "lmask" as the default irq affinity in for each interrupt in plic_irqdomain_map(). Fixes: f1ad1133b18f ("irqchip/sifive-plic: Add support for multiple PLICs") Cc: stable@vger.kernel.org Signed-off-by: Anup Patel <anup.patel@wdc.com> --- drivers/irqchip/irq-sifive-plic.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 822e074c0600..9f7f8ce88c00 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -176,9 +176,12 @@ static struct irq_chip plic_chip = { static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) { + struct plic_priv *priv = d->host_data; + irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data, handle_fasteoi_irq, NULL, NULL); irq_set_noprobe(irq); + irq_set_affinity(irq, &priv->lmask); return 0; } -- 2.25.1
next prev parent reply other threads:[~2020-05-18 9:15 UTC|newest] Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-05-18 9:14 [PATCH v2 0/3] More improvements for multiple PLICs Anup Patel 2020-05-18 9:14 ` Anup Patel 2020-05-18 9:14 ` Anup Patel [this message] 2020-05-18 9:14 ` [PATCH v2 1/3] irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map() Anup Patel 2020-05-21 22:06 ` Palmer Dabbelt 2020-05-21 22:06 ` Palmer Dabbelt 2020-05-22 6:44 ` Anup Patel 2020-05-22 6:44 ` Anup Patel 2020-05-30 7:46 ` [tip: irq/core] " tip-bot2 for Anup Patel 2020-05-18 9:14 ` [PATCH v2 2/3] irqchip/sifive-plic: Setup cpuhp once after boot CPU handler is present Anup Patel 2020-05-18 9:14 ` Anup Patel 2020-05-21 22:06 ` Palmer Dabbelt 2020-05-21 22:06 ` Palmer Dabbelt 2020-05-22 6:46 ` Anup Patel 2020-05-22 6:46 ` Anup Patel 2020-05-30 7:46 ` [tip: irq/core] " tip-bot2 for Anup Patel 2020-05-18 9:14 ` [PATCH v2 3/3] irqchip/sifive-plic: Improve boot prints for multiple PLIC instances Anup Patel 2020-05-18 9:14 ` Anup Patel 2020-05-21 22:06 ` Palmer Dabbelt 2020-05-21 22:06 ` Palmer Dabbelt 2020-05-30 7:46 ` [tip: irq/core] " tip-bot2 for Anup Patel 2020-05-21 22:06 ` [PATCH v2 0/3] More improvements for multiple PLICs Palmer Dabbelt 2020-05-21 22:06 ` Palmer Dabbelt 2020-05-25 10:08 ` Marc Zyngier 2020-05-25 10:08 ` Marc Zyngier
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