* [PATCH v6 01/21] target/mips: fpu: Demacro ADD.<D|S|PS>
2020-05-18 20:08 [PATCH v6 00/21] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
@ 2020-05-18 20:09 ` Aleksandar Markovic
2020-05-18 20:09 ` [PATCH v6 02/21] target/mips: fpu: Demacro SUB.<D|S|PS> Aleksandar Markovic
` (19 subsequent siblings)
20 siblings, 0 replies; 29+ messages in thread
From: Aleksandar Markovic @ 2020-05-18 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
This is just a cosmetic change to enable tools like gcov, gdb,
callgrind, etc. to better display involved source code.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 38 +++++++++++++++++++++++++++++++++++++-
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index 5287c86c61..984f3f4dfb 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1208,12 +1208,48 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
return ((uint64_t)wth2 << 32) | wt2; \
}
-FLOAT_BINOP(add)
FLOAT_BINOP(sub)
FLOAT_BINOP(mul)
FLOAT_BINOP(div)
#undef FLOAT_BINOP
+uint64_t helper_float_add_d(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint64_t dt2;
+
+ dt2 = float64_add(fdt0, fdt1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint32_t helper_float_add_s(CPUMIPSState *env,
+ uint32_t fst0, uint32_t fst1)
+{
+ uint32_t wt2;
+
+ wt2 = float32_sub(fst0, fst1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return wt2;
+}
+
+uint64_t helper_float_add_ps(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t wtl2;
+ uint32_t wth2;
+
+ wtl2 = float32_add(fstl0, fstl1, &env->active_fpu.fp_status);
+ wth2 = float32_add(fsth0, fsth1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return ((uint64_t)wth2 << 32) | wtl2;
+}
+
+
/* MIPS specific binary operations */
uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
{
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v6 02/21] target/mips: fpu: Demacro SUB.<D|S|PS>
2020-05-18 20:08 [PATCH v6 00/21] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
2020-05-18 20:09 ` [PATCH v6 01/21] target/mips: fpu: Demacro ADD.<D|S|PS> Aleksandar Markovic
@ 2020-05-18 20:09 ` Aleksandar Markovic
2020-05-18 20:09 ` [PATCH v6 03/21] target/mips: fpu: Demacro MUL.<D|S|PS> Aleksandar Markovic
` (18 subsequent siblings)
20 siblings, 0 replies; 29+ messages in thread
From: Aleksandar Markovic @ 2020-05-18 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
This is just a cosmetic change to enable tools like gcov, gdb,
callgrind, etc. to better display involved source code.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 37 ++++++++++++++++++++++++++++++++++++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index 984f3f4dfb..715a872cae 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1208,7 +1208,6 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
return ((uint64_t)wth2 << 32) | wt2; \
}
-FLOAT_BINOP(sub)
FLOAT_BINOP(mul)
FLOAT_BINOP(div)
#undef FLOAT_BINOP
@@ -1249,6 +1248,42 @@ uint64_t helper_float_add_ps(CPUMIPSState *env,
return ((uint64_t)wth2 << 32) | wtl2;
}
+uint64_t helper_float_sub_d(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint64_t dt2;
+
+ dt2 = float64_sub(fdt0, fdt1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint32_t helper_float_sub_s(CPUMIPSState *env,
+ uint32_t fst0, uint32_t fst1)
+{
+ uint32_t wt2;
+
+ wt2 = float32_sub(fst0, fst1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return wt2;
+}
+
+uint64_t helper_float_sub_ps(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t wtl2;
+ uint32_t wth2;
+
+ wtl2 = float32_sub(fstl0, fstl1, &env->active_fpu.fp_status);
+ wth2 = float32_sub(fsth0, fsth1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return ((uint64_t)wth2 << 32) | wtl2;
+}
+
/* MIPS specific binary operations */
uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v6 03/21] target/mips: fpu: Demacro MUL.<D|S|PS>
2020-05-18 20:08 [PATCH v6 00/21] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
2020-05-18 20:09 ` [PATCH v6 01/21] target/mips: fpu: Demacro ADD.<D|S|PS> Aleksandar Markovic
2020-05-18 20:09 ` [PATCH v6 02/21] target/mips: fpu: Demacro SUB.<D|S|PS> Aleksandar Markovic
@ 2020-05-18 20:09 ` Aleksandar Markovic
2020-05-18 20:09 ` [PATCH v6 04/21] target/mips: fpu: Demacro DIV.<D|S|PS> Aleksandar Markovic
` (17 subsequent siblings)
20 siblings, 0 replies; 29+ messages in thread
From: Aleksandar Markovic @ 2020-05-18 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
This is just a cosmetic change to enable tools like gcov, gdb,
callgrind, etc. to better display involved source code.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 37 ++++++++++++++++++++++++++++++++++++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index 715a872cae..449e945166 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1208,7 +1208,6 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
return ((uint64_t)wth2 << 32) | wt2; \
}
-FLOAT_BINOP(mul)
FLOAT_BINOP(div)
#undef FLOAT_BINOP
@@ -1284,6 +1283,42 @@ uint64_t helper_float_sub_ps(CPUMIPSState *env,
return ((uint64_t)wth2 << 32) | wtl2;
}
+uint64_t helper_float_mul_d(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint64_t dt2;
+
+ dt2 = float64_mul(fdt0, fdt1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint32_t helper_float_mul_s(CPUMIPSState *env,
+ uint32_t fst0, uint32_t fst1)
+{
+ uint32_t wt2;
+
+ wt2 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return wt2;
+}
+
+uint64_t helper_float_mul_ps(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t wtl2;
+ uint32_t wth2;
+
+ wtl2 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
+ wth2 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return ((uint64_t)wth2 << 32) | wtl2;
+}
+
/* MIPS specific binary operations */
uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v6 04/21] target/mips: fpu: Demacro DIV.<D|S|PS>
2020-05-18 20:08 [PATCH v6 00/21] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (2 preceding siblings ...)
2020-05-18 20:09 ` [PATCH v6 03/21] target/mips: fpu: Demacro MUL.<D|S|PS> Aleksandar Markovic
@ 2020-05-18 20:09 ` Aleksandar Markovic
2020-05-18 20:09 ` [PATCH v6 05/21] target/mips: fpu: Remove now unused macro FLOAT_BINOP Aleksandar Markovic
` (16 subsequent siblings)
20 siblings, 0 replies; 29+ messages in thread
From: Aleksandar Markovic @ 2020-05-18 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
This is just a cosmetic change to enable tools like gcov, gdb,
callgrind, etc. to better display involved source code.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 37 ++++++++++++++++++++++++++++++++++++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index 449e945166..2759c9989d 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1208,7 +1208,6 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
return ((uint64_t)wth2 << 32) | wt2; \
}
-FLOAT_BINOP(div)
#undef FLOAT_BINOP
uint64_t helper_float_add_d(CPUMIPSState *env,
@@ -1319,6 +1318,42 @@ uint64_t helper_float_mul_ps(CPUMIPSState *env,
return ((uint64_t)wth2 << 32) | wtl2;
}
+uint64_t helper_float_div_d(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint64_t dt2;
+
+ dt2 = float64_div(fdt0, fdt1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint32_t helper_float_div_s(CPUMIPSState *env,
+ uint32_t fst0, uint32_t fst1)
+{
+ uint32_t wt2;
+
+ wt2 = float32_div(fst0, fst1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return wt2;
+}
+
+uint64_t helper_float_div_ps(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t wtl2;
+ uint32_t wth2;
+
+ wtl2 = float32_div(fstl0, fstl1, &env->active_fpu.fp_status);
+ wth2 = float32_div(fsth0, fsth1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return ((uint64_t)wth2 << 32) | wtl2;
+}
+
/* MIPS specific binary operations */
uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v6 05/21] target/mips: fpu: Remove now unused macro FLOAT_BINOP
2020-05-18 20:08 [PATCH v6 00/21] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (3 preceding siblings ...)
2020-05-18 20:09 ` [PATCH v6 04/21] target/mips: fpu: Demacro DIV.<D|S|PS> Aleksandar Markovic
@ 2020-05-18 20:09 ` Aleksandar Markovic
2020-05-18 20:09 ` [PATCH v6 06/21] target/mips: fpu: Demacro MADD.<D|S|PS> Aleksandar Markovic
` (15 subsequent siblings)
20 siblings, 0 replies; 29+ messages in thread
From: Aleksandar Markovic @ 2020-05-18 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
After demacroing <ADD|SUB|MUL|DIV>.<D|S|PS>, this macro is not
needed anymore.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 39 ---------------------------------------
1 file changed, 39 deletions(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index 2759c9989d..a3a39681f8 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1170,45 +1170,6 @@ FLOAT_CLASS(class_d, 64)
#undef FLOAT_CLASS
/* binary operations */
-#define FLOAT_BINOP(name) \
-uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
- uint64_t fdt0, uint64_t fdt1) \
-{ \
- uint64_t dt2; \
- \
- dt2 = float64_ ## name(fdt0, fdt1, &env->active_fpu.fp_status);\
- update_fcr31(env, GETPC()); \
- return dt2; \
-} \
- \
-uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
- uint32_t fst0, uint32_t fst1) \
-{ \
- uint32_t wt2; \
- \
- wt2 = float32_ ## name(fst0, fst1, &env->active_fpu.fp_status);\
- update_fcr31(env, GETPC()); \
- return wt2; \
-} \
- \
-uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
- uint64_t fdt0, \
- uint64_t fdt1) \
-{ \
- uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
- uint32_t fsth0 = fdt0 >> 32; \
- uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
- uint32_t fsth1 = fdt1 >> 32; \
- uint32_t wt2; \
- uint32_t wth2; \
- \
- wt2 = float32_ ## name(fst0, fst1, &env->active_fpu.fp_status); \
- wth2 = float32_ ## name(fsth0, fsth1, &env->active_fpu.fp_status); \
- update_fcr31(env, GETPC()); \
- return ((uint64_t)wth2 << 32) | wt2; \
-}
-
-#undef FLOAT_BINOP
uint64_t helper_float_add_d(CPUMIPSState *env,
uint64_t fdt0, uint64_t fdt1)
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v6 06/21] target/mips: fpu: Demacro MADD.<D|S|PS>
2020-05-18 20:08 [PATCH v6 00/21] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (4 preceding siblings ...)
2020-05-18 20:09 ` [PATCH v6 05/21] target/mips: fpu: Remove now unused macro FLOAT_BINOP Aleksandar Markovic
@ 2020-05-18 20:09 ` Aleksandar Markovic
2020-05-18 20:09 ` [PATCH v6 07/21] target/mips: fpu: Demacro MSUB.<D|S|PS> Aleksandar Markovic
` (14 subsequent siblings)
20 siblings, 0 replies; 29+ messages in thread
From: Aleksandar Markovic @ 2020-05-18 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
This is just a cosmetic change to enable tools like gcov, gdb,
callgrind, etc. to better display involved source code.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 41 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index a3a39681f8..c070081cbc 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1495,12 +1495,51 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
update_fcr31(env, GETPC()); \
return ((uint64_t)fsth0 << 32) | fst0; \
}
-FLOAT_FMA(madd, 0)
FLOAT_FMA(msub, float_muladd_negate_c)
FLOAT_FMA(nmadd, float_muladd_negate_result)
FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
#undef FLOAT_FMA
+uint64_t helper_float_madd_d(CPUMIPSState *env, uint64_t fst0,
+ uint64_t fst1, uint64_t fst2)
+{
+ fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float64_add(fst0, fst2, &env->active_fpu.fp_status);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint32_t helper_float_madd_s(CPUMIPSState *env, uint32_t fst0,
+ uint32_t fst1, uint32_t fst2)
+{
+ fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float32_add(fst0, fst2, &env->active_fpu.fp_status);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint64_t helper_float_madd_ps(CPUMIPSState *env, uint64_t fdt0,
+ uint64_t fdt1, uint64_t fdt2)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
+ uint32_t fsth2 = fdt2 >> 32;
+
+ fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
+ fstl0 = float32_add(fstl0, fstl2, &env->active_fpu.fp_status);
+ fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
+ fsth0 = float32_add(fsth0, fsth2, &env->active_fpu.fp_status);
+
+ update_fcr31(env, GETPC());
+ return ((uint64_t)fsth0 << 32) | fstl0;
+}
+
+
#define FLOAT_FMADDSUB(name, bits, muladd_arg) \
uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
uint ## bits ## _t fs, \
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v6 07/21] target/mips: fpu: Demacro MSUB.<D|S|PS>
2020-05-18 20:08 [PATCH v6 00/21] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (5 preceding siblings ...)
2020-05-18 20:09 ` [PATCH v6 06/21] target/mips: fpu: Demacro MADD.<D|S|PS> Aleksandar Markovic
@ 2020-05-18 20:09 ` Aleksandar Markovic
2020-05-18 20:09 ` [PATCH v6 08/21] target/mips: fpu: Demacro NMADD.<D|S|PS> Aleksandar Markovic
` (13 subsequent siblings)
20 siblings, 0 replies; 29+ messages in thread
From: Aleksandar Markovic @ 2020-05-18 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
This is just a cosmetic change to enable tools like gcov, gdb,
callgrind, etc. to better display involved source code.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 40 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index c070081cbc..e37fc4075d 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1495,7 +1495,6 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
update_fcr31(env, GETPC()); \
return ((uint64_t)fsth0 << 32) | fst0; \
}
-FLOAT_FMA(msub, float_muladd_negate_c)
FLOAT_FMA(nmadd, float_muladd_negate_result)
FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
#undef FLOAT_FMA
@@ -1539,6 +1538,45 @@ uint64_t helper_float_madd_ps(CPUMIPSState *env, uint64_t fdt0,
return ((uint64_t)fsth0 << 32) | fstl0;
}
+uint64_t helper_float_msub_d(CPUMIPSState *env, uint64_t fst0,
+ uint64_t fst1, uint64_t fst2)
+{
+ fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float64_sub(fst0, fst2, &env->active_fpu.fp_status);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint32_t helper_float_msub_s(CPUMIPSState *env, uint32_t fst0,
+ uint32_t fst1, uint32_t fst2)
+{
+ fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float32_sub(fst0, fst2, &env->active_fpu.fp_status);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint64_t helper_float_msub_ps(CPUMIPSState *env, uint64_t fdt0,
+ uint64_t fdt1, uint64_t fdt2)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
+ uint32_t fsth2 = fdt2 >> 32;
+
+ fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
+ fstl0 = float32_sub(fstl0, fstl2, &env->active_fpu.fp_status);
+ fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
+ fsth0 = float32_sub(fsth0, fsth2, &env->active_fpu.fp_status);
+
+ update_fcr31(env, GETPC());
+ return ((uint64_t)fsth0 << 32) | fstl0;
+}
+
#define FLOAT_FMADDSUB(name, bits, muladd_arg) \
uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v6 08/21] target/mips: fpu: Demacro NMADD.<D|S|PS>
2020-05-18 20:08 [PATCH v6 00/21] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (6 preceding siblings ...)
2020-05-18 20:09 ` [PATCH v6 07/21] target/mips: fpu: Demacro MSUB.<D|S|PS> Aleksandar Markovic
@ 2020-05-18 20:09 ` Aleksandar Markovic
2020-05-18 20:09 ` [PATCH v6 09/21] target/mips: fpu: Demacro NMSUB.<D|S|PS> Aleksandar Markovic
` (12 subsequent siblings)
20 siblings, 0 replies; 29+ messages in thread
From: Aleksandar Markovic @ 2020-05-18 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
This is just a cosmetic change to enable tools like gcov, gdb,
callgrind, etc. to better display involved source code.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 44 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index e37fc4075d..d4c065f281 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1495,7 +1495,6 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
update_fcr31(env, GETPC()); \
return ((uint64_t)fsth0 << 32) | fst0; \
}
-FLOAT_FMA(nmadd, float_muladd_negate_result)
FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
#undef FLOAT_FMA
@@ -1577,6 +1576,49 @@ uint64_t helper_float_msub_ps(CPUMIPSState *env, uint64_t fdt0,
return ((uint64_t)fsth0 << 32) | fstl0;
}
+uint64_t helper_float_nmadd_d(CPUMIPSState *env, uint64_t fst0,
+ uint64_t fst1, uint64_t fst2)
+{
+ fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float64_add(fst0, fst2, &env->active_fpu.fp_status);
+ fst0 = float64_chs(fst0);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint32_t helper_float_nmadd_s(CPUMIPSState *env, uint32_t fst0,
+ uint32_t fst1, uint32_t fst2)
+{
+ fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float32_add(fst0, fst2, &env->active_fpu.fp_status);
+ fst0 = float32_chs(fst0);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint64_t helper_float_nmadd_ps(CPUMIPSState *env, uint64_t fdt0,
+ uint64_t fdt1, uint64_t fdt2)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
+ uint32_t fsth2 = fdt2 >> 32;
+
+ fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
+ fstl0 = float32_add(fstl0, fstl2, &env->active_fpu.fp_status);
+ fstl0 = float32_chs(fstl0);
+ fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
+ fsth0 = float32_add(fsth0, fsth2, &env->active_fpu.fp_status);
+ fsth0 = float32_chs(fsth0);
+
+ update_fcr31(env, GETPC());
+ return ((uint64_t)fsth0 << 32) | fstl0;
+}
+
#define FLOAT_FMADDSUB(name, bits, muladd_arg) \
uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v6 09/21] target/mips: fpu: Demacro NMSUB.<D|S|PS>
2020-05-18 20:08 [PATCH v6 00/21] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (7 preceding siblings ...)
2020-05-18 20:09 ` [PATCH v6 08/21] target/mips: fpu: Demacro NMADD.<D|S|PS> Aleksandar Markovic
@ 2020-05-18 20:09 ` Aleksandar Markovic
2020-05-18 20:09 ` [PATCH v6 10/21] target/mips: fpu: Remove now unused UNFUSED_FMA and FLOAT_FMA macros Aleksandar Markovic
` (11 subsequent siblings)
20 siblings, 0 replies; 29+ messages in thread
From: Aleksandar Markovic @ 2020-05-18 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
This is just a cosmetic change to enable tools like gcov, gdb,
callgrind, etc. to better display involved source code.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 44 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index d4c065f281..927bac24ac 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1495,7 +1495,6 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
update_fcr31(env, GETPC()); \
return ((uint64_t)fsth0 << 32) | fst0; \
}
-FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
#undef FLOAT_FMA
uint64_t helper_float_madd_d(CPUMIPSState *env, uint64_t fst0,
@@ -1619,6 +1618,49 @@ uint64_t helper_float_nmadd_ps(CPUMIPSState *env, uint64_t fdt0,
return ((uint64_t)fsth0 << 32) | fstl0;
}
+uint64_t helper_float_nmsub_d(CPUMIPSState *env, uint64_t fst0,
+ uint64_t fst1, uint64_t fst2)
+{
+ fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float64_sub(fst0, fst2, &env->active_fpu.fp_status);
+ fst0 = float64_chs(fst0);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint32_t helper_float_nmsub_s(CPUMIPSState *env, uint32_t fst0,
+ uint32_t fst1, uint32_t fst2)
+{
+ fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float32_sub(fst0, fst2, &env->active_fpu.fp_status);
+ fst0 = float32_chs(fst0);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint64_t helper_float_nmsub_ps(CPUMIPSState *env, uint64_t fdt0,
+ uint64_t fdt1, uint64_t fdt2)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
+ uint32_t fsth2 = fdt2 >> 32;
+
+ fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
+ fstl0 = float32_sub(fstl0, fstl2, &env->active_fpu.fp_status);
+ fstl0 = float32_chs(fstl0);
+ fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
+ fsth0 = float32_sub(fsth0, fsth2, &env->active_fpu.fp_status);
+ fsth0 = float32_chs(fsth0);
+
+ update_fcr31(env, GETPC());
+ return ((uint64_t)fsth0 << 32) | fstl0;
+}
+
#define FLOAT_FMADDSUB(name, bits, muladd_arg) \
uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v6 10/21] target/mips: fpu: Remove now unused UNFUSED_FMA and FLOAT_FMA macros
2020-05-18 20:08 [PATCH v6 00/21] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (8 preceding siblings ...)
2020-05-18 20:09 ` [PATCH v6 09/21] target/mips: fpu: Demacro NMSUB.<D|S|PS> Aleksandar Markovic
@ 2020-05-18 20:09 ` Aleksandar Markovic
2020-05-18 20:09 ` [PATCH v6 11/21] target/mips: fpu: Demacro CLASS.<D|S> Aleksandar Markovic
` (10 subsequent siblings)
20 siblings, 0 replies; 29+ messages in thread
From: Aleksandar Markovic @ 2020-05-18 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
After demacroing <MADD|MSUB|NMADD|NMSUB>.<D|S|PS>, these macros
are not needed anymore.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 50 ----------------------------------------
1 file changed, 50 deletions(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index 927bac24ac..e8e50e4bc0 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1446,56 +1446,6 @@ FLOAT_MINMAX(mina_d, 64, minnummag)
#undef FLOAT_MINMAX
/* ternary operations */
-#define UNFUSED_FMA(prefix, a, b, c, flags) \
-{ \
- a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
- if ((flags) & float_muladd_negate_c) { \
- a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
- } else { \
- a = prefix##_add(a, c, &env->active_fpu.fp_status); \
- } \
- if ((flags) & float_muladd_negate_result) { \
- a = prefix##_chs(a); \
- } \
-}
-
-/* FMA based operations */
-#define FLOAT_FMA(name, type) \
-uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
- uint64_t fdt0, uint64_t fdt1, \
- uint64_t fdt2) \
-{ \
- UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
- update_fcr31(env, GETPC()); \
- return fdt0; \
-} \
- \
-uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
- uint32_t fst0, uint32_t fst1, \
- uint32_t fst2) \
-{ \
- UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
- update_fcr31(env, GETPC()); \
- return fst0; \
-} \
- \
-uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
- uint64_t fdt0, uint64_t fdt1, \
- uint64_t fdt2) \
-{ \
- uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
- uint32_t fsth0 = fdt0 >> 32; \
- uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
- uint32_t fsth1 = fdt1 >> 32; \
- uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
- uint32_t fsth2 = fdt2 >> 32; \
- \
- UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
- UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
- update_fcr31(env, GETPC()); \
- return ((uint64_t)fsth0 << 32) | fst0; \
-}
-#undef FLOAT_FMA
uint64_t helper_float_madd_d(CPUMIPSState *env, uint64_t fst0,
uint64_t fst1, uint64_t fst2)
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v6 11/21] target/mips: fpu: Demacro CLASS.<D|S>
2020-05-18 20:08 [PATCH v6 00/21] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (9 preceding siblings ...)
2020-05-18 20:09 ` [PATCH v6 10/21] target/mips: fpu: Remove now unused UNFUSED_FMA and FLOAT_FMA macros Aleksandar Markovic
@ 2020-05-18 20:09 ` Aleksandar Markovic
2020-05-18 20:09 ` [PATCH v6 12/21] target/mips: fpu: Remove now unused FLOAT_CLASS macro Aleksandar Markovic
` (9 subsequent siblings)
20 siblings, 0 replies; 29+ messages in thread
From: Aleksandar Markovic @ 2020-05-18 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
This is just a cosmetic change to enable tools like gcov, gdb,
callgrind, etc. to better display involved source code.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 70 ++++++++++++++++++++++++++++++++++++++--
1 file changed, 68 insertions(+), 2 deletions(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index e8e50e4bc0..b3903f5357 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1165,10 +1165,76 @@ uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
return float_ ## name(arg, &env->active_fpu.fp_status); \
}
-FLOAT_CLASS(class_s, 32)
-FLOAT_CLASS(class_d, 64)
#undef FLOAT_CLASS
+uint64_t float_class_d(uint64_t arg, float_status *status)
+{
+ if (float64_is_signaling_nan(arg, status)) {
+ return FLOAT_CLASS_SIGNALING_NAN;
+ } else if (float64_is_quiet_nan(arg, status)) {
+ return FLOAT_CLASS_QUIET_NAN;
+ } else if (float64_is_neg(arg)) {
+ if (float64_is_infinity(arg)) {
+ return FLOAT_CLASS_NEGATIVE_INFINITY;
+ } else if (float64_is_zero(arg)) {
+ return FLOAT_CLASS_NEGATIVE_ZERO;
+ } else if (float64_is_zero_or_denormal(arg)) {
+ return FLOAT_CLASS_NEGATIVE_SUBNORMAL;
+ } else {
+ return FLOAT_CLASS_NEGATIVE_NORMAL;
+ }
+ } else {
+ if (float64_is_infinity(arg)) {
+ return FLOAT_CLASS_POSITIVE_INFINITY;
+ } else if (float64_is_zero(arg)) {
+ return FLOAT_CLASS_POSITIVE_ZERO;
+ } else if (float64_is_zero_or_denormal(arg)) {
+ return FLOAT_CLASS_POSITIVE_SUBNORMAL;
+ } else {
+ return FLOAT_CLASS_POSITIVE_NORMAL;
+ }
+ }
+}
+
+uint64_t helper_float_class_d(CPUMIPSState *env, uint64_t arg)
+{
+ return float_class_d(arg, &env->active_fpu.fp_status);
+}
+
+uint32_t float_class_s(uint32_t arg, float_status *status)
+{
+ if (float32_is_signaling_nan(arg, status)) {
+ return FLOAT_CLASS_SIGNALING_NAN;
+ } else if (float32_is_quiet_nan(arg, status)) {
+ return FLOAT_CLASS_QUIET_NAN;
+ } else if (float32_is_neg(arg)) {
+ if (float32_is_infinity(arg)) {
+ return FLOAT_CLASS_NEGATIVE_INFINITY;
+ } else if (float32_is_zero(arg)) {
+ return FLOAT_CLASS_NEGATIVE_ZERO;
+ } else if (float32_is_zero_or_denormal(arg)) {
+ return FLOAT_CLASS_NEGATIVE_SUBNORMAL;
+ } else {
+ return FLOAT_CLASS_NEGATIVE_NORMAL;
+ }
+ } else {
+ if (float32_is_infinity(arg)) {
+ return FLOAT_CLASS_POSITIVE_INFINITY;
+ } else if (float32_is_zero(arg)) {
+ return FLOAT_CLASS_POSITIVE_ZERO;
+ } else if (float32_is_zero_or_denormal(arg)) {
+ return FLOAT_CLASS_POSITIVE_SUBNORMAL;
+ } else {
+ return FLOAT_CLASS_POSITIVE_NORMAL;
+ }
+ }
+}
+
+uint32_t helper_float_class_s(CPUMIPSState *env, uint32_t arg)
+{
+ return float_class_s(arg, &env->active_fpu.fp_status);
+}
+
/* binary operations */
uint64_t helper_float_add_d(CPUMIPSState *env,
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v6 12/21] target/mips: fpu: Remove now unused FLOAT_CLASS macro
2020-05-18 20:08 [PATCH v6 00/21] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (10 preceding siblings ...)
2020-05-18 20:09 ` [PATCH v6 11/21] target/mips: fpu: Demacro CLASS.<D|S> Aleksandar Markovic
@ 2020-05-18 20:09 ` Aleksandar Markovic
2020-05-18 20:09 ` [PATCH v6 13/21] target/mips: fpu: Demacro RINT.<D|S> Aleksandar Markovic
` (8 subsequent siblings)
20 siblings, 0 replies; 29+ messages in thread
From: Aleksandar Markovic @ 2020-05-18 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
After demacroing CLASS.<D|S>, this macro is not needed anymore.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 39 ---------------------------------------
1 file changed, 39 deletions(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index b3903f5357..e227e53f70 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1128,45 +1128,6 @@ FLOAT_RINT(rint_d, 64)
#define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
#define FLOAT_CLASS_POSITIVE_ZERO 0x200
-#define FLOAT_CLASS(name, bits) \
-uint ## bits ## _t float_ ## name(uint ## bits ## _t arg, \
- float_status *status) \
-{ \
- if (float ## bits ## _is_signaling_nan(arg, status)) { \
- return FLOAT_CLASS_SIGNALING_NAN; \
- } else if (float ## bits ## _is_quiet_nan(arg, status)) { \
- return FLOAT_CLASS_QUIET_NAN; \
- } else if (float ## bits ## _is_neg(arg)) { \
- if (float ## bits ## _is_infinity(arg)) { \
- return FLOAT_CLASS_NEGATIVE_INFINITY; \
- } else if (float ## bits ## _is_zero(arg)) { \
- return FLOAT_CLASS_NEGATIVE_ZERO; \
- } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
- return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
- } else { \
- return FLOAT_CLASS_NEGATIVE_NORMAL; \
- } \
- } else { \
- if (float ## bits ## _is_infinity(arg)) { \
- return FLOAT_CLASS_POSITIVE_INFINITY; \
- } else if (float ## bits ## _is_zero(arg)) { \
- return FLOAT_CLASS_POSITIVE_ZERO; \
- } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
- return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
- } else { \
- return FLOAT_CLASS_POSITIVE_NORMAL; \
- } \
- } \
-} \
- \
-uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
- uint ## bits ## _t arg) \
-{ \
- return float_ ## name(arg, &env->active_fpu.fp_status); \
-}
-
-#undef FLOAT_CLASS
-
uint64_t float_class_d(uint64_t arg, float_status *status)
{
if (float64_is_signaling_nan(arg, status)) {
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v6 13/21] target/mips: fpu: Demacro RINT.<D|S>
2020-05-18 20:08 [PATCH v6 00/21] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (11 preceding siblings ...)
2020-05-18 20:09 ` [PATCH v6 12/21] target/mips: fpu: Remove now unused FLOAT_CLASS macro Aleksandar Markovic
@ 2020-05-18 20:09 ` Aleksandar Markovic
2020-05-18 20:09 ` [PATCH v6 14/21] target/mips: fpu: Remove now unused FLOAT_RINT macro Aleksandar Markovic
` (7 subsequent siblings)
20 siblings, 0 replies; 29+ messages in thread
From: Aleksandar Markovic @ 2020-05-18 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
This is just a cosmetic change to enable tools like gcov, gdb,
callgrind, etc. to better display involved source code.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index e227e53f70..dae1331f23 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1113,10 +1113,26 @@ uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
return fdret; \
}
-FLOAT_RINT(rint_s, 32)
-FLOAT_RINT(rint_d, 64)
#undef FLOAT_RINT
+uint64_t helper_float_rint_d(CPUMIPSState *env, uint64_t fs)
+{
+ uint64_t fdret;
+
+ fdret = float64_round_to_int(fs, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return fdret;
+}
+
+uint32_t helper_float_rint_s(CPUMIPSState *env, uint32_t fs)
+{
+ uint32_t fdret;
+
+ fdret = float32_round_to_int(fs, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return fdret;
+}
+
#define FLOAT_CLASS_SIGNALING_NAN 0x001
#define FLOAT_CLASS_QUIET_NAN 0x002
#define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v6 14/21] target/mips: fpu: Remove now unused FLOAT_RINT macro
2020-05-18 20:08 [PATCH v6 00/21] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (12 preceding siblings ...)
2020-05-18 20:09 ` [PATCH v6 13/21] target/mips: fpu: Demacro RINT.<D|S> Aleksandar Markovic
@ 2020-05-18 20:09 ` Aleksandar Markovic
2020-05-18 20:09 ` [PATCH v6 15/21] target/mips: fpu: Name better paired-single variables Aleksandar Markovic
` (6 subsequent siblings)
20 siblings, 0 replies; 29+ messages in thread
From: Aleksandar Markovic @ 2020-05-18 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
After demacroing RINT.<D|S>, this macro is not needed anymore.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 13 -------------
1 file changed, 13 deletions(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index dae1331f23..56ba49104e 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1102,19 +1102,6 @@ uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
return ((uint64_t)fsth2 << 32) | fst2;
}
-#define FLOAT_RINT(name, bits) \
-uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
- uint ## bits ## _t fs) \
-{ \
- uint ## bits ## _t fdret; \
- \
- fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
- update_fcr31(env, GETPC()); \
- return fdret; \
-}
-
-#undef FLOAT_RINT
-
uint64_t helper_float_rint_d(CPUMIPSState *env, uint64_t fs)
{
uint64_t fdret;
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v6 15/21] target/mips: fpu: Name better paired-single variables
2020-05-18 20:08 [PATCH v6 00/21] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (13 preceding siblings ...)
2020-05-18 20:09 ` [PATCH v6 14/21] target/mips: fpu: Remove now unused FLOAT_RINT macro Aleksandar Markovic
@ 2020-05-18 20:09 ` Aleksandar Markovic
2020-05-18 20:09 ` [PATCH v6 16/21] target/mips: fpu: Refactor conversion from ieee to mips exception flags Aleksandar Markovic
` (5 subsequent siblings)
20 siblings, 0 replies; 29+ messages in thread
From: Aleksandar Markovic @ 2020-05-18 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
Use consistently 'l' and 'h' for low and high halves.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 62 ++++++++++++++++++++--------------------
1 file changed, 31 insertions(+), 31 deletions(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index 56ba49104e..dbb8ca5692 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1059,14 +1059,14 @@ uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
{
- uint32_t fst2;
+ uint32_t fstl2;
uint32_t fsth2;
- fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF,
- &env->active_fpu.fp_status);
+ fstl2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF,
+ &env->active_fpu.fp_status);
fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
update_fcr31(env, GETPC());
- return ((uint64_t)fsth2 << 32) | fst2;
+ return ((uint64_t)fsth2 << 32) | fstl2;
}
uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
@@ -1091,15 +1091,15 @@ uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
{
- uint32_t fst2;
+ uint32_t fstl2;
uint32_t fsth2;
- fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
+ fstl2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
- fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
+ fstl2 = float32_div(float32_one, fstl2, &env->active_fpu.fp_status);
fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
update_fcr31(env, GETPC());
- return ((uint64_t)fsth2 << 32) | fst2;
+ return ((uint64_t)fsth2 << 32) | fstl2;
}
uint64_t helper_float_rint_d(CPUMIPSState *env, uint64_t fs)
@@ -1367,19 +1367,19 @@ uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
{
- uint32_t fst0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
uint32_t fsth0 = fdt0 >> 32;
- uint32_t fst2 = fdt2 & 0XFFFFFFFF;
+ uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
uint32_t fsth2 = fdt2 >> 32;
- fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
+ fstl2 = float32_mul(fstl0, fstl2, &env->active_fpu.fp_status);
fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
- fst2 = float32_chs(float32_sub(fst2, float32_one,
+ fstl2 = float32_chs(float32_sub(fstl2, float32_one,
&env->active_fpu.fp_status));
fsth2 = float32_chs(float32_sub(fsth2, float32_one,
&env->active_fpu.fp_status));
update_fcr31(env, GETPC());
- return ((uint64_t)fsth2 << 32) | fst2;
+ return ((uint64_t)fsth2 << 32) | fstl2;
}
uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
@@ -1404,51 +1404,51 @@ uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
{
- uint32_t fst0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
uint32_t fsth0 = fdt0 >> 32;
- uint32_t fst2 = fdt2 & 0XFFFFFFFF;
+ uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
uint32_t fsth2 = fdt2 >> 32;
- fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
+ fstl2 = float32_mul(fstl0, fstl2, &env->active_fpu.fp_status);
fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
- fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
+ fstl2 = float32_sub(fstl2, float32_one, &env->active_fpu.fp_status);
fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
- fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32,
+ fstl2 = float32_chs(float32_div(fstl2, FLOAT_TWO32,
&env->active_fpu.fp_status));
fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32,
&env->active_fpu.fp_status));
update_fcr31(env, GETPC());
- return ((uint64_t)fsth2 << 32) | fst2;
+ return ((uint64_t)fsth2 << 32) | fstl2;
}
uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
{
- uint32_t fst0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
uint32_t fsth0 = fdt0 >> 32;
- uint32_t fst1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
uint32_t fsth1 = fdt1 >> 32;
- uint32_t fst2;
+ uint32_t fstl2;
uint32_t fsth2;
- fst2 = float32_add(fst0, fsth0, &env->active_fpu.fp_status);
- fsth2 = float32_add(fst1, fsth1, &env->active_fpu.fp_status);
+ fstl2 = float32_add(fstl0, fsth0, &env->active_fpu.fp_status);
+ fsth2 = float32_add(fstl1, fsth1, &env->active_fpu.fp_status);
update_fcr31(env, GETPC());
- return ((uint64_t)fsth2 << 32) | fst2;
+ return ((uint64_t)fsth2 << 32) | fstl2;
}
uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
{
- uint32_t fst0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
uint32_t fsth0 = fdt0 >> 32;
- uint32_t fst1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
uint32_t fsth1 = fdt1 >> 32;
- uint32_t fst2;
+ uint32_t fstl2;
uint32_t fsth2;
- fst2 = float32_mul(fst0, fsth0, &env->active_fpu.fp_status);
- fsth2 = float32_mul(fst1, fsth1, &env->active_fpu.fp_status);
+ fstl2 = float32_mul(fstl0, fsth0, &env->active_fpu.fp_status);
+ fsth2 = float32_mul(fstl1, fsth1, &env->active_fpu.fp_status);
update_fcr31(env, GETPC());
- return ((uint64_t)fsth2 << 32) | fst2;
+ return ((uint64_t)fsth2 << 32) | fstl2;
}
#define FLOAT_MINMAX(name, bits, minmaxfunc) \
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v6 16/21] target/mips: fpu: Refactor conversion from ieee to mips exception flags
2020-05-18 20:08 [PATCH v6 00/21] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (14 preceding siblings ...)
2020-05-18 20:09 ` [PATCH v6 15/21] target/mips: fpu: Name better paired-single variables Aleksandar Markovic
@ 2020-05-18 20:09 ` Aleksandar Markovic
2020-05-18 20:09 ` [PATCH v6 17/21] MAINTAINERS: Change Aleksandar Rikalo's email address Aleksandar Markovic
` (4 subsequent siblings)
20 siblings, 0 replies; 29+ messages in thread
From: Aleksandar Markovic @ 2020-05-18 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
The original coversion function is used for regular and MSA floating
point instructions handling. Since there are some nuanced differences
between regular and MSA floating point exception handling, provide two
instances of the conversion function, rather than just a single common
one. Inline both instances of this function instances for the sake of
performance. Improve variable naming in surrounding code for clarity.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 55 +++++++++++++++-------------
target/mips/internal.h | 1 -
target/mips/msa_helper.c | 77 +++++++++++++++++++++++++++-------------
3 files changed, 82 insertions(+), 51 deletions(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index dbb8ca5692..7a3a61cab3 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -189,43 +189,48 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
}
}
-int ieee_ex_to_mips(int xcpt)
+static inline int ieee_to_mips_xcpt(int ieee_xcpt)
{
- int ret = 0;
- if (xcpt) {
- if (xcpt & float_flag_invalid) {
- ret |= FP_INVALID;
- }
- if (xcpt & float_flag_overflow) {
- ret |= FP_OVERFLOW;
- }
- if (xcpt & float_flag_underflow) {
- ret |= FP_UNDERFLOW;
- }
- if (xcpt & float_flag_divbyzero) {
- ret |= FP_DIV0;
- }
- if (xcpt & float_flag_inexact) {
- ret |= FP_INEXACT;
- }
+ int mips_xcpt = 0;
+
+ if (ieee_xcpt & float_flag_invalid) {
+ mips_xcpt |= FP_INVALID;
+ }
+ if (ieee_xcpt & float_flag_overflow) {
+ mips_xcpt |= FP_OVERFLOW;
}
- return ret;
+ if (ieee_xcpt & float_flag_underflow) {
+ mips_xcpt |= FP_UNDERFLOW;
+ }
+ if (ieee_xcpt & float_flag_divbyzero) {
+ mips_xcpt |= FP_DIV0;
+ }
+ if (ieee_xcpt & float_flag_inexact) {
+ mips_xcpt |= FP_INEXACT;
+ }
+
+ return mips_xcpt;
}
static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
{
- int tmp = ieee_ex_to_mips(get_float_exception_flags(
- &env->active_fpu.fp_status));
+ int ieee_exception_flags = get_float_exception_flags(
+ &env->active_fpu.fp_status);
+ int mips_exception_flags = 0;
+
+ if (ieee_exception_flags) {
+ mips_exception_flags = ieee_to_mips_xcpt(ieee_exception_flags);
+ }
- SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
+ SET_FP_CAUSE(env->active_fpu.fcr31, mips_exception_flags);
- if (tmp) {
+ if (mips_exception_flags) {
set_float_exception_flags(0, &env->active_fpu.fp_status);
- if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
+ if (GET_FP_ENABLE(env->active_fpu.fcr31) & mips_exception_flags) {
do_raise_exception(env, EXCP_FPE, pc);
} else {
- UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
+ UPDATE_FP_FLAGS(env->active_fpu.fcr31, mips_exception_flags);
}
}
}
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 1bf274b3ef..684356e309 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -224,7 +224,6 @@ uint32_t float_class_s(uint32_t arg, float_status *fst);
uint64_t float_class_d(uint64_t arg, float_status *fst);
extern unsigned int ieee_rm[];
-int ieee_ex_to_mips(int xcpt);
void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
static inline void restore_rounding_mode(CPUMIPSState *env)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 4065cfe4f7..c520405929 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -5419,54 +5419,81 @@ static inline void check_msacsr_cause(CPUMIPSState *env, uintptr_t retaddr)
#define CLEAR_IS_INEXACT 2
#define RECIPROCAL_INEXACT 4
-static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
+
+static inline int ieee_to_mips_xcpt_msa(int ieee_xcpt)
{
- int ieee_ex;
+ int mips_xcpt = 0;
- int c;
+ if (ieee_xcpt & float_flag_invalid) {
+ mips_xcpt |= FP_INVALID;
+ }
+ if (ieee_xcpt & float_flag_overflow) {
+ mips_xcpt |= FP_OVERFLOW;
+ }
+ if (ieee_xcpt & float_flag_underflow) {
+ mips_xcpt |= FP_UNDERFLOW;
+ }
+ if (ieee_xcpt & float_flag_divbyzero) {
+ mips_xcpt |= FP_DIV0;
+ }
+ if (ieee_xcpt & float_flag_inexact) {
+ mips_xcpt |= FP_INEXACT;
+ }
+
+ return mips_xcpt;
+}
+
+static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
+{
+ int ieee_exception_flags;
+ int mips_exception_flags = 0;
int cause;
int enable;
- ieee_ex = get_float_exception_flags(&env->active_tc.msa_fp_status);
+ ieee_exception_flags = get_float_exception_flags(
+ &env->active_tc.msa_fp_status);
/* QEMU softfloat does not signal all underflow cases */
if (denormal) {
- ieee_ex |= float_flag_underflow;
+ ieee_exception_flags |= float_flag_underflow;
+ }
+ if (ieee_exception_flags) {
+ mips_exception_flags = ieee_to_mips_xcpt_msa(ieee_exception_flags);
}
-
- c = ieee_ex_to_mips(ieee_ex);
enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
/* Set Inexact (I) when flushing inputs to zero */
- if ((ieee_ex & float_flag_input_denormal) &&
+ if ((ieee_exception_flags & float_flag_input_denormal) &&
(env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
if (action & CLEAR_IS_INEXACT) {
- c &= ~FP_INEXACT;
+ mips_exception_flags &= ~FP_INEXACT;
} else {
- c |= FP_INEXACT;
+ mips_exception_flags |= FP_INEXACT;
}
}
/* Set Inexact (I) and Underflow (U) when flushing outputs to zero */
- if ((ieee_ex & float_flag_output_denormal) &&
+ if ((ieee_exception_flags & float_flag_output_denormal) &&
(env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
- c |= FP_INEXACT;
+ mips_exception_flags |= FP_INEXACT;
if (action & CLEAR_FS_UNDERFLOW) {
- c &= ~FP_UNDERFLOW;
+ mips_exception_flags &= ~FP_UNDERFLOW;
} else {
- c |= FP_UNDERFLOW;
+ mips_exception_flags |= FP_UNDERFLOW;
}
}
/* Set Inexact (I) when Overflow (O) is not enabled */
- if ((c & FP_OVERFLOW) != 0 && (enable & FP_OVERFLOW) == 0) {
- c |= FP_INEXACT;
+ if ((mips_exception_flags & FP_OVERFLOW) != 0 &&
+ (enable & FP_OVERFLOW) == 0) {
+ mips_exception_flags |= FP_INEXACT;
}
/* Clear Exact Underflow when Underflow (U) is not enabled */
- if ((c & FP_UNDERFLOW) != 0 && (enable & FP_UNDERFLOW) == 0 &&
- (c & FP_INEXACT) == 0) {
- c &= ~FP_UNDERFLOW;
+ if ((mips_exception_flags & FP_UNDERFLOW) != 0 &&
+ (enable & FP_UNDERFLOW) == 0 &&
+ (mips_exception_flags & FP_INEXACT) == 0) {
+ mips_exception_flags &= ~FP_UNDERFLOW;
}
/*
@@ -5474,11 +5501,11 @@ static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
* divide by zero
*/
if ((action & RECIPROCAL_INEXACT) &&
- (c & (FP_INVALID | FP_DIV0)) == 0) {
- c = FP_INEXACT;
+ (mips_exception_flags & (FP_INVALID | FP_DIV0)) == 0) {
+ mips_exception_flags = FP_INEXACT;
}
- cause = c & enable; /* all current enabled exceptions */
+ cause = mips_exception_flags & enable; /* all current enabled exceptions */
if (cause == 0) {
/*
@@ -5486,7 +5513,7 @@ static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
* with all current exceptions
*/
SET_FP_CAUSE(env->active_tc.msacsr,
- (GET_FP_CAUSE(env->active_tc.msacsr) | c));
+ (GET_FP_CAUSE(env->active_tc.msacsr) | mips_exception_flags));
} else {
/* Current exceptions are enabled */
if ((env->active_tc.msacsr & MSACSR_NX_MASK) == 0) {
@@ -5495,11 +5522,11 @@ static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
* with all enabled exceptions
*/
SET_FP_CAUSE(env->active_tc.msacsr,
- (GET_FP_CAUSE(env->active_tc.msacsr) | c));
+ (GET_FP_CAUSE(env->active_tc.msacsr) | mips_exception_flags));
}
}
- return c;
+ return mips_exception_flags;
}
static inline int get_enabled_exceptions(const CPUMIPSState *env, int c)
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v6 17/21] MAINTAINERS: Change Aleksandar Rikalo's email address
2020-05-18 20:08 [PATCH v6 00/21] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (15 preceding siblings ...)
2020-05-18 20:09 ` [PATCH v6 16/21] target/mips: fpu: Refactor conversion from ieee to mips exception flags Aleksandar Markovic
@ 2020-05-18 20:09 ` Aleksandar Markovic
2020-05-26 7:44 ` Philippe Mathieu-Daudé
2020-05-18 20:09 ` [PATCH v6 18/21] target/mips: msa: Split helpers for MADDV.<B|H|W|D> Aleksandar Markovic
` (3 subsequent siblings)
20 siblings, 1 reply; 29+ messages in thread
From: Aleksandar Markovic @ 2020-05-18 20:09 UTC (permalink / raw)
To: qemu-devel
Cc: aleksandar.rikalo, Aleksandar Markovic, Philippe Mathieu-Daudé
Aleksandar Rikalo wants to use a different email address from
now on.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
.mailmap | 3 ++-
MAINTAINERS | 12 ++++++------
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/.mailmap b/.mailmap
index 6412067bde..e3628c7a66 100644
--- a/.mailmap
+++ b/.mailmap
@@ -42,7 +42,8 @@ Justin Terry (VM) <juterry@microsoft.com> Justin Terry (VM) via Qemu-devel <qemu
Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> <aleksandar.markovic@mips.com>
Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> <aleksandar.markovic@imgtec.com>
Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> <amarkovic@wavecomp.com>
-Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> <arikalo@wavecomp.com>
+Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> <arikalo@wavecomp.com>
+Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> <aleksandar.rikalo@rt-rk.com>
Anthony Liguori <anthony@codemonkey.ws> Anthony Liguori <aliguori@us.ibm.com>
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org>
diff --git a/MAINTAINERS b/MAINTAINERS
index 1f84e3ae2c..8d5562c5c7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -212,7 +212,7 @@ F: disas/microblaze.c
MIPS TCG CPUs
M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
R: Aurelien Jarno <aurelien@aurel32.net>
-R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
+R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
S: Maintained
F: target/mips/
F: default-configs/*mips*
@@ -1041,7 +1041,7 @@ MIPS Machines
-------------
Jazz
M: Hervé Poussineau <hpoussin@reactos.org>
-R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
+R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
S: Maintained
F: hw/mips/mips_jazz.c
F: hw/display/jazz_led.c
@@ -1062,7 +1062,7 @@ F: tests/acceptance/machine_mips_malta.py
Mipssim
M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
-R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
+R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
S: Odd Fixes
F: hw/mips/mips_mipssim.c
F: hw/net/mipsnet.c
@@ -1070,7 +1070,7 @@ F: hw/net/mipsnet.c
R4000
M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
R: Aurelien Jarno <aurelien@aurel32.net>
-R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
+R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
S: Obsolete
F: hw/mips/mips_r4k.c
@@ -1085,7 +1085,7 @@ F: include/hw/isa/vt82c686.h
Boston
M: Paul Burton <pburton@wavecomp.com>
-R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
+R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
S: Maintained
F: hw/core/loader-fit.c
F: hw/mips/boston.c
@@ -2582,7 +2582,7 @@ F: disas/i386.c
MIPS TCG target
M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
R: Aurelien Jarno <aurelien@aurel32.net>
-R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
+R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
S: Maintained
F: tcg/mips/
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH v6 17/21] MAINTAINERS: Change Aleksandar Rikalo's email address
2020-05-18 20:09 ` [PATCH v6 17/21] MAINTAINERS: Change Aleksandar Rikalo's email address Aleksandar Markovic
@ 2020-05-26 7:44 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-05-26 7:44 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel; +Cc: aleksandar.rikalo
On 5/18/20 10:09 PM, Aleksandar Markovic wrote:
> Aleksandar Rikalo wants to use a different email address from
> now on.
>
> Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
> ---
> .mailmap | 3 ++-
> MAINTAINERS | 12 ++++++------
> 2 files changed, 8 insertions(+), 7 deletions(-)
Thanks, queued to mips-next.
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v6 18/21] target/mips: msa: Split helpers for MADDV.<B|H|W|D>
2020-05-18 20:08 [PATCH v6 00/21] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (16 preceding siblings ...)
2020-05-18 20:09 ` [PATCH v6 17/21] MAINTAINERS: Change Aleksandar Rikalo's email address Aleksandar Markovic
@ 2020-05-18 20:09 ` Aleksandar Markovic
2020-05-18 20:09 ` [PATCH v6 19/21] target/mips: msa: Split helpers for MSUBV.<B|H|W|D> Aleksandar Markovic
` (2 subsequent siblings)
20 siblings, 0 replies; 29+ messages in thread
From: Aleksandar Markovic @ 2020-05-18 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/helper.h | 6 ++-
target/mips/msa_helper.c | 79 ++++++++++++++++++++++++++++++++++++----
target/mips/translate.c | 19 ++++++++--
3 files changed, 92 insertions(+), 12 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 84fdd9fd27..e479a22559 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -950,6 +950,11 @@ DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_maddv_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_maddv_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_maddv_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_maddv_d, void, env, i32, i32, i32)
+
DEF_HELPER_4(msa_asub_s_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_asub_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_asub_s_w, void, env, i32, i32, i32)
@@ -1069,7 +1074,6 @@ DEF_HELPER_5(msa_subs_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subsus_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subsuu_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_maddv_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_msubv_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_dotp_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_dotp_u_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index c520405929..6af9d3b752 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -2883,7 +2883,77 @@ void helper_msa_mod_u_d(CPUMIPSState *env,
* +---------------+----------------------------------------------------------+
*/
-/* TODO: insert Int Multiply group helpers here */
+static inline int64_t msa_maddv_df(uint32_t df, int64_t dest, int64_t arg1,
+ int64_t arg2)
+{
+ return dest + arg1 * arg2;
+}
+
+void helper_msa_maddv_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_maddv_df(DF_BYTE, pwt->b[0], pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_maddv_df(DF_BYTE, pwt->b[1], pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_maddv_df(DF_BYTE, pwt->b[2], pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_maddv_df(DF_BYTE, pwt->b[3], pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_maddv_df(DF_BYTE, pwt->b[4], pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_maddv_df(DF_BYTE, pwt->b[5], pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_maddv_df(DF_BYTE, pwt->b[6], pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_maddv_df(DF_BYTE, pwt->b[7], pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_maddv_df(DF_BYTE, pwt->b[8], pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_maddv_df(DF_BYTE, pwt->b[9], pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_maddv_df(DF_BYTE, pwt->b[10], pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_maddv_df(DF_BYTE, pwt->b[11], pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_maddv_df(DF_BYTE, pwt->b[12], pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_maddv_df(DF_BYTE, pwt->b[13], pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_maddv_df(DF_BYTE, pwt->b[14], pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_maddv_df(DF_BYTE, pwt->b[15], pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_maddv_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_maddv_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_maddv_df(DF_HALF, pwd->h[1], pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_maddv_df(DF_HALF, pwd->h[2], pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_maddv_df(DF_HALF, pwd->h[3], pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_maddv_df(DF_HALF, pwd->h[4], pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_maddv_df(DF_HALF, pwd->h[5], pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_maddv_df(DF_HALF, pwd->h[6], pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_maddv_df(DF_HALF, pwd->h[7], pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_maddv_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_maddv_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_maddv_df(DF_WORD, pwd->w[1], pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_maddv_df(DF_WORD, pwd->w[2], pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_maddv_df(DF_WORD, pwd->w[3], pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_maddv_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_maddv_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_maddv_df(DF_DOUBLE, pwd->d[1], pws->d[1], pwt->d[1]);
+}
/*
@@ -4816,12 +4886,6 @@ void helper_msa_sld_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
msa_sld_df(df, pwd, pws, env->active_tc.gpr[rt]);
}
-static inline int64_t msa_maddv_df(uint32_t df, int64_t dest, int64_t arg1,
- int64_t arg2)
-{
- return dest + arg1 * arg2;
-}
-
static inline int64_t msa_msubv_df(uint32_t df, int64_t dest, int64_t arg1,
int64_t arg2)
{
@@ -5002,7 +5066,6 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
} \
}
-MSA_TEROP_DF(maddv)
MSA_TEROP_DF(msubv)
MSA_TEROP_DF(dpadd_s)
MSA_TEROP_DF(dpadd_u)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 25b595a17d..42f2a759e5 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29057,6 +29057,22 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
+ case OPC_MADDV_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_maddv_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_maddv_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_maddv_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_maddv_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
case OPC_ASUB_S_df:
switch (df) {
case DF_BYTE:
@@ -29283,9 +29299,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_SUBS_U_df:
gen_helper_msa_subs_u_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MADDV_df:
- gen_helper_msa_maddv_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_SPLAT_df:
gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt);
break;
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v6 19/21] target/mips: msa: Split helpers for MSUBV.<B|H|W|D>
2020-05-18 20:08 [PATCH v6 00/21] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (17 preceding siblings ...)
2020-05-18 20:09 ` [PATCH v6 18/21] target/mips: msa: Split helpers for MADDV.<B|H|W|D> Aleksandar Markovic
@ 2020-05-18 20:09 ` Aleksandar Markovic
2020-05-18 20:09 ` [PATCH v6 20/21] hw/mips: Add some logging for bad register offset cases Aleksandar Markovic
2020-05-18 20:09 ` [PATCH v6 21/21] hw/mips: Rename malta/mipssim/r4k/jazz files in hw/mips Aleksandar Markovic
20 siblings, 0 replies; 29+ messages in thread
From: Aleksandar Markovic @ 2020-05-18 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/helper.h | 6 ++-
target/mips/msa_helper.c | 79 ++++++++++++++++++++++++++++++++++++----
target/mips/translate.c | 19 ++++++++--
3 files changed, 93 insertions(+), 11 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index e479a22559..7ca0036807 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -955,6 +955,11 @@ DEF_HELPER_4(msa_maddv_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_maddv_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_maddv_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_msubv_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_msubv_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_msubv_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_msubv_d, void, env, i32, i32, i32)
+
DEF_HELPER_4(msa_asub_s_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_asub_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_asub_s_w, void, env, i32, i32, i32)
@@ -1074,7 +1079,6 @@ DEF_HELPER_5(msa_subs_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subsus_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subsuu_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_msubv_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_dotp_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_dotp_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_dpadd_s_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 6af9d3b752..a0aac3ee10 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -2955,6 +2955,78 @@ void helper_msa_maddv_d(CPUMIPSState *env,
pwd->d[1] = msa_maddv_df(DF_DOUBLE, pwd->d[1], pws->d[1], pwt->d[1]);
}
+static inline int64_t msa_msubv_df(uint32_t df, int64_t dest, int64_t arg1,
+ int64_t arg2)
+{
+ return dest - arg1 * arg2;
+}
+
+void helper_msa_msubv_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_msubv_df(DF_BYTE, pwt->b[0], pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_msubv_df(DF_BYTE, pwt->b[1], pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_msubv_df(DF_BYTE, pwt->b[2], pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_msubv_df(DF_BYTE, pwt->b[3], pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_msubv_df(DF_BYTE, pwt->b[4], pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_msubv_df(DF_BYTE, pwt->b[5], pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_msubv_df(DF_BYTE, pwt->b[6], pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_msubv_df(DF_BYTE, pwt->b[7], pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_msubv_df(DF_BYTE, pwt->b[8], pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_msubv_df(DF_BYTE, pwt->b[9], pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_msubv_df(DF_BYTE, pwt->b[10], pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_msubv_df(DF_BYTE, pwt->b[11], pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_msubv_df(DF_BYTE, pwt->b[12], pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_msubv_df(DF_BYTE, pwt->b[13], pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_msubv_df(DF_BYTE, pwt->b[14], pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_msubv_df(DF_BYTE, pwt->b[15], pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_msubv_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_msubv_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_msubv_df(DF_HALF, pwd->h[1], pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_msubv_df(DF_HALF, pwd->h[2], pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_msubv_df(DF_HALF, pwd->h[3], pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_msubv_df(DF_HALF, pwd->h[4], pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_msubv_df(DF_HALF, pwd->h[5], pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_msubv_df(DF_HALF, pwd->h[6], pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_msubv_df(DF_HALF, pwd->h[7], pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_msubv_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_msubv_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_msubv_df(DF_WORD, pwd->w[1], pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_msubv_df(DF_WORD, pwd->w[2], pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_msubv_df(DF_WORD, pwd->w[3], pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_msubv_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_msubv_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_msubv_df(DF_DOUBLE, pwd->d[1], pws->d[1], pwt->d[1]);
+}
+
/*
* Int Subtract
@@ -4886,12 +4958,6 @@ void helper_msa_sld_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
msa_sld_df(df, pwd, pws, env->active_tc.gpr[rt]);
}
-static inline int64_t msa_msubv_df(uint32_t df, int64_t dest, int64_t arg1,
- int64_t arg2)
-{
- return dest - arg1 * arg2;
-}
-
static inline int64_t msa_dpadd_s_df(uint32_t df, int64_t dest, int64_t arg1,
int64_t arg2)
{
@@ -5066,7 +5132,6 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
} \
}
-MSA_TEROP_DF(msubv)
MSA_TEROP_DF(dpadd_s)
MSA_TEROP_DF(dpadd_u)
MSA_TEROP_DF(dpsub_s)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 42f2a759e5..6b6a92a84f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29073,6 +29073,22 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
+ case OPC_MSUBV_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_msubv_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_msubv_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_msubv_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_msubv_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
case OPC_ASUB_S_df:
switch (df) {
case DF_BYTE:
@@ -29305,9 +29321,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_SUBSUS_U_df:
gen_helper_msa_subsus_u_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MSUBV_df:
- gen_helper_msa_msubv_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_SUBSUU_S_df:
gen_helper_msa_subsuu_s_df(cpu_env, tdf, twd, tws, twt);
break;
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v6 20/21] hw/mips: Add some logging for bad register offset cases
2020-05-18 20:08 [PATCH v6 00/21] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (18 preceding siblings ...)
2020-05-18 20:09 ` [PATCH v6 19/21] target/mips: msa: Split helpers for MSUBV.<B|H|W|D> Aleksandar Markovic
@ 2020-05-18 20:09 ` Aleksandar Markovic
2020-05-26 7:42 ` Philippe Mathieu-Daudé
2020-05-18 20:09 ` [PATCH v6 21/21] hw/mips: Rename malta/mipssim/r4k/jazz files in hw/mips Aleksandar Markovic
20 siblings, 1 reply; 29+ messages in thread
From: Aleksandar Markovic @ 2020-05-18 20:09 UTC (permalink / raw)
To: qemu-devel
Cc: aleksandar.rikalo, Aleksandar Markovic, Philippe Mathieu-Daudé
Log the cases where a guest attempts read or write using bad
register offset.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
hw/mips/mips_malta.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index e4c4de1b4e..88869b828e 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -427,10 +427,9 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
break;
default:
-#if 0
- printf("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
- addr);
-#endif
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "malta_fpga_read: Bad register offset 0x"
+ TARGET_FMT_lx "\n", addr);
break;
}
return val;
@@ -515,10 +514,9 @@ static void malta_fpga_write(void *opaque, hwaddr addr,
break;
default:
-#if 0
- printf("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
- addr);
-#endif
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "malta_fpga_write: Bad register offset 0x"
+ TARGET_FMT_lx "\n", addr);
break;
}
}
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH v6 20/21] hw/mips: Add some logging for bad register offset cases
2020-05-18 20:09 ` [PATCH v6 20/21] hw/mips: Add some logging for bad register offset cases Aleksandar Markovic
@ 2020-05-26 7:42 ` Philippe Mathieu-Daudé
2020-05-26 10:05 ` Aleksandar Markovic
0 siblings, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-05-26 7:42 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel; +Cc: aleksandar.rikalo
On 5/18/20 10:09 PM, Aleksandar Markovic wrote:
> Log the cases where a guest attempts read or write using bad
> register offset.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Not well tested apparently, because it doesn't build with GCC 5.4.0
(Ubuntu):
hw/mips/malta.c: In function ‘malta_fpga_read’:
hw/mips/malta.c:430:85: error: format ‘%x’ expects argument of type
‘unsigned int’, but argument 2 has type ‘hwaddr {aka long unsigned int}’
[-Werror=format=]
hw/mips/malta.c: In function ‘malta_fpga_write’:
hw/mips/malta.c:517:85: error: format ‘%x’ expects argument of type
‘unsigned int’, but argument 2 has type ‘hwaddr {aka long unsigned int}’
[-Werror=format=]
cc1: all warnings being treated as errors
I amended this snippet ...:
-- >8 --
@@ -428,8 +428,8 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr
addr,
default:
qemu_log_mask(LOG_GUEST_ERROR,
- "malta_fpga_read: Bad register offset 0x"
- TARGET_FMT_lx "\n", addr);
+ "malta_fpga_read: Bad register addr
0x%"HWADDR_PRIX"\n",
+ addr);
break;
}
return val;
@@ -515,8 +515,8 @@ static void malta_fpga_write(void *opaque, hwaddr addr,
default:
qemu_log_mask(LOG_GUEST_ERROR,
- "malta_fpga_write: Bad register offset 0x"
- TARGET_FMT_lx "\n", addr);
+ "malta_fpga_write: Bad register addr
0x%"HWADDR_PRIX"\n",
+ addr);
break;
}
}
---
... and queued to mips-next,
Thanks,
Phil.
> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
> ---
> hw/mips/mips_malta.c | 14 ++++++--------
> 1 file changed, 6 insertions(+), 8 deletions(-)
>
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index e4c4de1b4e..88869b828e 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -427,10 +427,9 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
> break;
>
> default:
> -#if 0
> - printf("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
> - addr);
> -#endif
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "malta_fpga_read: Bad register offset 0x"
> + TARGET_FMT_lx "\n", addr);
> break;
> }
> return val;
> @@ -515,10 +514,9 @@ static void malta_fpga_write(void *opaque, hwaddr addr,
> break;
>
> default:
> -#if 0
> - printf("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
> - addr);
> -#endif
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "malta_fpga_write: Bad register offset 0x"
> + TARGET_FMT_lx "\n", addr);
> break;
> }
> }
>
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH v6 20/21] hw/mips: Add some logging for bad register offset cases
2020-05-26 7:42 ` Philippe Mathieu-Daudé
@ 2020-05-26 10:05 ` Aleksandar Markovic
2020-05-26 10:38 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 29+ messages in thread
From: Aleksandar Markovic @ 2020-05-26 10:05 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: aleksandar.rikalo, QEMU Developers
уто, 26. мај 2020. у 09:42 Philippe Mathieu-Daudé <f4bug@amsat.org> је
написао/ла:
>
> On 5/18/20 10:09 PM, Aleksandar Markovic wrote:
> > Log the cases where a guest attempts read or write using bad
> > register offset.
> >
> > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> > Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> Not well tested apparently, because it doesn't build with GCC 5.4.0
> (Ubuntu):
>
> hw/mips/malta.c: In function ‘malta_fpga_read’:
> hw/mips/malta.c:430:85: error: format ‘%x’ expects argument of type
> ‘unsigned int’, but argument 2 has type ‘hwaddr {aka long unsigned int}’
> [-Werror=format=]
> hw/mips/malta.c: In function ‘malta_fpga_write’:
> hw/mips/malta.c:517:85: error: format ‘%x’ expects argument of type
> ‘unsigned int’, but argument 2 has type ‘hwaddr {aka long unsigned int}’
> [-Werror=format=]
> cc1: all warnings being treated as errors
>
> I amended this snippet ...:
>
> -- >8 --
> @@ -428,8 +428,8 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr
> addr,
>
> default:
> qemu_log_mask(LOG_GUEST_ERROR,
> - "malta_fpga_read: Bad register offset 0x"
> - TARGET_FMT_lx "\n", addr);
> + "malta_fpga_read: Bad register addr
> 0x%"HWADDR_PRIX"\n",
> + addr);
> break;
> }
> return val;
> @@ -515,8 +515,8 @@ static void malta_fpga_write(void *opaque, hwaddr addr,
>
> default:
> qemu_log_mask(LOG_GUEST_ERROR,
> - "malta_fpga_write: Bad register offset 0x"
> - TARGET_FMT_lx "\n", addr);
> + "malta_fpga_write: Bad register addr
> 0x%"HWADDR_PRIX"\n",
> + addr);
> break;
> }
> }
> ---
>
> ... and queued to mips-next,
>
Hi, Philippe,
Many thanks for correcting my mistake in this patch!
May I ask you to refer to your queue as hw/mips-next, rather than
mips-next, for the sake of clarity?
And, when do you plan to send the pull request?
Thanks,
Aleksandar
> Thanks,
>
> Phil.
>
> > Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
> > ---
> > hw/mips/mips_malta.c | 14 ++++++--------
> > 1 file changed, 6 insertions(+), 8 deletions(-)
> >
> > diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> > index e4c4de1b4e..88869b828e 100644
> > --- a/hw/mips/mips_malta.c
> > +++ b/hw/mips/mips_malta.c
> > @@ -427,10 +427,9 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
> > break;
> >
> > default:
> > -#if 0
> > - printf("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
> > - addr);
> > -#endif
> > + qemu_log_mask(LOG_GUEST_ERROR,
> > + "malta_fpga_read: Bad register offset 0x"
> > + TARGET_FMT_lx "\n", addr);
> > break;
> > }
> > return val;
> > @@ -515,10 +514,9 @@ static void malta_fpga_write(void *opaque, hwaddr addr,
> > break;
> >
> > default:
> > -#if 0
> > - printf("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
> > - addr);
> > -#endif
> > + qemu_log_mask(LOG_GUEST_ERROR,
> > + "malta_fpga_write: Bad register offset 0x"
> > + TARGET_FMT_lx "\n", addr);
> > break;
> > }
> > }
> >
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH v6 20/21] hw/mips: Add some logging for bad register offset cases
2020-05-26 10:05 ` Aleksandar Markovic
@ 2020-05-26 10:38 ` Philippe Mathieu-Daudé
2020-05-26 10:46 ` Aleksandar Markovic
0 siblings, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-05-26 10:38 UTC (permalink / raw)
To: Aleksandar Markovic; +Cc: aleksandar.rikalo, QEMU Developers
On 5/26/20 12:05 PM, Aleksandar Markovic wrote:
> уто, 26. мај 2020. у 09:42 Philippe Mathieu-Daudé <f4bug@amsat.org> је
> написао/ла:
>>
>> On 5/18/20 10:09 PM, Aleksandar Markovic wrote:
>>> Log the cases where a guest attempts read or write using bad
>>> register offset.
>>>
>>> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>
>> Not well tested apparently, because it doesn't build with GCC 5.4.0
>> (Ubuntu):
>>
>> hw/mips/malta.c: In function ‘malta_fpga_read’:
>> hw/mips/malta.c:430:85: error: format ‘%x’ expects argument of type
>> ‘unsigned int’, but argument 2 has type ‘hwaddr {aka long unsigned int}’
>> [-Werror=format=]
>> hw/mips/malta.c: In function ‘malta_fpga_write’:
>> hw/mips/malta.c:517:85: error: format ‘%x’ expects argument of type
>> ‘unsigned int’, but argument 2 has type ‘hwaddr {aka long unsigned int}’
>> [-Werror=format=]
>> cc1: all warnings being treated as errors
>>
>> I amended this snippet ...:
>>
>> -- >8 --
>> @@ -428,8 +428,8 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr
>> addr,
>>
>> default:
>> qemu_log_mask(LOG_GUEST_ERROR,
>> - "malta_fpga_read: Bad register offset 0x"
>> - TARGET_FMT_lx "\n", addr);
>> + "malta_fpga_read: Bad register addr
>> 0x%"HWADDR_PRIX"\n",
>> + addr);
>> break;
>> }
>> return val;
>> @@ -515,8 +515,8 @@ static void malta_fpga_write(void *opaque, hwaddr addr,
>>
>> default:
>> qemu_log_mask(LOG_GUEST_ERROR,
>> - "malta_fpga_write: Bad register offset 0x"
>> - TARGET_FMT_lx "\n", addr);
>> + "malta_fpga_write: Bad register addr
>> 0x%"HWADDR_PRIX"\n",
>> + addr);
>> break;
>> }
>> }
>> ---
>>
>> ... and queued to mips-next,
>>
>
> Hi, Philippe,
>
> Many thanks for correcting my mistake in this patch!
> May I ask you to refer to your queue as hw/mips-next, rather than
> mips-next, for the sake of clarity?
Tags with '/' are hard to manage, let's use mips-hw-next,
mips-target-next for your pull requests and mips-kvm-next for Huacai's ones.
> And, when do you plan to send the pull request?
Waiting for Gerd's audio-next one to get merged because he took my
"mips_fulong2e: Remove unused 'audio/audio.h' include" patch and I don't
want Peter to have to manually resolve conflicts (there shouldn't be,
but I don't want to risk bother him with a "automatic 3-way merge" warning).
>
> Thanks,
> Aleksandar
>
>
>> Thanks,
>>
>> Phil.
>>
>>> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
>>> ---
>>> hw/mips/mips_malta.c | 14 ++++++--------
>>> 1 file changed, 6 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
>>> index e4c4de1b4e..88869b828e 100644
>>> --- a/hw/mips/mips_malta.c
>>> +++ b/hw/mips/mips_malta.c
>>> @@ -427,10 +427,9 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
>>> break;
>>>
>>> default:
>>> -#if 0
>>> - printf("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
>>> - addr);
>>> -#endif
>>> + qemu_log_mask(LOG_GUEST_ERROR,
>>> + "malta_fpga_read: Bad register offset 0x"
>>> + TARGET_FMT_lx "\n", addr);
>>> break;
>>> }
>>> return val;
>>> @@ -515,10 +514,9 @@ static void malta_fpga_write(void *opaque, hwaddr addr,
>>> break;
>>>
>>> default:
>>> -#if 0
>>> - printf("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
>>> - addr);
>>> -#endif
>>> + qemu_log_mask(LOG_GUEST_ERROR,
>>> + "malta_fpga_write: Bad register offset 0x"
>>> + TARGET_FMT_lx "\n", addr);
>>> break;
>>> }
>>> }
>>>
>
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH v6 20/21] hw/mips: Add some logging for bad register offset cases
2020-05-26 10:38 ` Philippe Mathieu-Daudé
@ 2020-05-26 10:46 ` Aleksandar Markovic
2020-05-27 7:52 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 29+ messages in thread
From: Aleksandar Markovic @ 2020-05-26 10:46 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: aleksandar.rikalo, QEMU Developers
уто, 26. мај 2020. у 12:38 Philippe Mathieu-Daudé <f4bug@amsat.org> је
написао/ла:
>
> On 5/26/20 12:05 PM, Aleksandar Markovic wrote:
> > уто, 26. мај 2020. у 09:42 Philippe Mathieu-Daudé <f4bug@amsat.org> је
> > написао/ла:
> >>
> >> On 5/18/20 10:09 PM, Aleksandar Markovic wrote:
> >>> Log the cases where a guest attempts read or write using bad
> >>> register offset.
> >>>
> >>> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> >>> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> >>
> >> Not well tested apparently, because it doesn't build with GCC 5.4.0
> >> (Ubuntu):
> >>
> >> hw/mips/malta.c: In function ‘malta_fpga_read’:
> >> hw/mips/malta.c:430:85: error: format ‘%x’ expects argument of type
> >> ‘unsigned int’, but argument 2 has type ‘hwaddr {aka long unsigned int}’
> >> [-Werror=format=]
> >> hw/mips/malta.c: In function ‘malta_fpga_write’:
> >> hw/mips/malta.c:517:85: error: format ‘%x’ expects argument of type
> >> ‘unsigned int’, but argument 2 has type ‘hwaddr {aka long unsigned int}’
> >> [-Werror=format=]
> >> cc1: all warnings being treated as errors
> >>
> >> I amended this snippet ...:
> >>
> >> -- >8 --
> >> @@ -428,8 +428,8 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr
> >> addr,
> >>
> >> default:
> >> qemu_log_mask(LOG_GUEST_ERROR,
> >> - "malta_fpga_read: Bad register offset 0x"
> >> - TARGET_FMT_lx "\n", addr);
> >> + "malta_fpga_read: Bad register addr
> >> 0x%"HWADDR_PRIX"\n",
> >> + addr);
> >> break;
> >> }
> >> return val;
> >> @@ -515,8 +515,8 @@ static void malta_fpga_write(void *opaque, hwaddr addr,
> >>
> >> default:
> >> qemu_log_mask(LOG_GUEST_ERROR,
> >> - "malta_fpga_write: Bad register offset 0x"
> >> - TARGET_FMT_lx "\n", addr);
> >> + "malta_fpga_write: Bad register addr
> >> 0x%"HWADDR_PRIX"\n",
> >> + addr);
> >> break;
> >> }
> >> }
> >> ---
> >>
> >> ... and queued to mips-next,
> >>
> >
> > Hi, Philippe,
> >
> > Many thanks for correcting my mistake in this patch!
> > May I ask you to refer to your queue as hw/mips-next, rather than
> > mips-next, for the sake of clarity?
>
> Tags with '/' are hard to manage, let's use mips-hw-next,
> mips-target-next for your pull requests and mips-kvm-next for Huacai's ones.
>
> > And, when do you plan to send the pull request?
>
> Waiting for Gerd's audio-next one to get merged because he took my
> "mips_fulong2e: Remove unused 'audio/audio.h' include" patch and I don't
> want Peter to have to manually resolve conflicts (there shouldn't be,
> but I don't want to risk bother him with a "automatic 3-way merge" warning).
>
Philippe, I think you created a lot of problems here without any real need.
We should sync between us rather than sent "surprise" "pull requests".
I am not happy with coordination of our common MIPS work.
> >
> > Thanks,
> > Aleksandar
> >
> >
> >> Thanks,
> >>
> >> Phil.
> >>
> >>> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
> >>> ---
> >>> hw/mips/mips_malta.c | 14 ++++++--------
> >>> 1 file changed, 6 insertions(+), 8 deletions(-)
> >>>
> >>> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> >>> index e4c4de1b4e..88869b828e 100644
> >>> --- a/hw/mips/mips_malta.c
> >>> +++ b/hw/mips/mips_malta.c
> >>> @@ -427,10 +427,9 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
> >>> break;
> >>>
> >>> default:
> >>> -#if 0
> >>> - printf("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
> >>> - addr);
> >>> -#endif
> >>> + qemu_log_mask(LOG_GUEST_ERROR,
> >>> + "malta_fpga_read: Bad register offset 0x"
> >>> + TARGET_FMT_lx "\n", addr);
> >>> break;
> >>> }
> >>> return val;
> >>> @@ -515,10 +514,9 @@ static void malta_fpga_write(void *opaque, hwaddr addr,
> >>> break;
> >>>
> >>> default:
> >>> -#if 0
> >>> - printf("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
> >>> - addr);
> >>> -#endif
> >>> + qemu_log_mask(LOG_GUEST_ERROR,
> >>> + "malta_fpga_write: Bad register offset 0x"
> >>> + TARGET_FMT_lx "\n", addr);
> >>> break;
> >>> }
> >>> }
> >>>
> >
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH v6 20/21] hw/mips: Add some logging for bad register offset cases
2020-05-26 10:46 ` Aleksandar Markovic
@ 2020-05-27 7:52 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-05-27 7:52 UTC (permalink / raw)
To: Aleksandar Markovic; +Cc: Aleksandar Rikalo, QEMU Developers
Hi Aleksandar,
On Tue, May 26, 2020 at 12:46 PM Aleksandar Markovic
<aleksandar.qemu.devel@gmail.com> wrote:
> уто, 26. мај 2020. у 12:38 Philippe Mathieu-Daudé <f4bug@amsat.org> је
> написао/ла:
> > On 5/26/20 12:05 PM, Aleksandar Markovic wrote:
> > > уто, 26. мај 2020. у 09:42 Philippe Mathieu-Daudé <f4bug@amsat.org> је
> > > написао/ла:
> > >>
> > >> On 5/18/20 10:09 PM, Aleksandar Markovic wrote:
> > >>> Log the cases where a guest attempts read or write using bad
> > >>> register offset.
> > >>>
> > >>> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> > >>> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> > >>
> > >> Not well tested apparently, because it doesn't build with GCC 5.4.0
> > >> (Ubuntu):
> > >>
> > >> hw/mips/malta.c: In function ‘malta_fpga_read’:
> > >> hw/mips/malta.c:430:85: error: format ‘%x’ expects argument of type
> > >> ‘unsigned int’, but argument 2 has type ‘hwaddr {aka long unsigned int}’
> > >> [-Werror=format=]
> > >> hw/mips/malta.c: In function ‘malta_fpga_write’:
> > >> hw/mips/malta.c:517:85: error: format ‘%x’ expects argument of type
> > >> ‘unsigned int’, but argument 2 has type ‘hwaddr {aka long unsigned int}’
> > >> [-Werror=format=]
> > >> cc1: all warnings being treated as errors
> > >>
> > >> I amended this snippet ...:
> > >>
> > >> -- >8 --
> > >> @@ -428,8 +428,8 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr
> > >> addr,
> > >>
> > >> default:
> > >> qemu_log_mask(LOG_GUEST_ERROR,
> > >> - "malta_fpga_read: Bad register offset 0x"
> > >> - TARGET_FMT_lx "\n", addr);
> > >> + "malta_fpga_read: Bad register addr
> > >> 0x%"HWADDR_PRIX"\n",
> > >> + addr);
> > >> break;
> > >> }
> > >> return val;
> > >> @@ -515,8 +515,8 @@ static void malta_fpga_write(void *opaque, hwaddr addr,
> > >>
> > >> default:
> > >> qemu_log_mask(LOG_GUEST_ERROR,
> > >> - "malta_fpga_write: Bad register offset 0x"
> > >> - TARGET_FMT_lx "\n", addr);
> > >> + "malta_fpga_write: Bad register addr
> > >> 0x%"HWADDR_PRIX"\n",
> > >> + addr);
> > >> break;
> > >> }
> > >> }
> > >> ---
> > >>
> > >> ... and queued to mips-next,
> > >>
> > >
> > > Hi, Philippe,
> > >
> > > Many thanks for correcting my mistake in this patch!
> > > May I ask you to refer to your queue as hw/mips-next, rather than
> > > mips-next, for the sake of clarity?
> >
> > Tags with '/' are hard to manage, let's use mips-hw-next,
> > mips-target-next for your pull requests and mips-kvm-next for Huacai's ones.
> >
> > > And, when do you plan to send the pull request?
> >
> > Waiting for Gerd's audio-next one to get merged because he took my
> > "mips_fulong2e: Remove unused 'audio/audio.h' include" patch and I don't
> > want Peter to have to manually resolve conflicts (there shouldn't be,
> > but I don't want to risk bother him with a "automatic 3-way merge" warning).
> >
>
> Philippe, I think you created a lot of problems here without any real need.
Did I?
>
> We should sync between us rather than sent "surprise" "pull requests".
This I clearly understood. I doubt this will ever happen again.
>
> I am not happy with coordination of our common MIPS work.
I am also unhappy with my MIPS contributions.
Regards,
Phil.
>
> > >
> > > Thanks,
> > > Aleksandar
> > >
> > >
> > >> Thanks,
> > >>
> > >> Phil.
> > >>
> > >>> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
> > >>> ---
> > >>> hw/mips/mips_malta.c | 14 ++++++--------
> > >>> 1 file changed, 6 insertions(+), 8 deletions(-)
> > >>>
> > >>> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> > >>> index e4c4de1b4e..88869b828e 100644
> > >>> --- a/hw/mips/mips_malta.c
> > >>> +++ b/hw/mips/mips_malta.c
> > >>> @@ -427,10 +427,9 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
> > >>> break;
> > >>>
> > >>> default:
> > >>> -#if 0
> > >>> - printf("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
> > >>> - addr);
> > >>> -#endif
> > >>> + qemu_log_mask(LOG_GUEST_ERROR,
> > >>> + "malta_fpga_read: Bad register offset 0x"
> > >>> + TARGET_FMT_lx "\n", addr);
> > >>> break;
> > >>> }
> > >>> return val;
> > >>> @@ -515,10 +514,9 @@ static void malta_fpga_write(void *opaque, hwaddr addr,
> > >>> break;
> > >>>
> > >>> default:
> > >>> -#if 0
> > >>> - printf("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
> > >>> - addr);
> > >>> -#endif
> > >>> + qemu_log_mask(LOG_GUEST_ERROR,
> > >>> + "malta_fpga_write: Bad register offset 0x"
> > >>> + TARGET_FMT_lx "\n", addr);
> > >>> break;
> > >>> }
> > >>> }
> > >>>
> > >
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v6 21/21] hw/mips: Rename malta/mipssim/r4k/jazz files in hw/mips
2020-05-18 20:08 [PATCH v6 00/21] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (19 preceding siblings ...)
2020-05-18 20:09 ` [PATCH v6 20/21] hw/mips: Add some logging for bad register offset cases Aleksandar Markovic
@ 2020-05-18 20:09 ` Aleksandar Markovic
2020-05-26 7:44 ` Philippe Mathieu-Daudé
20 siblings, 1 reply; 29+ messages in thread
From: Aleksandar Markovic @ 2020-05-18 20:09 UTC (permalink / raw)
To: qemu-devel
Cc: aleksandar.rikalo, Aleksandar Markovic, Philippe Mathieu-Daudé
Machine file names should not have prefix "mips_".
Fuloong2e machine source file will be handled in a separate patch,
to avoid conflicts. That patch is pending integration into the
main tree.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
MAINTAINERS | 9 ++++-----
hw/mips/Makefile.objs | 8 ++++----
hw/mips/{mips_jazz.c => jazz.c} | 0
hw/mips/{mips_malta.c => malta.c} | 0
hw/mips/{mips_mipssim.c => mipssim.c} | 0
hw/mips/{mips_r4k.c => r4k.c} | 0
6 files changed, 8 insertions(+), 9 deletions(-)
rename hw/mips/{mips_jazz.c => jazz.c} (100%)
rename hw/mips/{mips_malta.c => malta.c} (100%)
rename hw/mips/{mips_mipssim.c => mipssim.c} (100%)
rename hw/mips/{mips_r4k.c => r4k.c} (100%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8d5562c5c7..883d15c9d7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11,7 +11,6 @@ consult qemu-devel and not any specific individual privately.
Descriptions of section entries:
- M: Mail patches to: FullName <address@domain>
Maintainers are looking after a certain area and must be CCed on
patches. They are considered the main contact point.
R: Designated reviewer: FullName <address@domain>
@@ -1043,7 +1042,7 @@ Jazz
M: Hervé Poussineau <hpoussin@reactos.org>
R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
S: Maintained
-F: hw/mips/mips_jazz.c
+F: hw/mips/jazz.c
F: hw/display/jazz_led.c
F: hw/dma/rc4030.c
@@ -1054,7 +1053,7 @@ R: Aurelien Jarno <aurelien@aurel32.net>
S: Maintained
F: hw/isa/piix4.c
F: hw/acpi/piix4.c
-F: hw/mips/mips_malta.c
+F: hw/mips/malta.c
F: hw/mips/gt64xxx_pci.c
F: include/hw/southbridge/piix.h
F: tests/acceptance/linux_ssh_mips_malta.py
@@ -1064,7 +1063,7 @@ Mipssim
M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
S: Odd Fixes
-F: hw/mips/mips_mipssim.c
+F: hw/mips/mipssim.c
F: hw/net/mipsnet.c
R4000
@@ -1072,7 +1071,7 @@ M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
R: Aurelien Jarno <aurelien@aurel32.net>
R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
S: Obsolete
-F: hw/mips/mips_r4k.c
+F: hw/mips/r4k.c
Fulong 2E
M: Philippe Mathieu-Daudé <f4bug@amsat.org>
diff --git a/hw/mips/Makefile.objs b/hw/mips/Makefile.objs
index 525809af07..1d767ed9a8 100644
--- a/hw/mips/Makefile.objs
+++ b/hw/mips/Makefile.objs
@@ -1,8 +1,8 @@
obj-y += addr.o mips_int.o
-obj-$(CONFIG_R4K) += mips_r4k.o
-obj-$(CONFIG_MALTA) += gt64xxx_pci.o mips_malta.o
-obj-$(CONFIG_MIPSSIM) += mips_mipssim.o
-obj-$(CONFIG_JAZZ) += mips_jazz.o
+obj-$(CONFIG_R4K) += r4k.o
+obj-$(CONFIG_MALTA) += gt64xxx_pci.o malta.o
+obj-$(CONFIG_MIPSSIM) += mipssim.o
+obj-$(CONFIG_JAZZ) += jazz.o
obj-$(CONFIG_FULONG) += mips_fulong2e.o
obj-$(CONFIG_MIPS_CPS) += cps.o
obj-$(CONFIG_MIPS_BOSTON) += boston.o
diff --git a/hw/mips/mips_jazz.c b/hw/mips/jazz.c
similarity index 100%
rename from hw/mips/mips_jazz.c
rename to hw/mips/jazz.c
diff --git a/hw/mips/mips_malta.c b/hw/mips/malta.c
similarity index 100%
rename from hw/mips/mips_malta.c
rename to hw/mips/malta.c
diff --git a/hw/mips/mips_mipssim.c b/hw/mips/mipssim.c
similarity index 100%
rename from hw/mips/mips_mipssim.c
rename to hw/mips/mipssim.c
diff --git a/hw/mips/mips_r4k.c b/hw/mips/r4k.c
similarity index 100%
rename from hw/mips/mips_r4k.c
rename to hw/mips/r4k.c
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH v6 21/21] hw/mips: Rename malta/mipssim/r4k/jazz files in hw/mips
2020-05-18 20:09 ` [PATCH v6 21/21] hw/mips: Rename malta/mipssim/r4k/jazz files in hw/mips Aleksandar Markovic
@ 2020-05-26 7:44 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-05-26 7:44 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel; +Cc: aleksandar.rikalo
On 5/18/20 10:09 PM, Aleksandar Markovic wrote:
> Machine file names should not have prefix "mips_".
>
> Fuloong2e machine source file will be handled in a separate patch,
> to avoid conflicts. That patch is pending integration into the
> main tree.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
> ---
> MAINTAINERS | 9 ++++-----
> hw/mips/Makefile.objs | 8 ++++----
> hw/mips/{mips_jazz.c => jazz.c} | 0
> hw/mips/{mips_malta.c => malta.c} | 0
> hw/mips/{mips_mipssim.c => mipssim.c} | 0
> hw/mips/{mips_r4k.c => r4k.c} | 0
> 6 files changed, 8 insertions(+), 9 deletions(-)
> rename hw/mips/{mips_jazz.c => jazz.c} (100%)
> rename hw/mips/{mips_malta.c => malta.c} (100%)
> rename hw/mips/{mips_mipssim.c => mipssim.c} (100%)
> rename hw/mips/{mips_r4k.c => r4k.c} (100%)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 8d5562c5c7..883d15c9d7 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -11,7 +11,6 @@ consult qemu-devel and not any specific individual privately.
>
> Descriptions of section entries:
>
> - M: Mail patches to: FullName <address@domain>
Thanks, queued to mips-next without removing the 'M' tag description.
> Maintainers are looking after a certain area and must be CCed on
> patches. They are considered the main contact point.
> R: Designated reviewer: FullName <address@domain>
> @@ -1043,7 +1042,7 @@ Jazz
> M: Hervé Poussineau <hpoussin@reactos.org>
> R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
> S: Maintained
> -F: hw/mips/mips_jazz.c
> +F: hw/mips/jazz.c
> F: hw/display/jazz_led.c
> F: hw/dma/rc4030.c
>
> @@ -1054,7 +1053,7 @@ R: Aurelien Jarno <aurelien@aurel32.net>
> S: Maintained
> F: hw/isa/piix4.c
> F: hw/acpi/piix4.c
> -F: hw/mips/mips_malta.c
> +F: hw/mips/malta.c
> F: hw/mips/gt64xxx_pci.c
> F: include/hw/southbridge/piix.h
> F: tests/acceptance/linux_ssh_mips_malta.py
> @@ -1064,7 +1063,7 @@ Mipssim
> M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
> R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
> S: Odd Fixes
> -F: hw/mips/mips_mipssim.c
> +F: hw/mips/mipssim.c
> F: hw/net/mipsnet.c
>
> R4000
> @@ -1072,7 +1071,7 @@ M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
> R: Aurelien Jarno <aurelien@aurel32.net>
> R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
> S: Obsolete
> -F: hw/mips/mips_r4k.c
> +F: hw/mips/r4k.c
>
> Fulong 2E
> M: Philippe Mathieu-Daudé <f4bug@amsat.org>
> diff --git a/hw/mips/Makefile.objs b/hw/mips/Makefile.objs
> index 525809af07..1d767ed9a8 100644
> --- a/hw/mips/Makefile.objs
> +++ b/hw/mips/Makefile.objs
> @@ -1,8 +1,8 @@
> obj-y += addr.o mips_int.o
> -obj-$(CONFIG_R4K) += mips_r4k.o
> -obj-$(CONFIG_MALTA) += gt64xxx_pci.o mips_malta.o
> -obj-$(CONFIG_MIPSSIM) += mips_mipssim.o
> -obj-$(CONFIG_JAZZ) += mips_jazz.o
> +obj-$(CONFIG_R4K) += r4k.o
> +obj-$(CONFIG_MALTA) += gt64xxx_pci.o malta.o
> +obj-$(CONFIG_MIPSSIM) += mipssim.o
> +obj-$(CONFIG_JAZZ) += jazz.o
> obj-$(CONFIG_FULONG) += mips_fulong2e.o
> obj-$(CONFIG_MIPS_CPS) += cps.o
> obj-$(CONFIG_MIPS_BOSTON) += boston.o
> diff --git a/hw/mips/mips_jazz.c b/hw/mips/jazz.c
> similarity index 100%
> rename from hw/mips/mips_jazz.c
> rename to hw/mips/jazz.c
> diff --git a/hw/mips/mips_malta.c b/hw/mips/malta.c
> similarity index 100%
> rename from hw/mips/mips_malta.c
> rename to hw/mips/malta.c
> diff --git a/hw/mips/mips_mipssim.c b/hw/mips/mipssim.c
> similarity index 100%
> rename from hw/mips/mips_mipssim.c
> rename to hw/mips/mipssim.c
> diff --git a/hw/mips/mips_r4k.c b/hw/mips/r4k.c
> similarity index 100%
> rename from hw/mips/mips_r4k.c
> rename to hw/mips/r4k.c
>
^ permalink raw reply [flat|nested] 29+ messages in thread