[PATCH v2 0/7] Base support for POWER10

[PATCH v2 0/7] Base support for POWER10

[Alistair Popple]

This series brings together several previously posted patches required for
POWER10 support and introduces a new patch enabling POWER10 architected
mode to enable booting as a POWER10 pseries guest.

It includes support for enabling facilities related to MMA and prefix
instructions.

Changes from v1:
  - Two bug-fixes to enable prefix and MMA on pseries
  - Minor updates to commit message wording
  - Fixes a build error when CONFIG_KVM_BOOK3S_64_HV is enabled

Alistair Popple (7):
  powerpc: Add new HWCAP bits
  powerpc: Add support for ISA v3.1
  powerpc/dt_cpu_ftrs: Advertise support for ISA v3.1 if selected
  powerpc/dt_cpu_ftrs: Set current thread fscr bits
  powerpc/dt_cpu_ftrs: Enable Prefixed Instructions
  powerpc/dt_cpu_ftrs: Add MMA feature
  powerpc: Add POWER10 architected mode

 arch/powerpc/include/asm/cputable.h      | 16 +++++++++++--
 arch/powerpc/include/asm/mmu.h           |  1 +
 arch/powerpc/include/asm/prom.h          |  1 +
 arch/powerpc/include/asm/reg.h           |  6 +++--
 arch/powerpc/include/uapi/asm/cputable.h |  2 ++
 arch/powerpc/kernel/cpu_setup_power.S    | 20 ++++++++++++++--
 arch/powerpc/kernel/cputable.c           | 30 ++++++++++++++++++++++++
 arch/powerpc/kernel/dt_cpu_ftrs.c        | 26 +++++++++++++++++++-
 arch/powerpc/kernel/prom_init.c          | 12 ++++++++--
 arch/powerpc/kvm/book3s_hv.c             |  3 ---
 10 files changed, 105 insertions(+), 12 deletions(-)

-- 
2.20.1

[PATCH v2 1/7] powerpc: Add new HWCAP bits

[Alistair Popple]

POWER10 introduces two new architectural features - ISAv3.1 and matrix
multiply accumulate (MMA) instructions. Userspace detects the presence
of these features via two HWCAP bits introduced in this patch. These
bits have been agreed to by the compiler and binutils team.

Signed-off-by: Alistair Popple <alistair@popple.id.au>
---
 arch/powerpc/include/uapi/asm/cputable.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/powerpc/include/uapi/asm/cputable.h b/arch/powerpc/include/uapi/asm/cputable.h
index 540592034740..2692a56bf20b 100644
--- a/arch/powerpc/include/uapi/asm/cputable.h
+++ b/arch/powerpc/include/uapi/asm/cputable.h
@@ -50,6 +50,8 @@
 #define PPC_FEATURE2_DARN		0x00200000 /* darn random number insn */
 #define PPC_FEATURE2_SCV		0x00100000 /* scv syscall */
 #define PPC_FEATURE2_HTM_NO_SUSPEND	0x00080000 /* TM w/out suspended state */
+#define PPC_FEATURE2_ARCH_3_1		0x00040000 /* ISA 3.1 */
+#define PPC_FEATURE2_MMA		0x00020000 /* Matrix Multiply Accumulate */
 
 /*
  * IMPORTANT!
-- 
2.20.1

Re: [PATCH v2 1/7] powerpc: Add new HWCAP bits

[Michael Neuling]

On Tue, 2020-05-19 at 10:31 +1000, Alistair Popple wrote:
> POWER10 introduces two new architectural features - ISAv3.1 and matrix
> multiply accumulate (MMA) instructions. Userspace detects the presence
> of these features via two HWCAP bits introduced in this patch. These
> bits have been agreed to by the compiler and binutils team.
> 
> Signed-off-by: Alistair Popple <alistair@popple.id.au>

I've test booted this series + powerpc/next (30df74d67d) on top of powervm and
OPAL on a P10 simulator.

In both cases, it enables MMA and prefix instructions and advertises them via
HWCAP2 MMA + ISA 3.1. Hence:

Tested-by: Michael Neuling <mikey@neuling.org>

> ---
>  arch/powerpc/include/uapi/asm/cputable.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/powerpc/include/uapi/asm/cputable.h
> b/arch/powerpc/include/uapi/asm/cputable.h
> index 540592034740..2692a56bf20b 100644
> --- a/arch/powerpc/include/uapi/asm/cputable.h
> +++ b/arch/powerpc/include/uapi/asm/cputable.h
> @@ -50,6 +50,8 @@
>  #define PPC_FEATURE2_DARN		0x00200000 /* darn random number insn */
>  #define PPC_FEATURE2_SCV		0x00100000 /* scv syscall */
>  #define PPC_FEATURE2_HTM_NO_SUSPEND	0x00080000 /* TM w/out suspended state
> */
> +#define PPC_FEATURE2_ARCH_3_1		0x00040000 /* ISA 3.1 */
> +#define PPC_FEATURE2_MMA		0x00020000 /* Matrix Multiply Accumulate
> */
>  
>  /*
>   * IMPORTANT!

Re: [PATCH v2 1/7] powerpc: Add new HWCAP bits

[Paul A. Clarke]

On Tue, May 19, 2020 at 10:31:51AM +1000, Alistair Popple wrote:
> POWER10 introduces two new architectural features - ISAv3.1 and matrix
> multiply accumulate (MMA) instructions. Userspace detects the presence
> of these features via two HWCAP bits introduced in this patch. These
> bits have been agreed to by the compiler and binutils team.
> 
> Signed-off-by: Alistair Popple <alistair@popple.id.au>
> ---
>  arch/powerpc/include/uapi/asm/cputable.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/powerpc/include/uapi/asm/cputable.h b/arch/powerpc/include/uapi/asm/cputable.h
> index 540592034740..2692a56bf20b 100644
> --- a/arch/powerpc/include/uapi/asm/cputable.h
> +++ b/arch/powerpc/include/uapi/asm/cputable.h
> @@ -50,6 +50,8 @@
>  #define PPC_FEATURE2_DARN		0x00200000 /* darn random number insn */
>  #define PPC_FEATURE2_SCV		0x00100000 /* scv syscall */
>  #define PPC_FEATURE2_HTM_NO_SUSPEND	0x00080000 /* TM w/out suspended state */
> +#define PPC_FEATURE2_ARCH_3_1		0x00040000 /* ISA 3.1 */
> +#define PPC_FEATURE2_MMA		0x00020000 /* Matrix Multiply Accumulate */

Carrying the conclusion of the recent discussion further, this should also be
"Matrix-Multiply Assist".

PC

Re: [PATCH v2 1/7] powerpc: Add new HWCAP bits

[Michael Ellerman]

Alistair Popple <alistair@popple.id.au> writes:
> POWER10 introduces two new architectural features - ISAv3.1 and matrix
> multiply accumulate (MMA) instructions. Userspace detects the presence
> of these features via two HWCAP bits introduced in this patch. These
> bits have been agreed to by the compiler and binutils team.

Do we have an explanation of why we're exposing MMA separately.

I believe it's because ISA v3.1 says that MMA is optional, in the table
on page ix?

cheers

> diff --git a/arch/powerpc/include/uapi/asm/cputable.h b/arch/powerpc/include/uapi/asm/cputable.h
> index 540592034740..2692a56bf20b 100644
> --- a/arch/powerpc/include/uapi/asm/cputable.h
> +++ b/arch/powerpc/include/uapi/asm/cputable.h
> @@ -50,6 +50,8 @@
>  #define PPC_FEATURE2_DARN		0x00200000 /* darn random number insn */
>  #define PPC_FEATURE2_SCV		0x00100000 /* scv syscall */
>  #define PPC_FEATURE2_HTM_NO_SUSPEND	0x00080000 /* TM w/out suspended state */
> +#define PPC_FEATURE2_ARCH_3_1		0x00040000 /* ISA 3.1 */
> +#define PPC_FEATURE2_MMA		0x00020000 /* Matrix Multiply Accumulate */
>  
>  /*
>   * IMPORTANT!
> -- 
> 2.20.1

Re: [PATCH v2 1/7] powerpc: Add new HWCAP bits

[Alistair Popple]

On Wednesday, 20 May 2020 12:42:09 PM AEST Michael Ellerman wrote:
> Alistair Popple <alistair@popple.id.au> writes:
> > POWER10 introduces two new architectural features - ISAv3.1 and matrix
> > multiply accumulate (MMA) instructions. Userspace detects the presence
> > of these features via two HWCAP bits introduced in this patch. These
> > bits have been agreed to by the compiler and binutils team.
> 
> Do we have an explanation of why we're exposing MMA separately.
> 
> I believe it's because ISA v3.1 says that MMA is optional, in the table
> on page ix?

Right, MMA is an optional feature and software should check for its presence 
prior to use. This is explicitly stated in the ISA on pg. 574:

7.6.1.12 VSX Matrix-Multiply Assist (MMA) Instructions
The MMA facility is optional. Software that uses this facility should test for 
its availability and provide an alternate
execution path.

The HWCAP bit is the mechanism for that. I can add the description to the 
commit message.

- Alistair
 
> cheers
> 
> > diff --git a/arch/powerpc/include/uapi/asm/cputable.h
> > b/arch/powerpc/include/uapi/asm/cputable.h index
> > 540592034740..2692a56bf20b 100644
> > --- a/arch/powerpc/include/uapi/asm/cputable.h
> > +++ b/arch/powerpc/include/uapi/asm/cputable.h
> > @@ -50,6 +50,8 @@
> > 
> >  #define PPC_FEATURE2_DARN		0x00200000 /* darn random number insn */
> >  #define PPC_FEATURE2_SCV		0x00100000 /* scv syscall */
> >  #define PPC_FEATURE2_HTM_NO_SUSPEND	0x00080000 /* TM w/out suspended
> >  state */> 
> > +#define PPC_FEATURE2_ARCH_3_1		0x00040000 /* ISA 3.1 */
> > +#define PPC_FEATURE2_MMA		0x00020000 /* Matrix Multiply Accumulate */
> > 
> >  /*
> >  
> >   * IMPORTANT!

[PATCH v2 2/7] powerpc: Add support for ISA v3.1

[Alistair Popple]

Newer ISA versions are enabled by clearing all bits in the PCR
associated with previous versions of the ISA. Enable ISA v3.1 support
by updating the PCR mask to include ISA v3.0. This ensures all PCR
bits corresponding to earlier architecture versions get cleared
thereby enabling ISA v3.1 if supported by the hardware.

Signed-off-by: Alistair Popple <alistair@popple.id.au>
---
 arch/powerpc/include/asm/cputable.h | 1 +
 arch/powerpc/include/asm/reg.h      | 3 ++-
 arch/powerpc/kvm/book3s_hv.c        | 3 ---
 3 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 40a4d3c6fd99..36f894dea9e7 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -213,6 +213,7 @@ static inline void cpu_feature_keys_init(void) { }
 #define CPU_FTR_P9_TIDR			LONG_ASM_CONST(0x0000800000000000)
 #define CPU_FTR_P9_TLBIE_ERAT_BUG	LONG_ASM_CONST(0x0001000000000000)
 #define CPU_FTR_P9_RADIX_PREFETCH_BUG	LONG_ASM_CONST(0x0002000000000000)
+#define CPU_FTR_ARCH_31			LONG_ASM_CONST(0x0004000000000000)
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 773f76402392..1931b1142599 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -485,10 +485,11 @@
  * determine both the compatibility level which we want to emulate and the
  * compatibility level which the host is capable of emulating.
  */
+#define   PCR_ARCH_300	0x10		/* Architecture 3.00 */
 #define   PCR_ARCH_207	0x8		/* Architecture 2.07 */
 #define   PCR_ARCH_206	0x4		/* Architecture 2.06 */
 #define   PCR_ARCH_205	0x2		/* Architecture 2.05 */
-#define   PCR_LOW_BITS	(PCR_ARCH_207 | PCR_ARCH_206 | PCR_ARCH_205)
+#define   PCR_LOW_BITS	(PCR_ARCH_207 | PCR_ARCH_206 | PCR_ARCH_205 | PCR_ARCH_300)
 #define   PCR_MASK	~(PCR_HIGH_BITS | PCR_LOW_BITS)	/* PCR Reserved Bits */
 #define	SPRN_HEIR	0x153	/* Hypervisor Emulated Instruction Register */
 #define SPRN_TLBINDEXR	0x154	/* P7 TLB control register */
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 93493f0cbfe8..532215040f3e 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -344,9 +344,6 @@ static void kvmppc_set_pvr_hv(struct kvm_vcpu *vcpu, u32 pvr)
 	vcpu->arch.pvr = pvr;
 }
 
-/* Dummy value used in computing PCR value below */
-#define PCR_ARCH_300	(PCR_ARCH_207 << 1)
-
 static int kvmppc_set_arch_compat(struct kvm_vcpu *vcpu, u32 arch_compat)
 {
 	unsigned long host_pcr_bit = 0, guest_pcr_bit = 0;
-- 
2.20.1

Re: [PATCH v2 2/7] powerpc: Add support for ISA v3.1

[Jordan Niethe]

On Tue, May 19, 2020 at 10:39 AM Alistair Popple <alistair@popple.id.au> wrote:
>
> Newer ISA versions are enabled by clearing all bits in the PCR
> associated with previous versions of the ISA. Enable ISA v3.1 support
> by updating the PCR mask to include ISA v3.0. This ensures all PCR
> bits corresponding to earlier architecture versions get cleared
> thereby enabling ISA v3.1 if supported by the hardware.
>
> Signed-off-by: Alistair Popple <alistair@popple.id.au>
> ---
>  arch/powerpc/include/asm/cputable.h | 1 +
>  arch/powerpc/include/asm/reg.h      | 3 ++-
>  arch/powerpc/kvm/book3s_hv.c        | 3 ---
>  3 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
> index 40a4d3c6fd99..36f894dea9e7 100644
> --- a/arch/powerpc/include/asm/cputable.h
> +++ b/arch/powerpc/include/asm/cputable.h
> @@ -213,6 +213,7 @@ static inline void cpu_feature_keys_init(void) { }
>  #define CPU_FTR_P9_TIDR                        LONG_ASM_CONST(0x0000800000000000)
>  #define CPU_FTR_P9_TLBIE_ERAT_BUG      LONG_ASM_CONST(0x0001000000000000)
>  #define CPU_FTR_P9_RADIX_PREFETCH_BUG  LONG_ASM_CONST(0x0002000000000000)
> +#define CPU_FTR_ARCH_31                        LONG_ASM_CONST(0x0004000000000000)
>
>  #ifndef __ASSEMBLY__
>
> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
> index 773f76402392..1931b1142599 100644
> --- a/arch/powerpc/include/asm/reg.h
> +++ b/arch/powerpc/include/asm/reg.h
> @@ -485,10 +485,11 @@
>   * determine both the compatibility level which we want to emulate and the
>   * compatibility level which the host is capable of emulating.
>   */
> +#define   PCR_ARCH_300 0x10            /* Architecture 3.00 */
>  #define   PCR_ARCH_207 0x8             /* Architecture 2.07 */
>  #define   PCR_ARCH_206 0x4             /* Architecture 2.06 */
>  #define   PCR_ARCH_205 0x2             /* Architecture 2.05 */
> -#define   PCR_LOW_BITS (PCR_ARCH_207 | PCR_ARCH_206 | PCR_ARCH_205)
> +#define   PCR_LOW_BITS (PCR_ARCH_207 | PCR_ARCH_206 | PCR_ARCH_205 | PCR_ARCH_300)
>  #define   PCR_MASK     ~(PCR_HIGH_BITS | PCR_LOW_BITS) /* PCR Reserved Bits */
>  #define        SPRN_HEIR       0x153   /* Hypervisor Emulated Instruction Register */
>  #define SPRN_TLBINDEXR 0x154   /* P7 TLB control register */
> diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
> index 93493f0cbfe8..532215040f3e 100644
> --- a/arch/powerpc/kvm/book3s_hv.c
> +++ b/arch/powerpc/kvm/book3s_hv.c
> @@ -344,9 +344,6 @@ static void kvmppc_set_pvr_hv(struct kvm_vcpu *vcpu, u32 pvr)
>         vcpu->arch.pvr = pvr;
>  }
>
> -/* Dummy value used in computing PCR value below */
> -#define PCR_ARCH_300   (PCR_ARCH_207 << 1)
> -
Later will we need
+/* Dummy value used in computing PCR value below */
+#define PCR_ARCH_310   (PCR_ARCH_300 << 1)
?
>  static int kvmppc_set_arch_compat(struct kvm_vcpu *vcpu, u32 arch_compat)
>  {
>         unsigned long host_pcr_bit = 0, guest_pcr_bit = 0;
> --
> 2.20.1
>

Re: [PATCH v2 2/7] powerpc: Add support for ISA v3.1

[Alistair Popple]

On Tuesday, 19 May 2020 2:04:51 PM AEST Jordan Niethe wrote:
> On Tue, May 19, 2020 at 10:39 AM Alistair Popple <alistair@popple.id.au> 
wrote:
> > Newer ISA versions are enabled by clearing all bits in the PCR
> > associated with previous versions of the ISA. Enable ISA v3.1 support
> > by updating the PCR mask to include ISA v3.0. This ensures all PCR
> > bits corresponding to earlier architecture versions get cleared
> > thereby enabling ISA v3.1 if supported by the hardware.
> > 
> > Signed-off-by: Alistair Popple <alistair@popple.id.au>
> > ---
> > 
> >  arch/powerpc/include/asm/cputable.h | 1 +
> >  arch/powerpc/include/asm/reg.h      | 3 ++-
> >  arch/powerpc/kvm/book3s_hv.c        | 3 ---
> >  3 files changed, 3 insertions(+), 4 deletions(-)
> > 
> > diff --git a/arch/powerpc/include/asm/cputable.h
> > b/arch/powerpc/include/asm/cputable.h index 40a4d3c6fd99..36f894dea9e7
> > 100644
> > --- a/arch/powerpc/include/asm/cputable.h
> > +++ b/arch/powerpc/include/asm/cputable.h
> > @@ -213,6 +213,7 @@ static inline void cpu_feature_keys_init(void) { }
> > 
> >  #define CPU_FTR_P9_TIDR                       
> >  LONG_ASM_CONST(0x0000800000000000) #define CPU_FTR_P9_TLBIE_ERAT_BUG    
> >   LONG_ASM_CONST(0x0001000000000000) #define
> >  CPU_FTR_P9_RADIX_PREFETCH_BUG  LONG_ASM_CONST(0x0002000000000000)> 
> > +#define CPU_FTR_ARCH_31                       
> > LONG_ASM_CONST(0x0004000000000000)> 
> >  #ifndef __ASSEMBLY__
> > 
> > diff --git a/arch/powerpc/include/asm/reg.h
> > b/arch/powerpc/include/asm/reg.h index 773f76402392..1931b1142599 100644
> > --- a/arch/powerpc/include/asm/reg.h
> > +++ b/arch/powerpc/include/asm/reg.h
> > @@ -485,10 +485,11 @@
> > 
> >   * determine both the compatibility level which we want to emulate and
> >   the
> >   * compatibility level which the host is capable of emulating.
> >   */
> > 
> > +#define   PCR_ARCH_300 0x10            /* Architecture 3.00 */
> > 
> >  #define   PCR_ARCH_207 0x8             /* Architecture 2.07 */
> >  #define   PCR_ARCH_206 0x4             /* Architecture 2.06 */
> >  #define   PCR_ARCH_205 0x2             /* Architecture 2.05 */
> > 
> > -#define   PCR_LOW_BITS (PCR_ARCH_207 | PCR_ARCH_206 | PCR_ARCH_205)
> > +#define   PCR_LOW_BITS (PCR_ARCH_207 | PCR_ARCH_206 | PCR_ARCH_205 |
> > PCR_ARCH_300)> 
> >  #define   PCR_MASK     ~(PCR_HIGH_BITS | PCR_LOW_BITS) /* PCR Reserved
> >  Bits */ #define        SPRN_HEIR       0x153   /* Hypervisor Emulated
> >  Instruction Register */ #define SPRN_TLBINDEXR 0x154   /* P7 TLB control
> >  register */
> > 
> > diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
> > index 93493f0cbfe8..532215040f3e 100644
> > --- a/arch/powerpc/kvm/book3s_hv.c
> > +++ b/arch/powerpc/kvm/book3s_hv.c
> > @@ -344,9 +344,6 @@ static void kvmppc_set_pvr_hv(struct kvm_vcpu *vcpu,
> > u32 pvr)> 
> >         vcpu->arch.pvr = pvr;
> >  
> >  }
> > 
> > -/* Dummy value used in computing PCR value below */
> > -#define PCR_ARCH_300   (PCR_ARCH_207 << 1)
> > -
> 
> Later will we need
> +/* Dummy value used in computing PCR value below */
> +#define PCR_ARCH_310   (PCR_ARCH_300 << 1)
> ?

Correct. I left that out of this patch series though as I am putting together 
a separate series for basic P10 KVM enablement which will add the definition 
for ARCH 3.1.

- Alistair

> >  static int kvmppc_set_arch_compat(struct kvm_vcpu *vcpu, u32 arch_compat)
> >  {
> >  
> >         unsigned long host_pcr_bit = 0, guest_pcr_bit = 0;
> > 
> > --
> > 2.20.1

[PATCH v2 3/7] powerpc/dt_cpu_ftrs: Advertise support for ISA v3.1 if selected

[Alistair Popple]

On powernv hardware support for ISAv3.1 is advertised via a cpu feature
bit in the device tree. This patch enables the associated HWCAP bit if
the device tree indicates ISAv3.1 is available.

Signed-off-by: Alistair Popple <alistair@popple.id.au>
---
 arch/powerpc/kernel/dt_cpu_ftrs.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c b/arch/powerpc/kernel/dt_cpu_ftrs.c
index 36bc0d5c4f3a..b5e21264d168 100644
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -26,6 +26,7 @@
 /* Device-tree visible constants follow */
 #define ISA_V2_07B      2070
 #define ISA_V3_0B       3000
+#define ISA_V3_1        3100
 
 #define USABLE_PR               (1U << 0)
 #define USABLE_OS               (1U << 1)
@@ -654,6 +655,11 @@ static void __init cpufeatures_setup_start(u32 isa)
 		cur_cpu_spec->cpu_features |= CPU_FTR_ARCH_300;
 		cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_ARCH_3_00;
 	}
+
+	if (isa >= 3100) {
+		cur_cpu_spec->cpu_features |= CPU_FTR_ARCH_31;
+		cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_ARCH_3_1;
+	}
 }
 
 static bool __init cpufeatures_process_feature(struct dt_cpu_feature *f)
-- 
2.20.1

[PATCH v2 4/7] powerpc/dt_cpu_ftrs: Set current thread fscr bits

[Alistair Popple]

Setting the FSCR bit directly in the SPR only sets it during the initial
boot and early init of the kernel but not for the init process or any
subsequent kthreads. This is because the thread_struct for those is
copied from the current thread_struct setup at boot which doesn't
reflect any changes made to the FSCR during cpu feature detection. This
patch ensures the current thread state is updated to match once feature
detection is complete.

Signed-off-by: Alistair Popple <alistair@popple.id.au>
---
 arch/powerpc/kernel/dt_cpu_ftrs.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c b/arch/powerpc/kernel/dt_cpu_ftrs.c
index b5e21264d168..677190f70cac 100644
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -170,6 +170,7 @@ static int __init feat_try_enable_unknown(struct dt_cpu_feature *f)
 		u64 fscr = mfspr(SPRN_FSCR);
 		fscr |= 1UL << f->fscr_bit_nr;
 		mtspr(SPRN_FSCR, fscr);
+		current->thread.fscr |= 1UL << f->fscr_bit_nr;
 	} else {
 		/* Does not have a known recipe */
 		return 0;
@@ -205,6 +206,7 @@ static int __init feat_enable(struct dt_cpu_feature *f)
 			u64 fscr = mfspr(SPRN_FSCR);
 			fscr |= 1UL << f->fscr_bit_nr;
 			mtspr(SPRN_FSCR, fscr);
+			current->thread.fscr |= 1UL << f->fscr_bit_nr;
 		}
 	}
 
-- 
2.20.1

[PATCH v2 5/7] powerpc/dt_cpu_ftrs: Enable Prefixed Instructions

[Alistair Popple]

Prefix instructions have their own FSCR bit which needs to be enabled
via a CPU feature. The kernel will save the FSCR for problem state but
it needs to be enabled initially.

Signed-off-by: Alistair Popple <alistair@popple.id.au>
---
 arch/powerpc/kernel/dt_cpu_ftrs.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c b/arch/powerpc/kernel/dt_cpu_ftrs.c
index 677190f70cac..93c340906aad 100644
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -628,6 +628,7 @@ static struct dt_cpu_feature_match __initdata
 	{"vector-binary128", feat_enable, 0},
 	{"vector-binary16", feat_enable, 0},
 	{"wait-v3", feat_enable, 0},
+	{"prefix-instructions", feat_enable, 0},
 };
 
 static bool __initdata using_dt_cpu_ftrs;
-- 
2.20.1

[PATCH v2 6/7] powerpc/dt_cpu_ftrs: Add MMA feature

[Alistair Popple]

Matrix multiple accumulate (MMA) is a new feature added to ISAv3.1 and
POWER10. Support on powernv can be selected via a firmware CPU device
tree feature which enables it via a PCR bit.

Signed-off-by: Alistair Popple <alistair@popple.id.au>
---
 arch/powerpc/include/asm/reg.h    |  3 ++-
 arch/powerpc/kernel/dt_cpu_ftrs.c | 17 ++++++++++++++++-
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 1931b1142599..c446863a40cf 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -479,7 +479,8 @@
 #define   PCR_VEC_DIS	(__MASK(63-0))	/* Vec. disable (bit NA since POWER8) */
 #define   PCR_VSX_DIS	(__MASK(63-1))	/* VSX disable (bit NA since POWER8) */
 #define   PCR_TM_DIS	(__MASK(63-2))	/* Trans. memory disable (POWER8) */
-#define   PCR_HIGH_BITS	(PCR_VEC_DIS | PCR_VSX_DIS | PCR_TM_DIS)
+#define   PCR_MMA_DIS	(__MASK(63-3)) /* Matrix-Multiply Accelerator */
+#define   PCR_HIGH_BITS	(PCR_MMA_DIS | PCR_VEC_DIS | PCR_VSX_DIS | PCR_TM_DIS)
 /*
  * These bits are used in the function kvmppc_set_arch_compat() to specify and
  * determine both the compatibility level which we want to emulate and the
diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c b/arch/powerpc/kernel/dt_cpu_ftrs.c
index 93c340906aad..e7540ee5cad8 100644
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -75,6 +75,7 @@ static struct {
 	u64	lpcr_clear;
 	u64	hfscr;
 	u64	fscr;
+	u64	pcr;
 } system_registers;
 
 static void (*init_pmu_registers)(void);
@@ -102,7 +103,7 @@ static void __restore_cpu_cpufeatures(void)
 	if (hv_mode) {
 		mtspr(SPRN_LPID, 0);
 		mtspr(SPRN_HFSCR, system_registers.hfscr);
-		mtspr(SPRN_PCR, PCR_MASK);
+		mtspr(SPRN_PCR, system_registers.pcr);
 	}
 	mtspr(SPRN_FSCR, system_registers.fscr);
 
@@ -555,6 +556,18 @@ static int __init feat_enable_large_ci(struct dt_cpu_feature *f)
 	return 1;
 }
 
+static int __init feat_enable_mma(struct dt_cpu_feature *f)
+{
+	u64 pcr;
+
+	feat_enable(f);
+	pcr = mfspr(SPRN_PCR);
+	pcr &= ~PCR_MMA_DIS;
+	mtspr(SPRN_PCR, pcr);
+
+	return 1;
+}
+
 struct dt_cpu_feature_match {
 	const char *name;
 	int (*enable)(struct dt_cpu_feature *f);
@@ -629,6 +642,7 @@ static struct dt_cpu_feature_match __initdata
 	{"vector-binary16", feat_enable, 0},
 	{"wait-v3", feat_enable, 0},
 	{"prefix-instructions", feat_enable, 0},
+	{"matrix-multiply-accumulate", feat_enable_mma, 0},
 };
 
 static bool __initdata using_dt_cpu_ftrs;
@@ -779,6 +793,7 @@ static void __init cpufeatures_setup_finished(void)
 	system_registers.lpcr = mfspr(SPRN_LPCR);
 	system_registers.hfscr = mfspr(SPRN_HFSCR);
 	system_registers.fscr = mfspr(SPRN_FSCR);
+	system_registers.pcr = mfspr(SPRN_PCR);
 
 	pr_info("final cpu/mmu features = 0x%016lx 0x%08x\n",
 		cur_cpu_spec->cpu_features, cur_cpu_spec->mmu_features);
-- 
2.20.1

Re: [PATCH v2 6/7] powerpc/dt_cpu_ftrs: Add MMA feature

[Paul A. Clarke]

On Tue, May 19, 2020 at 10:31:56AM +1000, Alistair Popple wrote:
> Matrix multiple accumulate (MMA) is a new feature added to ISAv3.1 and

nit: "Matrix-Multiply Accelerator".

PC

Re: [PATCH v2 6/7] powerpc/dt_cpu_ftrs: Add MMA feature

[Segher Boessenkool]

On Tue, May 19, 2020 at 09:49:22AM -0500, Paul A. Clarke wrote:
> On Tue, May 19, 2020 at 10:31:56AM +1000, Alistair Popple wrote:
> > Matrix multiple accumulate (MMA) is a new feature added to ISAv3.1 and
> 
> nit: "Matrix-Multiply Accelerator".

"Matrix-Multiply Assist" in fact :-)


Segher

Re: [PATCH v2 6/7] powerpc/dt_cpu_ftrs: Add MMA feature

[Paul A. Clarke]

On Tue, May 19, 2020 at 10:05:56AM -0500, Segher Boessenkool wrote:
> On Tue, May 19, 2020 at 09:49:22AM -0500, Paul A. Clarke wrote:
> > On Tue, May 19, 2020 at 10:31:56AM +1000, Alistair Popple wrote:
> > > Matrix multiple accumulate (MMA) is a new feature added to ISAv3.1 and
> > 
> > nit: "Matrix-Multiply Accelerator".
> 
> "Matrix-Multiply Assist" in fact :-)

Not according to the ISA (p. 1129).

PC

Re: [PATCH v2 6/7] powerpc/dt_cpu_ftrs: Add MMA feature

[Segher Boessenkool]

On Tue, May 19, 2020 at 10:22:40AM -0500, Paul A. Clarke wrote:
> On Tue, May 19, 2020 at 10:05:56AM -0500, Segher Boessenkool wrote:
> > On Tue, May 19, 2020 at 09:49:22AM -0500, Paul A. Clarke wrote:
> > > On Tue, May 19, 2020 at 10:31:56AM +1000, Alistair Popple wrote:
> > > > Matrix multiple accumulate (MMA) is a new feature added to ISAv3.1 and
> > > 
> > > nit: "Matrix-Multiply Accelerator".
> > 
> > "Matrix-Multiply Assist" in fact :-)
> 
> Not according to the ISA (p. 1129).

There is one mistake in the 3.1 ABI yes, in the description for the PCR
bit of this same name.  Everything else calls this "assist", like all
similar things are called as well (whereas an "accelerator" is an
external device).


Segher

Re: [PATCH v2 6/7] powerpc/dt_cpu_ftrs: Add MMA feature

[Paul A. Clarke]

On Tue, May 19, 2020 at 10:28:55AM -0500, Segher Boessenkool wrote:
> On Tue, May 19, 2020 at 10:22:40AM -0500, Paul A. Clarke wrote:
> > On Tue, May 19, 2020 at 10:05:56AM -0500, Segher Boessenkool wrote:
> > > On Tue, May 19, 2020 at 09:49:22AM -0500, Paul A. Clarke wrote:
> > > > On Tue, May 19, 2020 at 10:31:56AM +1000, Alistair Popple wrote:
> > > > > Matrix multiple accumulate (MMA) is a new feature added to ISAv3.1 and
> > > > 
> > > > nit: "Matrix-Multiply Accelerator".
> > > 
> > > "Matrix-Multiply Assist" in fact :-)
> > 
> > Not according to the ISA (p. 1129).
> 
> There is one mistake in the 3.1 ABI yes, in the description for the PCR
> bit of this same name.  Everything else calls this "assist", like all
> similar things are called as well (whereas an "accelerator" is an
> external device).

I stand corrected. The PCR bit description is in error, and that's what I
was going by.  Section 7.6.1.12 "VSX Matrix-Multiply Assist (MMA)
Instructions" seems to be more definitive.  Thanks, Segher, for correcting
my correction.

Should be "Matrix-Multiply Assist".

:-)

PC

Re: [PATCH v2 6/7] powerpc/dt_cpu_ftrs: Add MMA feature

[Paul A. Clarke]

On Tue, May 19, 2020 at 10:31:56AM +1000, Alistair Popple wrote:
> Matrix multiple accumulate (MMA) is a new feature added to ISAv3.1 and

Conclusion is that this should be "Matrix-Multiply Assist", but then there
are a couple more below...

> POWER10. Support on powernv can be selected via a firmware CPU device
> tree feature which enables it via a PCR bit.
> 
> Signed-off-by: Alistair Popple <alistair@popple.id.au>
> ---
>  arch/powerpc/include/asm/reg.h    |  3 ++-
>  arch/powerpc/kernel/dt_cpu_ftrs.c | 17 ++++++++++++++++-
>  2 files changed, 18 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
> index 1931b1142599..c446863a40cf 100644
> --- a/arch/powerpc/include/asm/reg.h
> +++ b/arch/powerpc/include/asm/reg.h
> @@ -479,7 +479,8 @@
>  #define   PCR_VEC_DIS	(__MASK(63-0))	/* Vec. disable (bit NA since POWER8) */
>  #define   PCR_VSX_DIS	(__MASK(63-1))	/* VSX disable (bit NA since POWER8) */
>  #define   PCR_TM_DIS	(__MASK(63-2))	/* Trans. memory disable (POWER8) */
> -#define   PCR_HIGH_BITS	(PCR_VEC_DIS | PCR_VSX_DIS | PCR_TM_DIS)
> +#define   PCR_MMA_DIS	(__MASK(63-3)) /* Matrix-Multiply Accelerator */

also here.

> +#define   PCR_HIGH_BITS	(PCR_MMA_DIS | PCR_VEC_DIS | PCR_VSX_DIS | PCR_TM_DIS)
>  /*
>   * These bits are used in the function kvmppc_set_arch_compat() to specify and
>   * determine both the compatibility level which we want to emulate and the
> diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c b/arch/powerpc/kernel/dt_cpu_ftrs.c
> index 93c340906aad..e7540ee5cad8 100644
> --- a/arch/powerpc/kernel/dt_cpu_ftrs.c
> +++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
> @@ -75,6 +75,7 @@ static struct {
>  	u64	lpcr_clear;
>  	u64	hfscr;
>  	u64	fscr;
> +	u64	pcr;
>  } system_registers;
> 
>  static void (*init_pmu_registers)(void);
> @@ -102,7 +103,7 @@ static void __restore_cpu_cpufeatures(void)
>  	if (hv_mode) {
>  		mtspr(SPRN_LPID, 0);
>  		mtspr(SPRN_HFSCR, system_registers.hfscr);
> -		mtspr(SPRN_PCR, PCR_MASK);
> +		mtspr(SPRN_PCR, system_registers.pcr);
>  	}
>  	mtspr(SPRN_FSCR, system_registers.fscr);
> 
> @@ -555,6 +556,18 @@ static int __init feat_enable_large_ci(struct dt_cpu_feature *f)
>  	return 1;
>  }
> 
> +static int __init feat_enable_mma(struct dt_cpu_feature *f)
> +{
> +	u64 pcr;
> +
> +	feat_enable(f);
> +	pcr = mfspr(SPRN_PCR);
> +	pcr &= ~PCR_MMA_DIS;
> +	mtspr(SPRN_PCR, pcr);
> +
> +	return 1;
> +}
> +
>  struct dt_cpu_feature_match {
>  	const char *name;
>  	int (*enable)(struct dt_cpu_feature *f);
> @@ -629,6 +642,7 @@ static struct dt_cpu_feature_match __initdata
>  	{"vector-binary16", feat_enable, 0},
>  	{"wait-v3", feat_enable, 0},
>  	{"prefix-instructions", feat_enable, 0},
> +	{"matrix-multiply-accumulate", feat_enable_mma, 0},

and presumably here as well.

>  };

PC

Re: [PATCH v2 6/7] powerpc/dt_cpu_ftrs: Add MMA feature

[Alistair Popple]

Thanks, not sure where I got that name from but it's probably wrong in a few 
places. Will wait a bit in case there are any more comments and then respin 
the series to update the name.

- Alistair

On Wednesday, 20 May 2020 3:51:53 AM AEST Paul A. Clarke wrote:
> On Tue, May 19, 2020 at 10:31:56AM +1000, Alistair Popple wrote:
> > Matrix multiple accumulate (MMA) is a new feature added to ISAv3.1 and
> 
> Conclusion is that this should be "Matrix-Multiply Assist", but then there
> are a couple more below...
> 
> > POWER10. Support on powernv can be selected via a firmware CPU device
> > tree feature which enables it via a PCR bit.
> > 
> > Signed-off-by: Alistair Popple <alistair@popple.id.au>
> > ---
> > 
> >  arch/powerpc/include/asm/reg.h    |  3 ++-
> >  arch/powerpc/kernel/dt_cpu_ftrs.c | 17 ++++++++++++++++-
> >  2 files changed, 18 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/powerpc/include/asm/reg.h
> > b/arch/powerpc/include/asm/reg.h index 1931b1142599..c446863a40cf 100644
> > --- a/arch/powerpc/include/asm/reg.h
> > +++ b/arch/powerpc/include/asm/reg.h
> > @@ -479,7 +479,8 @@
> > 
> >  #define   PCR_VEC_DIS	(__MASK(63-0))	/* Vec. disable (bit NA since
> >  POWER8) */ #define   PCR_VSX_DIS	(__MASK(63-1))	/* VSX disable (bit NA
> >  since POWER8) */ #define   PCR_TM_DIS	(__MASK(63-2))	/* Trans. memory
> >  disable (POWER8) */> 
> > -#define   PCR_HIGH_BITS	(PCR_VEC_DIS | PCR_VSX_DIS | PCR_TM_DIS)
> > +#define   PCR_MMA_DIS	(__MASK(63-3)) /* Matrix-Multiply Accelerator */
> 
> also here.
> 
> > +#define   PCR_HIGH_BITS	(PCR_MMA_DIS | PCR_VEC_DIS | PCR_VSX_DIS |
> > PCR_TM_DIS)> 
> >  /*
> >  
> >   * These bits are used in the function kvmppc_set_arch_compat() to
> >   specify and * determine both the compatibility level which we want to
> >   emulate and the> 
> > diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c
> > b/arch/powerpc/kernel/dt_cpu_ftrs.c index 93c340906aad..e7540ee5cad8
> > 100644
> > --- a/arch/powerpc/kernel/dt_cpu_ftrs.c
> > +++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
> > @@ -75,6 +75,7 @@ static struct {
> > 
> >  	u64	lpcr_clear;
> >  	u64	hfscr;
> >  	u64	fscr;
> > 
> > +	u64	pcr;
> > 
> >  } system_registers;
> >  
> >  static void (*init_pmu_registers)(void);
> > 
> > @@ -102,7 +103,7 @@ static void __restore_cpu_cpufeatures(void)
> > 
> >  	if (hv_mode) {
> >  	
> >  		mtspr(SPRN_LPID, 0);
> >  		mtspr(SPRN_HFSCR, system_registers.hfscr);
> > 
> > -		mtspr(SPRN_PCR, PCR_MASK);
> > +		mtspr(SPRN_PCR, system_registers.pcr);
> > 
> >  	}
> >  	mtspr(SPRN_FSCR, system_registers.fscr);
> > 
> > @@ -555,6 +556,18 @@ static int __init feat_enable_large_ci(struct
> > dt_cpu_feature *f)> 
> >  	return 1;
> >  
> >  }
> > 
> > +static int __init feat_enable_mma(struct dt_cpu_feature *f)
> > +{
> > +	u64 pcr;
> > +
> > +	feat_enable(f);
> > +	pcr = mfspr(SPRN_PCR);
> > +	pcr &= ~PCR_MMA_DIS;
> > +	mtspr(SPRN_PCR, pcr);
> > +
> > +	return 1;
> > +}
> > +
> > 
> >  struct dt_cpu_feature_match {
> >  
> >  	const char *name;
> >  	int (*enable)(struct dt_cpu_feature *f);
> > 
> > @@ -629,6 +642,7 @@ static struct dt_cpu_feature_match __initdata
> > 
> >  	{"vector-binary16", feat_enable, 0},
> >  	{"wait-v3", feat_enable, 0},
> >  	{"prefix-instructions", feat_enable, 0},
> > 
> > +	{"matrix-multiply-accumulate", feat_enable_mma, 0},
> 
> and presumably here as well.
> 
> >  };
> 
> PC

[PATCH v2 7/7] powerpc: Add POWER10 architected mode

[Alistair Popple]

PVR value of 0x0F000006 means we are arch v3.1 compliant (i.e. POWER10).
This is used by phyp and kvm when booting as a pseries guest to detect
the presence of new P10 features and to enable the appropriate hwcap and
facility bits.

Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 arch/powerpc/include/asm/cputable.h   | 15 ++++++++++++--
 arch/powerpc/include/asm/mmu.h        |  1 +
 arch/powerpc/include/asm/prom.h       |  1 +
 arch/powerpc/kernel/cpu_setup_power.S | 20 ++++++++++++++++--
 arch/powerpc/kernel/cputable.c        | 30 +++++++++++++++++++++++++++
 arch/powerpc/kernel/prom_init.c       | 12 +++++++++--
 6 files changed, 73 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 36f894dea9e7..10b6d93c9d0b 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -468,6 +468,17 @@ static inline void cpu_feature_keys_init(void) { }
 #define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
 			       CPU_FTR_P9_TM_HV_ASSIST | \
 			       CPU_FTR_P9_TM_XER_SO_BUG)
+#define CPU_FTRS_POWER10 (CPU_FTR_LWSYNC | \
+	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
+	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
+	    CPU_FTR_COHERENT_ICACHE | \
+	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
+	    CPU_FTR_DSCR | CPU_FTR_SAO  | \
+	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
+	    CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
+	    CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
+	    CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_PKEY | \
+	    CPU_FTR_ARCH_31)
 #define CPU_FTRS_CELL	(CPU_FTR_LWSYNC | \
 	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -486,14 +497,14 @@ static inline void cpu_feature_keys_init(void) { }
 #define CPU_FTRS_POSSIBLE	\
 	    (CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \
 	     CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | CPU_FTRS_POWER9 | \
-	     CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2)
+	     CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
 #else
 #define CPU_FTRS_POSSIBLE	\
 	    (CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
 	     CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
 	     CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
 	     CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | CPU_FTRS_POWER9 | \
-	     CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2)
+	     CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
 #endif
 #else
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 0699cfeeb8c9..17b19510f204 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -122,6 +122,7 @@
 #define MMU_FTRS_POWER7		MMU_FTRS_POWER6
 #define MMU_FTRS_POWER8		MMU_FTRS_POWER6
 #define MMU_FTRS_POWER9		MMU_FTRS_POWER6
+#define MMU_FTRS_POWER10	MMU_FTRS_POWER6
 #define MMU_FTRS_CELL		MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
 				MMU_FTR_CI_LARGE_PAGE
 #define MMU_FTRS_PA6T		MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h
index 94e3fd54f2c8..324a13351749 100644
--- a/arch/powerpc/include/asm/prom.h
+++ b/arch/powerpc/include/asm/prom.h
@@ -117,6 +117,7 @@ extern int of_read_drc_info_cell(struct property **prop,
 #define OV1_PPC_2_07		0x01	/* set if we support PowerPC 2.07 */
 
 #define OV1_PPC_3_00		0x80	/* set if we support PowerPC 3.00 */
+#define OV1_PPC_3_1			0x40	/* set if we support PowerPC 3.1 */
 
 /* Option vector 2: Open Firmware options supported */
 #define OV2_REAL_MODE		0x20	/* set if we want OF in real mode */
diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
index a460298c7ddb..f3730cf904fa 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -91,10 +91,15 @@ _GLOBAL(__restore_cpu_power8)
 	mtlr	r11
 	blr
 
+_GLOBAL(__setup_cpu_power10)
+	mflr	r11
+	bl	__init_FSCR_P10
+	b	1f
+
 _GLOBAL(__setup_cpu_power9)
 	mflr	r11
 	bl	__init_FSCR
-	bl	__init_PMU
+1:	bl	__init_PMU
 	bl	__init_hvmode_206
 	mtlr	r11
 	beqlr
@@ -116,10 +121,15 @@ _GLOBAL(__setup_cpu_power9)
 	mtlr	r11
 	blr
 
+_GLOBAL(__restore_cpu_power10)
+	mflr	r11
+	bl	__init_FSCR_P10
+	b	1f
+
 _GLOBAL(__restore_cpu_power9)
 	mflr	r11
 	bl	__init_FSCR
-	bl	__init_PMU
+1:	bl	__init_PMU
 	mfmsr	r3
 	rldicl.	r0,r3,4,63
 	mtlr	r11
@@ -182,6 +192,12 @@ __init_LPCR_ISA300:
 	isync
 	blr
 
+__init_FSCR_P10:
+	mfspr	r3,SPRN_FSCR
+	ori	r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB|FSCR_PREFIX
+	mtspr	SPRN_FSCR,r3
+	blr
+
 __init_FSCR:
 	mfspr	r3,SPRN_FSCR
 	ori	r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 13eba2eb46fe..a17eeb311cdb 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -70,6 +70,8 @@ extern void __setup_cpu_power8(unsigned long offset, struct cpu_spec* spec);
 extern void __restore_cpu_power8(void);
 extern void __setup_cpu_power9(unsigned long offset, struct cpu_spec* spec);
 extern void __restore_cpu_power9(void);
+extern void __setup_cpu_power10(unsigned long offset, struct cpu_spec* spec);
+extern void __restore_cpu_power10(void);
 extern long __machine_check_early_realmode_p7(struct pt_regs *regs);
 extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
 extern long __machine_check_early_realmode_p9(struct pt_regs *regs);
@@ -119,6 +121,10 @@ extern void __restore_cpu_e6500(void);
 				 PPC_FEATURE2_ARCH_3_00 | \
 				 PPC_FEATURE2_HAS_IEEE128 | \
 				 PPC_FEATURE2_DARN )
+#define COMMON_USER_POWER10	COMMON_USER_POWER9
+#define COMMON_USER2_POWER10	(COMMON_USER2_POWER9 | \
+				 PPC_FEATURE2_ARCH_3_1 | \
+				 PPC_FEATURE2_MMA)
 
 #ifdef CONFIG_PPC_BOOK3E_64
 #define COMMON_USER_BOOKE	(COMMON_USER_PPC64 | PPC_FEATURE_BOOKE)
@@ -127,6 +133,14 @@ extern void __restore_cpu_e6500(void);
 				 PPC_FEATURE_BOOKE)
 #endif
 
+#ifdef CONFIG_PPC64
+static void setup_cpu_power10(unsigned long offset, struct cpu_spec* spec)
+{
+	__setup_cpu_power10(offset, spec);
+	current->thread.fscr |= FSCR_PREFIX;
+}
+#endif
+
 static struct cpu_spec __initdata cpu_specs[] = {
 #ifdef CONFIG_PPC_BOOK3S_64
 	{	/* PPC970 */
@@ -367,6 +381,22 @@ static struct cpu_spec __initdata cpu_specs[] = {
 		.cpu_restore		= __restore_cpu_power9,
 		.platform		= "power9",
 	},
+	{	/* 3.1-compliant processor, i.e. Power10 "architected" mode */
+		.pvr_mask		= 0xffffffff,
+		.pvr_value		= 0x0f000006,
+		.cpu_name		= "POWER10 (architected)",
+		.cpu_features		= CPU_FTRS_POWER10,
+		.cpu_user_features	= COMMON_USER_POWER10,
+		.cpu_user_features2	= COMMON_USER2_POWER10,
+		.mmu_features		= MMU_FTRS_POWER10,
+		.icache_bsize		= 128,
+		.dcache_bsize		= 128,
+		.oprofile_type		= PPC_OPROFILE_INVALID,
+		.oprofile_cpu_type	= "ppc64/ibm-compat-v1",
+		.cpu_setup		= setup_cpu_power10,
+		.cpu_restore		= __restore_cpu_power10,
+		.platform		= "power10",
+	},
 	{	/* Power7 */
 		.pvr_mask		= 0xffff0000,
 		.pvr_value		= 0x003f0000,
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 806be751c336..1ecadbd7e8b2 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -920,7 +920,7 @@ struct option_vector6 {
 } __packed;
 
 struct ibm_arch_vec {
-	struct { u32 mask, val; } pvrs[12];
+	struct { u32 mask, val; } pvrs[14];
 
 	u8 num_vectors;
 
@@ -973,6 +973,14 @@ static const struct ibm_arch_vec ibm_architecture_vec_template __initconst = {
 			.mask = cpu_to_be32(0xffff0000), /* POWER9 */
 			.val  = cpu_to_be32(0x004e0000),
 		},
+		{
+			.mask = cpu_to_be32(0xffff0000), /* POWER10 */
+			.val  = cpu_to_be32(0x00800000),
+		},
+		{
+			.mask = cpu_to_be32(0xffffffff), /* all 3.1-compliant */
+			.val  = cpu_to_be32(0x0f000006),
+		},
 		{
 			.mask = cpu_to_be32(0xffffffff), /* all 3.00-compliant */
 			.val  = cpu_to_be32(0x0f000005),
@@ -1002,7 +1010,7 @@ static const struct ibm_arch_vec ibm_architecture_vec_template __initconst = {
 		.byte1 = 0,
 		.arch_versions = OV1_PPC_2_00 | OV1_PPC_2_01 | OV1_PPC_2_02 | OV1_PPC_2_03 |
 				 OV1_PPC_2_04 | OV1_PPC_2_05 | OV1_PPC_2_06 | OV1_PPC_2_07,
-		.arch_versions3 = OV1_PPC_3_00,
+		.arch_versions3 = OV1_PPC_3_00 | OV1_PPC_3_1,
 	},
 
 	.vec2_len = VECTOR_LENGTH(sizeof(struct option_vector2)),
-- 
2.20.1

Re: [PATCH v2 7/7] powerpc: Add POWER10 architected mode

[Jordan Niethe]

On Tue, May 19, 2020 at 10:48 AM Alistair Popple <alistair@popple.id.au> wrote:
>
> PVR value of 0x0F000006 means we are arch v3.1 compliant (i.e. POWER10).
> This is used by phyp and kvm when booting as a pseries guest to detect
> the presence of new P10 features and to enable the appropriate hwcap and
> facility bits.
>
> Signed-off-by: Alistair Popple <alistair@popple.id.au>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
>  arch/powerpc/include/asm/cputable.h   | 15 ++++++++++++--
>  arch/powerpc/include/asm/mmu.h        |  1 +
>  arch/powerpc/include/asm/prom.h       |  1 +
>  arch/powerpc/kernel/cpu_setup_power.S | 20 ++++++++++++++++--
>  arch/powerpc/kernel/cputable.c        | 30 +++++++++++++++++++++++++++
>  arch/powerpc/kernel/prom_init.c       | 12 +++++++++--
>  6 files changed, 73 insertions(+), 6 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
> index 36f894dea9e7..10b6d93c9d0b 100644
> --- a/arch/powerpc/include/asm/cputable.h
> +++ b/arch/powerpc/include/asm/cputable.h
> @@ -468,6 +468,17 @@ static inline void cpu_feature_keys_init(void) { }
>  #define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
>                                CPU_FTR_P9_TM_HV_ASSIST | \
>                                CPU_FTR_P9_TM_XER_SO_BUG)
> +#define CPU_FTRS_POWER10 (CPU_FTR_LWSYNC | \
> +           CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
> +           CPU_FTR_MMCRA | CPU_FTR_SMT | \
> +           CPU_FTR_COHERENT_ICACHE | \
> +           CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
> +           CPU_FTR_DSCR | CPU_FTR_SAO  | \
> +           CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
> +           CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
> +           CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
> +           CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_PKEY | \
> +           CPU_FTR_ARCH_31)
>  #define CPU_FTRS_CELL  (CPU_FTR_LWSYNC | \
>             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
>             CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
> @@ -486,14 +497,14 @@ static inline void cpu_feature_keys_init(void) { }
>  #define CPU_FTRS_POSSIBLE      \
>             (CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \
>              CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | CPU_FTRS_POWER9 | \
> -            CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2)
> +            CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
>  #else
>  #define CPU_FTRS_POSSIBLE      \
>             (CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
>              CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
>              CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
>              CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | CPU_FTRS_POWER9 | \
> -            CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2)
> +            CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
>  #endif /* CONFIG_CPU_LITTLE_ENDIAN */
>  #endif
>  #else
> diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
> index 0699cfeeb8c9..17b19510f204 100644
> --- a/arch/powerpc/include/asm/mmu.h
> +++ b/arch/powerpc/include/asm/mmu.h
> @@ -122,6 +122,7 @@
>  #define MMU_FTRS_POWER7                MMU_FTRS_POWER6
>  #define MMU_FTRS_POWER8                MMU_FTRS_POWER6
>  #define MMU_FTRS_POWER9                MMU_FTRS_POWER6
> +#define MMU_FTRS_POWER10       MMU_FTRS_POWER6
>  #define MMU_FTRS_CELL          MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
>                                 MMU_FTR_CI_LARGE_PAGE
>  #define MMU_FTRS_PA6T          MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
> diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h
> index 94e3fd54f2c8..324a13351749 100644
> --- a/arch/powerpc/include/asm/prom.h
> +++ b/arch/powerpc/include/asm/prom.h
> @@ -117,6 +117,7 @@ extern int of_read_drc_info_cell(struct property **prop,
>  #define OV1_PPC_2_07           0x01    /* set if we support PowerPC 2.07 */
>
>  #define OV1_PPC_3_00           0x80    /* set if we support PowerPC 3.00 */
> +#define OV1_PPC_3_1                    0x40    /* set if we support PowerPC 3.1 */
>
>  /* Option vector 2: Open Firmware options supported */
>  #define OV2_REAL_MODE          0x20    /* set if we want OF in real mode */
> diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
> index a460298c7ddb..f3730cf904fa 100644
> --- a/arch/powerpc/kernel/cpu_setup_power.S
> +++ b/arch/powerpc/kernel/cpu_setup_power.S
> @@ -91,10 +91,15 @@ _GLOBAL(__restore_cpu_power8)
>         mtlr    r11
>         blr
>
> +_GLOBAL(__setup_cpu_power10)
> +       mflr    r11
> +       bl      __init_FSCR_P10
> +       b       1f
> +
>  _GLOBAL(__setup_cpu_power9)
>         mflr    r11
>         bl      __init_FSCR
> -       bl      __init_PMU
> +1:     bl      __init_PMU
>         bl      __init_hvmode_206
>         mtlr    r11
>         beqlr
> @@ -116,10 +121,15 @@ _GLOBAL(__setup_cpu_power9)
>         mtlr    r11
>         blr
>
> +_GLOBAL(__restore_cpu_power10)
> +       mflr    r11
> +       bl      __init_FSCR_P10
> +       b       1f
> +
>  _GLOBAL(__restore_cpu_power9)
>         mflr    r11
>         bl      __init_FSCR
> -       bl      __init_PMU
> +1:     bl      __init_PMU
>         mfmsr   r3
>         rldicl. r0,r3,4,63
>         mtlr    r11
> @@ -182,6 +192,12 @@ __init_LPCR_ISA300:
>         isync
>         blr
>
> +__init_FSCR_P10:
> +       mfspr   r3,SPRN_FSCR
> +       ori     r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB|FSCR_PREFIX
> +       mtspr   SPRN_FSCR,r3
> +       blr
> +
>  __init_FSCR:
>         mfspr   r3,SPRN_FSCR
>         ori     r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
> diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
> index 13eba2eb46fe..a17eeb311cdb 100644
> --- a/arch/powerpc/kernel/cputable.c
> +++ b/arch/powerpc/kernel/cputable.c
> @@ -70,6 +70,8 @@ extern void __setup_cpu_power8(unsigned long offset, struct cpu_spec* spec);
>  extern void __restore_cpu_power8(void);
>  extern void __setup_cpu_power9(unsigned long offset, struct cpu_spec* spec);
>  extern void __restore_cpu_power9(void);
> +extern void __setup_cpu_power10(unsigned long offset, struct cpu_spec* spec);
> +extern void __restore_cpu_power10(void);
>  extern long __machine_check_early_realmode_p7(struct pt_regs *regs);
>  extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
>  extern long __machine_check_early_realmode_p9(struct pt_regs *regs);
> @@ -119,6 +121,10 @@ extern void __restore_cpu_e6500(void);
>                                  PPC_FEATURE2_ARCH_3_00 | \
>                                  PPC_FEATURE2_HAS_IEEE128 | \
>                                  PPC_FEATURE2_DARN )
> +#define COMMON_USER_POWER10    COMMON_USER_POWER9
> +#define COMMON_USER2_POWER10   (COMMON_USER2_POWER9 | \
> +                                PPC_FEATURE2_ARCH_3_1 | \
> +                                PPC_FEATURE2_MMA)
>
>  #ifdef CONFIG_PPC_BOOK3E_64
>  #define COMMON_USER_BOOKE      (COMMON_USER_PPC64 | PPC_FEATURE_BOOKE)
> @@ -127,6 +133,14 @@ extern void __restore_cpu_e6500(void);
>                                  PPC_FEATURE_BOOKE)
>  #endif
>
> +#ifdef CONFIG_PPC64
> +static void setup_cpu_power10(unsigned long offset, struct cpu_spec* spec)
> +{
> +       __setup_cpu_power10(offset, spec);
> +       current->thread.fscr |= FSCR_PREFIX;
> +}
> +#endif
> +
>  static struct cpu_spec __initdata cpu_specs[] = {
>  #ifdef CONFIG_PPC_BOOK3S_64
>         {       /* PPC970 */
> @@ -367,6 +381,22 @@ static struct cpu_spec __initdata cpu_specs[] = {
>                 .cpu_restore            = __restore_cpu_power9,
>                 .platform               = "power9",
>         },
> +       {       /* 3.1-compliant processor, i.e. Power10 "architected" mode */
> +               .pvr_mask               = 0xffffffff,
> +               .pvr_value              = 0x0f000006,
> +               .cpu_name               = "POWER10 (architected)",
> +               .cpu_features           = CPU_FTRS_POWER10,
> +               .cpu_user_features      = COMMON_USER_POWER10,
> +               .cpu_user_features2     = COMMON_USER2_POWER10,
> +               .mmu_features           = MMU_FTRS_POWER10,
> +               .icache_bsize           = 128,
> +               .dcache_bsize           = 128,
> +               .oprofile_type          = PPC_OPROFILE_INVALID,
> +               .oprofile_cpu_type      = "ppc64/ibm-compat-v1",
> +               .cpu_setup              = setup_cpu_power10,
> +               .cpu_restore            = __restore_cpu_power10,
> +               .platform               = "power10",
> +       },
>         {       /* Power7 */
>                 .pvr_mask               = 0xffff0000,
>                 .pvr_value              = 0x003f0000,
> diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
> index 806be751c336..1ecadbd7e8b2 100644
> --- a/arch/powerpc/kernel/prom_init.c
> +++ b/arch/powerpc/kernel/prom_init.c
> @@ -920,7 +920,7 @@ struct option_vector6 {
>  } __packed;
>
>  struct ibm_arch_vec {
> -       struct { u32 mask, val; } pvrs[12];
> +       struct { u32 mask, val; } pvrs[14];
>
>         u8 num_vectors;
>
> @@ -973,6 +973,14 @@ static const struct ibm_arch_vec ibm_architecture_vec_template __initconst = {
>                         .mask = cpu_to_be32(0xffff0000), /* POWER9 */
>                         .val  = cpu_to_be32(0x004e0000),
>                 },
> +               {
> +                       .mask = cpu_to_be32(0xffff0000), /* POWER10 */
> +                       .val  = cpu_to_be32(0x00800000),
Should there be a POWER10 (raw) entry added to cpu_specs[] for this?
> +               },
> +               {
> +                       .mask = cpu_to_be32(0xffffffff), /* all 3.1-compliant */
> +                       .val  = cpu_to_be32(0x0f000006),
> +               },
>                 {
>                         .mask = cpu_to_be32(0xffffffff), /* all 3.00-compliant */
>                         .val  = cpu_to_be32(0x0f000005),
> @@ -1002,7 +1010,7 @@ static const struct ibm_arch_vec ibm_architecture_vec_template __initconst = {
>                 .byte1 = 0,
>                 .arch_versions = OV1_PPC_2_00 | OV1_PPC_2_01 | OV1_PPC_2_02 | OV1_PPC_2_03 |
>                                  OV1_PPC_2_04 | OV1_PPC_2_05 | OV1_PPC_2_06 | OV1_PPC_2_07,
> -               .arch_versions3 = OV1_PPC_3_00,
> +               .arch_versions3 = OV1_PPC_3_00 | OV1_PPC_3_1,
>         },
>
>         .vec2_len = VECTOR_LENGTH(sizeof(struct option_vector2)),
> --
> 2.20.1
>