* [PATCH 1/3] dt-bindings: arm: qcom: Add sm6125 SoC and xiaomi,willow @ 2020-05-17 11:54 Eli Riggs 2020-05-17 11:54 ` [PATCH 2/3] arm64: dts: qcom: Add initial sm6125 SoC support Eli Riggs ` (2 more replies) 0 siblings, 3 replies; 9+ messages in thread From: Eli Riggs @ 2020-05-17 11:54 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Rob Herring, linux-arm-msm, devicetree, linux-kernel Cc: ~postmarketos/upstreaming, Eli Riggs Add compatibles for SM6125 aka SDM665 aka Snapdragon 665, as well as xiaomi,willow aka Xiaomi Redmi Note 8T, the international edition of the Note 8. Signed-off-by: Eli Riggs <eli@rje.li> --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 64ddae3bd39fd..4142e38a353ef 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -38,6 +38,7 @@ description: | msm8996 sc7180 sdm845 + sm6125 The 'board' element must be one of the following strings: @@ -158,4 +159,9 @@ properties: - qcom,ipq6018-cp01-c1 - const: qcom,ipq6018 + - items: + - enum: + - xiaomi,willow + - const: qcom,sm6125 + ... -- 2.20.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/3] arm64: dts: qcom: Add initial sm6125 SoC support 2020-05-17 11:54 [PATCH 1/3] dt-bindings: arm: qcom: Add sm6125 SoC and xiaomi,willow Eli Riggs @ 2020-05-17 11:54 ` Eli Riggs 2020-05-19 6:08 ` Bjorn Andersson 2020-05-17 11:54 ` [PATCH 3/3] arm64: dts: qcom: Add initial support for Xiaomi Redmi Note 8T Eli Riggs 2020-05-28 20:28 ` [PATCH 1/3] dt-bindings: arm: qcom: Add sm6125 SoC and xiaomi,willow Rob Herring 2 siblings, 1 reply; 9+ messages in thread From: Eli Riggs @ 2020-05-17 11:54 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Rob Herring, linux-arm-msm, devicetree, linux-kernel Cc: ~postmarketos/upstreaming, Eli Riggs Initial support for SM6125 SoC. CPUs, fixed clocks, interrupt controller, and UART. This DTSI is ported from the forked vendor version from XiaoMi which can be found at [0]. It seems internally this board is referred to as "Trinket". Since GCC isn't upstreamed yet, we use dummy clocks for GENI. [0]: https://github.com/MiCode/Xiaomi_Kernel_OpenSource/blob/willow-p-oss/arch/arm64/boot/dts/qcom/trinket.dtsi Signed-off-by: Eli Riggs <eli@rje.li> --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 201 +++++++++++++++++++++++++++ 1 file changed, 201 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm6125.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi new file mode 100644 index 0000000000000..4931402d20c9d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. +// Copyright (C) 2019 XiaoMi, Inc. +// Copyright (C) 2020 Eli Riggs <eli@rje.li> + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "xo_board"; + }; + sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "sleep_clk"; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + CPU0: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + d-cache-size = <0x10000>; + i-cache-size = <0x10000>; + }; + CPU1: cpu@101 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x101>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + d-cache-size = <0x10000>; + i-cache-size = <0x10000>; + }; + CPU2: cpu@102 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x102>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + d-cache-size = <0x10000>; + i-cache-size = <0x10000>; + }; + CPU3: cpu@103 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x103>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + d-cache-size = <0x10000>; + i-cache-size = <0x10000>; + }; + CPU4: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + }; + CPU5: cpu@1 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x1>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + }; + CPU6: cpu@2 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x2>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + }; + CPU7: cpu@3 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x3>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + }; + cpu-map { + cluster0 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + cluster1 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + }; + }; + + memory { + device_type = "memory"; + /* We expect the bootloader to fill this in */ + reg = <0 0 0 0>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; + clock-frequency = <19200000>; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + reg = <0xf200000 0x10000>, /* GICD */ + <0xf300000 0x100000>; /* GICR * 8 */ + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* This GENI and its children actually use GCC clocks, + * but the bootloader has already set them up for us. + * xo_board is used as a dummy here so the driver doesn't + * give up. + */ + qupv3_0: geniqup@4ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x4ac0000 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&xo_board>, <&xo_board>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + qupv3_se4_2uart: serial@4a90000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x4a90000 0x4000>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&xo_board>; + }; + }; + }; +}; -- 2.20.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] arm64: dts: qcom: Add initial sm6125 SoC support 2020-05-17 11:54 ` [PATCH 2/3] arm64: dts: qcom: Add initial sm6125 SoC support Eli Riggs @ 2020-05-19 6:08 ` Bjorn Andersson 2020-05-19 11:18 ` Eli Riggs 0 siblings, 1 reply; 9+ messages in thread From: Bjorn Andersson @ 2020-05-19 6:08 UTC (permalink / raw) To: Eli Riggs Cc: Andy Gross, Rob Herring, linux-arm-msm, devicetree, linux-kernel, ~postmarketos/upstreaming On Sun 17 May 04:54 PDT 2020, Eli Riggs wrote: > Initial support for SM6125 SoC. CPUs, fixed clocks, > interrupt controller, and UART. > > This DTSI is ported from the forked vendor version from > XiaoMi which can be found at [0]. It seems internally > this board is referred to as "Trinket". > > Since GCC isn't upstreamed yet, we use dummy clocks for GENI. > > [0]: https://github.com/MiCode/Xiaomi_Kernel_OpenSource/blob/willow-p-oss/arch/arm64/boot/dts/qcom/trinket.dtsi > > Signed-off-by: Eli Riggs <eli@rje.li> > --- > arch/arm64/boot/dts/qcom/sm6125.dtsi | 201 +++++++++++++++++++++++++++ > 1 file changed, 201 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/sm6125.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi > new file mode 100644 > index 0000000000000..4931402d20c9d > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi > @@ -0,0 +1,201 @@ > +// SPDX-License-Identifier: GPL-2.0-only Please use dual GPL/BSD license for dts files, if you can. > +// Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. > +// Copyright (C) 2019 XiaoMi, Inc. > +// Copyright (C) 2020 Eli Riggs <eli@rje.li> > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + interrupt-parent = <&intc>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + chosen { }; > + > + clocks { > + xo_board: xo-board { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <19200000>; > + clock-output-names = "xo_board"; > + }; > + sleep-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <32000>; > + clock-output-names = "sleep_clk"; > + }; > + }; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + CPU0: cpu@100 { > + device_type = "cpu"; > + compatible = "qcom,kryo260"; > + reg = <0x0 0x100>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1638>; > + d-cache-size = <0x10000>; > + i-cache-size = <0x10000>; > + }; > + CPU1: cpu@101 { > + device_type = "cpu"; > + compatible = "qcom,kryo260"; > + reg = <0x0 0x101>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1638>; > + d-cache-size = <0x10000>; > + i-cache-size = <0x10000>; > + }; > + CPU2: cpu@102 { > + device_type = "cpu"; > + compatible = "qcom,kryo260"; > + reg = <0x0 0x102>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1638>; > + d-cache-size = <0x10000>; > + i-cache-size = <0x10000>; > + }; > + CPU3: cpu@103 { > + device_type = "cpu"; > + compatible = "qcom,kryo260"; > + reg = <0x0 0x103>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1638>; > + d-cache-size = <0x10000>; > + i-cache-size = <0x10000>; > + }; > + CPU4: cpu@0 { > + device_type = "cpu"; > + compatible = "qcom,kryo260"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1024>; > + d-cache-size = <0x8000>; > + i-cache-size = <0x8000>; > + }; > + CPU5: cpu@1 { > + device_type = "cpu"; > + compatible = "qcom,kryo260"; > + reg = <0x0 0x1>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1024>; > + d-cache-size = <0x8000>; > + i-cache-size = <0x8000>; > + }; > + CPU6: cpu@2 { > + device_type = "cpu"; > + compatible = "qcom,kryo260"; > + reg = <0x0 0x2>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1024>; > + d-cache-size = <0x8000>; > + i-cache-size = <0x8000>; > + }; > + CPU7: cpu@3 { > + device_type = "cpu"; > + compatible = "qcom,kryo260"; > + reg = <0x0 0x3>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1024>; > + d-cache-size = <0x8000>; > + i-cache-size = <0x8000>; > + }; > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&CPU4>; > + }; > + core1 { > + cpu = <&CPU5>; > + }; > + core2 { > + cpu = <&CPU6>; > + }; > + core3 { > + cpu = <&CPU7>; > + }; > + }; > + cluster1 { > + core0 { > + cpu = <&CPU0>; > + }; > + core1 { > + cpu = <&CPU1>; > + }; > + core2 { > + cpu = <&CPU2>; > + }; > + core3 { > + cpu = <&CPU3>; > + }; > + }; > + }; > + }; > + > + memory { > + device_type = "memory"; > + /* We expect the bootloader to fill this in */ > + reg = <0 0 0 0>; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, > + <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, > + <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, > + <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; > + clock-frequency = <19200000>; > + }; > + > + soc: soc { > + #address-cells = <1>; > + #size-cells = <1>; In order to describe the dma-ranges properly the address-cells needs to be 2, so please make both of these 2 from the start. > + ranges = <0 0 0 0xffffffff>; > + compatible = "simple-bus"; > + > + intc: interrupt-controller@f200000 { > + compatible = "arm,gic-v3"; > + reg = <0xf200000 0x10000>, /* GICD */ > + <0xf300000 0x100000>; /* GICR * 8 */ Please pad addresses to 8 digits and please sort nodes under /soc by address. > + #interrupt-cells = <3>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + interrupt-controller; > + #redistributor-regions = <1>; > + redistributor-stride = <0x0 0x20000>; > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + /* This GENI and its children actually use GCC clocks, > + * but the bootloader has already set them up for us. > + * xo_board is used as a dummy here so the driver doesn't > + * give up. > + */ Given that you won't get very far without GCC and e.g. pinctrl driver I would prefer to see some patches for those as well, to ensure that this will be able to go beyond basic UART. Regards, Bjorn > + qupv3_0: geniqup@4ac0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0x4ac0000 0x2000>; > + clock-names = "m-ahb", "s-ahb"; > + clocks = <&xo_board>, <&xo_board>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + qupv3_se4_2uart: serial@4a90000 { > + compatible = "qcom,geni-debug-uart"; > + reg = <0x4a90000 0x4000>; > + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&xo_board>; > + }; > + }; > + }; > +}; > -- > 2.20.1 > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] arm64: dts: qcom: Add initial sm6125 SoC support 2020-05-19 6:08 ` Bjorn Andersson @ 2020-05-19 11:18 ` Eli Riggs 2020-05-20 6:14 ` Bjorn Andersson 0 siblings, 1 reply; 9+ messages in thread From: Eli Riggs @ 2020-05-19 11:18 UTC (permalink / raw) To: Bjorn Andersson Cc: Andy Gross, Rob Herring, linux-arm-msm, devicetree, linux-kernel, ~postmarketos/upstreaming On Mon, 18 May 2020 23:08:48 -0700 Bjorn Andersson <bjorn.andersson@linaro.org> wrote: > Please use dual GPL/BSD license for dts files, if you can. Unfortunately the downstream tree I ported has a GPL-2-only header. > [...review] OK > Given that you won't get very far without GCC and e.g. pinctrl > driver I would prefer to see some patches for those as well, to > ensure that this will be able to go beyond basic UART. Cleaning up my gcc and clk-smd-rpm drivers now, as well as another patchset for pm6125, qusb2-phy, dwc3, and sdhci. TLMM in the vague future. Eli ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] arm64: dts: qcom: Add initial sm6125 SoC support 2020-05-19 11:18 ` Eli Riggs @ 2020-05-20 6:14 ` Bjorn Andersson 0 siblings, 0 replies; 9+ messages in thread From: Bjorn Andersson @ 2020-05-20 6:14 UTC (permalink / raw) To: Eli Riggs Cc: Andy Gross, Rob Herring, linux-arm-msm, devicetree, linux-kernel, ~postmarketos/upstreaming On Tue 19 May 04:18 PDT 2020, Eli Riggs wrote: > On Mon, 18 May 2020 23:08:48 -0700 > Bjorn Andersson <bjorn.andersson@linaro.org> wrote: > > > Please use dual GPL/BSD license for dts files, if you can. > > Unfortunately the downstream tree I ported has a GPL-2-only header. > > > [...review] > > OK > > > Given that you won't get very far without GCC and e.g. pinctrl > > driver I would prefer to see some patches for those as well, to > > ensure that this will be able to go beyond basic UART. > > Cleaning up my gcc and clk-smd-rpm drivers now, as well as another > patchset for pm6125, qusb2-phy, dwc3, and sdhci. TLMM in the vague > future. > Looking forward to review these! Regards, Bjorn ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 3/3] arm64: dts: qcom: Add initial support for Xiaomi Redmi Note 8T 2020-05-17 11:54 [PATCH 1/3] dt-bindings: arm: qcom: Add sm6125 SoC and xiaomi,willow Eli Riggs 2020-05-17 11:54 ` [PATCH 2/3] arm64: dts: qcom: Add initial sm6125 SoC support Eli Riggs @ 2020-05-17 11:54 ` Eli Riggs 2020-05-19 6:11 ` Bjorn Andersson 2020-05-28 20:28 ` [PATCH 1/3] dt-bindings: arm: qcom: Add sm6125 SoC and xiaomi,willow Rob Herring 2 siblings, 1 reply; 9+ messages in thread From: Eli Riggs @ 2020-05-17 11:54 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Rob Herring, linux-arm-msm, devicetree, linux-kernel Cc: ~postmarketos/upstreaming, Eli Riggs Adds initial device tree for Xiaomi Redmi Note 8T, codename xiaomi-willow. It uses the sm6125 SoC. Currently only boots into initrd shell over UART. Requires appended DTB with qcom,board-id = <0x22 0x0> and qcom,msm-id = <0x18a 0x10000> to actually boot. Signed-off-by: Eli Riggs <eli@rje.li> --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sm6125-xiaomi-willow.dts | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm6125-xiaomi-willow.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index cc103f7020fd6..060aa98200e47 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -22,6 +22,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm6125-xiaomi-willow.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-willow.dts b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-willow.dts new file mode 100644 index 0000000000000..444b32ccb9d48 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-willow.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (c) 2020, Eli Riggs <eli@rje.li> + +/dts-v1/; + +#include "sm6125.dtsi" + +/ { + model = "Xiaomi Redmi Note 8T"; + compatible = "xiaomi,willow", "qcom,sm6125"; + + aliases { + serial0 = &qupv3_se4_2uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; -- 2.20.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] arm64: dts: qcom: Add initial support for Xiaomi Redmi Note 8T 2020-05-17 11:54 ` [PATCH 3/3] arm64: dts: qcom: Add initial support for Xiaomi Redmi Note 8T Eli Riggs @ 2020-05-19 6:11 ` Bjorn Andersson 2020-05-19 11:20 ` Eli Riggs 0 siblings, 1 reply; 9+ messages in thread From: Bjorn Andersson @ 2020-05-19 6:11 UTC (permalink / raw) To: Eli Riggs Cc: Andy Gross, Rob Herring, linux-arm-msm, devicetree, linux-kernel, ~postmarketos/upstreaming On Sun 17 May 04:54 PDT 2020, Eli Riggs wrote: > Adds initial device tree for Xiaomi Redmi Note 8T, codename xiaomi-willow. > It uses the sm6125 SoC. Currently only boots into initrd shell over UART. > Requires appended DTB with qcom,board-id = <0x22 0x0> and > qcom,msm-id = <0x18a 0x10000> to actually boot. > If I read this correctly you need to supply board-id and msm-id in order to be able to get this booting? Even though we don't like them, I would prefer if you just add them in the dts file, in this patch. > Signed-off-by: Eli Riggs <eli@rje.li> > --- > arch/arm64/boot/dts/qcom/Makefile | 1 + > .../boot/dts/qcom/sm6125-xiaomi-willow.dts | 19 +++++++++++++++++++ > 2 files changed, 20 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/sm6125-xiaomi-willow.dts > > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile > index cc103f7020fd6..060aa98200e47 100644 > --- a/arch/arm64/boot/dts/qcom/Makefile > +++ b/arch/arm64/boot/dts/qcom/Makefile > @@ -22,6 +22,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb > dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb > dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb > dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb > +dtb-$(CONFIG_ARCH_QCOM) += sm6125-xiaomi-willow.dtb > dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb > dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb > dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb > diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-willow.dts b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-willow.dts > new file mode 100644 > index 0000000000000..444b32ccb9d48 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-willow.dts > @@ -0,0 +1,19 @@ > +// SPDX-License-Identifier: GPL-2.0-only Please make this GPL/BSD dual license. Apart from these few remarks your patches looks good, looking forward to see more of this platform! Regards, Bjorn > +// Copyright (c) 2020, Eli Riggs <eli@rje.li> > + > +/dts-v1/; > + > +#include "sm6125.dtsi" > + > +/ { > + model = "Xiaomi Redmi Note 8T"; > + compatible = "xiaomi,willow", "qcom,sm6125"; > + > + aliases { > + serial0 = &qupv3_se4_2uart; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > -- > 2.20.1 > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] arm64: dts: qcom: Add initial support for Xiaomi Redmi Note 8T 2020-05-19 6:11 ` Bjorn Andersson @ 2020-05-19 11:20 ` Eli Riggs 0 siblings, 0 replies; 9+ messages in thread From: Eli Riggs @ 2020-05-19 11:20 UTC (permalink / raw) To: Bjorn Andersson Cc: Andy Gross, Rob Herring, linux-arm-msm, devicetree, linux-kernel, ~postmarketos/upstreaming On Mon, 18 May 2020 23:11:14 -0700 Bjorn Andersson <bjorn.andersson@linaro.org> wrote: > On Sun 17 May 04:54 PDT 2020, Eli Riggs wrote: > > > Adds initial device tree for Xiaomi Redmi Note 8T, codename > > xiaomi-willow. It uses the sm6125 SoC. Currently only boots into > > initrd shell over UART. Requires appended DTB with qcom,board-id = > > <0x22 0x0> and qcom,msm-id = <0x18a 0x10000> to actually boot. > > > > If I read this correctly you need to supply board-id and msm-id in > order to be able to get this booting? > > Even though we don't like them, I would prefer if you just add them in > the dts file, in this patch. Yes, AFAICT the bootloader iterates over the appended DTBs and will only boot if it finds one with those matching properties. > > dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb > > dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb diff --git > > a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-willow.dts > > b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-willow.dts new file mode > > 100644 index 0000000000000..444b32ccb9d48 --- /dev/null > > +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-willow.dts > > @@ -0,0 +1,19 @@ > > +// SPDX-License-Identifier: GPL-2.0-only > > Please make this GPL/BSD dual license. > > Apart from these few remarks your patches looks good, looking forward > to see more of this platform! > > Regards, > Bjorn OK, thanks! ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] dt-bindings: arm: qcom: Add sm6125 SoC and xiaomi,willow 2020-05-17 11:54 [PATCH 1/3] dt-bindings: arm: qcom: Add sm6125 SoC and xiaomi,willow Eli Riggs 2020-05-17 11:54 ` [PATCH 2/3] arm64: dts: qcom: Add initial sm6125 SoC support Eli Riggs 2020-05-17 11:54 ` [PATCH 3/3] arm64: dts: qcom: Add initial support for Xiaomi Redmi Note 8T Eli Riggs @ 2020-05-28 20:28 ` Rob Herring 2 siblings, 0 replies; 9+ messages in thread From: Rob Herring @ 2020-05-28 20:28 UTC (permalink / raw) To: Eli Riggs Cc: Rob Herring, devicetree, Andy Gross, linux-arm-msm, Bjorn Andersson, ~postmarketos/upstreaming, linux-kernel On Sun, 17 May 2020 04:54:06 -0700, Eli Riggs wrote: > Add compatibles for SM6125 aka SDM665 aka Snapdragon 665, as well > as xiaomi,willow aka Xiaomi Redmi Note 8T, the international > edition of the Note 8. > > Signed-off-by: Eli Riggs <eli@rje.li> > --- > Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-05-28 20:28 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-05-17 11:54 [PATCH 1/3] dt-bindings: arm: qcom: Add sm6125 SoC and xiaomi,willow Eli Riggs 2020-05-17 11:54 ` [PATCH 2/3] arm64: dts: qcom: Add initial sm6125 SoC support Eli Riggs 2020-05-19 6:08 ` Bjorn Andersson 2020-05-19 11:18 ` Eli Riggs 2020-05-20 6:14 ` Bjorn Andersson 2020-05-17 11:54 ` [PATCH 3/3] arm64: dts: qcom: Add initial support for Xiaomi Redmi Note 8T Eli Riggs 2020-05-19 6:11 ` Bjorn Andersson 2020-05-19 11:20 ` Eli Riggs 2020-05-28 20:28 ` [PATCH 1/3] dt-bindings: arm: qcom: Add sm6125 SoC and xiaomi,willow Rob Herring
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