[PATCH v3 14/17] mtd: spi-nor-core: Perform a Soft Reset on shutdown

[Pratyush Yadav <p.yadav@ti.com>]

Hi Jagan,

On 13/05/20 12:14PM, Jagan Teki wrote:
> On Mon, Mar 30, 2020 at 9:16 PM Pratyush Yadav <p.yadav@ti.com> wrote:
> >
> > On probe, the SPI NOR core will put a flash in 8D-8D-8D mode if it
> > supports it. But Linux as of now expects to get the flash in 1S-1S-1S
> > mode. Handing the flash to Linux in Octal DTR mode means the kernel will
> > fail to detect the flash.
> >
> > So, we need to reset to Power-on-Reset (POR) state before handing off
> > the flash. A Software Reset command can be used to do this. Since the
> > command is optional, flashes have to specify they support it by using
> > the flag 'SPI_NOR_SOFT_RESET'.
> >
> > One limitation of the soft reset is that it will restore state from
> > non-volatile registers in some flashes. This means that if the flash was
> > set to 8D mode in a non-volatile configuration, a soft reset won't help.
> > This commit assumes that we don't set any non-volatile bits anywhere,
> > and the flash doesn't have any non-volatile Octal DTR mode
> > configuration.
> 
> Is this common for all 8D supported flash devices?

The standard allows a flash to restore state from non-volatile 
registers, but doesn't mandates it.

I looked at a few flashes (like the Cypress S28 and Micron MT35XU 
flashes which this series adds support for), and all of them restored 
state from non-volatile registers. I'm not aware of any flash that 
restores state to factory defaults ignoring its non-volatile 
configuration, but I haven't looked at all the datasheets out there to 
make a definitive claim.
 
> >
> > Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
> > ---
> >  drivers/mtd/spi/sf_internal.h  |  1 +
> >  drivers/mtd/spi/sf_probe.c     |  9 +++++
> >  drivers/mtd/spi/spi-nor-core.c | 66 ++++++++++++++++++++++++++++++++++
> >  include/linux/mtd/spi-nor.h    | 11 ++++++
> >  4 files changed, 87 insertions(+)
> >
> > diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
> > index 5780c81287..37e6657490 100644
> > --- a/drivers/mtd/spi/sf_internal.h
> > +++ b/drivers/mtd/spi/sf_internal.h
> > @@ -178,6 +186,7 @@ U_BOOT_DRIVER(spi_flash_std) = {
> >         .remove         = spi_flash_std_remove,
> >         .priv_auto_alloc_size = sizeof(struct spi_flash),
> >         .ops            = &spi_flash_std_ops,
> > +       .flags          = DM_FLAG_OS_PREPARE,
> >  };
> >
> >  #endif /* CONFIG_DM_SPI_FLASH */
> > diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> > index 5b995cda3f..52b3775035 100644
> > --- a/drivers/mtd/spi/spi-nor-core.c
> > +++ b/drivers/mtd/spi/spi-nor-core.c
> > @@ -186,6 +186,8 @@ struct spi_nor_fixups {
> >                           struct spi_nor_flash_parameter *params);
> >  };
> >
> > +#define SPI_NOR_SRST_SLEEP_LEN                 200
> > +
> >  /**
> >   * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
> >   *                        extension type.
> > @@ -2835,6 +2837,67 @@ static int spi_nor_init(struct spi_nor *nor)
> >         return 0;
> >  }
> >
> > +/**
> > + * spi_nor_soft_reset() - perform the JEDEC Software Reset sequence
> > + * @nor:       the spi_nor structure
> > + *
> > + * This function can be used to switch from Octal DTR mode to legacy mode on a
> > + * flash that supports it. The soft reset is executed in Octal DTR mode.
> > + *
> > + * Return: 0 for success, -errno for failure.
> > + */
> > +static int spi_nor_soft_reset(struct spi_nor *nor)
> > +{
> > +       struct spi_mem_op op;
> > +       int ret;
> > +       enum spi_nor_cmd_ext ext;
> > +
> > +       ext = nor->cmd_ext_type;
> > +       nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
> > +
> > +       op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 8),
> > +                       SPI_MEM_OP_NO_DUMMY,
> > +                       SPI_MEM_OP_NO_ADDR,
> > +                       SPI_MEM_OP_NO_DATA);
> > +       spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
> > +       ret = spi_mem_exec_op(nor->spi, &op);
> > +       if (ret) {
> > +               dev_warn(nor->dev, "Software reset enable failed: %d\n", ret);
> > +               goto out;
> > +       }
> > +
> > +       op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 8),
> > +                       SPI_MEM_OP_NO_DUMMY,
> > +                       SPI_MEM_OP_NO_ADDR,
> > +                       SPI_MEM_OP_NO_DATA);
> > +       spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
> > +       ret = spi_mem_exec_op(nor->spi, &op);
> > +       if (ret) {
> > +               dev_warn(nor->dev, "Software reset failed: %d\n", ret);
> > +               goto out;
> > +       }
> > +
> > +       /*
> > +        * Software Reset is not instant, and the delay varies from flash to
> > +        * flash. Looking at a few flashes, most range somewhere below 100
> > +        * microseconds. So, wait for 200ms just to be sure.
> > +        */
> > +       udelay(SPI_NOR_SRST_SLEEP_LEN);
> 
> Any reference for this delay? I mean datasheet?

Unfortunately, the timings for the two flashes this series adds support 
for are not public. But as examples, you can look at n25q (90 ns), mt25q 
(40 ns), (20 ns) w25q (30 us).

-- 
Regards,
Pratyush Yadav
Texas Instruments India