* [PATCH v4 1/5] target/i386: add missing vmx features for several CPU models
2020-05-20 2:10 [PATCH v4 0/5] modify CPU model info Chenyi Qiang
@ 2020-05-20 2:10 ` Chenyi Qiang
2020-05-20 2:10 ` [PATCH v4 2/5] target/i386: add fast short REP MOV support Chenyi Qiang
` (4 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Chenyi Qiang @ 2020-05-20 2:10 UTC (permalink / raw)
To: Paolo Bonzini, Richard Henderson, Eduardo Habkost
Cc: Xiaoyao Li, qemu-devel, Robert Hoo
Add some missing VMX features in Skylake-Server, Cascadelake-Server and
Icelake-Server CPU models based on the output of Paolo's script.
Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
---
target/i386/cpu.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 7a4a8e3847..2b653a0161 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2982,6 +2982,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Skylake)",
.versions = (X86CPUVersionDefinition[]) {
@@ -3110,6 +3111,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Cascadelake)",
.versions = (X86CPUVersionDefinition[]) {
@@ -3457,7 +3459,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
- VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
+ VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
+ VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Icelake)",
.versions = (X86CPUVersionDefinition[]) {
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v4 2/5] target/i386: add fast short REP MOV support
2020-05-20 2:10 [PATCH v4 0/5] modify CPU model info Chenyi Qiang
2020-05-20 2:10 ` [PATCH v4 1/5] target/i386: add missing vmx features for several CPU models Chenyi Qiang
@ 2020-05-20 2:10 ` Chenyi Qiang
2020-05-20 2:10 ` [PATCH v4 3/5] target/i386: add the missing features for Icelake-Server CPU model Chenyi Qiang
` (3 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Chenyi Qiang @ 2020-05-20 2:10 UTC (permalink / raw)
To: Paolo Bonzini, Richard Henderson, Eduardo Habkost
Cc: Xiaoyao Li, qemu-devel, Robert Hoo
For CPUs support fast short REP MOV[CPUID.(EAX=7,ECX=0):EDX(bit4)], e.g
Icelake and Tigerlake, expose it to the guest VM.
Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 2b653a0161..52f5aa5418 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -984,7 +984,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
- NULL, NULL, NULL, NULL,
+ "fsrm", NULL, NULL, NULL,
NULL, NULL, "md-clear", NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL /* pconfig */, NULL,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 408392dbf6..142256017b 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -772,6 +772,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
/* AVX512 Multiply Accumulation Single Precision */
#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
+/* Fast Short Rep Mov */
+#define CPUID_7_0_EDX_FSRM (1U << 4)
/* Speculation Control */
#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
/* Single Thread Indirect Branch Predictors */
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v4 3/5] target/i386: add the missing features for Icelake-Server CPU model
2020-05-20 2:10 [PATCH v4 0/5] modify CPU model info Chenyi Qiang
2020-05-20 2:10 ` [PATCH v4 1/5] target/i386: add missing vmx features for several CPU models Chenyi Qiang
2020-05-20 2:10 ` [PATCH v4 2/5] target/i386: add fast short REP MOV support Chenyi Qiang
@ 2020-05-20 2:10 ` Chenyi Qiang
2020-05-20 2:10 ` [PATCH v4 4/5] target/i386: modify Icelake-Server CPU model number Chenyi Qiang
` (2 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Chenyi Qiang @ 2020-05-20 2:10 UTC (permalink / raw)
To: Paolo Bonzini, Richard Henderson, Eduardo Habkost
Cc: Xiaoyao Li, qemu-devel, Robert Hoo
Add the missing features(sha-ni, avx512ifma, rdpid, fsrm) in the
Icelake-Server CPU model.
Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
---
target/i386/cpu.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 52f5aa5418..b4697b0148 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3488,6 +3488,16 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
},
},
+ {
+ .version = 4,
+ .props = (PropValue[]) {
+ { "sha-ni", "on" },
+ { "avx512ifma", "on" },
+ { "rdpid", "on" },
+ { "fsrm", "on" },
+ { /* end of list */ }
+ },
+ },
{ /* end of list */ }
}
},
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v4 4/5] target/i386: modify Icelake-Server CPU model number
2020-05-20 2:10 [PATCH v4 0/5] modify CPU model info Chenyi Qiang
` (2 preceding siblings ...)
2020-05-20 2:10 ` [PATCH v4 3/5] target/i386: add the missing features for Icelake-Server CPU model Chenyi Qiang
@ 2020-05-20 2:10 ` Chenyi Qiang
2020-05-20 2:10 ` [PATCH v4 5/5] target/i386: remove Icelake-Client CPU model Chenyi Qiang
2020-06-11 3:22 ` [PATCH v4 0/5] modify CPU model info Chenyi Qiang
5 siblings, 0 replies; 10+ messages in thread
From: Chenyi Qiang @ 2020-05-20 2:10 UTC (permalink / raw)
To: Paolo Bonzini, Richard Henderson, Eduardo Habkost
Cc: Xiaoyao Li, qemu-devel, Robert Hoo
According to the Intel Icelake family list, Icelake-Server uses model
number 106(0x6A).
Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b4697b0148..d59698710e 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3364,7 +3364,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
- .model = 134,
+ .model = 106,
.stepping = 0,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v4 5/5] target/i386: remove Icelake-Client CPU model
2020-05-20 2:10 [PATCH v4 0/5] modify CPU model info Chenyi Qiang
` (3 preceding siblings ...)
2020-05-20 2:10 ` [PATCH v4 4/5] target/i386: modify Icelake-Server CPU model number Chenyi Qiang
@ 2020-05-20 2:10 ` Chenyi Qiang
2020-05-20 9:17 ` Daniel P. Berrangé
2020-06-11 3:22 ` [PATCH v4 0/5] modify CPU model info Chenyi Qiang
5 siblings, 1 reply; 10+ messages in thread
From: Chenyi Qiang @ 2020-05-20 2:10 UTC (permalink / raw)
To: Paolo Bonzini, Richard Henderson, Eduardo Habkost
Cc: Xiaoyao Li, qemu-devel, Robert Hoo
There are no Icelake Desktop products in the market. Remove the
Icelake-Client CPU model.
Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
---
hw/i386/pc.c | 1 -
target/i386/cpu.c | 113 ----------------------------------------------
2 files changed, 114 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 2128f3d6fe..ecc5ab022b 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -127,7 +127,6 @@ GlobalProperty pc_compat_3_1[] = {
{ "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
{ "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
{ "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
- { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
{ "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
{ "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
{ TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index d59698710e..33c0fdc23f 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3246,119 +3246,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Cooperlake)",
},
- {
- .name = "Icelake-Client",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 126,
- .stepping = 0,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
- .features[FEAT_8000_0008_EBX] =
- CPUID_8000_0008_EBX_WBNOINVD,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
- CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
- CPUID_7_0_EBX_SMAP,
- .features[FEAT_7_0_ECX] =
- CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
- CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
- CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
- CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
- CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
- /* Missing: XSAVES (not supported by some Linux versions,
- * including v4.1 to v4.12).
- * KVM doesn't yet expose any XSAVES state save component,
- * and the only one defined in Skylake (processor tracing)
- * probably will block migration anyway.
- */
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
- CPUID_XSAVE_XGETBV1,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
- .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
- MSR_VMX_BASIC_TRUE_CTLS,
- .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
- VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
- VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
- .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
- MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
- MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
- MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
- MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
- MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
- MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
- .features[FEAT_VMX_EXIT_CTLS] =
- VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
- VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
- VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
- VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
- VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
- .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
- MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
- .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
- VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
- VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
- .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
- VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
- VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
- VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
- VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
- VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
- VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
- VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
- VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
- VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
- VMX_CPU_BASED_MONITOR_TRAP_FLAG |
- VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
- .features[FEAT_VMX_SECONDARY_CTLS] =
- VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
- VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
- VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
- VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
- VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
- VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
- VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
- .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
- .xlevel = 0x80000008,
- .model_id = "Intel Core Processor (Icelake)",
- .versions = (X86CPUVersionDefinition[]) {
- { .version = 1 },
- {
- .version = 2,
- .alias = "Icelake-Client-noTSX",
- .props = (PropValue[]) {
- { "hle", "off" },
- { "rtm", "off" },
- { /* end of list */ }
- },
- },
- { /* end of list */ }
- }
- },
{
.name = "Icelake-Server",
.level = 0xd,
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v4 5/5] target/i386: remove Icelake-Client CPU model
2020-05-20 2:10 ` [PATCH v4 5/5] target/i386: remove Icelake-Client CPU model Chenyi Qiang
@ 2020-05-20 9:17 ` Daniel P. Berrangé
2020-05-21 1:40 ` Robert Hoo
0 siblings, 1 reply; 10+ messages in thread
From: Daniel P. Berrangé @ 2020-05-20 9:17 UTC (permalink / raw)
To: Chenyi Qiang
Cc: Eduardo Habkost, Xiaoyao Li, qemu-devel, Robert Hoo,
Paolo Bonzini, Richard Henderson
On Wed, May 20, 2020 at 10:10:07AM +0800, Chenyi Qiang wrote:
> There are no Icelake Desktop products in the market. Remove the
> Icelake-Client CPU model.
QEMU has been shipping this CPU model for 2 years now. Regardless
of what CPUs Intel are selling, it is possible for users to be
running VMs with Icelake-Client CPU if their host satisfies the
listed features. So I don't think it is valid to remove this.
Regards,
Daniel
--
|: https://berrange.com -o- https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o- https://fstop138.berrange.com :|
|: https://entangle-photo.org -o- https://www.instagram.com/dberrange :|
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 5/5] target/i386: remove Icelake-Client CPU model
2020-05-20 9:17 ` Daniel P. Berrangé
@ 2020-05-21 1:40 ` Robert Hoo
2020-05-21 9:44 ` Daniel P. Berrangé
0 siblings, 1 reply; 10+ messages in thread
From: Robert Hoo @ 2020-05-21 1:40 UTC (permalink / raw)
To: Daniel P. Berrangé, Chenyi Qiang
Cc: qemu-devel, Paolo Bonzini, Xiaoyao Li, Eduardo Habkost,
Richard Henderson
On Wed, 2020-05-20 at 10:17 +0100, Daniel P. Berrangé wrote:
> On Wed, May 20, 2020 at 10:10:07AM +0800, Chenyi Qiang wrote:
> > There are no Icelake Desktop products in the market. Remove the
> > Icelake-Client CPU model.
>
> QEMU has been shipping this CPU model for 2 years now. Regardless
> of what CPUs Intel are selling, it is possible for users to be
> running VMs with Icelake-Client CPU if their host satisfies the
> listed features. So I don't think it is valid to remove this.
>
This 'Icelake-Client' actually doesn't exist. How do we define its
feature list? and who will be using it? If any special feature tailor
requirement, it can be simply achieved by '-cpu Icelake,+/-' features,
this is the correct way.
I think we should remove it. When we realize something's not correct,
we should fix it ASAP. Leaving it there will only cause more serious
issue in the future.
> Regards,
> Daniel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 5/5] target/i386: remove Icelake-Client CPU model
2020-05-21 1:40 ` Robert Hoo
@ 2020-05-21 9:44 ` Daniel P. Berrangé
0 siblings, 0 replies; 10+ messages in thread
From: Daniel P. Berrangé @ 2020-05-21 9:44 UTC (permalink / raw)
To: Robert Hoo
Cc: Eduardo Habkost, Xiaoyao Li, qemu-devel, Chenyi Qiang,
Paolo Bonzini, Richard Henderson
On Thu, May 21, 2020 at 09:40:55AM +0800, Robert Hoo wrote:
> On Wed, 2020-05-20 at 10:17 +0100, Daniel P. Berrangé wrote:
> > On Wed, May 20, 2020 at 10:10:07AM +0800, Chenyi Qiang wrote:
> > > There are no Icelake Desktop products in the market. Remove the
> > > Icelake-Client CPU model.
> >
> > QEMU has been shipping this CPU model for 2 years now. Regardless
> > of what CPUs Intel are selling, it is possible for users to be
> > running VMs with Icelake-Client CPU if their host satisfies the
> > listed features. So I don't think it is valid to remove this.
> >
> This 'Icelake-Client' actually doesn't exist. How do we define its
> feature list? and who will be using it? If any special feature tailor
> requirement, it can be simply achieved by '-cpu Icelake,+/-' features,
> this is the correct way.
Well its feature list is defined by what exists in QEMU code right
now. Presumably was based off some silicon that did exist in Intel
at some point, or it would not have been added to QEMU in the first
place ?
Changing guests to use "-cpu Icelake-Server,+/-" would be a guest
ABI change because of the different model number IIUC
> I think we should remove it. When we realize something's not correct,
> we should fix it ASAP. Leaving it there will only cause more serious
> issue in the future.
We have versioned CPU models so that we can fix mistakes in previously
defined CPU model features, without causing breakage for anything that
is using the previous incorrectly defined model. We can't version the
deletion of a CPU model though. I'm not seeing the serious harm that's
caused by the Icelake-Client CPU model existing though, and deleting
it will definitely cause harm to the config of anything that currently
happens to use it.
Maybe Icelake-Client could be turned into a deprecated alias for a
version of Icelake-Server that has the cutdown feature list ?
Regards,
Daniel
--
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 0/5] modify CPU model info
2020-05-20 2:10 [PATCH v4 0/5] modify CPU model info Chenyi Qiang
` (4 preceding siblings ...)
2020-05-20 2:10 ` [PATCH v4 5/5] target/i386: remove Icelake-Client CPU model Chenyi Qiang
@ 2020-06-11 3:22 ` Chenyi Qiang
5 siblings, 0 replies; 10+ messages in thread
From: Chenyi Qiang @ 2020-06-11 3:22 UTC (permalink / raw)
To: Paolo Bonzini, Richard Henderson, Eduardo Habkost
Cc: Xiaoyao Li, qemu-devel, Robert Hoo
Ping for comments.
Ignore the last patch("remove Icelake-Client CPU model").
Robert is working on the CPU model deprecation API in
https://lists.gnu.org/archive/html/qemu-devel/2020-06/msg03109.html
On 5/20/2020 10:10 AM, Chenyi Qiang wrote:
> Add the missing VMX features in Skylake-Server, Cascadelake-Server and
> Icelake-Server CPU models. In Icelake-Server CPU model, it lacks sha_ni,
> avx512ifma, rdpid and fsrm. The model number of Icelake-Server also needs
> to be fixed.
> Remove the Icelake-Client CPU model due to no Icelake Desktop products
> in the market.
>
> Changes in v4:
> - remove the Icelake-Client CPU model
>
> Changes in v3:
> - change the missing features of Icelake-Server from v3 to v4
>
> Changes in v2:
> - add missing features as a new version of CPU model
> - add the support of FSRM
> - add New CPUID of FSRM and RDPID in Icelake-Server CPU model
>
> Chenyi Qiang (5):
> target/i386: add missing vmx features for several CPU models
> target/i386: add fast short REP MOV support
> target/i386: add the missing features for Icelake-Server CPU model
> target/i386: modify Icelake-Server CPU model number
> target/i386: remove Icelake-Client CPU model
>
> hw/i386/pc.c | 1 -
> target/i386/cpu.c | 133 ++++++----------------------------------------
> target/i386/cpu.h | 2 +
> 3 files changed, 19 insertions(+), 117 deletions(-)
>
^ permalink raw reply [flat|nested] 10+ messages in thread