From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 13/29] hw/watchdog: Implement full i.MX watchdog support
Date: Thu, 21 May 2020 20:15:54 +0100 [thread overview]
Message-ID: <20200521191610.10941-14-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200521191610.10941-1-peter.maydell@linaro.org>
From: Guenter Roeck <linux@roeck-us.net>
Implement full support for the watchdog in i.MX systems.
Pretimeout support is optional because the watchdog hardware
on i.MX31 does not support pretimeouts.
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20200517162135.110364-3-linux@roeck-us.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/watchdog/wdt_imx2.h | 61 ++++++++-
hw/watchdog/wdt_imx2.c | 239 +++++++++++++++++++++++++++++++--
2 files changed, 285 insertions(+), 15 deletions(-)
diff --git a/include/hw/watchdog/wdt_imx2.h b/include/hw/watchdog/wdt_imx2.h
index b91b002528f..f9af6be4b69 100644
--- a/include/hw/watchdog/wdt_imx2.h
+++ b/include/hw/watchdog/wdt_imx2.h
@@ -12,22 +12,79 @@
#ifndef IMX2_WDT_H
#define IMX2_WDT_H
+#include "qemu/bitops.h"
#include "hw/sysbus.h"
+#include "hw/irq.h"
+#include "hw/ptimer.h"
#define TYPE_IMX2_WDT "imx2.wdt"
#define IMX2_WDT(obj) OBJECT_CHECK(IMX2WdtState, (obj), TYPE_IMX2_WDT)
enum IMX2WdtRegisters {
- IMX2_WDT_WCR = 0x0000,
- IMX2_WDT_REG_NUM = 0x0008 / sizeof(uint16_t) + 1,
+ IMX2_WDT_WCR = 0x0000, /* Control Register */
+ IMX2_WDT_WSR = 0x0002, /* Service Register */
+ IMX2_WDT_WRSR = 0x0004, /* Reset Status Register */
+ IMX2_WDT_WICR = 0x0006, /* Interrupt Control Register */
+ IMX2_WDT_WMCR = 0x0008, /* Misc Register */
};
+#define IMX2_WDT_MMIO_SIZE 0x000a
+
+/* Control Register definitions */
+#define IMX2_WDT_WCR_WT (0xFF << 8) /* Watchdog Timeout Field */
+#define IMX2_WDT_WCR_WDW BIT(7) /* WDOG Disable for Wait */
+#define IMX2_WDT_WCR_WDA BIT(5) /* WDOG Assertion */
+#define IMX2_WDT_WCR_SRS BIT(4) /* Software Reset Signal */
+#define IMX2_WDT_WCR_WDT BIT(3) /* WDOG Timeout Assertion */
+#define IMX2_WDT_WCR_WDE BIT(2) /* Watchdog Enable */
+#define IMX2_WDT_WCR_WDBG BIT(1) /* Watchdog Debug Enable */
+#define IMX2_WDT_WCR_WDZST BIT(0) /* Watchdog Timer Suspend */
+
+#define IMX2_WDT_WCR_LOCK_MASK (IMX2_WDT_WCR_WDZST | IMX2_WDT_WCR_WDBG \
+ | IMX2_WDT_WCR_WDW)
+
+/* Service Register definitions */
+#define IMX2_WDT_SEQ1 0x5555 /* service sequence 1 */
+#define IMX2_WDT_SEQ2 0xAAAA /* service sequence 2 */
+
+/* Reset Status Register definitions */
+#define IMX2_WDT_WRSR_TOUT BIT(1) /* Reset due to Timeout */
+#define IMX2_WDT_WRSR_SFTW BIT(0) /* Reset due to software reset */
+
+/* Interrupt Control Register definitions */
+#define IMX2_WDT_WICR_WIE BIT(15) /* Interrupt Enable */
+#define IMX2_WDT_WICR_WTIS BIT(14) /* Interrupt Status */
+#define IMX2_WDT_WICR_WICT 0xff /* Interrupt Timeout */
+#define IMX2_WDT_WICR_WICT_DEF 0x04 /* Default interrupt timeout (2s) */
+
+#define IMX2_WDT_WICR_LOCK_MASK (IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT)
+
+/* Misc Control Register definitions */
+#define IMX2_WDT_WMCR_PDE BIT(0) /* Power-Down Enable */
typedef struct IMX2WdtState {
/* <private> */
SysBusDevice parent_obj;
+ /*< public >*/
MemoryRegion mmio;
+ qemu_irq irq;
+
+ struct ptimer_state *timer;
+ struct ptimer_state *itimer;
+
+ bool pretimeout_support;
+ bool wicr_locked;
+
+ uint16_t wcr;
+ uint16_t wsr;
+ uint16_t wrsr;
+ uint16_t wicr;
+ uint16_t wmcr;
+
+ bool wcr_locked; /* affects WDZST, WDBG, and WDW */
+ bool wcr_wde_locked; /* affects WDE */
+ bool wcr_wdt_locked; /* affects WDT (never cleared) */
} IMX2WdtState;
#endif /* IMX2_WDT_H */
diff --git a/hw/watchdog/wdt_imx2.c b/hw/watchdog/wdt_imx2.c
index ad1ef02e9e7..855b51768a8 100644
--- a/hw/watchdog/wdt_imx2.c
+++ b/hw/watchdog/wdt_imx2.c
@@ -13,24 +13,189 @@
#include "qemu/bitops.h"
#include "qemu/module.h"
#include "sysemu/watchdog.h"
+#include "migration/vmstate.h"
+#include "hw/qdev-properties.h"
#include "hw/watchdog/wdt_imx2.h"
-#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
-#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
-
-static uint64_t imx2_wdt_read(void *opaque, hwaddr addr,
- unsigned int size)
+static void imx2_wdt_interrupt(void *opaque)
{
+ IMX2WdtState *s = IMX2_WDT(opaque);
+
+ s->wicr |= IMX2_WDT_WICR_WTIS;
+ qemu_set_irq(s->irq, 1);
+}
+
+static void imx2_wdt_expired(void *opaque)
+{
+ IMX2WdtState *s = IMX2_WDT(opaque);
+
+ s->wrsr = IMX2_WDT_WRSR_TOUT;
+
+ /* Perform watchdog action if watchdog is enabled */
+ if (s->wcr & IMX2_WDT_WCR_WDE) {
+ s->wrsr = IMX2_WDT_WRSR_TOUT;
+ watchdog_perform_action();
+ }
+}
+
+static void imx2_wdt_reset(DeviceState *dev)
+{
+ IMX2WdtState *s = IMX2_WDT(dev);
+
+ ptimer_transaction_begin(s->timer);
+ ptimer_stop(s->timer);
+ ptimer_transaction_commit(s->timer);
+
+ if (s->pretimeout_support) {
+ ptimer_transaction_begin(s->itimer);
+ ptimer_stop(s->itimer);
+ ptimer_transaction_commit(s->itimer);
+ }
+
+ s->wicr_locked = false;
+ s->wcr_locked = false;
+ s->wcr_wde_locked = false;
+
+ s->wcr = IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS;
+ s->wsr = 0;
+ s->wrsr &= ~(IMX2_WDT_WRSR_TOUT | IMX2_WDT_WRSR_SFTW);
+ s->wicr = IMX2_WDT_WICR_WICT_DEF;
+ s->wmcr = IMX2_WDT_WMCR_PDE;
+}
+
+static uint64_t imx2_wdt_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ IMX2WdtState *s = IMX2_WDT(opaque);
+
+ switch (addr) {
+ case IMX2_WDT_WCR:
+ return s->wcr;
+ case IMX2_WDT_WSR:
+ return s->wsr;
+ case IMX2_WDT_WRSR:
+ return s->wrsr;
+ case IMX2_WDT_WICR:
+ return s->wicr;
+ case IMX2_WDT_WMCR:
+ return s->wmcr;
+ }
return 0;
}
+static void imx_wdt2_update_itimer(IMX2WdtState *s, bool start)
+{
+ bool running = (s->wcr & IMX2_WDT_WCR_WDE) && (s->wcr & IMX2_WDT_WCR_WT);
+ bool enabled = s->wicr & IMX2_WDT_WICR_WIE;
+
+ ptimer_transaction_begin(s->itimer);
+ if (start || !enabled) {
+ ptimer_stop(s->itimer);
+ }
+ if (running && enabled) {
+ int count = ptimer_get_count(s->timer);
+ int pretimeout = s->wicr & IMX2_WDT_WICR_WICT;
+
+ /*
+ * Only (re-)start pretimeout timer if its counter value is larger
+ * than 0. Otherwise it will fire right away and we'll get an
+ * interrupt loop.
+ */
+ if (count > pretimeout) {
+ ptimer_set_count(s->itimer, count - pretimeout);
+ if (start) {
+ ptimer_run(s->itimer, 1);
+ }
+ }
+ }
+ ptimer_transaction_commit(s->itimer);
+}
+
+static void imx_wdt2_update_timer(IMX2WdtState *s, bool start)
+{
+ ptimer_transaction_begin(s->timer);
+ if (start) {
+ ptimer_stop(s->timer);
+ }
+ if ((s->wcr & IMX2_WDT_WCR_WDE) && (s->wcr & IMX2_WDT_WCR_WT)) {
+ int count = (s->wcr & IMX2_WDT_WCR_WT) >> 8;
+
+ /* A value of 0 reflects one period (0.5s). */
+ ptimer_set_count(s->timer, count + 1);
+ if (start) {
+ ptimer_run(s->timer, 1);
+ }
+ }
+ ptimer_transaction_commit(s->timer);
+ if (s->pretimeout_support) {
+ imx_wdt2_update_itimer(s, start);
+ }
+}
+
static void imx2_wdt_write(void *opaque, hwaddr addr,
uint64_t value, unsigned int size)
{
- if (addr == IMX2_WDT_WCR &&
- (~value & (IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS))) {
- watchdog_perform_action();
+ IMX2WdtState *s = IMX2_WDT(opaque);
+
+ switch (addr) {
+ case IMX2_WDT_WCR:
+ if (s->wcr_locked) {
+ value &= ~IMX2_WDT_WCR_LOCK_MASK;
+ value |= (s->wicr & IMX2_WDT_WCR_LOCK_MASK);
+ }
+ s->wcr_locked = true;
+ if (s->wcr_wde_locked) {
+ value &= ~IMX2_WDT_WCR_WDE;
+ value |= (s->wicr & ~IMX2_WDT_WCR_WDE);
+ } else if (value & IMX2_WDT_WCR_WDE) {
+ s->wcr_wde_locked = true;
+ }
+ if (s->wcr_wdt_locked) {
+ value &= ~IMX2_WDT_WCR_WDT;
+ value |= (s->wicr & ~IMX2_WDT_WCR_WDT);
+ } else if (value & IMX2_WDT_WCR_WDT) {
+ s->wcr_wdt_locked = true;
+ }
+
+ s->wcr = value;
+ if (!(value & IMX2_WDT_WCR_SRS)) {
+ s->wrsr = IMX2_WDT_WRSR_SFTW;
+ }
+ if (!(value & (IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS)) ||
+ (!(value & IMX2_WDT_WCR_WT) && (value & IMX2_WDT_WCR_WDE))) {
+ watchdog_perform_action();
+ }
+ s->wcr |= IMX2_WDT_WCR_SRS;
+ imx_wdt2_update_timer(s, true);
+ break;
+ case IMX2_WDT_WSR:
+ if (s->wsr == IMX2_WDT_SEQ1 && value == IMX2_WDT_SEQ2) {
+ imx_wdt2_update_timer(s, false);
+ }
+ s->wsr = value;
+ break;
+ case IMX2_WDT_WRSR:
+ break;
+ case IMX2_WDT_WICR:
+ if (!s->pretimeout_support) {
+ return;
+ }
+ value &= IMX2_WDT_WICR_LOCK_MASK | IMX2_WDT_WICR_WTIS;
+ if (s->wicr_locked) {
+ value &= IMX2_WDT_WICR_WTIS;
+ value |= (s->wicr & IMX2_WDT_WICR_LOCK_MASK);
+ }
+ s->wicr = value | (s->wicr & IMX2_WDT_WICR_WTIS);
+ if (value & IMX2_WDT_WICR_WTIS) {
+ s->wicr &= ~IMX2_WDT_WICR_WTIS;
+ qemu_set_irq(s->irq, 0);
+ }
+ imx_wdt2_update_itimer(s, true);
+ s->wicr_locked = true;
+ break;
+ case IMX2_WDT_WMCR:
+ s->wmcr = value & IMX2_WDT_WMCR_PDE;
+ break;
}
}
@@ -45,28 +210,76 @@ static const MemoryRegionOps imx2_wdt_ops = {
* real device but in practice there is no reason for a guest
* to access this device unaligned.
*/
- .min_access_size = 4,
- .max_access_size = 4,
+ .min_access_size = 2,
+ .max_access_size = 2,
.unaligned = false,
},
};
+static const VMStateDescription vmstate_imx2_wdt = {
+ .name = "imx2.wdt",
+ .fields = (VMStateField[]) {
+ VMSTATE_PTIMER(timer, IMX2WdtState),
+ VMSTATE_PTIMER(itimer, IMX2WdtState),
+ VMSTATE_BOOL(wicr_locked, IMX2WdtState),
+ VMSTATE_BOOL(wcr_locked, IMX2WdtState),
+ VMSTATE_BOOL(wcr_wde_locked, IMX2WdtState),
+ VMSTATE_BOOL(wcr_wdt_locked, IMX2WdtState),
+ VMSTATE_UINT16(wcr, IMX2WdtState),
+ VMSTATE_UINT16(wsr, IMX2WdtState),
+ VMSTATE_UINT16(wrsr, IMX2WdtState),
+ VMSTATE_UINT16(wmcr, IMX2WdtState),
+ VMSTATE_UINT16(wicr, IMX2WdtState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static void imx2_wdt_realize(DeviceState *dev, Error **errp)
{
IMX2WdtState *s = IMX2_WDT(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
memory_region_init_io(&s->mmio, OBJECT(dev),
&imx2_wdt_ops, s,
- TYPE_IMX2_WDT".mmio",
- IMX2_WDT_REG_NUM * sizeof(uint16_t));
- sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
+ TYPE_IMX2_WDT,
+ IMX2_WDT_MMIO_SIZE);
+ sysbus_init_mmio(sbd, &s->mmio);
+ sysbus_init_irq(sbd, &s->irq);
+
+ s->timer = ptimer_init(imx2_wdt_expired, s,
+ PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |
+ PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
+ PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
+ ptimer_transaction_begin(s->timer);
+ ptimer_set_freq(s->timer, 2);
+ ptimer_set_limit(s->timer, 0xff, 1);
+ ptimer_transaction_commit(s->timer);
+ if (s->pretimeout_support) {
+ s->itimer = ptimer_init(imx2_wdt_interrupt, s,
+ PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |
+ PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
+ PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
+ ptimer_transaction_begin(s->itimer);
+ ptimer_set_freq(s->itimer, 2);
+ ptimer_set_limit(s->itimer, 0xff, 1);
+ ptimer_transaction_commit(s->itimer);
+ }
}
+static Property imx2_wdt_properties[] = {
+ DEFINE_PROP_BOOL("pretimeout-support", IMX2WdtState, pretimeout_support,
+ false),
+};
+
static void imx2_wdt_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ device_class_set_props(dc, imx2_wdt_properties);
dc->realize = imx2_wdt_realize;
+ dc->reset = imx2_wdt_reset;
+ dc->vmsd = &vmstate_imx2_wdt;
+ dc->desc = "i.MX watchdog timer";
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
}
--
2.20.1
next prev parent reply other threads:[~2020-05-21 19:25 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-21 19:15 [PULL 00/29] target-arm queue Peter Maydell
2020-05-21 19:15 ` [PULL 01/29] tests/acceptance: Add a test for the canon-a1100 machine Peter Maydell
2020-05-21 19:15 ` [PULL 02/29] docs/system: Add 'Arm' to the Integrator/CP document title Peter Maydell
2020-05-21 19:15 ` [PULL 03/29] docs/system: Sort Arm board index into alphabetical order Peter Maydell
2020-05-21 19:15 ` [PULL 04/29] docs/system: Document Arm Versatile Express boards Peter Maydell
2020-05-21 19:15 ` [PULL 05/29] docs/system: Document the various MPS2 models Peter Maydell
2020-05-21 19:15 ` [PULL 06/29] docs/system: Document Musca boards Peter Maydell
2020-05-21 19:15 ` [PULL 07/29] linux-user/arm: BKPT should cause SIGTRAP, not be a syscall Peter Maydell
2020-05-21 19:15 ` [PULL 08/29] linux-user/arm: Remove bogus SVC 0xf0002 handling Peter Maydell
2020-05-21 19:15 ` [PULL 09/29] linux-user/arm: Handle invalid arm-specific syscalls correctly Peter Maydell
2020-05-21 19:15 ` [PULL 10/29] linux-user/arm: Fix identification of syscall numbers Peter Maydell
2020-05-21 19:15 ` [PULL 11/29] target/arm: Remove unused GEN_NEON_INTEGER_OP macro Peter Maydell
2020-05-21 19:15 ` [PULL 12/29] hw: Move i.MX watchdog driver to hw/watchdog Peter Maydell
2020-05-21 19:15 ` Peter Maydell [this message]
2020-05-21 19:15 ` [PULL 14/29] hw/arm/fsl-imx25: Wire up watchdog Peter Maydell
2020-05-21 19:15 ` [PULL 15/29] hw/arm/fsl-imx31: " Peter Maydell
2020-05-21 19:15 ` [PULL 16/29] hw/arm/fsl-imx6: Connect watchdog interrupts Peter Maydell
2020-05-21 19:15 ` [PULL 17/29] hw/arm/fsl-imx6ul: " Peter Maydell
2020-05-21 19:15 ` [PULL 18/29] hw/arm/fsl-imx7: Instantiate various unimplemented devices Peter Maydell
2020-05-21 19:16 ` [PULL 19/29] hw/arm/fsl-imx7: Connect watchdog interrupts Peter Maydell
2020-05-21 19:16 ` [PULL 20/29] hw/arm/integratorcp: Replace hw_error() by qemu_log_mask() Peter Maydell
2020-05-21 19:16 ` [PULL 21/29] hw/arm/pxa2xx: " Peter Maydell
2020-05-21 19:16 ` [PULL 22/29] hw/char/xilinx_uartlite: " Peter Maydell
2020-05-21 19:16 ` [PULL 23/29] hw/timer/exynos4210_mct: " Peter Maydell
2020-05-21 19:16 ` [PULL 24/29] ARM: PL061: Introduce N_GPIOS Peter Maydell
2020-05-21 19:16 ` [PULL 25/29] target/arm: Use tcg_gen_gvec_mov for clear_vec_high Peter Maydell
2020-05-21 19:16 ` [PULL 26/29] target/arm: Use clear_vec_high more effectively Peter Maydell
2020-05-21 19:16 ` [PULL 27/29] target/arm: Allow user-mode code to write CPSR.E via MSR Peter Maydell
2020-05-21 19:16 ` [PULL 28/29] linux-user/arm: Reset CPSR_E when entering a signal handler Peter Maydell
2020-05-21 19:16 ` [PULL 29/29] linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32 Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200521191610.10941-14-peter.maydell@linaro.org \
--to=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.