* [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions
@ 2020-05-21 19:24 Stephen Long
2020-05-21 19:24 ` [RISU PATCH v2 01/22] sve2.risu: Add patterns for floating-point pairwise ops Stephen Long
` (21 more replies)
0 siblings, 22 replies; 23+ messages in thread
From: Stephen Long @ 2020-05-21 19:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
Added risu patterns for all the sve2 instructions. Please point all any
glaring mistakes.
Stephen Long (22):
sve2.risu: Add patterns for floating-point pairwise ops
sve2.risu: Add patterns for integer multiply (unpredicated) ops
sve2.risu: Add patterns for integer (predicated) ops
sve2.risu: Add patterns for widening integer arithmetic ops
sve2.risu: Add patterns for misc ops
sve2.risu: Add patterns for accumulate ops
sve2.risu: Add patterns for narrowing ops
sve2.risu: Add patterns for character match insns
sve2.risu: Add patterns for histogram computation ops
sve2.risu: Add patterns for crypto operations
sve2.risu: Add patterns for bitwise shift (unpredicated) ops
sve2.risu: Add patterns for fp convert precision odd elems insns
sve2.risu: Add patterns for bitwise logical (unpredicated) ops
sve2.risu: Add patterns for fp unary ops (predicated)
sve2.risu: Add patterns for table lookup insns
sve2.risu: Add patterns for integer multiply-add (unpredicated) ops
sve2.risu: Add patterns for multiply (indexed) ops
sve2.risu: Add patterns for permute vector ops
sve2.risu: Add patterns for integer compare ops
sve2.risu: Add patterns for fp widening multiply-add ops
sve2.risu: Add patterns for gather load insns
sve2.risu: Add patterns for scatter store insns
sve2.risu | 524 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 524 insertions(+)
create mode 100755 sve2.risu
--
2.25.1
^ permalink raw reply [flat|nested] 23+ messages in thread
* [RISU PATCH v2 01/22] sve2.risu: Add patterns for floating-point pairwise ops
2020-05-21 19:24 [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions Stephen Long
@ 2020-05-21 19:24 ` Stephen Long
2020-05-21 19:24 ` [RISU PATCH v2 02/22] sve2.risu: Add patterns for integer multiply (unpredicated) ops Stephen Long
` (20 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Stephen Long @ 2020-05-21 19:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
sve2.risu | 14 ++++++++++++++
1 file changed, 14 insertions(+)
create mode 100755 sve2.risu
diff --git a/sve2.risu b/sve2.risu
new file mode 100755
index 0000000..78debd9
--- /dev/null
+++ b/sve2.risu
@@ -0,0 +1,14 @@
+# Input file for risugen defining AArch64 SVE2 instructions
+.mode arm.aarch64
+
+# Floating Point Pairwise
+FADDP A64_V 01100100 size:2 010 000 100 pg:3 zm:5 zdn:5 \
+!constraints { $size != 0; }
+FMAXNMP A64_V 01100100 size:2 010 100 100 pg:3 zm:5 zdn:5 \
+!constraints { $size != 0; }
+FMINNMP A64_V 01100100 size:2 010 101 100 pg:3 zm:5 zdn:5 \
+!constraints { $size != 0; }
+FMAXP A64_V 01100100 size:2 010 110 100 pg:3 zm:5 zdn:5 \
+!constraints { $size != 0; }
+FMINP A64_V 01100100 size:2 010 111 100 pg:3 zm:5 zdn:5 \
+!constraints { $size != 0; }
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [RISU PATCH v2 02/22] sve2.risu: Add patterns for integer multiply (unpredicated) ops
2020-05-21 19:24 [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions Stephen Long
2020-05-21 19:24 ` [RISU PATCH v2 01/22] sve2.risu: Add patterns for floating-point pairwise ops Stephen Long
@ 2020-05-21 19:24 ` Stephen Long
2020-05-21 19:24 ` [RISU PATCH v2 03/22] sve2.risu: Add patterns for integer (predicated) ops Stephen Long
` (19 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Stephen Long @ 2020-05-21 19:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
sve2.risu | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index 78debd9..346b812 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -1,6 +1,16 @@
# Input file for risugen defining AArch64 SVE2 instructions
.mode arm.aarch64
+# Integer Multiply (Unpredicated)
+## integer multiply vectors (unpredicated)
+MUL A64_V 00000100 size:2 1 zm:5 0110 00 zn:5 zd:5
+SMULH A64_V 00000100 size:2 1 zm:5 0110 10 zn:5 zd:5
+UMULH A64_V 00000100 size:2 1 zm:5 0110 11 zn:5 zd:5
+PMUL A64_V 00000100 00 1 zm:5 0110 01 zn:5 zd:5
+## signed saturating doubling multiply high (unpredicated)
+SQDMULH A64_V 00000100 size:2 1 zm:5 01110 0 zn:5 zd:5
+SQRDMULH A64_V 00000100 size:2 1 zm:5 01110 1 zn:5 zd:5
+
# Floating Point Pairwise
FADDP A64_V 01100100 size:2 010 000 100 pg:3 zm:5 zdn:5 \
!constraints { $size != 0; }
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [RISU PATCH v2 03/22] sve2.risu: Add patterns for integer (predicated) ops
2020-05-21 19:24 [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions Stephen Long
2020-05-21 19:24 ` [RISU PATCH v2 01/22] sve2.risu: Add patterns for floating-point pairwise ops Stephen Long
2020-05-21 19:24 ` [RISU PATCH v2 02/22] sve2.risu: Add patterns for integer multiply (unpredicated) ops Stephen Long
@ 2020-05-21 19:24 ` Stephen Long
2020-05-21 19:24 ` [RISU PATCH v2 04/22] sve2.risu: Add patterns for widening integer arithmetic ops Stephen Long
` (18 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Stephen Long @ 2020-05-21 19:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
sve2.risu | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index 346b812..f2e4dba 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -11,6 +11,57 @@ PMUL A64_V 00000100 00 1 zm:5 0110 01 zn:5 zd:5
SQDMULH A64_V 00000100 size:2 1 zm:5 01110 0 zn:5 zd:5
SQRDMULH A64_V 00000100 size:2 1 zm:5 01110 1 zn:5 zd:5
+# Integer Predicated
+## integer pairwise add and accumulate long
+SADALP A64_V 01000100 size:2 00010 0 101 pg:3 zn:5 zda:5 \
+!constraints { $size != 0; }
+UADALP A64_V 01000100 size:2 00010 1 101 pg:3 zn:5 zda:5 \
+!constraints { $size != 0; }
+## integer unary (predicated)
+URECPE A64_V 01000100 size:2 00 0 0 00 101 pg:3 zn:5 zda:5 \
+!constraints { $size == 2; }
+URSQRTE A64_V 01000100 size:2 00 0 0 01 101 pg:3 zn:5 zda:5 \
+!constraints { $size == 2; }
+SQABS A64_V 01000100 size:2 00 1 0 00 101 pg:3 zn:5 zda:5
+SQNEG A64_V 01000100 size:2 00 1 0 01 101 pg:3 zn:5 zda:5
+## saturating/rounding bitwise shift left (predicated)
+SRSHL A64_V 01000100 size:2 00 0010 100 pg:3 zm:5 zdn:5
+URSHL A64_V 01000100 size:2 00 0011 100 pg:3 zm:5 zdn:5
+SRSHLR A64_V 01000100 size:2 00 0110 100 pg:3 zm:5 zdn:5
+URSHLR A64_V 01000100 size:2 00 0111 100 pg:3 zm:5 zdn:5
+SQSHL_vec A64_V 01000100 size:2 00 1000 100 pg:3 zm:5 zdn:5
+UQSHL_vec A64_V 01000100 size:2 00 1001 100 pg:3 zm:5 zdn:5
+SQRSHL A64_V 01000100 size:2 00 1010 100 pg:3 zm:5 zdn:5
+UQRSHL A64_V 01000100 size:2 00 1011 100 pg:3 zm:5 zdn:5
+SQSHLR A64_V 01000100 size:2 00 1100 100 pg:3 zm:5 zdn:5
+UQSHLR A64_V 01000100 size:2 00 1101 100 pg:3 zm:5 zdn:5
+SQRSHLR A64_V 01000100 size:2 00 1110 100 pg:3 zm:5 zdn:5
+UQRSHLR A64_V 01000100 size:2 00 1111 100 pg:3 zm:5 zdn:5
+## integer halving add/subtract (predicated)
+SHADD A64_V 01000100 size:2 010 000 100 pg:3 zm:5 zdn:5
+UHADD A64_V 01000100 size:2 010 001 100 pg:3 zm:5 zdn:5
+SHSUB A64_V 01000100 size:2 010 010 100 pg:3 zm:5 zdn:5
+UHSUB A64_V 01000100 size:2 010 011 100 pg:3 zm:5 zdn:5
+SRHADD A64_V 01000100 size:2 010 100 100 pg:3 zm:5 zdn:5
+URHADD A64_V 01000100 size:2 010 101 100 pg:3 zm:5 zdn:5
+SHSUBR A64_V 01000100 size:2 010 110 100 pg:3 zm:5 zdn:5
+UHSUBR A64_V 01000100 size:2 010 111 100 pg:3 zm:5 zdn:5
+## integer pairwise arithmetic
+ADDP A64_V 01000100 size:2 010 001 101 pg:3 zm:5 zdn:5
+SMAXP A64_V 01000100 size:2 010 100 101 pg:3 zm:5 zdn:5
+UMAXP A64_V 01000100 size:2 010 101 101 pg:3 zm:5 zdn:5
+SMINP A64_V 01000100 size:2 010 110 101 pg:3 zm:5 zdn:5
+UMINP A64_V 01000100 size:2 010 111 101 pg:3 zm:5 zdn:5
+## saturating add/subtract
+SQADD A64_V 01000100 size:2 011 000 100 pg:3 zm:5 zdn:5
+UQADD A64_V 01000100 size:2 011 001 100 pg:3 zm:5 zdn:5
+SQSUB A64_V 01000100 size:2 011 010 100 pg:3 zm:5 zdn:5
+UQSUB A64_V 01000100 size:2 011 011 100 pg:3 zm:5 zdn:5
+SUQADD A64_V 01000100 size:2 011 100 100 pg:3 zm:5 zdn:5
+USQADD A64_V 01000100 size:2 011 101 100 pg:3 zm:5 zdn:5
+SQSUBR A64_V 01000100 size:2 011 110 100 pg:3 zm:5 zdn:5
+UQSUBR A64_V 01000100 size:2 011 111 100 pg:3 zm:5 zdn:5
+
# Floating Point Pairwise
FADDP A64_V 01100100 size:2 010 000 100 pg:3 zm:5 zdn:5 \
!constraints { $size != 0; }
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [RISU PATCH v2 04/22] sve2.risu: Add patterns for widening integer arithmetic ops
2020-05-21 19:24 [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions Stephen Long
` (2 preceding siblings ...)
2020-05-21 19:24 ` [RISU PATCH v2 03/22] sve2.risu: Add patterns for integer (predicated) ops Stephen Long
@ 2020-05-21 19:24 ` Stephen Long
2020-05-21 19:24 ` [RISU PATCH v2 05/22] sve2.risu: Add patterns for misc ops Stephen Long
` (17 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Stephen Long @ 2020-05-21 19:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
sve2.risu | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index f2e4dba..50ff756 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -62,6 +62,67 @@ USQADD A64_V 01000100 size:2 011 101 100 pg:3 zm:5 zdn:5
SQSUBR A64_V 01000100 size:2 011 110 100 pg:3 zm:5 zdn:5
UQSUBR A64_V 01000100 size:2 011 111 100 pg:3 zm:5 zdn:5
+# Widening Integer Arithmetic
+## integer add/subtract long
+SADDLB A64_V 01000101 size:2 0 zm:5 00 0000 zn:5 zd:5 \
+!constraints { $size != 0; }
+SADDLT A64_V 01000101 size:2 0 zm:5 00 0001 zn:5 zd:5 \
+!constraints { $size != 0; }
+UADDLB A64_V 01000101 size:2 0 zm:5 00 0010 zn:5 zd:5 \
+!constraints { $size != 0; }
+UADDLT A64_V 01000101 size:2 0 zm:5 00 0011 zn:5 zd:5 \
+!constraints { $size != 0; }
+SSUBLB A64_V 01000101 size:2 0 zm:5 00 0100 zn:5 zd:5 \
+!constraints { $size != 0; }
+SSUBLT A64_V 01000101 size:2 0 zm:5 00 0101 zn:5 zd:5 \
+!constraints { $size != 0; }
+USUBLB A64_V 01000101 size:2 0 zm:5 00 0110 zn:5 zd:5 \
+!constraints { $size != 0; }
+USUBLT A64_V 01000101 size:2 0 zm:5 00 0111 zn:5 zd:5 \
+!constraints { $size != 0; }
+SABDLB A64_V 01000101 size:2 0 zm:5 00 1100 zn:5 zd:5 \
+!constraints { $size != 0; }
+SABDLT A64_V 01000101 size:2 0 zm:5 00 1101 zn:5 zd:5 \
+!constraints { $size != 0; }
+UABDLB A64_V 01000101 size:2 0 zm:5 00 1110 zn:5 zd:5 \
+!constraints { $size != 0; }
+UABDLT A64_V 01000101 size:2 0 zm:5 00 1111 zn:5 zd:5 \
+!constraints { $size != 0; }
+## integer add/subtract wide
+SADDWB A64_V 01000101 size:2 0 zm:5 010 000 zn:5 zd:5 \
+!constraints { $size != 0; }
+SADDWT A64_V 01000101 size:2 0 zm:5 010 001 zn:5 zd:5 \
+!constraints { $size != 0; }
+UADDWB A64_V 01000101 size:2 0 zm:5 010 010 zn:5 zd:5 \
+!constraints { $size != 0; }
+UADDWT A64_V 01000101 size:2 0 zm:5 010 011 zn:5 zd:5 \
+!constraints { $size != 0; }
+SSUBWB A64_V 01000101 size:2 0 zm:5 010 100 zn:5 zd:5 \
+!constraints { $size != 0; }
+SSUBWT A64_V 01000101 size:2 0 zm:5 010 101 zn:5 zd:5 \
+!constraints { $size != 0; }
+USUBWB A64_V 01000101 size:2 0 zm:5 010 110 zn:5 zd:5 \
+!constraints { $size != 0; }
+USUBWT A64_V 01000101 size:2 0 zm:5 010 111 zn:5 zd:5 \
+!constraints { $size != 0; }
+## integer multiply long
+SQDMULLB A64_V 01000101 size:2 0 zm:5 011 000 zn:5 zd:5 \
+!constraints { $size != 0; }
+SQDMULLT A64_V 01000101 size:2 0 zm:5 011 001 zn:5 zd:5 \
+!constraints { $size != 0; }
+PMULLB A64_V 01000101 size:2 0 zm:5 011 010 zn:5 zd:5 \
+!constraints { $size != 0; }
+PMULLT A64_V 01000101 size:2 0 zm:5 011 011 zn:5 zd:5 \
+!constraints { $size != 0; }
+SMULLB A64_V 01000101 size:2 0 zm:5 011 100 zn:5 zd:5 \
+!constraints { $size != 0; }
+SMULLT A64_V 01000101 size:2 0 zm:5 011 101 zn:5 zd:5 \
+!constraints { $size != 0; }
+UMULLB A64_V 01000101 size:2 0 zm:5 011 110 zn:5 zd:5 \
+!constraints { $size != 0; }
+UMULLT A64_V 01000101 size:2 0 zm:5 011 111 zn:5 zd:5 \
+!constraints { $size != 0; }
+
# Floating Point Pairwise
FADDP A64_V 01100100 size:2 010 000 100 pg:3 zm:5 zdn:5 \
!constraints { $size != 0; }
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [RISU PATCH v2 05/22] sve2.risu: Add patterns for misc ops
2020-05-21 19:24 [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions Stephen Long
` (3 preceding siblings ...)
2020-05-21 19:24 ` [RISU PATCH v2 04/22] sve2.risu: Add patterns for widening integer arithmetic ops Stephen Long
@ 2020-05-21 19:24 ` Stephen Long
2020-05-21 19:24 ` [RISU PATCH v2 06/22] sve2.risu: Add patterns for accumulate ops Stephen Long
` (16 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Stephen Long @ 2020-05-21 19:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
sve2.risu | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index 50ff756..ca14193 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -123,6 +123,31 @@ UMULLB A64_V 01000101 size:2 0 zm:5 011 110 zn:5 zd:5 \
UMULLT A64_V 01000101 size:2 0 zm:5 011 111 zn:5 zd:5 \
!constraints { $size != 0; }
+# Misc
+## bitwise shift left long
+SSHLLB A64_V 010001010 tszh:1 0 tszl:2 imm3:3 1010 00 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+SSHLLT A64_V 010001010 tszh:1 0 tszl:2 imm3:3 1010 01 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+USHLLB A64_V 010001010 tszh:1 0 tszl:2 imm3:3 1010 10 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+USHLLT A64_V 010001010 tszh:1 0 tszl:2 imm3:3 1010 11 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+## integer add/subtract interleaved long
+SADDLBT A64_V 01000101 size:2 0 zm:5 1000 00 zn:5 zd:5 \
+!constraints { $size != 0; }
+SSUBLBT A64_V 01000101 size:2 0 zm:5 1000 10 zn:5 zd:5 \
+!constraints { $size != 0; }
+SSUBLTB A64_V 01000101 size:2 0 zm:5 1000 11 zn:5 zd:5 \
+!constraints { $size != 0; }
+## bitwise exclusive-or interleaved
+EORBT A64_V 01000101 size:2 0 zm:5 10010 0 zn:5 zd:5
+EORTB A64_V 01000101 size:2 0 zm:5 10010 1 zn:5 zd:5
+## bitwise permute
+BEXT A64_V 01000101 size:2 0 zm:5 1011 00 zn:5 zd:5
+BDEP A64_V 01000101 size:2 0 zm:5 1011 01 zn:5 zd:5
+BGRP A64_V 01000101 size:2 0 zm:5 1011 10 zn:5 zd:5
+
# Floating Point Pairwise
FADDP A64_V 01100100 size:2 010 000 100 pg:3 zm:5 zdn:5 \
!constraints { $size != 0; }
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [RISU PATCH v2 06/22] sve2.risu: Add patterns for accumulate ops
2020-05-21 19:24 [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions Stephen Long
` (4 preceding siblings ...)
2020-05-21 19:24 ` [RISU PATCH v2 05/22] sve2.risu: Add patterns for misc ops Stephen Long
@ 2020-05-21 19:24 ` Stephen Long
2020-05-21 19:24 ` [RISU PATCH v2 07/22] sve2.risu: Add patterns for narrowing ops Stephen Long
` (15 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Stephen Long @ 2020-05-21 19:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
sve2.risu | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index ca14193..caca5c0 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -148,6 +148,42 @@ BEXT A64_V 01000101 size:2 0 zm:5 1011 00 zn:5 zd:5
BDEP A64_V 01000101 size:2 0 zm:5 1011 01 zn:5 zd:5
BGRP A64_V 01000101 size:2 0 zm:5 1011 10 zn:5 zd:5
+# Accumulate
+## complex integer add
+CADD A64_V 01000101 size:2 00000 0 11011 rot:1 zm:5 zdn:5
+SQCADD A64_V 01000101 size:2 00000 1 11011 rot:1 zm:5 zdn:5
+## integer absolute difference and accumulate long
+SABALB A64_V 01000101 size:2 0 zm:5 1100 00 zn:5 zda:5 \
+!constraints { $size != 0; }
+SABALT A64_V 01000101 size:2 0 zm:5 1100 01 zn:5 zda:5 \
+!constraints { $size != 0; }
+UABALB A64_V 01000101 size:2 0 zm:5 1100 10 zn:5 zda:5 \
+!constraints { $size != 0; }
+UABALT A64_V 01000101 size:2 0 zm:5 1100 11 zn:5 zda:5 \
+!constraints { $size != 0; }
+## integer add/subtract long with carry
+ADCLB A64_V 01000101 0 size:1 0 zm:5 11010 0 zn:5 zda:5
+ADCLT A64_V 01000101 0 size:1 0 zm:5 11010 1 zn:5 zda:5
+SBCLB A64_V 01000101 1 size:1 0 zm:5 11010 0 zn:5 zda:5
+SBCLT A64_V 01000101 1 size:1 0 zm:5 11010 1 zn:5 zda:5
+## bitwise shift right and accumulate
+SSRA A64_V 01000101 tszh:2 0 tszl:2 imm3:3 1110 00 zn:5 zda:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+USRA A64_V 01000101 tszh:2 0 tszl:2 imm3:3 1110 01 zn:5 zda:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+SRSRA A64_V 01000101 tszh:2 0 tszl:2 imm3:3 1110 10 zn:5 zda:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+URSRA A64_V 01000101 tszh:2 0 tszl:2 imm3:3 1110 11 zn:5 zda:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+## bitwise shift and insert
+SRI A64_V 01000101 tszh:2 0 tszl:2 imm3:3 11110 0 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+SLI A64_V 01000101 tszh:2 0 tszl:2 imm3:3 11110 1 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+## integer absolute difference and accumulate
+SABA A64_V 01000101 size:2 0 zm:5 11111 0 zn:5 zda:5
+UABA A64_V 01000101 size:2 0 zm:5 11111 1 zn:5 zda:5
+
# Floating Point Pairwise
FADDP A64_V 01100100 size:2 010 000 100 pg:3 zm:5 zdn:5 \
!constraints { $size != 0; }
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [RISU PATCH v2 07/22] sve2.risu: Add patterns for narrowing ops
2020-05-21 19:24 [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions Stephen Long
` (5 preceding siblings ...)
2020-05-21 19:24 ` [RISU PATCH v2 06/22] sve2.risu: Add patterns for accumulate ops Stephen Long
@ 2020-05-21 19:24 ` Stephen Long
2020-05-21 19:24 ` [RISU PATCH v2 08/22] sve2.risu: Add patterns for character match insns Stephen Long
` (14 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Stephen Long @ 2020-05-21 19:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
sve2.risu | 76 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index caca5c0..1ebb08c 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -184,6 +184,82 @@ SLI A64_V 01000101 tszh:2 0 tszl:2 imm3:3 11110 1 zn:5 zd:5 \
SABA A64_V 01000101 size:2 0 zm:5 11111 0 zn:5 zda:5
UABA A64_V 01000101 size:2 0 zm:5 11111 1 zn:5 zda:5
+# Narrowing
+## saturating extract narrow
+SQXTNB_H A64_V 010001010 0101 000010 000 zn:5 zd:5
+SQXTNB_S A64_V 010001010 0110 000010 000 zn:5 zd:5
+SQXTNB_D A64_V 010001010 1100 000010 000 zn:5 zd:5
+
+SQXTNT_H A64_V 010001010 0101 000010 001 zn:5 zd:5
+SQXTNT_S A64_V 010001010 0110 000010 001 zn:5 zd:5
+SQXTNT_D A64_V 010001010 1100 000010 001 zn:5 zd:5
+
+UQXTNB_H A64_V 010001010 0101 000010 010 zn:5 zd:5
+UQXTNB_S A64_V 010001010 0110 000010 010 zn:5 zd:5
+UQXTNB_D A64_V 010001010 1100 000010 010 zn:5 zd:5
+
+UQXTNT_H A64_V 010001010 0101 000010 011 zn:5 zd:5
+UQXTNT_S A64_V 010001010 0110 000010 011 zn:5 zd:5
+UQXTNT_D A64_V 010001010 1100 000010 011 zn:5 zd:5
+
+SQXTUNB_H A64_V 010001010 0101 000010 100 zn:5 zd:5
+SQXTUNB_S A64_V 010001010 0110 000010 100 zn:5 zd:5
+SQXTUNB_D A64_V 010001010 1100 000010 100 zn:5 zd:5
+
+SQXTUNT_H A64_V 010001010 0101 000010 101 zn:5 zd:5
+SQXTUNT_S A64_V 010001010 0110 000010 101 zn:5 zd:5
+SQXTUNT_D A64_V 010001010 1100 000010 101 zn:5 zd:5
+## bitwise shift right narrow
+SQSHRUNB A64_V 010001010 tszh:1 1 tszl:2 imm3:3 00 0000 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+SQSHRUNT A64_V 010001010 tszh:1 1 tszl:2 imm3:3 00 0001 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+SQRSHRUNB A64_V 010001010 tszh:1 1 tszl:2 imm3:3 00 0010 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+SQRSHRUNT A64_V 010001010 tszh:1 1 tszl:2 imm3:3 00 0011 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+SHRNB A64_V 010001010 tszh:1 1 tszl:2 imm3:3 00 0100 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+SHRNT A64_V 010001010 tszh:1 1 tszl:2 imm3:3 00 0101 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+RSHRNB A64_V 010001010 tszh:1 1 tszl:2 imm3:3 00 0110 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+RSHRNT A64_V 010001010 tszh:1 1 tszl:2 imm3:3 00 0111 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+SQSHRNB A64_V 010001010 tszh:1 1 tszl:2 imm3:3 00 1000 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+SQSHRNT A64_V 010001010 tszh:1 1 tszl:2 imm3:3 00 1001 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+SQRSHRNB A64_V 010001010 tszh:1 1 tszl:2 imm3:3 00 1010 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+SQRSHRNT A64_V 010001010 tszh:1 1 tszl:2 imm3:3 00 1011 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+UQSHRNB A64_V 010001010 tszh:1 1 tszl:2 imm3:3 00 1100 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+UQSHRNT A64_V 010001010 tszh:1 1 tszl:2 imm3:3 00 1101 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+UQRSHRNB A64_V 010001010 tszh:1 1 tszl:2 imm3:3 00 1110 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+UQRSHRNT A64_V 010001010 tszh:1 1 tszl:2 imm3:3 00 1111 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+## integer add/subtract narrow high part
+ADDHNB A64_V 01000101 size:2 1 zm:5 011 000 zn:5 zd:5 \
+!constraints { $size != 0; }
+ADDHNT A64_V 01000101 size:2 1 zm:5 011 001 zn:5 zd:5 \
+!constraints { $size != 0; }
+RADDHNB A64_V 01000101 size:2 1 zm:5 011 010 zn:5 zd:5 \
+!constraints { $size != 0; }
+RADDHNT A64_V 01000101 size:2 1 zm:5 011 011 zn:5 zd:5 \
+!constraints { $size != 0; }
+SUBHNB A64_V 01000101 size:2 1 zm:5 011 100 zn:5 zd:5 \
+!constraints { $size != 0; }
+SUBHNT A64_V 01000101 size:2 1 zm:5 011 101 zn:5 zd:5 \
+!constraints { $size != 0; }
+RSUBHNB A64_V 01000101 size:2 1 zm:5 011 110 zn:5 zd:5 \
+!constraints { $size != 0; }
+RSUBHNT A64_V 01000101 size:2 1 zm:5 011 111 zn:5 zd:5 \
+!constraints { $size != 0; }
+
# Floating Point Pairwise
FADDP A64_V 01100100 size:2 010 000 100 pg:3 zm:5 zdn:5 \
!constraints { $size != 0; }
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [RISU PATCH v2 08/22] sve2.risu: Add patterns for character match insns
2020-05-21 19:24 [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions Stephen Long
` (6 preceding siblings ...)
2020-05-21 19:24 ` [RISU PATCH v2 07/22] sve2.risu: Add patterns for narrowing ops Stephen Long
@ 2020-05-21 19:24 ` Stephen Long
2020-05-21 19:24 ` [RISU PATCH v2 09/22] sve2.risu: Add patterns for histogram computation ops Stephen Long
` (13 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Stephen Long @ 2020-05-21 19:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
sve2.risu | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index 1ebb08c..5bd515c 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -260,6 +260,12 @@ RSUBHNB A64_V 01000101 size:2 1 zm:5 011 110 zn:5 zd:5 \
RSUBHNT A64_V 01000101 size:2 1 zm:5 011 111 zn:5 zd:5 \
!constraints { $size != 0; }
+# Character Match
+MATCH A64_V 01000101 size:2 1 zm:5 100 pg:3 zn:5 0 pd:4 \
+!constraints { $size < 2; }
+NMATCH A64_V 01000101 size:2 1 zm:5 100 pg:3 zn:5 1 pd:4 \
+!constraints { $size < 2; }
+
# Floating Point Pairwise
FADDP A64_V 01100100 size:2 010 000 100 pg:3 zm:5 zdn:5 \
!constraints { $size != 0; }
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [RISU PATCH v2 09/22] sve2.risu: Add patterns for histogram computation ops
2020-05-21 19:24 [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions Stephen Long
` (7 preceding siblings ...)
2020-05-21 19:24 ` [RISU PATCH v2 08/22] sve2.risu: Add patterns for character match insns Stephen Long
@ 2020-05-21 19:24 ` Stephen Long
2020-05-21 19:24 ` [RISU PATCH v2 10/22] sve2.risu: Add patterns for crypto operations Stephen Long
` (12 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Stephen Long @ 2020-05-21 19:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
sve2.risu | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index 5bd515c..725bbd2 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -266,6 +266,12 @@ MATCH A64_V 01000101 size:2 1 zm:5 100 pg:3 zn:5 0 pd:4 \
NMATCH A64_V 01000101 size:2 1 zm:5 100 pg:3 zn:5 1 pd:4 \
!constraints { $size < 2; }
+# Histogram Computation
+HISTSEG A64_V 01000101 size:2 1 zm:5 101000 zn:5 zd:5 \
+!constraints { $size != 0; }
+HISTCNT A64_V 01000101 size:2 1 zm:5 110 pg:3 zn:5 zd:5 \
+!constraints { $size > 1; }
+
# Floating Point Pairwise
FADDP A64_V 01100100 size:2 010 000 100 pg:3 zm:5 zdn:5 \
!constraints { $size != 0; }
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [RISU PATCH v2 10/22] sve2.risu: Add patterns for crypto operations
2020-05-21 19:24 [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions Stephen Long
` (8 preceding siblings ...)
2020-05-21 19:24 ` [RISU PATCH v2 09/22] sve2.risu: Add patterns for histogram computation ops Stephen Long
@ 2020-05-21 19:24 ` Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 11/22] sve2.risu: Add patterns for bitwise shift (unpredicated) ops Stephen Long
` (11 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Stephen Long @ 2020-05-21 19:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
sve2.risu | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index 725bbd2..6177848 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -272,6 +272,18 @@ HISTSEG A64_V 01000101 size:2 1 zm:5 101000 zn:5 zd:5 \
HISTCNT A64_V 01000101 size:2 1 zm:5 110 pg:3 zn:5 zd:5 \
!constraints { $size > 1; }
+# Crypto Extensions
+## crypto unary operations
+AESMC A64_V 01000101 size:2 10000011100 0 00000 zdn:5
+AESIMC A64_V 01000101 size:2 10000011100 1 00000 zdn:5
+## crypto destructive binary operations
+AESE A64_V 01000101 00 10001 0 11100 0 zm:5 zdn:5
+AESD A64_V 01000101 00 10001 0 11100 1 zm:5 zdn:5
+SM4E A64_V 01000101 00 10001 1 11100 0 zm:5 zdn:5
+## crypto constructive binary operations
+SM4EKEY A64_V 01000101 00 1 zm:5 11110 0 zn:5 zd:5
+RAX1 A64_V 01000101 00 1 zm:5 11110 1 zn:5 zd:5
+
# Floating Point Pairwise
FADDP A64_V 01100100 size:2 010 000 100 pg:3 zm:5 zdn:5 \
!constraints { $size != 0; }
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [RISU PATCH v2 11/22] sve2.risu: Add patterns for bitwise shift (unpredicated) ops
2020-05-21 19:24 [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions Stephen Long
` (9 preceding siblings ...)
2020-05-21 19:24 ` [RISU PATCH v2 10/22] sve2.risu: Add patterns for crypto operations Stephen Long
@ 2020-05-21 19:25 ` Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 12/22] sve2.risu: Add patterns for fp convert precision odd elems insns Stephen Long
` (10 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Stephen Long @ 2020-05-21 19:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
sve2.risu | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index 6177848..adc5dd1 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -1,6 +1,19 @@
# Input file for risugen defining AArch64 SVE2 instructions
.mode arm.aarch64
+# Bitwise Shift (Unpredicated)
+## bitwise shift by immediate (predicated)
+SQSHL_imm A64_V 00000100 tszh:2 00 0110 100 pg:3 tszl:2 imm3:3 zdn:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+UQSHL_imm A64_V 00000100 tszh:2 00 0111 100 pg:3 tszl:2 imm3:3 zdn:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+SRSHR A64_V 00000100 tszh:2 00 1100 100 pg:3 tszl:2 imm3:3 zdn:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+URSHR A64_V 00000100 tszh:2 00 1101 100 pg:3 tszl:2 imm3:3 zdn:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+SQSHLU A64_V 00000100 tszh:2 00 1111 100 pg:3 tszl:2 imm3:3 zdn:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+
# Integer Multiply (Unpredicated)
## integer multiply vectors (unpredicated)
MUL A64_V 00000100 size:2 1 zm:5 0110 00 zn:5 zd:5
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [RISU PATCH v2 12/22] sve2.risu: Add patterns for fp convert precision odd elems insns
2020-05-21 19:24 [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions Stephen Long
` (10 preceding siblings ...)
2020-05-21 19:25 ` [RISU PATCH v2 11/22] sve2.risu: Add patterns for bitwise shift (unpredicated) ops Stephen Long
@ 2020-05-21 19:25 ` Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 13/22] sve2.risu: Add patterns for bitwise logical (unpredicated) ops Stephen Long
` (9 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Stephen Long @ 2020-05-21 19:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
sve2.risu | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index adc5dd1..4b2a79d 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -297,6 +297,13 @@ SM4E A64_V 01000101 00 10001 1 11100 0 zm:5 zdn:5
SM4EKEY A64_V 01000101 00 1 zm:5 11110 0 zn:5 zd:5
RAX1 A64_V 01000101 00 1 zm:5 11110 1 zn:5 zd:5
+# Floating Point Convert Precision Odd Elements
+FCVTXNT A64_V 01100100 00 0010 10 101 pg:3 zn:5 zd:5
+FCVTNT_SH A64_V 01100100 10 0010 00 101 pg:3 zn:5 zd:5
+FCVTLT_HS A64_V 01100100 10 0010 01 101 pg:3 zn:5 zd:5
+FCVTNT_DS A64_V 01100100 11 0010 10 101 pg:3 zn:5 zd:5
+FCVTLT_SD A64_V 01100100 11 0010 11 101 pg:3 zn:5 zd:5
+
# Floating Point Pairwise
FADDP A64_V 01100100 size:2 010 000 100 pg:3 zm:5 zdn:5 \
!constraints { $size != 0; }
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [RISU PATCH v2 13/22] sve2.risu: Add patterns for bitwise logical (unpredicated) ops
2020-05-21 19:24 [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions Stephen Long
` (11 preceding siblings ...)
2020-05-21 19:25 ` [RISU PATCH v2 12/22] sve2.risu: Add patterns for fp convert precision odd elems insns Stephen Long
@ 2020-05-21 19:25 ` Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 14/22] sve2.risu: Add patterns for fp unary ops (predicated) Stephen Long
` (8 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Stephen Long @ 2020-05-21 19:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
sve2.risu | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index 4b2a79d..313c5ac 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -1,6 +1,17 @@
# Input file for risugen defining AArch64 SVE2 instructions
.mode arm.aarch64
+# Bitwise Logical (Unpredicated)
+XAR A64_V 00000100 tszh:2 1 tszl:2 imm3:3 001101 zm:5 zdn:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+## bitwise ternary operations
+EOR3 A64_V 00000100 00 1 zm:5 00111 0 zk:5 zdn:5
+BSL A64_V 00000100 00 1 zm:5 00111 1 zk:5 zdn:5
+BCAX A64_V 00000100 01 1 zm:5 00111 0 zk:5 zdn:5
+BSL1N A64_V 00000100 01 1 zm:5 00111 1 zk:5 zdn:5
+BSL2N A64_V 00000100 10 1 zm:5 00111 1 zk:5 zdn:5
+NBSL A64_V 00000100 11 1 zm:5 00111 1 zk:5 zdn:5
+
# Bitwise Shift (Unpredicated)
## bitwise shift by immediate (predicated)
SQSHL_imm A64_V 00000100 tszh:2 00 0110 100 pg:3 tszl:2 imm3:3 zdn:5 \
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [RISU PATCH v2 14/22] sve2.risu: Add patterns for fp unary ops (predicated)
2020-05-21 19:24 [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions Stephen Long
` (12 preceding siblings ...)
2020-05-21 19:25 ` [RISU PATCH v2 13/22] sve2.risu: Add patterns for bitwise logical (unpredicated) ops Stephen Long
@ 2020-05-21 19:25 ` Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 15/22] sve2.risu: Add patterns for table lookup insns Stephen Long
` (7 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Stephen Long @ 2020-05-21 19:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
sve2.risu | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index 313c5ac..48b2957 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -315,6 +315,13 @@ FCVTLT_HS A64_V 01100100 10 0010 01 101 pg:3 zn:5 zd:5
FCVTNT_DS A64_V 01100100 11 0010 10 101 pg:3 zn:5 zd:5
FCVTLT_SD A64_V 01100100 11 0010 11 101 pg:3 zn:5 zd:5
+# Floating Point Unary Operations (Predicated)
+## floating-point convert precision
+FCVTX A64_V 01100101 00 0010 10 101 pg:3 zn:5 zd:5
+## floating-point convert to integer
+FLOGB A64_V 01100101 00 011 size:2 0101 p:3 zn:5 zd:5 \
+!constraints { $size != 0; }
+
# Floating Point Pairwise
FADDP A64_V 01100100 size:2 010 000 100 pg:3 zm:5 zdn:5 \
!constraints { $size != 0; }
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [RISU PATCH v2 15/22] sve2.risu: Add patterns for table lookup insns
2020-05-21 19:24 [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions Stephen Long
` (13 preceding siblings ...)
2020-05-21 19:25 ` [RISU PATCH v2 14/22] sve2.risu: Add patterns for fp unary ops (predicated) Stephen Long
@ 2020-05-21 19:25 ` Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 16/22] sve2.risu: Add patterns for integer multiply-add (unpredicated) ops Stephen Long
` (6 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Stephen Long @ 2020-05-21 19:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
sve2.risu | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index 48b2957..c48717b 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -333,3 +333,7 @@ FMAXP A64_V 01100100 size:2 010 110 100 pg:3 zm:5 zdn:5 \
!constraints { $size != 0; }
FMINP A64_V 01100100 size:2 010 111 100 pg:3 zm:5 zdn:5 \
!constraints { $size != 0; }
+
+# Table Lookup
+TBL A64_V 00000101 size:2 1 zm:5 00101 0 zn:5 zd:5
+TBX A64_V 00000101 size:2 1 zm:5 00101 1 zn:5 zd:5
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [RISU PATCH v2 16/22] sve2.risu: Add patterns for integer multiply-add (unpredicated) ops
2020-05-21 19:24 [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions Stephen Long
` (14 preceding siblings ...)
2020-05-21 19:25 ` [RISU PATCH v2 15/22] sve2.risu: Add patterns for table lookup insns Stephen Long
@ 2020-05-21 19:25 ` Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 17/22] sve2.risu: Add patterns for multiply (indexed) ops Stephen Long
` (5 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Stephen Long @ 2020-05-21 19:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
sve2.risu | 41 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index c48717b..8602059 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -25,6 +25,47 @@ URSHR A64_V 00000100 tszh:2 00 1101 100 pg:3 tszl:2 imm3:3 zdn:5 \
SQSHLU A64_V 00000100 tszh:2 00 1111 100 pg:3 tszl:2 imm3:3 zdn:5 \
!constraints { !($tszh == 0 && $tszl == 0); }
+# Integer Multiply-Add (Unpredicated)
+CDOT A64_V 01000100 size:2 0 zm:5 0001 rot:2 zn:5 zda:5 \
+!constraints { $size > 1; }
+## saturating multiply-add interleaved long
+SQDMLALBT A64_V 01000100 size:2 0 zm:5 00001 0 zn:5 zda:5 \
+!constraints { $size != 0; }
+SQDMLSLBT A64_V 01000100 size:2 0 zm:5 00001 1 zn:5 zda:5 \
+!constraints { $size != 0; }
+## complex integer multiply-add
+CMLA A64_V 01000100 size:2 0 zm:5 001 0 rot:2 zn:5 zda:5
+SQRDCMLAH A64_V 01000100 size:2 0 zm:5 001 1 rot:2 zn:5 zda:5
+## integer multiply-add long
+SMLALB A64_V 01000100 size:2 0 zm:5 010 000 zn:5 zda:5 \
+!constraints { $size != 0; }
+SMLALT A64_V 01000100 size:2 0 zm:5 010 001 zn:5 zda:5 \
+!constraints { $size != 0; }
+UMLALB A64_V 01000100 size:2 0 zm:5 010 010 zn:5 zda:5 \
+!constraints { $size != 0; }
+UMLALT A64_V 01000100 size:2 0 zm:5 010 011 zn:5 zda:5 \
+!constraints { $size != 0; }
+SMLSLB A64_V 01000100 size:2 0 zm:5 010 100 zn:5 zda:5 \
+!constraints { $size != 0; }
+SMLSLT A64_V 01000100 size:2 0 zm:5 010 101 zn:5 zda:5 \
+!constraints { $size != 0; }
+UMLSLB A64_V 01000100 size:2 0 zm:5 010 110 zn:5 zda:5 \
+!constraints { $size != 0; }
+UMLSLT A64_V 01000100 size:2 0 zm:5 010 111 zn:5 zda:5 \
+!constraints { $size != 0; }
+## saturating multiply-add long
+SQDMLALB A64_V 01000100 size:2 0 zm:5 0110 00 zn:5 zda:5 \
+!constraints { $size != 0; }
+SQDMLALT A64_V 01000100 size:2 0 zm:5 0110 01 zn:5 zda:5 \
+!constraints { $size != 0; }
+SQDMLSLB A64_V 01000100 size:2 0 zm:5 0110 10 zn:5 zda:5 \
+!constraints { $size != 0; }
+SQDMLSLT A64_V 01000100 size:2 0 zm:5 0110 11 zn:5 zda:5 \
+!constraints { $size != 0; }
+## saturating multiply-add high
+SQRDMLAH A64_V 01000100 size:2 0 zm:5 01110 0 zn:5 zda:5
+SQRDMLSH A64_V 01000100 size:2 0 zm:5 01110 1 zn:5 zda:5
+
# Integer Multiply (Unpredicated)
## integer multiply vectors (unpredicated)
MUL A64_V 00000100 size:2 1 zm:5 0110 00 zn:5 zd:5
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [RISU PATCH v2 17/22] sve2.risu: Add patterns for multiply (indexed) ops
2020-05-21 19:24 [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions Stephen Long
` (15 preceding siblings ...)
2020-05-21 19:25 ` [RISU PATCH v2 16/22] sve2.risu: Add patterns for integer multiply-add (unpredicated) ops Stephen Long
@ 2020-05-21 19:25 ` Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 18/22] sve2.risu: Add patterns for permute vector ops Stephen Long
` (4 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Stephen Long @ 2020-05-21 19:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
sve2.risu | 86 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 86 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index 8602059..1bcbd93 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -66,6 +66,92 @@ SQDMLSLT A64_V 01000100 size:2 0 zm:5 0110 11 zn:5 zda:5 \
SQRDMLAH A64_V 01000100 size:2 0 zm:5 01110 0 zn:5 zda:5
SQRDMLSH A64_V 01000100 size:2 0 zm:5 01110 1 zn:5 zda:5
+# Multiply (Indexed)
+## integer multiply-add (indexed)
+MLA_H A64_V 01000100 0 i3h:1 1 i3l:2 zm:3 00001 0 zn:5 zda:5
+MLS_H A64_V 01000100 0 i3h:1 1 i3l:2 zm:3 00001 1 zn:5 zda:5
+
+MLA_S A64_V 01000100 1 0 1 i2:2 zm:3 00001 0 zn:5 zda:5
+MLS_S A64_V 01000100 1 0 1 i2:2 zm:3 00001 1 zn:5 zda:5
+
+MLA_D A64_V 01000100 1 1 1 i1:1 zm:4 00001 0 zn:5 zda:5
+MLS_D A64_V 01000100 1 1 1 i1:1 zm:4 00001 1 zn:5 zda:5
+## saturating multiply-add high (indexed)
+SQRDMLAH_H A64_V 01000100 0 i3h:1 1 i3l:2 zm:3 00010 0 zn:5 zda:5
+SQRDMLSH_H A64_V 01000100 0 i3h:1 1 i3l:2 zm:3 00010 1 zn:5 zda:5
+
+SQRDMLAH_S A64_V 01000100 1 0 1 i2:2 zm:3 00010 0 zn:5 zda:5
+SQRDMLSH_S A64_V 01000100 1 0 1 i2:2 zm:3 00010 1 zn:5 zda:5
+
+SQRDMLAH_D A64_V 01000100 1 1 1 i1:1 zm:4 00010 0 zn:5 zda:5
+SQRDMLSH_D A64_V 01000100 1 1 1 i1:1 zm:4 00010 1 zn:5 zda:5
+## saturating multiply-add (indexed)
+SQDMLALB_S A64_V 01000100 1 0 1 i3h:2 zm:3 001 0 i3l:1 0 zn:5 zda:5
+SQDMLALT_S A64_V 01000100 1 0 1 i3h:2 zm:3 001 0 i3l:1 1 zn:5 zda:5
+SQDMLSLB_S A64_V 01000100 1 0 1 i3h:2 zm:3 001 1 i3l:1 0 zn:5 zda:5
+SQDMLSLT_S A64_V 01000100 1 0 1 i3h:2 zm:3 001 1 i3l:1 1 zn:5 zda:5
+
+SQDMLALB_D A64_V 01000100 1 1 1 i2h:1 zm:4 001 0 i2l:1 0 zn:5 zda:5
+SQDMLALT_D A64_V 01000100 1 1 1 i2h:1 zm:4 001 0 i2l:1 1 zn:5 zda:5
+SQDMLSLB_D A64_V 01000100 1 1 1 i2h:1 zm:4 001 1 i2l:1 0 zn:5 zda:5
+SQDMLSLT_D A64_V 01000100 1 1 1 i2h:1 zm:4 001 1 i2l:1 1 zn:5 zda:5
+## complex integer dot product (indexed)
+CDOT_S A64_V 01000100 1 0 1 i2:2 zm:3 0100 rot:2 zn:5 zda:5
+CDOT_D A64_V 01000100 1 1 1 i1:1 zm:4 0100 rot:2 zn:5 zda:5
+## complex integer multiply-add (indexed)
+CMLA_S A64_V 01000100 1 0 1 i2:2 zm:3 0110 rot:2 zn:5 zda:5
+CMLA_D A64_V 01000100 1 1 1 i1:1 zm:4 0110 rot:2 zn:5 zda:5
+## complex saturating multiply-add (indexed)
+SQRDCMLAH_H A64_V 01000100 1 0 1 i2:2 zm:3 0111 rot:2 zn:5 zda:5
+SQRDCMLAH_S A64_V 01000100 1 1 1 i1:1 zm:4 0111 rot:2 zn:5 zda:5
+## integer multiply-add long (indexed)
+SMLALB_S A64_V 01000100 101 i3h:2 zm:3 1000 i3l:1 0 zn:5 zda:5
+SMLALT_S A64_V 01000100 101 i3h:2 zm:3 1000 i3l:1 1 zn:5 zda:5
+UMLALB_S A64_V 01000100 101 i3h:2 zm:3 1001 i3l:1 0 zn:5 zda:5
+UMLALT_S A64_V 01000100 101 i3h:2 zm:3 1001 i3l:1 1 zn:5 zda:5
+SMLSLB_S A64_V 01000100 101 i3h:2 zm:3 1010 i3l:1 0 zn:5 zda:5
+SMLSLT_S A64_V 01000100 101 i3h:2 zm:3 1010 i3l:1 1 zn:5 zda:5
+UMLSLB_S A64_V 01000100 101 i3h:2 zm:3 1011 i3l:1 0 zn:5 zda:5
+UMLSLT_S A64_V 01000100 101 i3h:2 zm:3 1011 i3l:1 1 zn:5 zda:5
+
+SMLALB_D A64_V 01000100 111 i2h:1 zm:4 1000 i2l:1 0 zn:5 zda:5
+SMLALT_D A64_V 01000100 111 i2h:1 zm:4 1000 i2l:1 1 zn:5 zda:5
+UMLALB_D A64_V 01000100 111 i2h:1 zm:4 1001 i2l:1 0 zn:5 zda:5
+UMLALT_D A64_V 01000100 111 i2h:1 zm:4 1001 i2l:1 1 zn:5 zda:5
+SMLSLB_D A64_V 01000100 111 i2h:1 zm:4 1010 i2l:1 0 zn:5 zda:5
+SMLSLT_D A64_V 01000100 111 i2h:1 zm:4 1010 i2l:1 1 zn:5 zda:5
+UMLSLB_D A64_V 01000100 111 i2h:1 zm:4 1011 i2l:1 0 zn:5 zda:5
+UMLSLT_D A64_V 01000100 111 i2h:1 zm:4 1011 i2l:1 1 zn:5 zda:5
+## integer multiply long (indexed)
+SMULLB_S A64_V 01000100 101 i3h:2 zm:3 1100 i3l:1 0 zn:5 zd:5
+SMULLT_S A64_V 01000100 101 i3h:2 zm:3 1100 i3l:1 1 zn:5 zd:5
+UMULLB_S A64_V 01000100 101 i3h:2 zm:3 1101 i3l:1 0 zn:5 zd:5
+UMULLT_S A64_V 01000100 101 i3h:2 zm:3 1101 i3l:1 1 zn:5 zd:5
+
+SMULLB_D A64_V 01000100 111 i2h:1 zm:4 1100 i2l:1 0 zn:5 zd:5
+SMULLT_D A64_V 01000100 111 i2h:1 zm:4 1100 i2l:1 1 zn:5 zd:5
+UMULLB_D A64_V 01000100 111 i2h:1 zm:4 1101 i2l:1 0 zn:5 zd:5
+UMULLT_D A64_V 01000100 111 i2h:1 zm:4 1101 i2l:1 1 zn:5 zd:5
+## saturating multiply (indexed)
+SQDMULLB_S A64_V 01000100 101 i3h:2 zm:3 1110 i3l:1 0 zn:5 zd:5
+SQDMULLT_S A64_V 01000100 101 i3h:2 zm:3 1110 i3l:1 1 zn:5 zd:5
+
+SQDMULLB_D A64_V 01000100 111 i2h:1 zm:4 1110 i2l:1 0 zn:5 zd:5
+SQDMULLT_D A64_V 01000100 111 i2h:1 zm:4 1110 i2l:1 1 zn:5 zd:5
+## saturating multiply high (indexed)
+SQDMULH_H A64_V 01000100 0 i3h:1 1 i3l:2 zm:3 11110 0 zn:5 zd:5
+SQRDMULH_H A64_V 01000100 0 i3h:1 1 i3l:2 zm:3 11110 1 zn:5 zd:5
+
+SQDMULH_S A64_V 01000100 101 i2:2 zm:3 11110 0 zn:5 zd:5
+SQRDMULH_S A64_V 01000100 101 i2:2 zm:3 11110 1 zn:5 zd:5
+
+SQDMULH_D A64_V 01000100 111 i1:1 zm:4 11110 0 zn:5 zd:5
+SQRDMULH_D A64_V 01000100 111 i1:1 zm:4 11110 1 zn:5 zd:5
+## integer multiply (indexed)
+MUL_H A64_V 01000100 0 i3h:1 1 i3l:2 zm:3 111110 zn:5 zd:5
+MUL_S A64_V 01000100 101 i2:2 zm:3 111110 zn:5 zd:5
+MUL_D A64_V 01000100 111 i1:1 zm:4 111110 zn:5 zd:5
+
# Integer Multiply (Unpredicated)
## integer multiply vectors (unpredicated)
MUL A64_V 00000100 size:2 1 zm:5 0110 00 zn:5 zd:5
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [RISU PATCH v2 18/22] sve2.risu: Add patterns for permute vector ops
2020-05-21 19:24 [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions Stephen Long
` (16 preceding siblings ...)
2020-05-21 19:25 ` [RISU PATCH v2 17/22] sve2.risu: Add patterns for multiply (indexed) ops Stephen Long
@ 2020-05-21 19:25 ` Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 19/22] sve2.risu: Add patterns for integer compare ops Stephen Long
` (3 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Stephen Long @ 2020-05-21 19:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
sve2.risu | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index 1bcbd93..7f70bfa 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -1,6 +1,12 @@
# Input file for risugen defining AArch64 SVE2 instructions
.mode arm.aarch64
+# Permute Vector (Predicated) Constructive
+SLICE A64_V 00000101 size:2 101101100 pg:3 zn:5 zd:5
+
+# Permute Vector (Extract) Constructive
+EXT A64_V 00000101011 imm8h:5 000 imm8l:3 zn:5 zd:5
+
# Bitwise Logical (Unpredicated)
XAR A64_V 00000100 tszh:2 1 tszl:2 imm3:3 001101 zm:5 zdn:5 \
!constraints { !($tszh == 0 && $tszl == 0); }
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [RISU PATCH v2 19/22] sve2.risu: Add patterns for integer compare ops
2020-05-21 19:24 [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions Stephen Long
` (17 preceding siblings ...)
2020-05-21 19:25 ` [RISU PATCH v2 18/22] sve2.risu: Add patterns for permute vector ops Stephen Long
@ 2020-05-21 19:25 ` Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 20/22] sve2.risu: Add patterns for fp widening multiply-add ops Stephen Long
` (2 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Stephen Long @ 2020-05-21 19:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
sve2.risu | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index 7f70bfa..44f227e 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -470,3 +470,13 @@ FMINP A64_V 01100100 size:2 010 111 100 pg:3 zm:5 zdn:5 \
# Table Lookup
TBL A64_V 00000101 size:2 1 zm:5 00101 0 zn:5 zd:5
TBX A64_V 00000101 size:2 1 zm:5 00101 1 zn:5 zd:5
+
+# Integer Compare (Scalars)
+## integer compare scalar count and limit
+WHILEGE A64_V 00100101 size:2 1 rm:5 000 sf:1 00 rn:5 0 pd:4
+WHILEGT A64_V 00100101 size:2 1 rm:5 000 sf:1 00 rn:5 1 pd:4
+WHILEHI A64_V 00100101 size:2 1 rm:5 000 sf:1 10 rn:5 1 pd:4
+WHILEHS A64_V 00100101 size:2 1 rm:5 000 sf:1 10 rn:5 0 pd:4
+## pointer conflict compare
+WHILEWR A64_V 00100101 size:2 1 rm:5 001100 rn:5 0 pd:4
+WHILERW A64_V 00100101 size:2 1 rm:5 001100 rn:5 1 pd:4
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [RISU PATCH v2 20/22] sve2.risu: Add patterns for fp widening multiply-add ops
2020-05-21 19:24 [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions Stephen Long
` (18 preceding siblings ...)
2020-05-21 19:25 ` [RISU PATCH v2 19/22] sve2.risu: Add patterns for integer compare ops Stephen Long
@ 2020-05-21 19:25 ` Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 21/22] sve2.risu: Add patterns for gather load insns Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 22/22] sve2.risu: Add patterns for scatter store insns Stephen Long
21 siblings, 0 replies; 23+ messages in thread
From: Stephen Long @ 2020-05-21 19:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
sve2.risu | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index 44f227e..d0ad7c9 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -480,3 +480,17 @@ WHILEHS A64_V 00100101 size:2 1 rm:5 000 sf:1 10 rn:5 0 pd:4
## pointer conflict compare
WHILEWR A64_V 00100101 size:2 1 rm:5 001100 rn:5 0 pd:4
WHILERW A64_V 00100101 size:2 1 rm:5 001100 rn:5 1 pd:4
+
+# Floating Point Widening Multiply-Add (Indexed)
+## floating-point multiply-add long (indexed)
+FMLALB_idx A64_V 011001001 01 i3h:2 zm:3 0100 i3l:1 0 zn:5 zda:5
+FMLALT_idx A64_V 011001001 01 i3h:2 zm:3 0100 i3l:1 1 zn:5 zda:5
+FMLSLB_idx A64_V 011001001 01 i3h:2 zm:3 0110 i3l:1 0 zn:5 zda:5
+FMLSLT_idx A64_V 011001001 01 i3h:2 zm:3 0110 i3l:1 1 zn:5 zda:5
+
+# Floating Point Widening Multiply-Add
+## floating-point multiply-add long
+FMLALB_vec A64_V 011001001 01 zm:5 100 000 zn:5 zda:5
+FMLALT_vec A64_V 011001001 01 zm:5 100 001 zn:5 zda:5
+FMLSLB_vec A64_V 011001001 01 zm:5 101 000 zn:5 zda:5
+FMLSLT_vec A64_V 011001001 01 zm:5 101 001 zn:5 zda:5
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [RISU PATCH v2 21/22] sve2.risu: Add patterns for gather load insns
2020-05-21 19:24 [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions Stephen Long
` (19 preceding siblings ...)
2020-05-21 19:25 ` [RISU PATCH v2 20/22] sve2.risu: Add patterns for fp widening multiply-add ops Stephen Long
@ 2020-05-21 19:25 ` Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 22/22] sve2.risu: Add patterns for scatter store insns Stephen Long
21 siblings, 0 replies; 23+ messages in thread
From: Stephen Long @ 2020-05-21 19:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
sve2.risu | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index d0ad7c9..84ae527 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -494,3 +494,23 @@ FMLALB_vec A64_V 011001001 01 zm:5 100 000 zn:5 zda:5
FMLALT_vec A64_V 011001001 01 zm:5 100 001 zn:5 zda:5
FMLSLB_vec A64_V 011001001 01 zm:5 101 000 zn:5 zda:5
FMLSLT_vec A64_V 011001001 01 zm:5 101 001 zn:5 zda:5
+
+# 32-Bit Gather
+## 32-bit gather non-temporal load (scalar plus 32-bit unscaled offsets)
+LDNT1SB_32 A64_V 1000010 00 00 rm:5 100 pg:3 zn:5 zt:5
+LDNT1B_32 A64_V 1000010 00 00 rm:5 101 pg:3 zn:5 zt:5
+LDNT1SH_32 A64_V 1000010 01 00 rm:5 100 pg:3 zn:5 zt:5
+LDNT1H_32 A64_V 1000010 01 00 rm:5 101 pg:3 zn:5 zt:5
+LDNT1W_32 A64_V 1000010 10 00 rm:5 101 pg:3 zn:5 zt:5
+
+# 64-Bit Gather
+## 64-bit gather non-temporal load
+## (scalar plus unpacked 32-bit unscaled offsets)
+LDNT1SB_64 A64_V 1100010 00 00 rm:5 100 pg:3 zn:5 zt:5
+LDNT1B_64 A64_V 1100010 00 00 rm:5 110 pg:3 zn:5 zt:5
+LDNT1SH_64 A64_V 1100010 01 00 rm:5 100 pg:3 zn:5 zt:5
+LDNT1H_64 A64_V 1100010 01 00 rm:5 110 pg:3 zn:5 zt:5
+LDNT1SW_64 A64_V 1100010 10 00 rm:5 100 pg:3 zn:5 zt:5
+LDNT1W_64 A64_V 1100010 10 00 rm:5 110 pg:3 zn:5 zt:5
+LDNT1D_64 A64_V 1100010 11 00 rm:5 110 pg:3 zn:5 zt:5
+
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [RISU PATCH v2 22/22] sve2.risu: Add patterns for scatter store insns
2020-05-21 19:24 [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions Stephen Long
` (20 preceding siblings ...)
2020-05-21 19:25 ` [RISU PATCH v2 21/22] sve2.risu: Add patterns for gather load insns Stephen Long
@ 2020-05-21 19:25 ` Stephen Long
21 siblings, 0 replies; 23+ messages in thread
From: Stephen Long @ 2020-05-21 19:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
sve2.risu | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index 84ae527..00ac186 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -514,3 +514,11 @@ LDNT1SW_64 A64_V 1100010 10 00 rm:5 100 pg:3 zn:5 zt:5
LDNT1W_64 A64_V 1100010 10 00 rm:5 110 pg:3 zn:5 zt:5
LDNT1D_64 A64_V 1100010 11 00 rm:5 110 pg:3 zn:5 zt:5
+# 32-Bit Scatter
+## 32-bit scatter non-temporal store (vector, scalar)
+STNT1_32 A64_V 1110010 msz:2 10 rm:5 001 pg:3 zn:5 zt:5 \
+!constraints { $msz != 3; }
+
+# 64-Bit Scatter
+## 64-bit scatter non-temporal store (vector, scalar)
+STNT1_64 A64_V 1110010 msz:2 00 rm:5 001 pg:3 zn:5 zt:5
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
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2020-05-21 19:24 [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions Stephen Long
2020-05-21 19:24 ` [RISU PATCH v2 01/22] sve2.risu: Add patterns for floating-point pairwise ops Stephen Long
2020-05-21 19:24 ` [RISU PATCH v2 02/22] sve2.risu: Add patterns for integer multiply (unpredicated) ops Stephen Long
2020-05-21 19:24 ` [RISU PATCH v2 03/22] sve2.risu: Add patterns for integer (predicated) ops Stephen Long
2020-05-21 19:24 ` [RISU PATCH v2 04/22] sve2.risu: Add patterns for widening integer arithmetic ops Stephen Long
2020-05-21 19:24 ` [RISU PATCH v2 05/22] sve2.risu: Add patterns for misc ops Stephen Long
2020-05-21 19:24 ` [RISU PATCH v2 06/22] sve2.risu: Add patterns for accumulate ops Stephen Long
2020-05-21 19:24 ` [RISU PATCH v2 07/22] sve2.risu: Add patterns for narrowing ops Stephen Long
2020-05-21 19:24 ` [RISU PATCH v2 08/22] sve2.risu: Add patterns for character match insns Stephen Long
2020-05-21 19:24 ` [RISU PATCH v2 09/22] sve2.risu: Add patterns for histogram computation ops Stephen Long
2020-05-21 19:24 ` [RISU PATCH v2 10/22] sve2.risu: Add patterns for crypto operations Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 11/22] sve2.risu: Add patterns for bitwise shift (unpredicated) ops Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 12/22] sve2.risu: Add patterns for fp convert precision odd elems insns Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 13/22] sve2.risu: Add patterns for bitwise logical (unpredicated) ops Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 14/22] sve2.risu: Add patterns for fp unary ops (predicated) Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 15/22] sve2.risu: Add patterns for table lookup insns Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 16/22] sve2.risu: Add patterns for integer multiply-add (unpredicated) ops Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 17/22] sve2.risu: Add patterns for multiply (indexed) ops Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 18/22] sve2.risu: Add patterns for permute vector ops Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 19/22] sve2.risu: Add patterns for integer compare ops Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 20/22] sve2.risu: Add patterns for fp widening multiply-add ops Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 21/22] sve2.risu: Add patterns for gather load insns Stephen Long
2020-05-21 19:25 ` [RISU PATCH v2 22/22] sve2.risu: Add patterns for scatter store insns Stephen Long
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