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* [PATCH net] net: dsa: felix: send VLANs on CPU port as egress-tagged
@ 2020-05-27 16:48 Vladimir Oltean
  2020-05-27 16:50 ` Florian Fainelli
  2020-05-27 18:41 ` David Miller
  0 siblings, 2 replies; 3+ messages in thread
From: Vladimir Oltean @ 2020-05-27 16:48 UTC (permalink / raw)
  To: davem; +Cc: andrew, f.fainelli, vivien.didelot, netdev

From: Vladimir Oltean <vladimir.oltean@nxp.com>

As explained in other commits before (b9cd75e66895 and 87b0f983f66f),
ocelot switches have a single egress-untagged VLAN per port, and the
driver would deny adding a second one while an egress-untagged VLAN
already exists.

But on the CPU port (where the VLAN configuration is implicit, because
there is no net device for the bridge to control), the DSA core attempts
to add a VLAN using the same flags as were used for the front-panel
port. This would make adding any untagged VLAN fail due to the CPU port
rejecting the configuration:

bridge vlan add dev swp0 vid 100 pvid untagged
[ 1865.854253] mscc_felix 0000:00:00.5: Port already has a native VLAN: 1
[ 1865.860824] mscc_felix 0000:00:00.5: Failed to add VLAN 100 to port 5: -16

(note that port 5 is the CPU port and not the front-panel swp0).

So this hardware will send all VLANs as tagged towards the CPU.

Fixes: 56051948773e ("net: dsa: ocelot: add driver for Felix switch family")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 drivers/net/dsa/ocelot/felix.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/net/dsa/ocelot/felix.c b/drivers/net/dsa/ocelot/felix.c
index a6e272d2110d..66648986e6e3 100644
--- a/drivers/net/dsa/ocelot/felix.c
+++ b/drivers/net/dsa/ocelot/felix.c
@@ -103,13 +103,17 @@ static void felix_vlan_add(struct dsa_switch *ds, int port,
 			   const struct switchdev_obj_port_vlan *vlan)
 {
 	struct ocelot *ocelot = ds->priv;
+	u16 flags = vlan->flags;
 	u16 vid;
 	int err;
 
+	if (dsa_is_cpu_port(ds, port))
+		flags &= ~BRIDGE_VLAN_INFO_UNTAGGED;
+
 	for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
 		err = ocelot_vlan_add(ocelot, port, vid,
-				      vlan->flags & BRIDGE_VLAN_INFO_PVID,
-				      vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED);
+				      flags & BRIDGE_VLAN_INFO_PVID,
+				      flags & BRIDGE_VLAN_INFO_UNTAGGED);
 		if (err) {
 			dev_err(ds->dev, "Failed to add VLAN %d to port %d: %d\n",
 				vid, port, err);
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 3+ messages in thread

* Re: [PATCH net] net: dsa: felix: send VLANs on CPU port as egress-tagged
  2020-05-27 16:48 [PATCH net] net: dsa: felix: send VLANs on CPU port as egress-tagged Vladimir Oltean
@ 2020-05-27 16:50 ` Florian Fainelli
  2020-05-27 18:41 ` David Miller
  1 sibling, 0 replies; 3+ messages in thread
From: Florian Fainelli @ 2020-05-27 16:50 UTC (permalink / raw)
  To: Vladimir Oltean, davem; +Cc: andrew, vivien.didelot, netdev



On 5/27/2020 9:48 AM, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> As explained in other commits before (b9cd75e66895 and 87b0f983f66f),
> ocelot switches have a single egress-untagged VLAN per port, and the
> driver would deny adding a second one while an egress-untagged VLAN
> already exists.
> 
> But on the CPU port (where the VLAN configuration is implicit, because
> there is no net device for the bridge to control), the DSA core attempts
> to add a VLAN using the same flags as were used for the front-panel
> port. This would make adding any untagged VLAN fail due to the CPU port
> rejecting the configuration:
> 
> bridge vlan add dev swp0 vid 100 pvid untagged
> [ 1865.854253] mscc_felix 0000:00:00.5: Port already has a native VLAN: 1
> [ 1865.860824] mscc_felix 0000:00:00.5: Failed to add VLAN 100 to port 5: -16
> 
> (note that port 5 is the CPU port and not the front-panel swp0).
> 
> So this hardware will send all VLANs as tagged towards the CPU.
> 
> Fixes: 56051948773e ("net: dsa: ocelot: add driver for Felix switch family")
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH net] net: dsa: felix: send VLANs on CPU port as egress-tagged
  2020-05-27 16:48 [PATCH net] net: dsa: felix: send VLANs on CPU port as egress-tagged Vladimir Oltean
  2020-05-27 16:50 ` Florian Fainelli
@ 2020-05-27 18:41 ` David Miller
  1 sibling, 0 replies; 3+ messages in thread
From: David Miller @ 2020-05-27 18:41 UTC (permalink / raw)
  To: olteanv; +Cc: andrew, f.fainelli, vivien.didelot, netdev

From: Vladimir Oltean <olteanv@gmail.com>
Date: Wed, 27 May 2020 19:48:03 +0300

> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> As explained in other commits before (b9cd75e66895 and 87b0f983f66f),
> ocelot switches have a single egress-untagged VLAN per port, and the
> driver would deny adding a second one while an egress-untagged VLAN
> already exists.
> 
> But on the CPU port (where the VLAN configuration is implicit, because
> there is no net device for the bridge to control), the DSA core attempts
> to add a VLAN using the same flags as were used for the front-panel
> port. This would make adding any untagged VLAN fail due to the CPU port
> rejecting the configuration:
> 
> bridge vlan add dev swp0 vid 100 pvid untagged
> [ 1865.854253] mscc_felix 0000:00:00.5: Port already has a native VLAN: 1
> [ 1865.860824] mscc_felix 0000:00:00.5: Failed to add VLAN 100 to port 5: -16
> 
> (note that port 5 is the CPU port and not the front-panel swp0).
> 
> So this hardware will send all VLANs as tagged towards the CPU.
> 
> Fixes: 56051948773e ("net: dsa: ocelot: add driver for Felix switch family")
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Applied and queued up for -stable, thanks.

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2020-05-27 18:48 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-27 16:48 [PATCH net] net: dsa: felix: send VLANs on CPU port as egress-tagged Vladimir Oltean
2020-05-27 16:50 ` Florian Fainelli
2020-05-27 18:41 ` David Miller

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