Re: [PATCH v3 09/10] dmaengine: dw: Introduce max burst length hw config

From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Serge Semin <fancer.lancer@gmail.com>,
	Vinod Koul <vkoul@kernel.org>, Viresh Kumar <vireshk@kernel.org>,
	Dan Williams <dan.j.williams@intel.com>,
	Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
	Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	Arnd Bergmann <arnd@arndb.de>, Rob Herring <robh+dt@kernel.org>,
	<linux-mips@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<dmaengine@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 09/10] dmaengine: dw: Introduce max burst length hw config
Date: Thu, 28 May 2020 22:53:38 +0300	[thread overview]
Message-ID: <20200528195338.yzl35nhogmyikv43@mobilestation> (raw)
In-Reply-To: <20200528154022.3reghhjcd4dnsr3g@mobilestation>

On Thu, May 28, 2020 at 06:40:22PM +0300, Serge Semin wrote:
> On Thu, May 28, 2020 at 05:52:24PM +0300, Andy Shevchenko wrote:
> > On Wed, May 27, 2020 at 01:50:20AM +0300, Serge Semin wrote:
> > > IP core of the DW DMA controller may be synthesized with different
> > > max burst length of the transfers per each channel. According to Synopsis
> > > having the fixed maximum burst transactions length may provide some
> > > performance gain. At the same time setting up the source and destination
> > > multi size exceeding the max burst length limitation may cause a serious
> > > problems. In our case the DMA transaction just hangs up. In order to fix
> > > this lets introduce the max burst length platform config of the DW DMA
> > > controller device and don't let the DMA channels configuration code
> > > exceed the burst length hardware limitation.
> > > 
> > > Note the maximum burst length parameter can be detected either in runtime
> > > from the DWC parameter registers or from the dedicated DT property.
> > > Depending on the IP core configuration the maximum value can vary from
> > > channel to channel so by overriding the channel slave max_burst capability
> > > we make sure a DMA consumer will get the channel-specific max burst
> > > length.
> > 
> > ...
> > 
> > >  static void dwc_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
> > >  {
> > > +	struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
> > >  
> > 
> 
> > Perhaps,
> > 
> > 	/* DesignWare DMA supports burst value from 0 */
> > 	caps->min_burst = 0;
> 
> Regarding min_burst being zero. I don't fully understand what it means.
> It means no burst or burst with minimum length or what?
> In fact DW DMA burst length starts from 1. Remember the burst-length run-time
> parameter we were arguing about? Anyway the driver makes sure that both
> 0 and 1 requested burst length are setup as burst length of 1 in the
> CTLx.SRC_MSIZE, CTLx.DST_MSIZE fields.
> 
> I agree with the rest of your comments below.
> 
> -Sergey
> 
> > 

It would be also better to initialize the dw->dma.min_burst field instead
of setting caps->min_burst in the dwc_caps callback, since the min burst length
can't vary from channel to channel and it will be copied to the caps->min_burst
field anyway in the dma_get_slave_caps() method.

-Sergey