* [Intel-gfx] [PATCH i-g-t v3] i915/gem_exec_balancer: Randomise bonded submission @ 2020-05-29 13:58 ` Chris Wilson 0 siblings, 0 replies; 8+ messages in thread From: Chris Wilson @ 2020-05-29 13:58 UTC (permalink / raw) To: intel-gfx; +Cc: igt-dev, Chris Wilson Randomly submit a paired spinner and its cancellation as a bonded (submit fence) pair. Apply congestion to the engine with more bonded pairs to see if the execution order fails. If we prevent a cancellation from running, then the spinner will remain spinning forever. v2: Test both immediate submission and fenced submission v3: Copy-n-paste a single context variant Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- tests/i915/gem_exec_balancer.c | 341 +++++++++++++++++++++++++++++++++ 1 file changed, 341 insertions(+) diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c index 80ae82416..07fe45920 100644 --- a/tests/i915/gem_exec_balancer.c +++ b/tests/i915/gem_exec_balancer.c @@ -1154,6 +1154,342 @@ static void bonded_semaphore(int i915) gem_context_destroy(i915, ctx); } +static void __bonded_pair(int i915, + const struct i915_engine_class_instance *siblings, + unsigned int count, + unsigned int flags, + unsigned long *out) +#define B_FENCE 0x1 +#define B_HOSTILE 0x2 +#define B_MANY 0x4 +{ + struct drm_i915_gem_exec_object2 batch = {}; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&batch), + .buffer_count = 1, + }; + unsigned long cycles = 0; + unsigned int spinner; + igt_spin_t *a; + int timeline; + uint32_t A; + + srandom(getpid()); + + spinner = IGT_SPIN_POLL_RUN; + if (flags & B_HOSTILE) + spinner |= IGT_SPIN_NO_PREEMPTION; + + A = gem_context_create(i915); + set_load_balancer(i915, A, siblings, count, NULL); + a = igt_spin_new(i915, A, .flags = spinner); + igt_spin_end(a); + gem_sync(i915, a->handle); + + timeline = sw_sync_timeline_create(); + + igt_until_timeout(2) { + unsigned int master; + int fence; + + master = 1; + if (flags & B_MANY) + master = rand() % count + 1; + + fence = -1; + if (flags & B_FENCE) + fence = sw_sync_timeline_create_fence(timeline, + cycles + 1); + + igt_spin_reset(a); + a->execbuf.flags = master | I915_EXEC_FENCE_OUT; + if (fence != -1) { + a->execbuf.rsvd2 = fence; + a->execbuf.flags |= I915_EXEC_FENCE_IN; + } + gem_execbuf_wr(i915, &a->execbuf); + + batch.handle = create_semaphore_to_spinner(i915, a); + execbuf.rsvd1 = a->execbuf.rsvd1; + execbuf.rsvd2 = a->execbuf.rsvd2 >> 32; + do { + execbuf.flags = rand() % count + 1; + } while (execbuf.flags == master); + execbuf.flags |= I915_EXEC_FENCE_SUBMIT; + gem_execbuf(i915, &execbuf); + gem_close(i915, batch.handle); + + if (fence != -1) { + sw_sync_timeline_inc(timeline, 1); + close(fence); + } + close(a->execbuf.rsvd2 >> 32); + + gem_sync(i915, a->handle); + + cycles++; + } + + close(timeline); + igt_spin_free(i915, a); + gem_context_destroy(i915, A); + + *out = cycles; +} + +static void bonded_pair(int i915) +{ + static const unsigned int phases[] = { + 0, + B_FENCE, + B_MANY, + B_HOSTILE, + B_HOSTILE | B_FENCE, + }; + unsigned long *cycles; + + /* + * The purpose of bonded submission is to execute one or more requests + * concurrently. However, the very nature of that requires coordinated + * submission across multiple engines. + */ + igt_require(gem_scheduler_has_preemption(i915)); + + cycles = mmap(0, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); + + for (int class = 0; class < 32; class++) { + struct i915_engine_class_instance *siblings; + unsigned int count; + + siblings = list_engines(i915, 1u << class, &count); + if (count < 2) + continue; + + igt_info("Class %u, 1 thread\n", class); + for (int i = 0; i < ARRAY_SIZE(phases); i++) { + cycles[0] = 0; + __bonded_pair(i915, + siblings, count, + phases[i], + &cycles[0]); + gem_quiescent_gpu(i915); + igt_info("%s %s %s submission, %lu cycles\n", + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", + phases[i] & B_MANY ? "many-master" : "single-master", + phases[i] & B_FENCE ? "fenced" : "immediate", + cycles[0]); + } + + igt_info("Class %u, %d threads\n", class, count + 1); + for (int i = 0; i < ARRAY_SIZE(phases); i++) { + memset(cycles, 0, (count + 1) * sizeof(*cycles)); + igt_fork(child, count + 1) + __bonded_pair(i915, + siblings, count, + phases[i], + &cycles[child]); + igt_waitchildren(); + gem_quiescent_gpu(i915); + + for (int child = 1; child < count + 1; child++) + cycles[0] += cycles[child]; + + igt_info("%s %s %s submission, %lu cycles\n", + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", + phases[i] & B_MANY ? "many-master" : "single-master", + phases[i] & B_FENCE ? "fenced" : "immediate", + cycles[0]); + } + free(siblings); + } + + munmap(cycles, 4096); +} + +static void __bonded_dual(int i915, + const struct i915_engine_class_instance *siblings, + unsigned int count, + unsigned int flags, + unsigned long *out) +{ + struct drm_i915_gem_exec_object2 batch = {}; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&batch), + .buffer_count = 1, + }; + unsigned long cycles = 0; + unsigned int spinner; + igt_spin_t *a, *b; + int timeline; + uint32_t A, B; + + srandom(getpid()); + + spinner = IGT_SPIN_POLL_RUN; + if (flags & B_HOSTILE) + spinner |= IGT_SPIN_NO_PREEMPTION; + + A = gem_context_create(i915); + set_load_balancer(i915, A, siblings, count, NULL); + a = igt_spin_new(i915, A, .flags = spinner); + igt_spin_end(a); + gem_sync(i915, a->handle); + + B = gem_context_create(i915); + set_load_balancer(i915, B, siblings, count, NULL); + b = igt_spin_new(i915, B, .flags = spinner); + igt_spin_end(b); + gem_sync(i915, b->handle); + + timeline = sw_sync_timeline_create(); + + igt_until_timeout(2) { + unsigned int master; + int fence; + + master = 1; + if (flags & B_MANY) + master = rand() % count + 1; + + fence = -1; + if (flags & B_FENCE) + fence = sw_sync_timeline_create_fence(timeline, + cycles + 1); + + igt_spin_reset(a); + a->execbuf.flags = master | I915_EXEC_FENCE_OUT; + if (fence != -1) { + a->execbuf.rsvd2 = fence; + a->execbuf.flags |= I915_EXEC_FENCE_IN; + } + gem_execbuf_wr(i915, &a->execbuf); + + igt_spin_reset(b); + b->execbuf.flags = master | I915_EXEC_FENCE_OUT; + if (fence != -1) { + b->execbuf.rsvd2 = fence; + b->execbuf.flags |= I915_EXEC_FENCE_IN; + } + gem_execbuf_wr(i915, &b->execbuf); + + if (rand() % 1) + igt_swap(a, b); + + batch.handle = create_semaphore_to_spinner(i915, a); + execbuf.rsvd1 = a->execbuf.rsvd1; + execbuf.rsvd2 = a->execbuf.rsvd2 >> 32; + do { + execbuf.flags = rand() % count + 1; + } while (execbuf.flags == master); + execbuf.flags |= I915_EXEC_FENCE_SUBMIT; + gem_execbuf(i915, &execbuf); + gem_close(i915, batch.handle); + + batch.handle = create_semaphore_to_spinner(i915, b); + execbuf.rsvd1 = b->execbuf.rsvd1; + execbuf.rsvd2 = b->execbuf.rsvd2 >> 32; + do { + execbuf.flags = rand() % count + 1; + } while (execbuf.flags == master); + execbuf.flags |= I915_EXEC_FENCE_SUBMIT; + gem_execbuf(i915, &execbuf); + gem_close(i915, batch.handle); + + if (fence != -1) { + sw_sync_timeline_inc(timeline, 1); + close(fence); + } + close(a->execbuf.rsvd2 >> 32); + close(b->execbuf.rsvd2 >> 32); + + gem_sync(i915, a->handle); + gem_sync(i915, b->handle); + + cycles++; + } + + close(timeline); + + igt_spin_free(i915, a); + igt_spin_free(i915, b); + + gem_context_destroy(i915, A); + gem_context_destroy(i915, B); + + *out = cycles; +} + +static void bonded_dual(int i915) +{ + static const unsigned int phases[] = { + 0, + B_FENCE, + B_MANY, + B_HOSTILE, + B_HOSTILE | B_FENCE, + }; + unsigned long *cycles; + + + /* + * This is the same test as bonded_pair() but with the slight extra + * stress of having two inflight clients and interchanging them + * in a thread. + */ + igt_require(gem_scheduler_has_preemption(i915)); + + cycles = mmap(0, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); + + for (int class = 0; class < 32; class++) { + struct i915_engine_class_instance *siblings; + unsigned int count; + + siblings = list_engines(i915, 1u << class, &count); + if (count < 2) + continue; + + igt_info("Class %u, 1 thread\n", class); + for (int i = 0; i < ARRAY_SIZE(phases); i++) { + cycles[0] = 0; + __bonded_dual(i915, + siblings, count, + phases[i], + &cycles[0]); + gem_quiescent_gpu(i915); + igt_info("%s %s %s submission, %lu cycles\n", + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", + phases[i] & B_MANY ? "many-master" : "single-master", + phases[i] & B_FENCE ? "fenced" : "immediate", + cycles[0]); + } + + igt_info("Class %u, %d threads\n", class, count + 1); + for (int i = 0; i < ARRAY_SIZE(phases); i++) { + memset(cycles, 0, (count + 1) * sizeof(*cycles)); + igt_fork(child, count + 1) + __bonded_dual(i915, + siblings, count, + phases[i], + &cycles[child]); + igt_waitchildren(); + gem_quiescent_gpu(i915); + + for (int child = 1; child < count + 1; child++) + cycles[0] += cycles[child]; + + igt_info("%s %s %s submission, %lu cycles\n", + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", + phases[i] & B_MANY ? "many-master" : "single-master", + phases[i] & B_FENCE ? "fenced" : "immediate", + cycles[0]); + } + + free(siblings); + } + + munmap(cycles, 4096); +} + static void __bonded_nohang(int i915, uint32_t ctx, const struct i915_engine_class_instance *siblings, unsigned int count, @@ -2284,6 +2620,11 @@ igt_main igt_subtest("bonded-semaphore") bonded_semaphore(i915); + igt_subtest("bonded-pair") + bonded_pair(i915); + igt_subtest("bonded-dual") + bonded_dual(i915); + igt_fixture { igt_stop_hang_detector(); } -- 2.27.0.rc2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [igt-dev] [PATCH i-g-t v3] i915/gem_exec_balancer: Randomise bonded submission @ 2020-05-29 13:58 ` Chris Wilson 0 siblings, 0 replies; 8+ messages in thread From: Chris Wilson @ 2020-05-29 13:58 UTC (permalink / raw) To: intel-gfx; +Cc: igt-dev, Tvrtko Ursulin, Chris Wilson Randomly submit a paired spinner and its cancellation as a bonded (submit fence) pair. Apply congestion to the engine with more bonded pairs to see if the execution order fails. If we prevent a cancellation from running, then the spinner will remain spinning forever. v2: Test both immediate submission and fenced submission v3: Copy-n-paste a single context variant Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- tests/i915/gem_exec_balancer.c | 341 +++++++++++++++++++++++++++++++++ 1 file changed, 341 insertions(+) diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c index 80ae82416..07fe45920 100644 --- a/tests/i915/gem_exec_balancer.c +++ b/tests/i915/gem_exec_balancer.c @@ -1154,6 +1154,342 @@ static void bonded_semaphore(int i915) gem_context_destroy(i915, ctx); } +static void __bonded_pair(int i915, + const struct i915_engine_class_instance *siblings, + unsigned int count, + unsigned int flags, + unsigned long *out) +#define B_FENCE 0x1 +#define B_HOSTILE 0x2 +#define B_MANY 0x4 +{ + struct drm_i915_gem_exec_object2 batch = {}; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&batch), + .buffer_count = 1, + }; + unsigned long cycles = 0; + unsigned int spinner; + igt_spin_t *a; + int timeline; + uint32_t A; + + srandom(getpid()); + + spinner = IGT_SPIN_POLL_RUN; + if (flags & B_HOSTILE) + spinner |= IGT_SPIN_NO_PREEMPTION; + + A = gem_context_create(i915); + set_load_balancer(i915, A, siblings, count, NULL); + a = igt_spin_new(i915, A, .flags = spinner); + igt_spin_end(a); + gem_sync(i915, a->handle); + + timeline = sw_sync_timeline_create(); + + igt_until_timeout(2) { + unsigned int master; + int fence; + + master = 1; + if (flags & B_MANY) + master = rand() % count + 1; + + fence = -1; + if (flags & B_FENCE) + fence = sw_sync_timeline_create_fence(timeline, + cycles + 1); + + igt_spin_reset(a); + a->execbuf.flags = master | I915_EXEC_FENCE_OUT; + if (fence != -1) { + a->execbuf.rsvd2 = fence; + a->execbuf.flags |= I915_EXEC_FENCE_IN; + } + gem_execbuf_wr(i915, &a->execbuf); + + batch.handle = create_semaphore_to_spinner(i915, a); + execbuf.rsvd1 = a->execbuf.rsvd1; + execbuf.rsvd2 = a->execbuf.rsvd2 >> 32; + do { + execbuf.flags = rand() % count + 1; + } while (execbuf.flags == master); + execbuf.flags |= I915_EXEC_FENCE_SUBMIT; + gem_execbuf(i915, &execbuf); + gem_close(i915, batch.handle); + + if (fence != -1) { + sw_sync_timeline_inc(timeline, 1); + close(fence); + } + close(a->execbuf.rsvd2 >> 32); + + gem_sync(i915, a->handle); + + cycles++; + } + + close(timeline); + igt_spin_free(i915, a); + gem_context_destroy(i915, A); + + *out = cycles; +} + +static void bonded_pair(int i915) +{ + static const unsigned int phases[] = { + 0, + B_FENCE, + B_MANY, + B_HOSTILE, + B_HOSTILE | B_FENCE, + }; + unsigned long *cycles; + + /* + * The purpose of bonded submission is to execute one or more requests + * concurrently. However, the very nature of that requires coordinated + * submission across multiple engines. + */ + igt_require(gem_scheduler_has_preemption(i915)); + + cycles = mmap(0, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); + + for (int class = 0; class < 32; class++) { + struct i915_engine_class_instance *siblings; + unsigned int count; + + siblings = list_engines(i915, 1u << class, &count); + if (count < 2) + continue; + + igt_info("Class %u, 1 thread\n", class); + for (int i = 0; i < ARRAY_SIZE(phases); i++) { + cycles[0] = 0; + __bonded_pair(i915, + siblings, count, + phases[i], + &cycles[0]); + gem_quiescent_gpu(i915); + igt_info("%s %s %s submission, %lu cycles\n", + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", + phases[i] & B_MANY ? "many-master" : "single-master", + phases[i] & B_FENCE ? "fenced" : "immediate", + cycles[0]); + } + + igt_info("Class %u, %d threads\n", class, count + 1); + for (int i = 0; i < ARRAY_SIZE(phases); i++) { + memset(cycles, 0, (count + 1) * sizeof(*cycles)); + igt_fork(child, count + 1) + __bonded_pair(i915, + siblings, count, + phases[i], + &cycles[child]); + igt_waitchildren(); + gem_quiescent_gpu(i915); + + for (int child = 1; child < count + 1; child++) + cycles[0] += cycles[child]; + + igt_info("%s %s %s submission, %lu cycles\n", + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", + phases[i] & B_MANY ? "many-master" : "single-master", + phases[i] & B_FENCE ? "fenced" : "immediate", + cycles[0]); + } + free(siblings); + } + + munmap(cycles, 4096); +} + +static void __bonded_dual(int i915, + const struct i915_engine_class_instance *siblings, + unsigned int count, + unsigned int flags, + unsigned long *out) +{ + struct drm_i915_gem_exec_object2 batch = {}; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&batch), + .buffer_count = 1, + }; + unsigned long cycles = 0; + unsigned int spinner; + igt_spin_t *a, *b; + int timeline; + uint32_t A, B; + + srandom(getpid()); + + spinner = IGT_SPIN_POLL_RUN; + if (flags & B_HOSTILE) + spinner |= IGT_SPIN_NO_PREEMPTION; + + A = gem_context_create(i915); + set_load_balancer(i915, A, siblings, count, NULL); + a = igt_spin_new(i915, A, .flags = spinner); + igt_spin_end(a); + gem_sync(i915, a->handle); + + B = gem_context_create(i915); + set_load_balancer(i915, B, siblings, count, NULL); + b = igt_spin_new(i915, B, .flags = spinner); + igt_spin_end(b); + gem_sync(i915, b->handle); + + timeline = sw_sync_timeline_create(); + + igt_until_timeout(2) { + unsigned int master; + int fence; + + master = 1; + if (flags & B_MANY) + master = rand() % count + 1; + + fence = -1; + if (flags & B_FENCE) + fence = sw_sync_timeline_create_fence(timeline, + cycles + 1); + + igt_spin_reset(a); + a->execbuf.flags = master | I915_EXEC_FENCE_OUT; + if (fence != -1) { + a->execbuf.rsvd2 = fence; + a->execbuf.flags |= I915_EXEC_FENCE_IN; + } + gem_execbuf_wr(i915, &a->execbuf); + + igt_spin_reset(b); + b->execbuf.flags = master | I915_EXEC_FENCE_OUT; + if (fence != -1) { + b->execbuf.rsvd2 = fence; + b->execbuf.flags |= I915_EXEC_FENCE_IN; + } + gem_execbuf_wr(i915, &b->execbuf); + + if (rand() % 1) + igt_swap(a, b); + + batch.handle = create_semaphore_to_spinner(i915, a); + execbuf.rsvd1 = a->execbuf.rsvd1; + execbuf.rsvd2 = a->execbuf.rsvd2 >> 32; + do { + execbuf.flags = rand() % count + 1; + } while (execbuf.flags == master); + execbuf.flags |= I915_EXEC_FENCE_SUBMIT; + gem_execbuf(i915, &execbuf); + gem_close(i915, batch.handle); + + batch.handle = create_semaphore_to_spinner(i915, b); + execbuf.rsvd1 = b->execbuf.rsvd1; + execbuf.rsvd2 = b->execbuf.rsvd2 >> 32; + do { + execbuf.flags = rand() % count + 1; + } while (execbuf.flags == master); + execbuf.flags |= I915_EXEC_FENCE_SUBMIT; + gem_execbuf(i915, &execbuf); + gem_close(i915, batch.handle); + + if (fence != -1) { + sw_sync_timeline_inc(timeline, 1); + close(fence); + } + close(a->execbuf.rsvd2 >> 32); + close(b->execbuf.rsvd2 >> 32); + + gem_sync(i915, a->handle); + gem_sync(i915, b->handle); + + cycles++; + } + + close(timeline); + + igt_spin_free(i915, a); + igt_spin_free(i915, b); + + gem_context_destroy(i915, A); + gem_context_destroy(i915, B); + + *out = cycles; +} + +static void bonded_dual(int i915) +{ + static const unsigned int phases[] = { + 0, + B_FENCE, + B_MANY, + B_HOSTILE, + B_HOSTILE | B_FENCE, + }; + unsigned long *cycles; + + + /* + * This is the same test as bonded_pair() but with the slight extra + * stress of having two inflight clients and interchanging them + * in a thread. + */ + igt_require(gem_scheduler_has_preemption(i915)); + + cycles = mmap(0, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); + + for (int class = 0; class < 32; class++) { + struct i915_engine_class_instance *siblings; + unsigned int count; + + siblings = list_engines(i915, 1u << class, &count); + if (count < 2) + continue; + + igt_info("Class %u, 1 thread\n", class); + for (int i = 0; i < ARRAY_SIZE(phases); i++) { + cycles[0] = 0; + __bonded_dual(i915, + siblings, count, + phases[i], + &cycles[0]); + gem_quiescent_gpu(i915); + igt_info("%s %s %s submission, %lu cycles\n", + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", + phases[i] & B_MANY ? "many-master" : "single-master", + phases[i] & B_FENCE ? "fenced" : "immediate", + cycles[0]); + } + + igt_info("Class %u, %d threads\n", class, count + 1); + for (int i = 0; i < ARRAY_SIZE(phases); i++) { + memset(cycles, 0, (count + 1) * sizeof(*cycles)); + igt_fork(child, count + 1) + __bonded_dual(i915, + siblings, count, + phases[i], + &cycles[child]); + igt_waitchildren(); + gem_quiescent_gpu(i915); + + for (int child = 1; child < count + 1; child++) + cycles[0] += cycles[child]; + + igt_info("%s %s %s submission, %lu cycles\n", + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", + phases[i] & B_MANY ? "many-master" : "single-master", + phases[i] & B_FENCE ? "fenced" : "immediate", + cycles[0]); + } + + free(siblings); + } + + munmap(cycles, 4096); +} + static void __bonded_nohang(int i915, uint32_t ctx, const struct i915_engine_class_instance *siblings, unsigned int count, @@ -2284,6 +2620,11 @@ igt_main igt_subtest("bonded-semaphore") bonded_semaphore(i915); + igt_subtest("bonded-pair") + bonded_pair(i915); + igt_subtest("bonded-dual") + bonded_dual(i915); + igt_fixture { igt_stop_hang_detector(); } -- 2.27.0.rc2 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for i915/gem_exec_balancer: Randomise bonded submission (rev3) 2020-05-29 13:58 ` [igt-dev] " Chris Wilson (?) @ 2020-05-29 14:34 ` Patchwork -1 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2020-05-29 14:34 UTC (permalink / raw) To: Chris Wilson; +Cc: igt-dev == Series Details == Series: i915/gem_exec_balancer: Randomise bonded submission (rev3) URL : https://patchwork.freedesktop.org/series/77701/ State : success == Summary == CI Bug Log - changes from CI_DRM_8553 -> IGTPW_4624 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/index.html Known issues ------------ Here are the changes found in IGTPW_4624 that come from known issues: ### IGT changes ### #### Warnings #### * igt@i915_pm_rpm@module-reload: - fi-glk-dsi: [TIMEOUT][1] ([i915#1288]) -> [TIMEOUT][2] ([i915#1288] / [i915#1958]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/fi-glk-dsi/igt@i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/fi-glk-dsi/igt@i915_pm_rpm@module-reload.html [i915#1288]: https://gitlab.freedesktop.org/drm/intel/issues/1288 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 Participating hosts (51 -> 44) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5683 -> IGTPW_4624 CI-20190529: 20190529 CI_DRM_8553: 9f1b8b4fcb466dc714b1f825fd93e3bbd29c7de6 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_4624: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/index.html IGT_5683: 757b6e72d546fd2dbc3801a73796d67b0854021b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Testlist changes == +igt@gem_exec_balancer@bonded-dual +igt@gem_exec_balancer@bonded-pair == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/index.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [igt-dev] [PATCH i-g-t v3] i915/gem_exec_balancer: Randomise bonded submission 2020-05-29 13:58 ` [igt-dev] " Chris Wilson @ 2020-05-29 15:08 ` Tvrtko Ursulin -1 siblings, 0 replies; 8+ messages in thread From: Tvrtko Ursulin @ 2020-05-29 15:08 UTC (permalink / raw) To: Chris Wilson, intel-gfx; +Cc: igt-dev On 29/05/2020 14:58, Chris Wilson wrote: > Randomly submit a paired spinner and its cancellation as a bonded > (submit fence) pair. Apply congestion to the engine with more bonded > pairs to see if the execution order fails. If we prevent a cancellation > from running, then the spinner will remain spinning forever. > > v2: Test both immediate submission and fenced submission > v3: Copy-n-paste a single context variant > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > --- > tests/i915/gem_exec_balancer.c | 341 +++++++++++++++++++++++++++++++++ > 1 file changed, 341 insertions(+) > > diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c > index 80ae82416..07fe45920 100644 > --- a/tests/i915/gem_exec_balancer.c > +++ b/tests/i915/gem_exec_balancer.c > @@ -1154,6 +1154,342 @@ static void bonded_semaphore(int i915) > gem_context_destroy(i915, ctx); > } > > +static void __bonded_pair(int i915, > + const struct i915_engine_class_instance *siblings, > + unsigned int count, > + unsigned int flags, > + unsigned long *out) > +#define B_FENCE 0x1 > +#define B_HOSTILE 0x2 > +#define B_MANY 0x4 > +{ > + struct drm_i915_gem_exec_object2 batch = {}; > + struct drm_i915_gem_execbuffer2 execbuf = { > + .buffers_ptr = to_user_pointer(&batch), > + .buffer_count = 1, > + }; > + unsigned long cycles = 0; > + unsigned int spinner; > + igt_spin_t *a; > + int timeline; > + uint32_t A; > + > + srandom(getpid()); > + > + spinner = IGT_SPIN_POLL_RUN; > + if (flags & B_HOSTILE) > + spinner |= IGT_SPIN_NO_PREEMPTION; > + > + A = gem_context_create(i915); > + set_load_balancer(i915, A, siblings, count, NULL); > + a = igt_spin_new(i915, A, .flags = spinner); > + igt_spin_end(a); > + gem_sync(i915, a->handle); > + > + timeline = sw_sync_timeline_create(); > + > + igt_until_timeout(2) { > + unsigned int master; > + int fence; > + > + master = 1; > + if (flags & B_MANY) > + master = rand() % count + 1; > + > + fence = -1; > + if (flags & B_FENCE) > + fence = sw_sync_timeline_create_fence(timeline, > + cycles + 1); > + > + igt_spin_reset(a); > + a->execbuf.flags = master | I915_EXEC_FENCE_OUT; > + if (fence != -1) { > + a->execbuf.rsvd2 = fence; > + a->execbuf.flags |= I915_EXEC_FENCE_IN; > + } > + gem_execbuf_wr(i915, &a->execbuf); > + > + batch.handle = create_semaphore_to_spinner(i915, a); > + execbuf.rsvd1 = a->execbuf.rsvd1; > + execbuf.rsvd2 = a->execbuf.rsvd2 >> 32; > + do { > + execbuf.flags = rand() % count + 1; > + } while (execbuf.flags == master); > + execbuf.flags |= I915_EXEC_FENCE_SUBMIT; > + gem_execbuf(i915, &execbuf); > + gem_close(i915, batch.handle); > + > + if (fence != -1) { > + sw_sync_timeline_inc(timeline, 1); > + close(fence); > + } > + close(a->execbuf.rsvd2 >> 32); > + > + gem_sync(i915, a->handle); > + > + cycles++; > + } > + > + close(timeline); > + igt_spin_free(i915, a); > + gem_context_destroy(i915, A); > + > + *out = cycles; > +} > + > +static void bonded_pair(int i915) > +{ > + static const unsigned int phases[] = { > + 0, > + B_FENCE, > + B_MANY, > + B_HOSTILE, > + B_HOSTILE | B_FENCE, > + }; > + unsigned long *cycles; > + > + /* > + * The purpose of bonded submission is to execute one or more requests > + * concurrently. However, the very nature of that requires coordinated > + * submission across multiple engines. > + */ > + igt_require(gem_scheduler_has_preemption(i915)); > + > + cycles = mmap(0, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); > + > + for (int class = 0; class < 32; class++) { > + struct i915_engine_class_instance *siblings; > + unsigned int count; > + > + siblings = list_engines(i915, 1u << class, &count); > + if (count < 2) > + continue; > + > + igt_info("Class %u, 1 thread\n", class); > + for (int i = 0; i < ARRAY_SIZE(phases); i++) { > + cycles[0] = 0; > + __bonded_pair(i915, > + siblings, count, > + phases[i], > + &cycles[0]); > + gem_quiescent_gpu(i915); > + igt_info("%s %s %s submission, %lu cycles\n", > + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", > + phases[i] & B_MANY ? "many-master" : "single-master", > + phases[i] & B_FENCE ? "fenced" : "immediate", > + cycles[0]); > + } > + > + igt_info("Class %u, %d threads\n", class, count + 1); > + for (int i = 0; i < ARRAY_SIZE(phases); i++) { > + memset(cycles, 0, (count + 1) * sizeof(*cycles)); > + igt_fork(child, count + 1) > + __bonded_pair(i915, > + siblings, count, > + phases[i], > + &cycles[child]); > + igt_waitchildren(); > + gem_quiescent_gpu(i915); > + > + for (int child = 1; child < count + 1; child++) > + cycles[0] += cycles[child]; > + > + igt_info("%s %s %s submission, %lu cycles\n", > + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", > + phases[i] & B_MANY ? "many-master" : "single-master", > + phases[i] & B_FENCE ? "fenced" : "immediate", > + cycles[0]); > + } > + free(siblings); > + } > + > + munmap(cycles, 4096); > +} > + > +static void __bonded_dual(int i915, > + const struct i915_engine_class_instance *siblings, > + unsigned int count, > + unsigned int flags, > + unsigned long *out) > +{ > + struct drm_i915_gem_exec_object2 batch = {}; > + struct drm_i915_gem_execbuffer2 execbuf = { > + .buffers_ptr = to_user_pointer(&batch), > + .buffer_count = 1, > + }; > + unsigned long cycles = 0; > + unsigned int spinner; > + igt_spin_t *a, *b; > + int timeline; > + uint32_t A, B; > + > + srandom(getpid()); > + > + spinner = IGT_SPIN_POLL_RUN; > + if (flags & B_HOSTILE) > + spinner |= IGT_SPIN_NO_PREEMPTION; > + > + A = gem_context_create(i915); > + set_load_balancer(i915, A, siblings, count, NULL); > + a = igt_spin_new(i915, A, .flags = spinner); > + igt_spin_end(a); > + gem_sync(i915, a->handle); > + > + B = gem_context_create(i915); > + set_load_balancer(i915, B, siblings, count, NULL); > + b = igt_spin_new(i915, B, .flags = spinner); > + igt_spin_end(b); > + gem_sync(i915, b->handle); > + > + timeline = sw_sync_timeline_create(); > + > + igt_until_timeout(2) { > + unsigned int master; > + int fence; > + > + master = 1; > + if (flags & B_MANY) > + master = rand() % count + 1; > + > + fence = -1; > + if (flags & B_FENCE) > + fence = sw_sync_timeline_create_fence(timeline, > + cycles + 1); > + > + igt_spin_reset(a); > + a->execbuf.flags = master | I915_EXEC_FENCE_OUT; > + if (fence != -1) { > + a->execbuf.rsvd2 = fence; > + a->execbuf.flags |= I915_EXEC_FENCE_IN; > + } > + gem_execbuf_wr(i915, &a->execbuf); > + > + igt_spin_reset(b); > + b->execbuf.flags = master | I915_EXEC_FENCE_OUT; > + if (fence != -1) { > + b->execbuf.rsvd2 = fence; > + b->execbuf.flags |= I915_EXEC_FENCE_IN; > + } > + gem_execbuf_wr(i915, &b->execbuf); > + > + if (rand() % 1) > + igt_swap(a, b); > + > + batch.handle = create_semaphore_to_spinner(i915, a); > + execbuf.rsvd1 = a->execbuf.rsvd1; > + execbuf.rsvd2 = a->execbuf.rsvd2 >> 32; > + do { > + execbuf.flags = rand() % count + 1; > + } while (execbuf.flags == master); > + execbuf.flags |= I915_EXEC_FENCE_SUBMIT; > + gem_execbuf(i915, &execbuf); > + gem_close(i915, batch.handle); > + > + batch.handle = create_semaphore_to_spinner(i915, b); > + execbuf.rsvd1 = b->execbuf.rsvd1; > + execbuf.rsvd2 = b->execbuf.rsvd2 >> 32; > + do { > + execbuf.flags = rand() % count + 1; > + } while (execbuf.flags == master); > + execbuf.flags |= I915_EXEC_FENCE_SUBMIT; > + gem_execbuf(i915, &execbuf); > + gem_close(i915, batch.handle); > + > + if (fence != -1) { > + sw_sync_timeline_inc(timeline, 1); > + close(fence); > + } > + close(a->execbuf.rsvd2 >> 32); > + close(b->execbuf.rsvd2 >> 32); > + > + gem_sync(i915, a->handle); > + gem_sync(i915, b->handle); > + > + cycles++; > + } > + > + close(timeline); > + > + igt_spin_free(i915, a); > + igt_spin_free(i915, b); > + > + gem_context_destroy(i915, A); > + gem_context_destroy(i915, B); > + > + *out = cycles; > +} > + > +static void bonded_dual(int i915) > +{ > + static const unsigned int phases[] = { > + 0, > + B_FENCE, > + B_MANY, > + B_HOSTILE, > + B_HOSTILE | B_FENCE, > + }; > + unsigned long *cycles; > + > + > + /* > + * This is the same test as bonded_pair() but with the slight extra > + * stress of having two inflight clients and interchanging them > + * in a thread. > + */ > + igt_require(gem_scheduler_has_preemption(i915)); > + > + cycles = mmap(0, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); > + > + for (int class = 0; class < 32; class++) { > + struct i915_engine_class_instance *siblings; > + unsigned int count; > + > + siblings = list_engines(i915, 1u << class, &count); > + if (count < 2) > + continue; > + > + igt_info("Class %u, 1 thread\n", class); > + for (int i = 0; i < ARRAY_SIZE(phases); i++) { > + cycles[0] = 0; > + __bonded_dual(i915, > + siblings, count, > + phases[i], > + &cycles[0]); > + gem_quiescent_gpu(i915); > + igt_info("%s %s %s submission, %lu cycles\n", > + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", > + phases[i] & B_MANY ? "many-master" : "single-master", > + phases[i] & B_FENCE ? "fenced" : "immediate", > + cycles[0]); > + } > + > + igt_info("Class %u, %d threads\n", class, count + 1); > + for (int i = 0; i < ARRAY_SIZE(phases); i++) { > + memset(cycles, 0, (count + 1) * sizeof(*cycles)); > + igt_fork(child, count + 1) > + __bonded_dual(i915, > + siblings, count, > + phases[i], > + &cycles[child]); > + igt_waitchildren(); > + gem_quiescent_gpu(i915); > + > + for (int child = 1; child < count + 1; child++) > + cycles[0] += cycles[child]; > + > + igt_info("%s %s %s submission, %lu cycles\n", > + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", > + phases[i] & B_MANY ? "many-master" : "single-master", > + phases[i] & B_FENCE ? "fenced" : "immediate", > + cycles[0]); > + } > + > + free(siblings); > + } > + > + munmap(cycles, 4096); > +} > + > static void __bonded_nohang(int i915, uint32_t ctx, > const struct i915_engine_class_instance *siblings, > unsigned int count, > @@ -2284,6 +2620,11 @@ igt_main > igt_subtest("bonded-semaphore") > bonded_semaphore(i915); > > + igt_subtest("bonded-pair") > + bonded_pair(i915); > + igt_subtest("bonded-dual") > + bonded_dual(i915); > + > igt_fixture { > igt_stop_hang_detector(); > } > "Runner" (non underscore functions) could have been shared easily but okay: Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v3] i915/gem_exec_balancer: Randomise bonded submission @ 2020-05-29 15:08 ` Tvrtko Ursulin 0 siblings, 0 replies; 8+ messages in thread From: Tvrtko Ursulin @ 2020-05-29 15:08 UTC (permalink / raw) To: Chris Wilson, intel-gfx; +Cc: igt-dev, Tvrtko Ursulin On 29/05/2020 14:58, Chris Wilson wrote: > Randomly submit a paired spinner and its cancellation as a bonded > (submit fence) pair. Apply congestion to the engine with more bonded > pairs to see if the execution order fails. If we prevent a cancellation > from running, then the spinner will remain spinning forever. > > v2: Test both immediate submission and fenced submission > v3: Copy-n-paste a single context variant > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > --- > tests/i915/gem_exec_balancer.c | 341 +++++++++++++++++++++++++++++++++ > 1 file changed, 341 insertions(+) > > diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c > index 80ae82416..07fe45920 100644 > --- a/tests/i915/gem_exec_balancer.c > +++ b/tests/i915/gem_exec_balancer.c > @@ -1154,6 +1154,342 @@ static void bonded_semaphore(int i915) > gem_context_destroy(i915, ctx); > } > > +static void __bonded_pair(int i915, > + const struct i915_engine_class_instance *siblings, > + unsigned int count, > + unsigned int flags, > + unsigned long *out) > +#define B_FENCE 0x1 > +#define B_HOSTILE 0x2 > +#define B_MANY 0x4 > +{ > + struct drm_i915_gem_exec_object2 batch = {}; > + struct drm_i915_gem_execbuffer2 execbuf = { > + .buffers_ptr = to_user_pointer(&batch), > + .buffer_count = 1, > + }; > + unsigned long cycles = 0; > + unsigned int spinner; > + igt_spin_t *a; > + int timeline; > + uint32_t A; > + > + srandom(getpid()); > + > + spinner = IGT_SPIN_POLL_RUN; > + if (flags & B_HOSTILE) > + spinner |= IGT_SPIN_NO_PREEMPTION; > + > + A = gem_context_create(i915); > + set_load_balancer(i915, A, siblings, count, NULL); > + a = igt_spin_new(i915, A, .flags = spinner); > + igt_spin_end(a); > + gem_sync(i915, a->handle); > + > + timeline = sw_sync_timeline_create(); > + > + igt_until_timeout(2) { > + unsigned int master; > + int fence; > + > + master = 1; > + if (flags & B_MANY) > + master = rand() % count + 1; > + > + fence = -1; > + if (flags & B_FENCE) > + fence = sw_sync_timeline_create_fence(timeline, > + cycles + 1); > + > + igt_spin_reset(a); > + a->execbuf.flags = master | I915_EXEC_FENCE_OUT; > + if (fence != -1) { > + a->execbuf.rsvd2 = fence; > + a->execbuf.flags |= I915_EXEC_FENCE_IN; > + } > + gem_execbuf_wr(i915, &a->execbuf); > + > + batch.handle = create_semaphore_to_spinner(i915, a); > + execbuf.rsvd1 = a->execbuf.rsvd1; > + execbuf.rsvd2 = a->execbuf.rsvd2 >> 32; > + do { > + execbuf.flags = rand() % count + 1; > + } while (execbuf.flags == master); > + execbuf.flags |= I915_EXEC_FENCE_SUBMIT; > + gem_execbuf(i915, &execbuf); > + gem_close(i915, batch.handle); > + > + if (fence != -1) { > + sw_sync_timeline_inc(timeline, 1); > + close(fence); > + } > + close(a->execbuf.rsvd2 >> 32); > + > + gem_sync(i915, a->handle); > + > + cycles++; > + } > + > + close(timeline); > + igt_spin_free(i915, a); > + gem_context_destroy(i915, A); > + > + *out = cycles; > +} > + > +static void bonded_pair(int i915) > +{ > + static const unsigned int phases[] = { > + 0, > + B_FENCE, > + B_MANY, > + B_HOSTILE, > + B_HOSTILE | B_FENCE, > + }; > + unsigned long *cycles; > + > + /* > + * The purpose of bonded submission is to execute one or more requests > + * concurrently. However, the very nature of that requires coordinated > + * submission across multiple engines. > + */ > + igt_require(gem_scheduler_has_preemption(i915)); > + > + cycles = mmap(0, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); > + > + for (int class = 0; class < 32; class++) { > + struct i915_engine_class_instance *siblings; > + unsigned int count; > + > + siblings = list_engines(i915, 1u << class, &count); > + if (count < 2) > + continue; > + > + igt_info("Class %u, 1 thread\n", class); > + for (int i = 0; i < ARRAY_SIZE(phases); i++) { > + cycles[0] = 0; > + __bonded_pair(i915, > + siblings, count, > + phases[i], > + &cycles[0]); > + gem_quiescent_gpu(i915); > + igt_info("%s %s %s submission, %lu cycles\n", > + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", > + phases[i] & B_MANY ? "many-master" : "single-master", > + phases[i] & B_FENCE ? "fenced" : "immediate", > + cycles[0]); > + } > + > + igt_info("Class %u, %d threads\n", class, count + 1); > + for (int i = 0; i < ARRAY_SIZE(phases); i++) { > + memset(cycles, 0, (count + 1) * sizeof(*cycles)); > + igt_fork(child, count + 1) > + __bonded_pair(i915, > + siblings, count, > + phases[i], > + &cycles[child]); > + igt_waitchildren(); > + gem_quiescent_gpu(i915); > + > + for (int child = 1; child < count + 1; child++) > + cycles[0] += cycles[child]; > + > + igt_info("%s %s %s submission, %lu cycles\n", > + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", > + phases[i] & B_MANY ? "many-master" : "single-master", > + phases[i] & B_FENCE ? "fenced" : "immediate", > + cycles[0]); > + } > + free(siblings); > + } > + > + munmap(cycles, 4096); > +} > + > +static void __bonded_dual(int i915, > + const struct i915_engine_class_instance *siblings, > + unsigned int count, > + unsigned int flags, > + unsigned long *out) > +{ > + struct drm_i915_gem_exec_object2 batch = {}; > + struct drm_i915_gem_execbuffer2 execbuf = { > + .buffers_ptr = to_user_pointer(&batch), > + .buffer_count = 1, > + }; > + unsigned long cycles = 0; > + unsigned int spinner; > + igt_spin_t *a, *b; > + int timeline; > + uint32_t A, B; > + > + srandom(getpid()); > + > + spinner = IGT_SPIN_POLL_RUN; > + if (flags & B_HOSTILE) > + spinner |= IGT_SPIN_NO_PREEMPTION; > + > + A = gem_context_create(i915); > + set_load_balancer(i915, A, siblings, count, NULL); > + a = igt_spin_new(i915, A, .flags = spinner); > + igt_spin_end(a); > + gem_sync(i915, a->handle); > + > + B = gem_context_create(i915); > + set_load_balancer(i915, B, siblings, count, NULL); > + b = igt_spin_new(i915, B, .flags = spinner); > + igt_spin_end(b); > + gem_sync(i915, b->handle); > + > + timeline = sw_sync_timeline_create(); > + > + igt_until_timeout(2) { > + unsigned int master; > + int fence; > + > + master = 1; > + if (flags & B_MANY) > + master = rand() % count + 1; > + > + fence = -1; > + if (flags & B_FENCE) > + fence = sw_sync_timeline_create_fence(timeline, > + cycles + 1); > + > + igt_spin_reset(a); > + a->execbuf.flags = master | I915_EXEC_FENCE_OUT; > + if (fence != -1) { > + a->execbuf.rsvd2 = fence; > + a->execbuf.flags |= I915_EXEC_FENCE_IN; > + } > + gem_execbuf_wr(i915, &a->execbuf); > + > + igt_spin_reset(b); > + b->execbuf.flags = master | I915_EXEC_FENCE_OUT; > + if (fence != -1) { > + b->execbuf.rsvd2 = fence; > + b->execbuf.flags |= I915_EXEC_FENCE_IN; > + } > + gem_execbuf_wr(i915, &b->execbuf); > + > + if (rand() % 1) > + igt_swap(a, b); > + > + batch.handle = create_semaphore_to_spinner(i915, a); > + execbuf.rsvd1 = a->execbuf.rsvd1; > + execbuf.rsvd2 = a->execbuf.rsvd2 >> 32; > + do { > + execbuf.flags = rand() % count + 1; > + } while (execbuf.flags == master); > + execbuf.flags |= I915_EXEC_FENCE_SUBMIT; > + gem_execbuf(i915, &execbuf); > + gem_close(i915, batch.handle); > + > + batch.handle = create_semaphore_to_spinner(i915, b); > + execbuf.rsvd1 = b->execbuf.rsvd1; > + execbuf.rsvd2 = b->execbuf.rsvd2 >> 32; > + do { > + execbuf.flags = rand() % count + 1; > + } while (execbuf.flags == master); > + execbuf.flags |= I915_EXEC_FENCE_SUBMIT; > + gem_execbuf(i915, &execbuf); > + gem_close(i915, batch.handle); > + > + if (fence != -1) { > + sw_sync_timeline_inc(timeline, 1); > + close(fence); > + } > + close(a->execbuf.rsvd2 >> 32); > + close(b->execbuf.rsvd2 >> 32); > + > + gem_sync(i915, a->handle); > + gem_sync(i915, b->handle); > + > + cycles++; > + } > + > + close(timeline); > + > + igt_spin_free(i915, a); > + igt_spin_free(i915, b); > + > + gem_context_destroy(i915, A); > + gem_context_destroy(i915, B); > + > + *out = cycles; > +} > + > +static void bonded_dual(int i915) > +{ > + static const unsigned int phases[] = { > + 0, > + B_FENCE, > + B_MANY, > + B_HOSTILE, > + B_HOSTILE | B_FENCE, > + }; > + unsigned long *cycles; > + > + > + /* > + * This is the same test as bonded_pair() but with the slight extra > + * stress of having two inflight clients and interchanging them > + * in a thread. > + */ > + igt_require(gem_scheduler_has_preemption(i915)); > + > + cycles = mmap(0, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); > + > + for (int class = 0; class < 32; class++) { > + struct i915_engine_class_instance *siblings; > + unsigned int count; > + > + siblings = list_engines(i915, 1u << class, &count); > + if (count < 2) > + continue; > + > + igt_info("Class %u, 1 thread\n", class); > + for (int i = 0; i < ARRAY_SIZE(phases); i++) { > + cycles[0] = 0; > + __bonded_dual(i915, > + siblings, count, > + phases[i], > + &cycles[0]); > + gem_quiescent_gpu(i915); > + igt_info("%s %s %s submission, %lu cycles\n", > + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", > + phases[i] & B_MANY ? "many-master" : "single-master", > + phases[i] & B_FENCE ? "fenced" : "immediate", > + cycles[0]); > + } > + > + igt_info("Class %u, %d threads\n", class, count + 1); > + for (int i = 0; i < ARRAY_SIZE(phases); i++) { > + memset(cycles, 0, (count + 1) * sizeof(*cycles)); > + igt_fork(child, count + 1) > + __bonded_dual(i915, > + siblings, count, > + phases[i], > + &cycles[child]); > + igt_waitchildren(); > + gem_quiescent_gpu(i915); > + > + for (int child = 1; child < count + 1; child++) > + cycles[0] += cycles[child]; > + > + igt_info("%s %s %s submission, %lu cycles\n", > + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", > + phases[i] & B_MANY ? "many-master" : "single-master", > + phases[i] & B_FENCE ? "fenced" : "immediate", > + cycles[0]); > + } > + > + free(siblings); > + } > + > + munmap(cycles, 4096); > +} > + > static void __bonded_nohang(int i915, uint32_t ctx, > const struct i915_engine_class_instance *siblings, > unsigned int count, > @@ -2284,6 +2620,11 @@ igt_main > igt_subtest("bonded-semaphore") > bonded_semaphore(i915); > > + igt_subtest("bonded-pair") > + bonded_pair(i915); > + igt_subtest("bonded-dual") > + bonded_dual(i915); > + > igt_fixture { > igt_stop_hang_detector(); > } > "Runner" (non underscore functions) could have been shared easily but okay: Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Regards, Tvrtko _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [igt-dev] [PATCH i-g-t v3] i915/gem_exec_balancer: Randomise bonded submission 2020-05-29 15:08 ` Tvrtko Ursulin @ 2020-05-29 15:13 ` Chris Wilson -1 siblings, 0 replies; 8+ messages in thread From: Chris Wilson @ 2020-05-29 15:13 UTC (permalink / raw) To: Tvrtko Ursulin, intel-gfx; +Cc: igt-dev Quoting Tvrtko Ursulin (2020-05-29 16:08:25) > > On 29/05/2020 14:58, Chris Wilson wrote: > > Randomly submit a paired spinner and its cancellation as a bonded > > (submit fence) pair. Apply congestion to the engine with more bonded > > pairs to see if the execution order fails. If we prevent a cancellation > > from running, then the spinner will remain spinning forever. > > > > v2: Test both immediate submission and fenced submission > > v3: Copy-n-paste a single context variant > > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > --- > > tests/i915/gem_exec_balancer.c | 341 +++++++++++++++++++++++++++++++++ > > 1 file changed, 341 insertions(+) > > > > diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c > > index 80ae82416..07fe45920 100644 > > --- a/tests/i915/gem_exec_balancer.c > > +++ b/tests/i915/gem_exec_balancer.c > > @@ -1154,6 +1154,342 @@ static void bonded_semaphore(int i915) > > gem_context_destroy(i915, ctx); > > } > > > > +static void __bonded_pair(int i915, > > + const struct i915_engine_class_instance *siblings, > > + unsigned int count, > > + unsigned int flags, > > + unsigned long *out) > > +#define B_FENCE 0x1 > > +#define B_HOSTILE 0x2 > > +#define B_MANY 0x4 > > +{ > > + struct drm_i915_gem_exec_object2 batch = {}; > > + struct drm_i915_gem_execbuffer2 execbuf = { > > + .buffers_ptr = to_user_pointer(&batch), > > + .buffer_count = 1, > > + }; > > + unsigned long cycles = 0; > > + unsigned int spinner; > > + igt_spin_t *a; > > + int timeline; > > + uint32_t A; > > + > > + srandom(getpid()); > > + > > + spinner = IGT_SPIN_POLL_RUN; > > + if (flags & B_HOSTILE) > > + spinner |= IGT_SPIN_NO_PREEMPTION; > > + > > + A = gem_context_create(i915); > > + set_load_balancer(i915, A, siblings, count, NULL); > > + a = igt_spin_new(i915, A, .flags = spinner); > > + igt_spin_end(a); > > + gem_sync(i915, a->handle); > > + > > + timeline = sw_sync_timeline_create(); > > + > > + igt_until_timeout(2) { > > + unsigned int master; > > + int fence; > > + > > + master = 1; > > + if (flags & B_MANY) > > + master = rand() % count + 1; > > + > > + fence = -1; > > + if (flags & B_FENCE) > > + fence = sw_sync_timeline_create_fence(timeline, > > + cycles + 1); > > + > > + igt_spin_reset(a); > > + a->execbuf.flags = master | I915_EXEC_FENCE_OUT; > > + if (fence != -1) { > > + a->execbuf.rsvd2 = fence; > > + a->execbuf.flags |= I915_EXEC_FENCE_IN; > > + } > > + gem_execbuf_wr(i915, &a->execbuf); > > + > > + batch.handle = create_semaphore_to_spinner(i915, a); > > + execbuf.rsvd1 = a->execbuf.rsvd1; > > + execbuf.rsvd2 = a->execbuf.rsvd2 >> 32; > > + do { > > + execbuf.flags = rand() % count + 1; > > + } while (execbuf.flags == master); > > + execbuf.flags |= I915_EXEC_FENCE_SUBMIT; > > + gem_execbuf(i915, &execbuf); > > + gem_close(i915, batch.handle); > > + > > + if (fence != -1) { > > + sw_sync_timeline_inc(timeline, 1); > > + close(fence); > > + } > > + close(a->execbuf.rsvd2 >> 32); > > + > > + gem_sync(i915, a->handle); > > + > > + cycles++; > > + } > > + > > + close(timeline); > > + igt_spin_free(i915, a); > > + gem_context_destroy(i915, A); > > + > > + *out = cycles; > > +} > > + > > +static void bonded_pair(int i915) > > +{ > > + static const unsigned int phases[] = { > > + 0, > > + B_FENCE, > > + B_MANY, > > + B_HOSTILE, > > + B_HOSTILE | B_FENCE, > > + }; > > + unsigned long *cycles; > > + > > + /* > > + * The purpose of bonded submission is to execute one or more requests > > + * concurrently. However, the very nature of that requires coordinated > > + * submission across multiple engines. > > + */ > > + igt_require(gem_scheduler_has_preemption(i915)); > > + > > + cycles = mmap(0, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); > > + > > + for (int class = 0; class < 32; class++) { > > + struct i915_engine_class_instance *siblings; > > + unsigned int count; > > + > > + siblings = list_engines(i915, 1u << class, &count); > > + if (count < 2) > > + continue; > > + > > + igt_info("Class %u, 1 thread\n", class); > > + for (int i = 0; i < ARRAY_SIZE(phases); i++) { > > + cycles[0] = 0; > > + __bonded_pair(i915, > > + siblings, count, > > + phases[i], > > + &cycles[0]); > > + gem_quiescent_gpu(i915); > > + igt_info("%s %s %s submission, %lu cycles\n", > > + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", > > + phases[i] & B_MANY ? "many-master" : "single-master", > > + phases[i] & B_FENCE ? "fenced" : "immediate", > > + cycles[0]); > > + } > > + > > + igt_info("Class %u, %d threads\n", class, count + 1); > > + for (int i = 0; i < ARRAY_SIZE(phases); i++) { > > + memset(cycles, 0, (count + 1) * sizeof(*cycles)); > > + igt_fork(child, count + 1) > > + __bonded_pair(i915, > > + siblings, count, > > + phases[i], > > + &cycles[child]); > > + igt_waitchildren(); > > + gem_quiescent_gpu(i915); > > + > > + for (int child = 1; child < count + 1; child++) > > + cycles[0] += cycles[child]; > > + > > + igt_info("%s %s %s submission, %lu cycles\n", > > + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", > > + phases[i] & B_MANY ? "many-master" : "single-master", > > + phases[i] & B_FENCE ? "fenced" : "immediate", > > + cycles[0]); > > + } > > + free(siblings); > > + } > > + > > + munmap(cycles, 4096); > > +} > > + > > +static void __bonded_dual(int i915, > > + const struct i915_engine_class_instance *siblings, > > + unsigned int count, > > + unsigned int flags, > > + unsigned long *out) > > +{ > > + struct drm_i915_gem_exec_object2 batch = {}; > > + struct drm_i915_gem_execbuffer2 execbuf = { > > + .buffers_ptr = to_user_pointer(&batch), > > + .buffer_count = 1, > > + }; > > + unsigned long cycles = 0; > > + unsigned int spinner; > > + igt_spin_t *a, *b; > > + int timeline; > > + uint32_t A, B; > > + > > + srandom(getpid()); > > + > > + spinner = IGT_SPIN_POLL_RUN; > > + if (flags & B_HOSTILE) > > + spinner |= IGT_SPIN_NO_PREEMPTION; > > + > > + A = gem_context_create(i915); > > + set_load_balancer(i915, A, siblings, count, NULL); > > + a = igt_spin_new(i915, A, .flags = spinner); > > + igt_spin_end(a); > > + gem_sync(i915, a->handle); > > + > > + B = gem_context_create(i915); > > + set_load_balancer(i915, B, siblings, count, NULL); > > + b = igt_spin_new(i915, B, .flags = spinner); > > + igt_spin_end(b); > > + gem_sync(i915, b->handle); > > + > > + timeline = sw_sync_timeline_create(); > > + > > + igt_until_timeout(2) { > > + unsigned int master; > > + int fence; > > + > > + master = 1; > > + if (flags & B_MANY) > > + master = rand() % count + 1; > > + > > + fence = -1; > > + if (flags & B_FENCE) > > + fence = sw_sync_timeline_create_fence(timeline, > > + cycles + 1); > > + > > + igt_spin_reset(a); > > + a->execbuf.flags = master | I915_EXEC_FENCE_OUT; > > + if (fence != -1) { > > + a->execbuf.rsvd2 = fence; > > + a->execbuf.flags |= I915_EXEC_FENCE_IN; > > + } > > + gem_execbuf_wr(i915, &a->execbuf); > > + > > + igt_spin_reset(b); > > + b->execbuf.flags = master | I915_EXEC_FENCE_OUT; > > + if (fence != -1) { > > + b->execbuf.rsvd2 = fence; > > + b->execbuf.flags |= I915_EXEC_FENCE_IN; > > + } > > + gem_execbuf_wr(i915, &b->execbuf); > > + > > + if (rand() % 1) > > + igt_swap(a, b); > > + > > + batch.handle = create_semaphore_to_spinner(i915, a); > > + execbuf.rsvd1 = a->execbuf.rsvd1; > > + execbuf.rsvd2 = a->execbuf.rsvd2 >> 32; > > + do { > > + execbuf.flags = rand() % count + 1; > > + } while (execbuf.flags == master); > > + execbuf.flags |= I915_EXEC_FENCE_SUBMIT; > > + gem_execbuf(i915, &execbuf); > > + gem_close(i915, batch.handle); > > + > > + batch.handle = create_semaphore_to_spinner(i915, b); > > + execbuf.rsvd1 = b->execbuf.rsvd1; > > + execbuf.rsvd2 = b->execbuf.rsvd2 >> 32; > > + do { > > + execbuf.flags = rand() % count + 1; > > + } while (execbuf.flags == master); > > + execbuf.flags |= I915_EXEC_FENCE_SUBMIT; > > + gem_execbuf(i915, &execbuf); > > + gem_close(i915, batch.handle); > > + > > + if (fence != -1) { > > + sw_sync_timeline_inc(timeline, 1); > > + close(fence); > > + } > > + close(a->execbuf.rsvd2 >> 32); > > + close(b->execbuf.rsvd2 >> 32); > > + > > + gem_sync(i915, a->handle); > > + gem_sync(i915, b->handle); > > + > > + cycles++; > > + } > > + > > + close(timeline); > > + > > + igt_spin_free(i915, a); > > + igt_spin_free(i915, b); > > + > > + gem_context_destroy(i915, A); > > + gem_context_destroy(i915, B); > > + > > + *out = cycles; > > +} > > + > > +static void bonded_dual(int i915) > > +{ > > + static const unsigned int phases[] = { > > + 0, > > + B_FENCE, > > + B_MANY, > > + B_HOSTILE, > > + B_HOSTILE | B_FENCE, > > + }; > > + unsigned long *cycles; > > + > > + > > + /* > > + * This is the same test as bonded_pair() but with the slight extra > > + * stress of having two inflight clients and interchanging them > > + * in a thread. > > + */ > > + igt_require(gem_scheduler_has_preemption(i915)); > > + > > + cycles = mmap(0, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); > > + > > + for (int class = 0; class < 32; class++) { > > + struct i915_engine_class_instance *siblings; > > + unsigned int count; > > + > > + siblings = list_engines(i915, 1u << class, &count); > > + if (count < 2) > > + continue; > > + > > + igt_info("Class %u, 1 thread\n", class); > > + for (int i = 0; i < ARRAY_SIZE(phases); i++) { > > + cycles[0] = 0; > > + __bonded_dual(i915, > > + siblings, count, > > + phases[i], > > + &cycles[0]); > > + gem_quiescent_gpu(i915); > > + igt_info("%s %s %s submission, %lu cycles\n", > > + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", > > + phases[i] & B_MANY ? "many-master" : "single-master", > > + phases[i] & B_FENCE ? "fenced" : "immediate", > > + cycles[0]); > > + } > > + > > + igt_info("Class %u, %d threads\n", class, count + 1); > > + for (int i = 0; i < ARRAY_SIZE(phases); i++) { > > + memset(cycles, 0, (count + 1) * sizeof(*cycles)); > > + igt_fork(child, count + 1) > > + __bonded_dual(i915, > > + siblings, count, > > + phases[i], > > + &cycles[child]); > > + igt_waitchildren(); > > + gem_quiescent_gpu(i915); > > + > > + for (int child = 1; child < count + 1; child++) > > + cycles[0] += cycles[child]; > > + > > + igt_info("%s %s %s submission, %lu cycles\n", > > + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", > > + phases[i] & B_MANY ? "many-master" : "single-master", > > + phases[i] & B_FENCE ? "fenced" : "immediate", > > + cycles[0]); > > + } > > + > > + free(siblings); > > + } > > + > > + munmap(cycles, 4096); > > +} > > + > > static void __bonded_nohang(int i915, uint32_t ctx, > > const struct i915_engine_class_instance *siblings, > > unsigned int count, > > @@ -2284,6 +2620,11 @@ igt_main > > igt_subtest("bonded-semaphore") > > bonded_semaphore(i915); > > > > + igt_subtest("bonded-pair") > > + bonded_pair(i915); > > + igt_subtest("bonded-dual") > > + bonded_dual(i915); > > + > > igt_fixture { > > igt_stop_hang_detector(); > > } > > > > > "Runner" (non underscore functions) could have been shared easily but okay: Copy-n-paste, 2 keypresses. Sharing, many. I was saving Joules but not electronvolts. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v3] i915/gem_exec_balancer: Randomise bonded submission @ 2020-05-29 15:13 ` Chris Wilson 0 siblings, 0 replies; 8+ messages in thread From: Chris Wilson @ 2020-05-29 15:13 UTC (permalink / raw) To: Tvrtko Ursulin, intel-gfx; +Cc: igt-dev, Tvrtko Ursulin Quoting Tvrtko Ursulin (2020-05-29 16:08:25) > > On 29/05/2020 14:58, Chris Wilson wrote: > > Randomly submit a paired spinner and its cancellation as a bonded > > (submit fence) pair. Apply congestion to the engine with more bonded > > pairs to see if the execution order fails. If we prevent a cancellation > > from running, then the spinner will remain spinning forever. > > > > v2: Test both immediate submission and fenced submission > > v3: Copy-n-paste a single context variant > > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > --- > > tests/i915/gem_exec_balancer.c | 341 +++++++++++++++++++++++++++++++++ > > 1 file changed, 341 insertions(+) > > > > diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c > > index 80ae82416..07fe45920 100644 > > --- a/tests/i915/gem_exec_balancer.c > > +++ b/tests/i915/gem_exec_balancer.c > > @@ -1154,6 +1154,342 @@ static void bonded_semaphore(int i915) > > gem_context_destroy(i915, ctx); > > } > > > > +static void __bonded_pair(int i915, > > + const struct i915_engine_class_instance *siblings, > > + unsigned int count, > > + unsigned int flags, > > + unsigned long *out) > > +#define B_FENCE 0x1 > > +#define B_HOSTILE 0x2 > > +#define B_MANY 0x4 > > +{ > > + struct drm_i915_gem_exec_object2 batch = {}; > > + struct drm_i915_gem_execbuffer2 execbuf = { > > + .buffers_ptr = to_user_pointer(&batch), > > + .buffer_count = 1, > > + }; > > + unsigned long cycles = 0; > > + unsigned int spinner; > > + igt_spin_t *a; > > + int timeline; > > + uint32_t A; > > + > > + srandom(getpid()); > > + > > + spinner = IGT_SPIN_POLL_RUN; > > + if (flags & B_HOSTILE) > > + spinner |= IGT_SPIN_NO_PREEMPTION; > > + > > + A = gem_context_create(i915); > > + set_load_balancer(i915, A, siblings, count, NULL); > > + a = igt_spin_new(i915, A, .flags = spinner); > > + igt_spin_end(a); > > + gem_sync(i915, a->handle); > > + > > + timeline = sw_sync_timeline_create(); > > + > > + igt_until_timeout(2) { > > + unsigned int master; > > + int fence; > > + > > + master = 1; > > + if (flags & B_MANY) > > + master = rand() % count + 1; > > + > > + fence = -1; > > + if (flags & B_FENCE) > > + fence = sw_sync_timeline_create_fence(timeline, > > + cycles + 1); > > + > > + igt_spin_reset(a); > > + a->execbuf.flags = master | I915_EXEC_FENCE_OUT; > > + if (fence != -1) { > > + a->execbuf.rsvd2 = fence; > > + a->execbuf.flags |= I915_EXEC_FENCE_IN; > > + } > > + gem_execbuf_wr(i915, &a->execbuf); > > + > > + batch.handle = create_semaphore_to_spinner(i915, a); > > + execbuf.rsvd1 = a->execbuf.rsvd1; > > + execbuf.rsvd2 = a->execbuf.rsvd2 >> 32; > > + do { > > + execbuf.flags = rand() % count + 1; > > + } while (execbuf.flags == master); > > + execbuf.flags |= I915_EXEC_FENCE_SUBMIT; > > + gem_execbuf(i915, &execbuf); > > + gem_close(i915, batch.handle); > > + > > + if (fence != -1) { > > + sw_sync_timeline_inc(timeline, 1); > > + close(fence); > > + } > > + close(a->execbuf.rsvd2 >> 32); > > + > > + gem_sync(i915, a->handle); > > + > > + cycles++; > > + } > > + > > + close(timeline); > > + igt_spin_free(i915, a); > > + gem_context_destroy(i915, A); > > + > > + *out = cycles; > > +} > > + > > +static void bonded_pair(int i915) > > +{ > > + static const unsigned int phases[] = { > > + 0, > > + B_FENCE, > > + B_MANY, > > + B_HOSTILE, > > + B_HOSTILE | B_FENCE, > > + }; > > + unsigned long *cycles; > > + > > + /* > > + * The purpose of bonded submission is to execute one or more requests > > + * concurrently. However, the very nature of that requires coordinated > > + * submission across multiple engines. > > + */ > > + igt_require(gem_scheduler_has_preemption(i915)); > > + > > + cycles = mmap(0, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); > > + > > + for (int class = 0; class < 32; class++) { > > + struct i915_engine_class_instance *siblings; > > + unsigned int count; > > + > > + siblings = list_engines(i915, 1u << class, &count); > > + if (count < 2) > > + continue; > > + > > + igt_info("Class %u, 1 thread\n", class); > > + for (int i = 0; i < ARRAY_SIZE(phases); i++) { > > + cycles[0] = 0; > > + __bonded_pair(i915, > > + siblings, count, > > + phases[i], > > + &cycles[0]); > > + gem_quiescent_gpu(i915); > > + igt_info("%s %s %s submission, %lu cycles\n", > > + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", > > + phases[i] & B_MANY ? "many-master" : "single-master", > > + phases[i] & B_FENCE ? "fenced" : "immediate", > > + cycles[0]); > > + } > > + > > + igt_info("Class %u, %d threads\n", class, count + 1); > > + for (int i = 0; i < ARRAY_SIZE(phases); i++) { > > + memset(cycles, 0, (count + 1) * sizeof(*cycles)); > > + igt_fork(child, count + 1) > > + __bonded_pair(i915, > > + siblings, count, > > + phases[i], > > + &cycles[child]); > > + igt_waitchildren(); > > + gem_quiescent_gpu(i915); > > + > > + for (int child = 1; child < count + 1; child++) > > + cycles[0] += cycles[child]; > > + > > + igt_info("%s %s %s submission, %lu cycles\n", > > + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", > > + phases[i] & B_MANY ? "many-master" : "single-master", > > + phases[i] & B_FENCE ? "fenced" : "immediate", > > + cycles[0]); > > + } > > + free(siblings); > > + } > > + > > + munmap(cycles, 4096); > > +} > > + > > +static void __bonded_dual(int i915, > > + const struct i915_engine_class_instance *siblings, > > + unsigned int count, > > + unsigned int flags, > > + unsigned long *out) > > +{ > > + struct drm_i915_gem_exec_object2 batch = {}; > > + struct drm_i915_gem_execbuffer2 execbuf = { > > + .buffers_ptr = to_user_pointer(&batch), > > + .buffer_count = 1, > > + }; > > + unsigned long cycles = 0; > > + unsigned int spinner; > > + igt_spin_t *a, *b; > > + int timeline; > > + uint32_t A, B; > > + > > + srandom(getpid()); > > + > > + spinner = IGT_SPIN_POLL_RUN; > > + if (flags & B_HOSTILE) > > + spinner |= IGT_SPIN_NO_PREEMPTION; > > + > > + A = gem_context_create(i915); > > + set_load_balancer(i915, A, siblings, count, NULL); > > + a = igt_spin_new(i915, A, .flags = spinner); > > + igt_spin_end(a); > > + gem_sync(i915, a->handle); > > + > > + B = gem_context_create(i915); > > + set_load_balancer(i915, B, siblings, count, NULL); > > + b = igt_spin_new(i915, B, .flags = spinner); > > + igt_spin_end(b); > > + gem_sync(i915, b->handle); > > + > > + timeline = sw_sync_timeline_create(); > > + > > + igt_until_timeout(2) { > > + unsigned int master; > > + int fence; > > + > > + master = 1; > > + if (flags & B_MANY) > > + master = rand() % count + 1; > > + > > + fence = -1; > > + if (flags & B_FENCE) > > + fence = sw_sync_timeline_create_fence(timeline, > > + cycles + 1); > > + > > + igt_spin_reset(a); > > + a->execbuf.flags = master | I915_EXEC_FENCE_OUT; > > + if (fence != -1) { > > + a->execbuf.rsvd2 = fence; > > + a->execbuf.flags |= I915_EXEC_FENCE_IN; > > + } > > + gem_execbuf_wr(i915, &a->execbuf); > > + > > + igt_spin_reset(b); > > + b->execbuf.flags = master | I915_EXEC_FENCE_OUT; > > + if (fence != -1) { > > + b->execbuf.rsvd2 = fence; > > + b->execbuf.flags |= I915_EXEC_FENCE_IN; > > + } > > + gem_execbuf_wr(i915, &b->execbuf); > > + > > + if (rand() % 1) > > + igt_swap(a, b); > > + > > + batch.handle = create_semaphore_to_spinner(i915, a); > > + execbuf.rsvd1 = a->execbuf.rsvd1; > > + execbuf.rsvd2 = a->execbuf.rsvd2 >> 32; > > + do { > > + execbuf.flags = rand() % count + 1; > > + } while (execbuf.flags == master); > > + execbuf.flags |= I915_EXEC_FENCE_SUBMIT; > > + gem_execbuf(i915, &execbuf); > > + gem_close(i915, batch.handle); > > + > > + batch.handle = create_semaphore_to_spinner(i915, b); > > + execbuf.rsvd1 = b->execbuf.rsvd1; > > + execbuf.rsvd2 = b->execbuf.rsvd2 >> 32; > > + do { > > + execbuf.flags = rand() % count + 1; > > + } while (execbuf.flags == master); > > + execbuf.flags |= I915_EXEC_FENCE_SUBMIT; > > + gem_execbuf(i915, &execbuf); > > + gem_close(i915, batch.handle); > > + > > + if (fence != -1) { > > + sw_sync_timeline_inc(timeline, 1); > > + close(fence); > > + } > > + close(a->execbuf.rsvd2 >> 32); > > + close(b->execbuf.rsvd2 >> 32); > > + > > + gem_sync(i915, a->handle); > > + gem_sync(i915, b->handle); > > + > > + cycles++; > > + } > > + > > + close(timeline); > > + > > + igt_spin_free(i915, a); > > + igt_spin_free(i915, b); > > + > > + gem_context_destroy(i915, A); > > + gem_context_destroy(i915, B); > > + > > + *out = cycles; > > +} > > + > > +static void bonded_dual(int i915) > > +{ > > + static const unsigned int phases[] = { > > + 0, > > + B_FENCE, > > + B_MANY, > > + B_HOSTILE, > > + B_HOSTILE | B_FENCE, > > + }; > > + unsigned long *cycles; > > + > > + > > + /* > > + * This is the same test as bonded_pair() but with the slight extra > > + * stress of having two inflight clients and interchanging them > > + * in a thread. > > + */ > > + igt_require(gem_scheduler_has_preemption(i915)); > > + > > + cycles = mmap(0, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); > > + > > + for (int class = 0; class < 32; class++) { > > + struct i915_engine_class_instance *siblings; > > + unsigned int count; > > + > > + siblings = list_engines(i915, 1u << class, &count); > > + if (count < 2) > > + continue; > > + > > + igt_info("Class %u, 1 thread\n", class); > > + for (int i = 0; i < ARRAY_SIZE(phases); i++) { > > + cycles[0] = 0; > > + __bonded_dual(i915, > > + siblings, count, > > + phases[i], > > + &cycles[0]); > > + gem_quiescent_gpu(i915); > > + igt_info("%s %s %s submission, %lu cycles\n", > > + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", > > + phases[i] & B_MANY ? "many-master" : "single-master", > > + phases[i] & B_FENCE ? "fenced" : "immediate", > > + cycles[0]); > > + } > > + > > + igt_info("Class %u, %d threads\n", class, count + 1); > > + for (int i = 0; i < ARRAY_SIZE(phases); i++) { > > + memset(cycles, 0, (count + 1) * sizeof(*cycles)); > > + igt_fork(child, count + 1) > > + __bonded_dual(i915, > > + siblings, count, > > + phases[i], > > + &cycles[child]); > > + igt_waitchildren(); > > + gem_quiescent_gpu(i915); > > + > > + for (int child = 1; child < count + 1; child++) > > + cycles[0] += cycles[child]; > > + > > + igt_info("%s %s %s submission, %lu cycles\n", > > + phases[i] & B_HOSTILE ? "Non-preemptible" : "Preemptible", > > + phases[i] & B_MANY ? "many-master" : "single-master", > > + phases[i] & B_FENCE ? "fenced" : "immediate", > > + cycles[0]); > > + } > > + > > + free(siblings); > > + } > > + > > + munmap(cycles, 4096); > > +} > > + > > static void __bonded_nohang(int i915, uint32_t ctx, > > const struct i915_engine_class_instance *siblings, > > unsigned int count, > > @@ -2284,6 +2620,11 @@ igt_main > > igt_subtest("bonded-semaphore") > > bonded_semaphore(i915); > > > > + igt_subtest("bonded-pair") > > + bonded_pair(i915); > > + igt_subtest("bonded-dual") > > + bonded_dual(i915); > > + > > igt_fixture { > > igt_stop_hang_detector(); > > } > > > > > "Runner" (non underscore functions) could have been shared easily but okay: Copy-n-paste, 2 keypresses. Sharing, many. I was saving Joules but not electronvolts. -Chris _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 8+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for i915/gem_exec_balancer: Randomise bonded submission (rev3) 2020-05-29 13:58 ` [igt-dev] " Chris Wilson ` (2 preceding siblings ...) (?) @ 2020-05-29 16:53 ` Patchwork -1 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2020-05-29 16:53 UTC (permalink / raw) To: Chris Wilson; +Cc: igt-dev == Series Details == Series: i915/gem_exec_balancer: Randomise bonded submission (rev3) URL : https://patchwork.freedesktop.org/series/77701/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8553_full -> IGTPW_4624_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with IGTPW_4624_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_4624_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in IGTPW_4624_full: ### IGT changes ### #### Possible regressions #### * igt@gem_busy@close-race: - shard-hsw: [PASS][1] -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-hsw2/igt@gem_busy@close-race.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-hsw4/igt@gem_busy@close-race.html * {igt@gem_exec_balancer@bonded-dual} (NEW): - shard-iclb: NOTRUN -> [FAIL][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-iclb2/igt@gem_exec_balancer@bonded-dual.html - shard-tglb: NOTRUN -> [FAIL][4] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-tglb1/igt@gem_exec_balancer@bonded-dual.html * {igt@gem_exec_balancer@bonded-pair} (NEW): - shard-kbl: NOTRUN -> [FAIL][5] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-kbl4/igt@gem_exec_balancer@bonded-pair.html New tests --------- New tests have been introduced between CI_DRM_8553_full and IGTPW_4624_full: ### New IGT tests (2) ### * igt@gem_exec_balancer@bonded-dual: - Statuses : 3 fail(s) 2 pass(s) 2 skip(s) - Exec time: [0.0, 33.09] s * igt@gem_exec_balancer@bonded-pair: - Statuses : 1 fail(s) 4 pass(s) 2 skip(s) - Exec time: [0.0, 32.42] s Known issues ------------ Here are the changes found in IGTPW_4624_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_pm_dc@dc6-psr: - shard-iclb: [PASS][6] -> [FAIL][7] ([i915#1899]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-iclb2/igt@i915_pm_dc@dc6-psr.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-iclb4/igt@i915_pm_dc@dc6-psr.html * igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen: - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#54]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-kbl7/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html - shard-apl: [PASS][10] -> [FAIL][11] ([i915#54]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-apl3/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-apl6/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][12] -> [DMESG-FAIL][13] ([i915#1926]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-hsw2/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-hsw1/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-kbl: [PASS][14] -> [INCOMPLETE][15] ([i915#155]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane@plane-position-covered-pipe-c-planes: - shard-kbl: [PASS][16] -> [DMESG-WARN][17] ([i915#165] / [i915#78]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-kbl6/igt@kms_plane@plane-position-covered-pipe-c-planes.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-kbl2/igt@kms_plane@plane-position-covered-pipe-c-planes.html * igt@kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant: - shard-apl: [PASS][18] -> [FAIL][19] ([fdo#108145] / [i915#265] / [i915#95]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-apl7/igt@kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html * igt@kms_psr2_su@frontbuffer: - shard-tglb: [PASS][20] -> [SKIP][21] ([i915#1911]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-tglb5/igt@kms_psr2_su@frontbuffer.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-tglb1/igt@kms_psr2_su@frontbuffer.html - shard-iclb: [PASS][22] -> [SKIP][23] ([fdo#109642] / [fdo#111068]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-iclb2/igt@kms_psr2_su@frontbuffer.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-iclb4/igt@kms_psr2_su@frontbuffer.html * igt@kms_psr@psr2_cursor_render: - shard-iclb: [PASS][24] -> [SKIP][25] ([fdo#109441]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-iclb2/igt@kms_psr@psr2_cursor_render.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-iclb5/igt@kms_psr@psr2_cursor_render.html * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend: - shard-iclb: [PASS][26] -> [INCOMPLETE][27] ([i915#1078] / [i915#1185]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-iclb6/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-iclb3/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html * igt@kms_vblank@pipe-b-accuracy-idle: - shard-glk: [PASS][28] -> [TIMEOUT][29] ([i915#1958]) +1 similar issue [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-glk6/igt@kms_vblank@pipe-b-accuracy-idle.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-glk8/igt@kms_vblank@pipe-b-accuracy-idle.html #### Possible fixes #### * igt@gem_softpin@noreloc-s3: - shard-kbl: [INCOMPLETE][30] ([i915#1959]) -> [PASS][31] [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-kbl6/igt@gem_softpin@noreloc-s3.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-kbl1/igt@gem_softpin@noreloc-s3.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-tglb: [SKIP][32] ([i915#1904]) -> [PASS][33] [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-tglb2/igt@i915_pm_dc@dc3co-vpb-simulation.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-tglb8/igt@i915_pm_dc@dc3co-vpb-simulation.html * igt@i915_pm_dc@dc5-psr: - shard-iclb: [FAIL][34] ([i915#1899]) -> [PASS][35] [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-iclb4/igt@i915_pm_dc@dc5-psr.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-iclb1/igt@i915_pm_dc@dc5-psr.html * igt@i915_suspend@fence-restore-untiled: - shard-kbl: [DMESG-WARN][36] ([i915#180]) -> [PASS][37] +2 similar issues [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-kbl1/igt@i915_suspend@fence-restore-untiled.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-kbl3/igt@i915_suspend@fence-restore-untiled.html * {igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-c}: - shard-kbl: [DMESG-WARN][38] ([i915#165] / [i915#180]) -> [PASS][39] [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-kbl2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-c.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-kbl1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-c.html * igt@kms_cursor_legacy@cursora-vs-flipb-toggle: - shard-glk: [DMESG-FAIL][40] ([i915#1925] / [i915#1926]) -> [PASS][41] [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-glk7/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-glk1/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html * igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled: - shard-kbl: [FAIL][42] ([i915#177] / [i915#52] / [i915#54] / [i915#93] / [i915#95]) -> [PASS][43] +1 similar issue [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-kbl4/igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-kbl3/igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled.html * igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled: - shard-apl: [FAIL][44] ([i915#52] / [i915#54] / [i915#95]) -> [PASS][45] +1 similar issue [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-apl6/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-apl6/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html * igt@kms_fbcon_fbt@psr-suspend: - shard-iclb: [INCOMPLETE][46] ([i915#1185]) -> [PASS][47] [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-iclb3/igt@kms_fbcon_fbt@psr-suspend.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-iclb6/igt@kms_fbcon_fbt@psr-suspend.html * igt@kms_hdmi_inject@inject-audio: - shard-tglb: [SKIP][48] ([i915#433]) -> [PASS][49] [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-tglb2/igt@kms_hdmi_inject@inject-audio.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-tglb2/igt@kms_hdmi_inject@inject-audio.html * igt@kms_panel_fitting@atomic-fastset: - shard-tglb: [FAIL][50] ([i915#83]) -> [PASS][51] [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-tglb5/igt@kms_panel_fitting@atomic-fastset.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-tglb5/igt@kms_panel_fitting@atomic-fastset.html - shard-iclb: [FAIL][52] ([i915#83]) -> [PASS][53] [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-iclb2/igt@kms_panel_fitting@atomic-fastset.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-iclb8/igt@kms_panel_fitting@atomic-fastset.html * igt@kms_plane_cursor@pipe-a-overlay-size-256: - shard-apl: [FAIL][54] ([i915#1559] / [i915#95]) -> [PASS][55] [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-apl2/igt@kms_plane_cursor@pipe-a-overlay-size-256.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-apl3/igt@kms_plane_cursor@pipe-a-overlay-size-256.html * igt@kms_plane_cursor@pipe-a-viewport-size-64: - shard-kbl: [FAIL][56] ([i915#1559] / [i915#93] / [i915#95]) -> [PASS][57] +1 similar issue [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-kbl4/igt@kms_plane_cursor@pipe-a-viewport-size-64.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-kbl4/igt@kms_plane_cursor@pipe-a-viewport-size-64.html * igt@kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [SKIP][58] ([fdo#109441]) -> [PASS][59] +1 similar issue [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-iclb4/igt@kms_psr@psr2_primary_mmap_cpu.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html * igt@kms_vblank@pipe-b-ts-continuation-suspend: - shard-apl: [DMESG-WARN][60] ([i915#180]) -> [PASS][61] +1 similar issue [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-apl4/igt@kms_vblank@pipe-b-ts-continuation-suspend.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-apl1/igt@kms_vblank@pipe-b-ts-continuation-suspend.html - shard-kbl: [INCOMPLETE][62] ([i915#155]) -> [PASS][63] [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-kbl3/igt@kms_vblank@pipe-b-ts-continuation-suspend.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-kbl6/igt@kms_vblank@pipe-b-ts-continuation-suspend.html * igt@perf@mi-rpc: - shard-hsw: [INCOMPLETE][64] ([i915#61]) -> [PASS][65] [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-hsw5/igt@perf@mi-rpc.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-hsw7/igt@perf@mi-rpc.html * {igt@perf@polling-parameterized}: - shard-hsw: [FAIL][66] ([i915#1542]) -> [PASS][67] [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-hsw6/igt@perf@polling-parameterized.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-hsw7/igt@perf@polling-parameterized.html #### Warnings #### * igt@i915_pm_dc@dc6-psr: - shard-tglb: [FAIL][68] ([i915#454]) -> [FAIL][69] ([i915#1899]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-tglb1/igt@i915_pm_dc@dc6-psr.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-tglb1/igt@i915_pm_dc@dc6-psr.html * igt@kms_color_chamelium@pipe-c-ctm-0-75: - shard-glk: [SKIP][70] ([fdo#109271] / [fdo#111827]) -> [TIMEOUT][71] ([i915#1366] / [i915#1958]) [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-glk7/igt@kms_color_chamelium@pipe-c-ctm-0-75.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-glk8/igt@kms_color_chamelium@pipe-c-ctm-0-75.html * igt@kms_content_protection@lic: - shard-apl: [TIMEOUT][72] ([i915#1319]) -> [TIMEOUT][73] ([i915#1319] / [i915#1635]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-apl7/igt@kms_content_protection@lic.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-apl2/igt@kms_content_protection@lic.html * igt@kms_content_protection@uevent: - shard-kbl: [FAIL][74] ([i915#357]) -> [FAIL][75] ([i915#357] / [i915#93] / [i915#95]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-kbl3/igt@kms_content_protection@uevent.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-kbl6/igt@kms_content_protection@uevent.html - shard-apl: [FAIL][76] ([i915#357]) -> [FAIL][77] ([i915#357] / [i915#95]) [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-apl4/igt@kms_content_protection@uevent.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-apl1/igt@kms_content_protection@uevent.html * igt@kms_plane_lowres@pipe-b-tiling-yf: - shard-hsw: [SKIP][78] ([fdo#109271] / [i915#1927]) -> [SKIP][79] ([fdo#109271]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-hsw2/igt@kms_plane_lowres@pipe-b-tiling-yf.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-hsw2/igt@kms_plane_lowres@pipe-b-tiling-yf.html * igt@kms_psr2_su@page_flip: - shard-iclb: [SKIP][80] ([fdo#109642] / [fdo#111068]) -> [FAIL][81] ([i915#608]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8553/shard-iclb7/igt@kms_psr2_su@page_flip.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/shard-iclb2/igt@kms_psr2_su@page_flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1078]: https://gitlab.freedesktop.org/drm/intel/issues/1078 [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1366]: https://gitlab.freedesktop.org/drm/intel/issues/1366 [i915#1519]: https://gitlab.freedesktop.org/drm/intel/issues/1519 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1559]: https://gitlab.freedesktop.org/drm/intel/issues/1559 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#177]: https://gitlab.freedesktop.org/drm/intel/issues/177 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899 [i915#1904]: https://gitlab.freedesktop.org/drm/intel/issues/1904 [i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1927]: https://gitlab.freedesktop.org/drm/intel/issues/1927 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1959]: https://gitlab.freedesktop.org/drm/intel/issues/1959 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#357]: https://gitlab.freedesktop.org/drm/intel/issues/357 [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#608]: https://gitlab.freedesktop.org/drm/intel/issues/608 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78 [i915#83]: https://gitlab.freedesktop.org/drm/intel/issues/83 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 8) ------------------------------ Missing (3): pig-skl-6260u pig-glk-j5005 pig-icl-1065g7 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5683 -> IGTPW_4624 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_8553: 9f1b8b4fcb466dc714b1f825fd93e3bbd29c7de6 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_4624: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/index.html IGT_5683: 757b6e72d546fd2dbc3801a73796d67b0854021b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4624/index.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-05-29 16:53 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-05-29 13:58 [Intel-gfx] [PATCH i-g-t v3] i915/gem_exec_balancer: Randomise bonded submission Chris Wilson 2020-05-29 13:58 ` [igt-dev] " Chris Wilson 2020-05-29 14:34 ` [igt-dev] ✓ Fi.CI.BAT: success for i915/gem_exec_balancer: Randomise bonded submission (rev3) Patchwork 2020-05-29 15:08 ` [Intel-gfx] [igt-dev] [PATCH i-g-t v3] i915/gem_exec_balancer: Randomise bonded submission Tvrtko Ursulin 2020-05-29 15:08 ` Tvrtko Ursulin 2020-05-29 15:13 ` [Intel-gfx] " Chris Wilson 2020-05-29 15:13 ` Chris Wilson 2020-05-29 16:53 ` [igt-dev] ✗ Fi.CI.IGT: failure for i915/gem_exec_balancer: Randomise bonded submission (rev3) Patchwork
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