[PATCH v2 0/3] CPUCFG emulation future-proofing & HWCAP addition

[PATCH v2 0/3] CPUCFG emulation future-proofing & HWCAP addition

[WANG Xuerui]

This patch series future-proofs the CPUCFG emulation, in light of
possibility of new Loongson cores still lacking native CPUCFG.
Also an HWCAP flag bit is allocated and exposed for userspace's probing
convenience, per the earlier plan shared on the mailing list.

Tested on Loongson-3A3000 and Loongson-3A4000. Compile-tested with
64r2_defconfig.

v2:
- unconditionally bump PERF_COUNT_SW_EMULATION_FAULTS even on
  unsupported core models
- reordered model match arms per Huacai's review
- tweaked commit message of 2nd patch

WANG Xuerui (3):
  MIPS: Loongson64: Guard against future cores without CPUCFG
  MIPS: Expose Loongson CPUCFG availability via HWCAP
  MIPS: Loongson64: Reorder CPUCFG model match arms

 .../include/asm/mach-loongson64/cpucfg-emul.h | 11 +++
 arch/mips/include/uapi/asm/hwcap.h            |  1 +
 arch/mips/kernel/traps.c                      |  4 ++
 arch/mips/loongson64/cpucfg-emul.c            | 70 +++++++++++--------
 4 files changed, 56 insertions(+), 30 deletions(-)

-- 
2.26.2

[PATCH v2 1/3] MIPS: Loongson64: Guard against future cores without CPUCFG

[WANG Xuerui]

Previously it was thought that all future Loongson cores would come with
native CPUCFG. From new information shared by Huacai this is definitely
not true (maybe some future 2K cores, for example), so collisions at
PRID_REV level are inevitable. The CPU model matching needs to take
PRID_IMP into consideration.

The emulation logic needs to be disabled for those future cores as well,
as we cannot possibly encode their non-discoverable features right now.

Reported-by: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 .../include/asm/mach-loongson64/cpucfg-emul.h | 11 ++++++
 arch/mips/kernel/traps.c                      |  4 ++
 arch/mips/loongson64/cpucfg-emul.c            | 37 ++++++++++---------
 3 files changed, 35 insertions(+), 17 deletions(-)

diff --git a/arch/mips/include/asm/mach-loongson64/cpucfg-emul.h b/arch/mips/include/asm/mach-loongson64/cpucfg-emul.h
index 01dc308df7b2..d64af19c210d 100644
--- a/arch/mips/include/asm/mach-loongson64/cpucfg-emul.h
+++ b/arch/mips/include/asm/mach-loongson64/cpucfg-emul.h
@@ -12,6 +12,12 @@
 
 void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c);
 
+static inline bool loongson3_cpucfg_emulation_enabled(struct cpuinfo_mips *c)
+{
+	/* All supported cores have non-zero LOONGSON_CFG1 data. */
+	return c->loongson3_cpucfg_data[0] != 0;
+}
+
 static inline u32 loongson3_cpucfg_read_synthesized(struct cpuinfo_mips *c,
 	__u64 sel)
 {
@@ -53,6 +59,11 @@ static inline void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
 {
 }
 
+static inline bool loongson3_cpucfg_emulation_enabled(struct cpuinfo_mips *c)
+{
+	return false;
+}
+
 static inline u32 loongson3_cpucfg_read_synthesized(struct cpuinfo_mips *c,
 	__u64 sel)
 {
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 2d5b16daf331..22f805a73921 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -722,6 +722,10 @@ static int simulate_loongson3_cpucfg(struct pt_regs *regs,
 
 		perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
 
+		/* Do not emulate on unsupported core models. */
+		if (!loongson3_cpucfg_emulation_enabled(&current_cpu_data))
+			return -1;
+
 		regs->regs[rd] = loongson3_cpucfg_read_synthesized(
 			&current_cpu_data, sel);
 
diff --git a/arch/mips/loongson64/cpucfg-emul.c b/arch/mips/loongson64/cpucfg-emul.c
index fdd52b21c1df..c16023a13379 100644
--- a/arch/mips/loongson64/cpucfg-emul.c
+++ b/arch/mips/loongson64/cpucfg-emul.c
@@ -134,13 +134,9 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
 	c->loongson3_cpucfg_data[1] = 0;
 	c->loongson3_cpucfg_data[2] = 0;
 
-	/* Add CPUCFG features non-discoverable otherwise.
-	 *
-	 * All Loongson processors covered by CPUCFG emulation have distinct
-	 * PRID_REV, so take advantage of this.
-	 */
-	switch (c->processor_id & PRID_REV_MASK) {
-	case PRID_REV_LOONGSON3A_R1:
+	/* Add CPUCFG features non-discoverable otherwise. */
+	switch (c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) {
+	case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R1:
 		c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
 			LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LSUCA |
 			LOONGSON_CFG1_LLSYNC | LOONGSON_CFG1_TGTSYNC);
@@ -153,8 +149,8 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
 			LOONGSON_CFG3_LCAMVW_REV1);
 		break;
 
-	case PRID_REV_LOONGSON3B_R1:
-	case PRID_REV_LOONGSON3B_R2:
+	case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3B_R1:
+	case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3B_R2:
 		c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
 			LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LSUCA |
 			LOONGSON_CFG1_LLSYNC | LOONGSON_CFG1_TGTSYNC);
@@ -167,10 +163,10 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
 			LOONGSON_CFG3_LCAMVW_REV1);
 		break;
 
-	case PRID_REV_LOONGSON2K_R1_0:
-	case PRID_REV_LOONGSON2K_R1_1:
-	case PRID_REV_LOONGSON2K_R1_2:
-	case PRID_REV_LOONGSON2K_R1_3:
+	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_0:
+	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_1:
+	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_2:
+	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_3:
 		decode_loongson_config6(c);
 		probe_uca(c);
 
@@ -183,10 +179,10 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
 		c->loongson3_cpucfg_data[2] = 0;
 		break;
 
-	case PRID_REV_LOONGSON3A_R2_0:
-	case PRID_REV_LOONGSON3A_R2_1:
-	case PRID_REV_LOONGSON3A_R3_0:
-	case PRID_REV_LOONGSON3A_R3_1:
+	case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0:
+	case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_1:
+	case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R3_0:
+	case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R3_1:
 		decode_loongson_config6(c);
 		probe_uca(c);
 
@@ -203,6 +199,13 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
 			LOONGSON_CFG3_LCAMKW_REV1 |
 			LOONGSON_CFG3_LCAMVW_REV1);
 		break;
+
+	default:
+		/* It is possible that some future Loongson cores still do
+		 * not have CPUCFG, so do not emulate anything for these
+		 * cores.
+		 */
+		return;
 	}
 
 	/* This feature is set by firmware, but all known Loongson-64 systems
-- 
2.26.2

[PATCH v2 2/3] MIPS: Expose Loongson CPUCFG availability via HWCAP

[WANG Xuerui]

The point is to allow userspace to probe for CPUCFG without possibly
triggering invalid instructions. In addition to that, future Loongson
feature bits could all be stuffed into CPUCFG bit fields (or "leaves"
in x86-speak) if Loongson does not make mistakes, so ELF HWCAP bits are
conserved.

Userspace can determine native CPUCFG availability by checking the LCSRP
(Loongson CSR Present) bit in CPUCFG output after seeing CPUCFG bit in
HWCAP. Native CPUCFG always sets the LCSRP bit, as CPUCFG is part of the
Loongson CSR ASE, while the emulation intentionally leaves this bit
clear.

The other existing Loongson-specific HWCAP bits are, to my best
knowledge, unused, as

(1) they are fairly recent additions,
(2) Loongson never back-ported the patch into their kernel fork, and
(3) Loongson's existing installed base rarely upgrade, if ever;

However, they are still considered userspace ABI, hence unfortunately
unremovable. But hopefully at least we could stop adding new Loongson
HWCAP bits in the future.

Cc: Paul Burton <paulburton@kernel.org>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Huacai Chen <chenhc@lemote.com>
Signed-off-by: WANG Xuerui <git@xen0n.name>
---

v2: tweaked commit message.

 arch/mips/include/uapi/asm/hwcap.h | 1 +
 arch/mips/loongson64/cpucfg-emul.c | 9 ++++++++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/uapi/asm/hwcap.h b/arch/mips/include/uapi/asm/hwcap.h
index 1ade1daa4921..b7e02bdc1985 100644
--- a/arch/mips/include/uapi/asm/hwcap.h
+++ b/arch/mips/include/uapi/asm/hwcap.h
@@ -17,5 +17,6 @@
 #define HWCAP_LOONGSON_MMI  (1 << 11)
 #define HWCAP_LOONGSON_EXT  (1 << 12)
 #define HWCAP_LOONGSON_EXT2 (1 << 13)
+#define HWCAP_LOONGSON_CPUCFG (1 << 14)
 
 #endif /* _UAPI_ASM_HWCAP_H */
diff --git a/arch/mips/loongson64/cpucfg-emul.c b/arch/mips/loongson64/cpucfg-emul.c
index c16023a13379..ca75f07252df 100644
--- a/arch/mips/loongson64/cpucfg-emul.c
+++ b/arch/mips/loongson64/cpucfg-emul.c
@@ -4,6 +4,7 @@
 #include <linux/types.h>
 #include <asm/cpu.h>
 #include <asm/cpu-info.h>
+#include <asm/elf.h>
 
 #include <loongson_regs.h>
 #include <cpucfg-emul.h>
@@ -128,7 +129,7 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
 
 	/* CPUs with CPUCFG support don't need to synthesize anything. */
 	if (cpu_has_cfg())
-		return;
+		goto have_cpucfg_now;
 
 	c->loongson3_cpucfg_data[0] = 0;
 	c->loongson3_cpucfg_data[1] = 0;
@@ -217,4 +218,10 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
 	patch_cpucfg_sel1(c);
 	patch_cpucfg_sel2(c);
 	patch_cpucfg_sel3(c);
+
+have_cpucfg_now:
+	/* We have usable CPUCFG now, emulated or not.
+	 * Announce CPUCFG availability to userspace via hwcap.
+	 */
+	elf_hwcap |= HWCAP_LOONGSON_CPUCFG;
 }
-- 
2.26.2

[PATCH v2 3/3] MIPS: Loongson64: Reorder CPUCFG model match arms

[WANG Xuerui]

Originally the match arms are ordered by model release date, however
the LOONGSON_64R cores are even more reduced capability-wise. So put
them at top of the switch block.

Suggested-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/mips/loongson64/cpucfg-emul.c | 32 +++++++++++++++---------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/mips/loongson64/cpucfg-emul.c b/arch/mips/loongson64/cpucfg-emul.c
index ca75f07252df..cd619b47ba1f 100644
--- a/arch/mips/loongson64/cpucfg-emul.c
+++ b/arch/mips/loongson64/cpucfg-emul.c
@@ -137,6 +137,22 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
 
 	/* Add CPUCFG features non-discoverable otherwise. */
 	switch (c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) {
+	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_0:
+	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_1:
+	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_2:
+	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_3:
+		decode_loongson_config6(c);
+		probe_uca(c);
+
+		c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
+			LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LLSYNC |
+			LOONGSON_CFG1_TGTSYNC);
+		c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
+			LOONGSON_CFG2_LBT2 | LOONGSON_CFG2_LPMP |
+			LOONGSON_CFG2_LPM_REV2);
+		c->loongson3_cpucfg_data[2] = 0;
+		break;
+
 	case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R1:
 		c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
 			LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LSUCA |
@@ -164,22 +180,6 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
 			LOONGSON_CFG3_LCAMVW_REV1);
 		break;
 
-	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_0:
-	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_1:
-	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_2:
-	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_3:
-		decode_loongson_config6(c);
-		probe_uca(c);
-
-		c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
-			LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LLSYNC |
-			LOONGSON_CFG1_TGTSYNC);
-		c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
-			LOONGSON_CFG2_LBT2 | LOONGSON_CFG2_LPMP |
-			LOONGSON_CFG2_LPM_REV2);
-		c->loongson3_cpucfg_data[2] = 0;
-		break;
-
 	case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0:
 	case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_1:
 	case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R3_0:
-- 
2.26.2

Re: [PATCH v2 1/3] MIPS: Loongson64: Guard against future cores without CPUCFG

[Huacai Chen]

Reviewed-by: Huacai Chen <chenhc@lemote.com>

On Sat, May 30, 2020 at 3:34 PM WANG Xuerui <git@xen0n.name> wrote:
>
> Previously it was thought that all future Loongson cores would come with
> native CPUCFG. From new information shared by Huacai this is definitely
> not true (maybe some future 2K cores, for example), so collisions at
> PRID_REV level are inevitable. The CPU model matching needs to take
> PRID_IMP into consideration.
>
> The emulation logic needs to be disabled for those future cores as well,
> as we cannot possibly encode their non-discoverable features right now.
>
> Reported-by: Huacai Chen <chenhc@lemote.com>
> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Signed-off-by: WANG Xuerui <git@xen0n.name>
> ---
>  .../include/asm/mach-loongson64/cpucfg-emul.h | 11 ++++++
>  arch/mips/kernel/traps.c                      |  4 ++
>  arch/mips/loongson64/cpucfg-emul.c            | 37 ++++++++++---------
>  3 files changed, 35 insertions(+), 17 deletions(-)
>
> diff --git a/arch/mips/include/asm/mach-loongson64/cpucfg-emul.h b/arch/mips/include/asm/mach-loongson64/cpucfg-emul.h
> index 01dc308df7b2..d64af19c210d 100644
> --- a/arch/mips/include/asm/mach-loongson64/cpucfg-emul.h
> +++ b/arch/mips/include/asm/mach-loongson64/cpucfg-emul.h
> @@ -12,6 +12,12 @@
>
>  void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c);
>
> +static inline bool loongson3_cpucfg_emulation_enabled(struct cpuinfo_mips *c)
> +{
> +       /* All supported cores have non-zero LOONGSON_CFG1 data. */
> +       return c->loongson3_cpucfg_data[0] != 0;
> +}
> +
>  static inline u32 loongson3_cpucfg_read_synthesized(struct cpuinfo_mips *c,
>         __u64 sel)
>  {
> @@ -53,6 +59,11 @@ static inline void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
>  {
>  }
>
> +static inline bool loongson3_cpucfg_emulation_enabled(struct cpuinfo_mips *c)
> +{
> +       return false;
> +}
> +
>  static inline u32 loongson3_cpucfg_read_synthesized(struct cpuinfo_mips *c,
>         __u64 sel)
>  {
> diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
> index 2d5b16daf331..22f805a73921 100644
> --- a/arch/mips/kernel/traps.c
> +++ b/arch/mips/kernel/traps.c
> @@ -722,6 +722,10 @@ static int simulate_loongson3_cpucfg(struct pt_regs *regs,
>
>                 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
>
> +               /* Do not emulate on unsupported core models. */
> +               if (!loongson3_cpucfg_emulation_enabled(&current_cpu_data))
> +                       return -1;
> +
>                 regs->regs[rd] = loongson3_cpucfg_read_synthesized(
>                         &current_cpu_data, sel);
>
> diff --git a/arch/mips/loongson64/cpucfg-emul.c b/arch/mips/loongson64/cpucfg-emul.c
> index fdd52b21c1df..c16023a13379 100644
> --- a/arch/mips/loongson64/cpucfg-emul.c
> +++ b/arch/mips/loongson64/cpucfg-emul.c
> @@ -134,13 +134,9 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
>         c->loongson3_cpucfg_data[1] = 0;
>         c->loongson3_cpucfg_data[2] = 0;
>
> -       /* Add CPUCFG features non-discoverable otherwise.
> -        *
> -        * All Loongson processors covered by CPUCFG emulation have distinct
> -        * PRID_REV, so take advantage of this.
> -        */
> -       switch (c->processor_id & PRID_REV_MASK) {
> -       case PRID_REV_LOONGSON3A_R1:
> +       /* Add CPUCFG features non-discoverable otherwise. */
> +       switch (c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) {
> +       case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R1:
>                 c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
>                         LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LSUCA |
>                         LOONGSON_CFG1_LLSYNC | LOONGSON_CFG1_TGTSYNC);
> @@ -153,8 +149,8 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
>                         LOONGSON_CFG3_LCAMVW_REV1);
>                 break;
>
> -       case PRID_REV_LOONGSON3B_R1:
> -       case PRID_REV_LOONGSON3B_R2:
> +       case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3B_R1:
> +       case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3B_R2:
>                 c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
>                         LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LSUCA |
>                         LOONGSON_CFG1_LLSYNC | LOONGSON_CFG1_TGTSYNC);
> @@ -167,10 +163,10 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
>                         LOONGSON_CFG3_LCAMVW_REV1);
>                 break;
>
> -       case PRID_REV_LOONGSON2K_R1_0:
> -       case PRID_REV_LOONGSON2K_R1_1:
> -       case PRID_REV_LOONGSON2K_R1_2:
> -       case PRID_REV_LOONGSON2K_R1_3:
> +       case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_0:
> +       case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_1:
> +       case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_2:
> +       case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_3:
>                 decode_loongson_config6(c);
>                 probe_uca(c);
>
> @@ -183,10 +179,10 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
>                 c->loongson3_cpucfg_data[2] = 0;
>                 break;
>
> -       case PRID_REV_LOONGSON3A_R2_0:
> -       case PRID_REV_LOONGSON3A_R2_1:
> -       case PRID_REV_LOONGSON3A_R3_0:
> -       case PRID_REV_LOONGSON3A_R3_1:
> +       case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0:
> +       case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_1:
> +       case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R3_0:
> +       case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R3_1:
>                 decode_loongson_config6(c);
>                 probe_uca(c);
>
> @@ -203,6 +199,13 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
>                         LOONGSON_CFG3_LCAMKW_REV1 |
>                         LOONGSON_CFG3_LCAMVW_REV1);
>                 break;
> +
> +       default:
> +               /* It is possible that some future Loongson cores still do
> +                * not have CPUCFG, so do not emulate anything for these
> +                * cores.
> +                */
> +               return;
>         }
>
>         /* This feature is set by firmware, but all known Loongson-64 systems
> --
> 2.26.2
>

Re: [PATCH v2 2/3] MIPS: Expose Loongson CPUCFG availability via HWCAP

[Huacai Chen]

Reviewed-by: Huacai Chen <chenhc@lemote.com>

On Sat, May 30, 2020 at 3:34 PM WANG Xuerui <git@xen0n.name> wrote:
>
> The point is to allow userspace to probe for CPUCFG without possibly
> triggering invalid instructions. In addition to that, future Loongson
> feature bits could all be stuffed into CPUCFG bit fields (or "leaves"
> in x86-speak) if Loongson does not make mistakes, so ELF HWCAP bits are
> conserved.
>
> Userspace can determine native CPUCFG availability by checking the LCSRP
> (Loongson CSR Present) bit in CPUCFG output after seeing CPUCFG bit in
> HWCAP. Native CPUCFG always sets the LCSRP bit, as CPUCFG is part of the
> Loongson CSR ASE, while the emulation intentionally leaves this bit
> clear.
>
> The other existing Loongson-specific HWCAP bits are, to my best
> knowledge, unused, as
>
> (1) they are fairly recent additions,
> (2) Loongson never back-ported the patch into their kernel fork, and
> (3) Loongson's existing installed base rarely upgrade, if ever;
>
> However, they are still considered userspace ABI, hence unfortunately
> unremovable. But hopefully at least we could stop adding new Loongson
> HWCAP bits in the future.
>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Cc: Huacai Chen <chenhc@lemote.com>
> Signed-off-by: WANG Xuerui <git@xen0n.name>
> ---
>
> v2: tweaked commit message.
>
>  arch/mips/include/uapi/asm/hwcap.h | 1 +
>  arch/mips/loongson64/cpucfg-emul.c | 9 ++++++++-
>  2 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/arch/mips/include/uapi/asm/hwcap.h b/arch/mips/include/uapi/asm/hwcap.h
> index 1ade1daa4921..b7e02bdc1985 100644
> --- a/arch/mips/include/uapi/asm/hwcap.h
> +++ b/arch/mips/include/uapi/asm/hwcap.h
> @@ -17,5 +17,6 @@
>  #define HWCAP_LOONGSON_MMI  (1 << 11)
>  #define HWCAP_LOONGSON_EXT  (1 << 12)
>  #define HWCAP_LOONGSON_EXT2 (1 << 13)
> +#define HWCAP_LOONGSON_CPUCFG (1 << 14)
>
>  #endif /* _UAPI_ASM_HWCAP_H */
> diff --git a/arch/mips/loongson64/cpucfg-emul.c b/arch/mips/loongson64/cpucfg-emul.c
> index c16023a13379..ca75f07252df 100644
> --- a/arch/mips/loongson64/cpucfg-emul.c
> +++ b/arch/mips/loongson64/cpucfg-emul.c
> @@ -4,6 +4,7 @@
>  #include <linux/types.h>
>  #include <asm/cpu.h>
>  #include <asm/cpu-info.h>
> +#include <asm/elf.h>
>
>  #include <loongson_regs.h>
>  #include <cpucfg-emul.h>
> @@ -128,7 +129,7 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
>
>         /* CPUs with CPUCFG support don't need to synthesize anything. */
>         if (cpu_has_cfg())
> -               return;
> +               goto have_cpucfg_now;
>
>         c->loongson3_cpucfg_data[0] = 0;
>         c->loongson3_cpucfg_data[1] = 0;
> @@ -217,4 +218,10 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
>         patch_cpucfg_sel1(c);
>         patch_cpucfg_sel2(c);
>         patch_cpucfg_sel3(c);
> +
> +have_cpucfg_now:
> +       /* We have usable CPUCFG now, emulated or not.
> +        * Announce CPUCFG availability to userspace via hwcap.
> +        */
> +       elf_hwcap |= HWCAP_LOONGSON_CPUCFG;
>  }
> --
> 2.26.2
>

Re: [PATCH v2 3/3] MIPS: Loongson64: Reorder CPUCFG model match arms

[Huacai Chen]

Reviewed-by: Huacai Chen <chenhc@lemote.com>

On Sat, May 30, 2020 at 3:34 PM WANG Xuerui <git@xen0n.name> wrote:
>
> Originally the match arms are ordered by model release date, however
> the LOONGSON_64R cores are even more reduced capability-wise. So put
> them at top of the switch block.
>
> Suggested-by: Huacai Chen <chenhc@lemote.com>
> Signed-off-by: WANG Xuerui <git@xen0n.name>
> ---
>  arch/mips/loongson64/cpucfg-emul.c | 32 +++++++++++++++---------------
>  1 file changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/arch/mips/loongson64/cpucfg-emul.c b/arch/mips/loongson64/cpucfg-emul.c
> index ca75f07252df..cd619b47ba1f 100644
> --- a/arch/mips/loongson64/cpucfg-emul.c
> +++ b/arch/mips/loongson64/cpucfg-emul.c
> @@ -137,6 +137,22 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
>
>         /* Add CPUCFG features non-discoverable otherwise. */
>         switch (c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) {
> +       case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_0:
> +       case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_1:
> +       case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_2:
> +       case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_3:
> +               decode_loongson_config6(c);
> +               probe_uca(c);
> +
> +               c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
> +                       LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LLSYNC |
> +                       LOONGSON_CFG1_TGTSYNC);
> +               c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
> +                       LOONGSON_CFG2_LBT2 | LOONGSON_CFG2_LPMP |
> +                       LOONGSON_CFG2_LPM_REV2);
> +               c->loongson3_cpucfg_data[2] = 0;
> +               break;
> +
>         case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R1:
>                 c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
>                         LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LSUCA |
> @@ -164,22 +180,6 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
>                         LOONGSON_CFG3_LCAMVW_REV1);
>                 break;
>
> -       case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_0:
> -       case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_1:
> -       case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_2:
> -       case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_3:
> -               decode_loongson_config6(c);
> -               probe_uca(c);
> -
> -               c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
> -                       LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LLSYNC |
> -                       LOONGSON_CFG1_TGTSYNC);
> -               c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
> -                       LOONGSON_CFG2_LBT2 | LOONGSON_CFG2_LPMP |
> -                       LOONGSON_CFG2_LPM_REV2);
> -               c->loongson3_cpucfg_data[2] = 0;
> -               break;
> -
>         case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0:
>         case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_1:
>         case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R3_0:
> --
> 2.26.2
>

Re: [PATCH v2 0/3] CPUCFG emulation future-proofing & HWCAP addition

[Thomas Bogendoerfer]

On Sat, May 30, 2020 at 03:32:40PM +0800, WANG Xuerui wrote:
> This patch series future-proofs the CPUCFG emulation, in light of
> possibility of new Loongson cores still lacking native CPUCFG.
> Also an HWCAP flag bit is allocated and exposed for userspace's probing
> convenience, per the earlier plan shared on the mailing list.
> 
> Tested on Loongson-3A3000 and Loongson-3A4000. Compile-tested with
> 64r2_defconfig.
> 
> v2:
> - unconditionally bump PERF_COUNT_SW_EMULATION_FAULTS even on
>   unsupported core models
> - reordered model match arms per Huacai's review
> - tweaked commit message of 2nd patch
> 
> WANG Xuerui (3):
>   MIPS: Loongson64: Guard against future cores without CPUCFG
>   MIPS: Expose Loongson CPUCFG availability via HWCAP
>   MIPS: Loongson64: Reorder CPUCFG model match arms
> 
>  .../include/asm/mach-loongson64/cpucfg-emul.h | 11 +++
>  arch/mips/include/uapi/asm/hwcap.h            |  1 +
>  arch/mips/kernel/traps.c                      |  4 ++
>  arch/mips/loongson64/cpucfg-emul.c            | 70 +++++++++++--------
>  4 files changed, 56 insertions(+), 30 deletions(-)

series applied to mips-next.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]