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* [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM
@ 2020-06-02 13:34 Zhiqiang Hou
  2020-06-02 13:34 ` [PATCHv2 01/36] dm: spi: Convert Freescale ESPI driver to driver model Zhiqiang Hou
                   ` (35 more replies)
  0 siblings, 36 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:34 UTC (permalink / raw)
  To: u-boot

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Merged the following 2 series and added P1010RDB boards into the
support list.
https://patchwork.ozlabs.org/project/uboot/list/?series=126119&archive=both&state=%2a
https://patchwork.ozlabs.org/project/uboot/list/?series=138873

Depends on:
https://patchwork.ozlabs.org/project/uboot/list/?series=180837

Chuanhua Han (4):
  dm: spi: Convert Freescale ESPI driver to driver model
  powerpc: dts: t2080: add espi controller node support
  powerpc: dts: t2080qds: add espi slave nodes support
  configs: enable espi device module in T2080QDS

Hou Zhiqiang (3):
  dts: P1010: Add eSPI controller DT node
  dts: P1010RDB: Add eSPI slave DT nodes
  configs: P1010RDB: Enable eSPI controller and SPI flash DM driver

Xiaowei Bao (29):
  dts: P1020: Add ESPI DT nodes
  dts: P1020RDB: Add ESPI slave device node
  configs: P1020RDB: Enable ESPI driver
  dts: P2020: Add ESPI DT nodes
  dts: P2020RDB: Add ESPI slave device node
  configs: P2020RDB: Enable ESPI driver
  dts: P2041: Add ESPI DT nodes
  dts: P2041RDB: Add ESPI slave device node
  configs: P2041RDB: Enable ESPI driver
  dts: P3041: Add ESPI DT nodes
  dts: P3041DS: Add ESPI slave device node
  configs: P3041DS: Enable ESPI driver
  dts: P4080: Add ESPI DT nodes
  dts: P4080DS: Add ESPI slave device node
  configs: P4080DS: Enable ESPI driver
  dts: P5040: Add ESPI DT nodes
  dts: P5040DS: Add ESPI slave device node
  configs: P5040DS: Enable ESPI driver
  dts: T102x: Add ESPI DT nodes
  dts: T1024RDB: Add ESPI slave device node
  configs: T1024RDB: Enable ESPI driver
  dts: T104x: Add ESPI DT nodes
  dts: T1042D4RDB: Add ESPI slave device node
  configs: T1042D4RDB: Enable ESPI driver
  dts: T2080RDB: Add ESPI slave device node
  configs: T2080RDB: Enable ESPI driver
  dts: T4240: Add ESPI DT nodes
  dts: T4240RDB: Add ESPI slave device node
  configs: T4240RDB: Enable ESPI driver

 arch/powerpc/dts/p1010rdb-pa.dts             |   1 +
 arch/powerpc/dts/p1010rdb-pa_36b.dts         |   1 +
 arch/powerpc/dts/p1010rdb.dtsi               |  17 +
 arch/powerpc/dts/p1010si-post.dtsi           |  10 +
 arch/powerpc/dts/p1020-post.dtsi             |   9 +
 arch/powerpc/dts/p1020rdb-pc.dts             |  15 +
 arch/powerpc/dts/p1020rdb-pc_36b.dts         |  15 +
 arch/powerpc/dts/p1020rdb-pd.dts             |  15 +
 arch/powerpc/dts/p2020-post.dtsi             |   9 +
 arch/powerpc/dts/p2020rdb-pc.dts             |  15 +
 arch/powerpc/dts/p2020rdb-pc_36b.dts         |  15 +
 arch/powerpc/dts/p2041.dtsi                  |   9 +
 arch/powerpc/dts/p2041rdb.dts                |  14 +
 arch/powerpc/dts/p3041.dtsi                  |   9 +
 arch/powerpc/dts/p3041ds.dts                 |  14 +
 arch/powerpc/dts/p4080.dtsi                  |   9 +
 arch/powerpc/dts/p4080ds.dts                 |  14 +
 arch/powerpc/dts/p5040.dtsi                  |   9 +
 arch/powerpc/dts/p5040ds.dts                 |  14 +
 arch/powerpc/dts/t1024rdb.dts                |  15 +
 arch/powerpc/dts/t102x.dtsi                  |   9 +
 arch/powerpc/dts/t1042d4rdb.dts              |  15 +
 arch/powerpc/dts/t104x.dtsi                  |   9 +
 arch/powerpc/dts/t2080.dtsi                  |  10 +
 arch/powerpc/dts/t2080qds.dts                |  33 ++
 arch/powerpc/dts/t2080rdb.dts                |  15 +
 arch/powerpc/dts/t4240.dtsi                  |   9 +
 arch/powerpc/dts/t4240rdb.dts                |  15 +
 configs/P1010RDB-PA_36BIT_NAND_defconfig     |   2 +
 configs/P1010RDB-PA_36BIT_NOR_defconfig      |   2 +
 configs/P1010RDB-PA_36BIT_SDCARD_defconfig   |   2 +
 configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig |   2 +
 configs/P1010RDB-PA_NAND_defconfig           |   2 +
 configs/P1010RDB-PA_NOR_defconfig            |   2 +
 configs/P1010RDB-PA_SDCARD_defconfig         |   2 +
 configs/P1010RDB-PA_SPIFLASH_defconfig       |   2 +
 configs/P1010RDB-PB_36BIT_NAND_defconfig     |   2 +
 configs/P1010RDB-PB_36BIT_NOR_defconfig      |   2 +
 configs/P1010RDB-PB_36BIT_SDCARD_defconfig   |   2 +
 configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig |   2 +
 configs/P1010RDB-PB_NAND_defconfig           |   2 +
 configs/P1010RDB-PB_NOR_defconfig            |   2 +
 configs/P1010RDB-PB_SDCARD_defconfig         |   2 +
 configs/P1010RDB-PB_SPIFLASH_defconfig       |   2 +
 configs/P1020RDB-PC_36BIT_NAND_defconfig     |   2 +
 configs/P1020RDB-PC_36BIT_SDCARD_defconfig   |   2 +
 configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig |   2 +
 configs/P1020RDB-PC_36BIT_defconfig          |   2 +
 configs/P1020RDB-PC_NAND_defconfig           |   2 +
 configs/P1020RDB-PC_SDCARD_defconfig         |   2 +
 configs/P1020RDB-PC_SPIFLASH_defconfig       |   2 +
 configs/P1020RDB-PC_defconfig                |   2 +
 configs/P1020RDB-PD_NAND_defconfig           |   2 +
 configs/P1020RDB-PD_SDCARD_defconfig         |   2 +
 configs/P1020RDB-PD_SPIFLASH_defconfig       |   2 +
 configs/P1020RDB-PD_defconfig                |   2 +
 configs/P2020RDB-PC_36BIT_NAND_defconfig     |   2 +
 configs/P2020RDB-PC_36BIT_SDCARD_defconfig   |   2 +
 configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig |   2 +
 configs/P2020RDB-PC_36BIT_defconfig          |   2 +
 configs/P2020RDB-PC_NAND_defconfig           |   2 +
 configs/P2020RDB-PC_SDCARD_defconfig         |   2 +
 configs/P2020RDB-PC_SPIFLASH_defconfig       |   2 +
 configs/P2020RDB-PC_defconfig                |   2 +
 configs/P2041RDB_NAND_defconfig              |   2 +
 configs/P2041RDB_SDCARD_defconfig            |   2 +
 configs/P2041RDB_SPIFLASH_defconfig          |   2 +
 configs/P2041RDB_defconfig                   |   2 +
 configs/P3041DS_NAND_defconfig               |   2 +
 configs/P3041DS_SDCARD_defconfig             |   2 +
 configs/P3041DS_SPIFLASH_defconfig           |   2 +
 configs/P3041DS_defconfig                    |   2 +
 configs/P4080DS_SDCARD_defconfig             |   2 +
 configs/P4080DS_SPIFLASH_defconfig           |   2 +
 configs/P4080DS_defconfig                    |   2 +
 configs/P5040DS_NAND_defconfig               |   2 +
 configs/P5040DS_SDCARD_defconfig             |   2 +
 configs/P5040DS_SPIFLASH_defconfig           |   2 +
 configs/P5040DS_defconfig                    |   2 +
 configs/T1024RDB_NAND_defconfig              |   2 +
 configs/T1024RDB_SDCARD_defconfig            |   2 +
 configs/T1024RDB_SPIFLASH_defconfig          |   2 +
 configs/T1024RDB_defconfig                   |   2 +
 configs/T1042D4RDB_NAND_defconfig            |   2 +
 configs/T1042D4RDB_SDCARD_defconfig          |   2 +
 configs/T1042D4RDB_SPIFLASH_defconfig        |   2 +
 configs/T1042D4RDB_defconfig                 |   2 +
 configs/T2080QDS_NAND_defconfig              |   2 +
 configs/T2080QDS_SDCARD_defconfig            |   2 +
 configs/T2080QDS_SECURE_BOOT_defconfig       |   2 +
 configs/T2080QDS_SPIFLASH_defconfig          |   2 +
 configs/T2080QDS_SRIO_PCIE_BOOT_defconfig    |   2 +
 configs/T2080QDS_defconfig                   |   2 +
 configs/T2080RDB_NAND_defconfig              |   2 +
 configs/T2080RDB_SDCARD_defconfig            |   2 +
 configs/T2080RDB_SPIFLASH_defconfig          |   2 +
 configs/T2080RDB_defconfig                   |   2 +
 configs/T4240RDB_SDCARD_defconfig            |   2 +
 configs/T4240RDB_defconfig                   |   2 +
 drivers/spi/fsl_espi.c                       | 444 ++++++++++++++-----
 include/dm/platform_data/fsl_espi.h          |  16 +
 101 files changed, 823 insertions(+), 123 deletions(-)
 create mode 100644 include/dm/platform_data/fsl_espi.h

-- 
2.17.1

^ permalink raw reply	[flat|nested] 41+ messages in thread
* [PATCHv2 01/36] dm: spi: Convert Freescale ESPI driver to driver model
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
@ 2020-06-02 13:34 ` Zhiqiang Hou
  2020-06-02 19:28   ` Jagan Teki
  2020-06-02 13:34 ` [PATCHv2 02/36] powerpc: dts: t2080: add espi controller node support Zhiqiang Hou
                   ` (34 subsequent siblings)
  35 siblings, 1 reply; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:34 UTC (permalink / raw)
  To: u-boot

From: Chuanhua Han <chuanhua.han@nxp.com>

Modify the Freescale ESPI driver to support the driver model.
Also resolved the following problems:

===================== WARNING ======================
This board does not use CONFIG_DM_SPI. Please update
the board before v2019.04 for no dm conversion
and v2019.07 for partially dm converted drivers.
Failure to update can lead to driver/board removal
See doc/driver-model/MIGRATION.txt for more info.
====================================================
===================== WARNING ======================
This board does not use CONFIG_DM_SPI_FLASH. Please update
the board to use CONFIG_SPI_FLASH before the v2019.07 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 drivers/spi/fsl_espi.c              | 444 ++++++++++++++++++++--------
 include/dm/platform_data/fsl_espi.h |  16 +
 2 files changed, 337 insertions(+), 123 deletions(-)
 create mode 100644 include/dm/platform_data/fsl_espi.h

diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
index 50d194f614..5c76fd962e 100644
--- a/drivers/spi/fsl_espi.c
+++ b/drivers/spi/fsl_espi.c
@@ -3,7 +3,9 @@
  * eSPI controller driver.
  *
  * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  * Author: Mingkai Hu (Mingkai.hu at freescale.com)
+ *	   Chuanhua Han (chuanhua.han at nxp.com)
  */
 
 #include <common.h>
@@ -14,10 +16,16 @@
 #include <malloc.h>
 #include <spi.h>
 #include <asm/immap_85xx.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <dm/platform_data/fsl_espi.h>
 
 struct fsl_spi_slave {
 	struct spi_slave slave;
 	ccsr_espi_t	*espi;
+	u32		speed_hz;
+	unsigned int	cs;
 	unsigned int	div16;
 	unsigned int	pm;
 	int		tx_timeout;
@@ -31,6 +39,9 @@ struct fsl_spi_slave {
 #define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave)
 #define US_PER_SECOND		1000000UL
 
+/* default SCK frequency, unit: HZ */
+#define FSL_ESPI_DEFAULT_SCK_FREQ   10000000
+
 #define ESPI_MAX_CS_NUM		4
 #define ESPI_FIFO_WIDTH_BIT	32
 
@@ -65,116 +76,27 @@ struct fsl_spi_slave {
 
 #define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0
 
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-		unsigned int max_hz, unsigned int mode)
-{
-	struct fsl_spi_slave *fsl;
-	sys_info_t sysinfo;
-	unsigned long spibrg = 0;
-	unsigned long spi_freq = 0;
-	unsigned char pm = 0;
-
-	if (!spi_cs_is_valid(bus, cs))
-		return NULL;
-
-	fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);
-	if (!fsl)
-		return NULL;
-
-	fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
-	fsl->mode = mode;
-	fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
-
-	/* Set eSPI BRG clock source */
-	get_sys_info(&sysinfo);
-	spibrg = sysinfo.freq_systembus / 2;
-	fsl->div16 = 0;
-	if ((spibrg / max_hz) > 32) {
-		fsl->div16 = ESPI_CSMODE_DIV16;
-		pm = spibrg / (max_hz * 16 * 2);
-		if (pm > 16) {
-			pm = 16;
-			debug("Requested speed is too low: %d Hz, %ld Hz "
-				"is used.\n", max_hz, spibrg / (32 * 16));
-		}
-	} else
-		pm = spibrg / (max_hz * 2);
-	if (pm)
-		pm--;
-	fsl->pm = pm;
-
-	if (fsl->div16)
-		spi_freq = spibrg / ((pm + 1) * 2 * 16);
-	else
-		spi_freq = spibrg / ((pm + 1) * 2);
-
-	/* set tx_timeout to 10 times of one espi FIFO entry go out */
-	fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT
-				* 10), spi_freq);
-
-	return &fsl->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
-	struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
-	free(fsl);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
+void fsl_spi_cs_activate(struct spi_slave *slave, uint cs)
 {
 	struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
 	ccsr_espi_t *espi = fsl->espi;
-	unsigned char pm = fsl->pm;
-	unsigned int cs = slave->cs;
-	unsigned int mode =  fsl->mode;
-	unsigned int div16 = fsl->div16;
-	int i;
-
-	debug("%s: bus:%i cs:%i\n", __func__, slave->bus, cs);
-
-	/* Enable eSPI interface */
-	out_be32(&espi->mode, ESPI_MODE_RXTHR(3)
-			| ESPI_MODE_TXTHR(4) | ESPI_MODE_EN);
-
-	out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */
-	out_be32(&espi->mask, 0x00000000); /* Mask  all eSPI interrupts */
-
-	/* Init CS mode interface */
-	for (i = 0; i < ESPI_MAX_CS_NUM; i++)
-		out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL);
-
-	out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) &
-		~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16
-		| ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK
-		| ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF)));
-
-	/* Set eSPI BRG clock source */
-	out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
-		| ESPI_CSMODE_PM(pm) | div16);
-
-	/* Set eSPI mode */
-	if (mode & SPI_CPHA)
-		out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
-			| ESPI_CSMODE_CP_BEGIN_EDGCLK);
-	if (mode & SPI_CPOL)
-		out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
-			| ESPI_CSMODE_CI_INACTIVEHIGH);
-
-	/* Character bit order: msb first */
-	out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
-		| ESPI_CSMODE_REV_MSB_FIRST);
-
-	/* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */
-	out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
-		| ESPI_CSMODE_LEN(7));
+	unsigned int com = 0;
+	size_t data_len = fsl->data_len;
 
-	return 0;
+	com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF));
+	com |= ESPI_COM_CS(cs);
+	com |= ESPI_COM_TRANLEN(data_len - 1);
+	out_be32(&espi->com, com);
 }
 
-void spi_release_bus(struct spi_slave *slave)
+void fsl_spi_cs_deactivate(struct spi_slave *slave)
 {
+	struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
+	ccsr_espi_t *espi = fsl->espi;
 
+	/* clear the RXCNT and TXCNT */
+	out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN));
+	out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN);
 }
 
 static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout)
@@ -207,7 +129,8 @@ static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout)
 		debug("***spi_xfer:...Tx timeout! event = %08x\n", event);
 }
 
-static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes)
+static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din,
+		       unsigned int bytes)
 {
 	ccsr_espi_t *espi = fsl->espi;
 	unsigned int tmpdin, rx_times;
@@ -239,10 +162,17 @@ static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes)
 	return bytes;
 }
 
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
-		void *data_in, unsigned long flags)
+void  espi_release_bus(struct fsl_spi_slave *fsl)
 {
-	struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
+	/* Disable the SPI hardware */
+	 out_be32(&fsl->espi->mode,
+		  in_be32(&fsl->espi->mode) & (~ESPI_MODE_EN));
+}
+
+int espi_xfer(struct fsl_spi_slave *fsl,  uint cs, unsigned int bitlen,
+	      const void *data_out, void *data_in, unsigned long flags)
+{
+	struct spi_slave *slave = &fsl->slave;
 	ccsr_espi_t *espi = fsl->espi;
 	unsigned int event, rx_bytes;
 	const void *dout = NULL;
@@ -261,13 +191,14 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
 	max_tran_len = fsl->max_transfer_length;
 	switch (flags) {
 	case SPI_XFER_BEGIN:
-		cmd_len = fsl->cmd_len = data_len;
+		cmd_len = data_len;
+		fsl->cmd_len = cmd_len;
 		memcpy(cmd_buf, data_out, cmd_len);
 		return 0;
 	case 0:
 	case SPI_XFER_END:
 		if (bitlen == 0) {
-			spi_cs_deactivate(slave);
+			fsl_spi_cs_deactivate(slave);
 			return 0;
 		}
 		buf_len = 2 * cmd_len + min(data_len, (size_t)max_tran_len);
@@ -307,7 +238,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
 		num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4);
 		num_bytes = (tran_len + cmd_len) % 4;
 		fsl->data_len = tran_len + cmd_len;
-		spi_cs_activate(slave);
+		fsl_spi_cs_activate(slave, cs);
 
 		/* Clear all eSPI events */
 		out_be32(&espi->event , 0xffffffff);
@@ -350,37 +281,304 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
 				*(int *)buffer += tran_len;
 			}
 		}
-		spi_cs_deactivate(slave);
+		fsl_spi_cs_deactivate(slave);
 	}
 
 	free(buffer);
 	return 0;
 }
 
+void espi_claim_bus(struct fsl_spi_slave *fsl, unsigned int cs)
+{
+	ccsr_espi_t *espi = fsl->espi;
+	unsigned char pm = fsl->pm;
+	unsigned int mode =  fsl->mode;
+	unsigned int div16 = fsl->div16;
+	int i;
+
+	/* Enable eSPI interface */
+	out_be32(&espi->mode, ESPI_MODE_RXTHR(3)
+			| ESPI_MODE_TXTHR(4) | ESPI_MODE_EN);
+
+	out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */
+	out_be32(&espi->mask, 0x00000000); /* Mask  all eSPI interrupts */
+
+	/* Init CS mode interface */
+	for (i = 0; i < ESPI_MAX_CS_NUM; i++)
+		out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL);
+
+	out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) &
+		~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16
+		| ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK
+		| ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF)));
+
+	/* Set eSPI BRG clock source */
+	out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
+		| ESPI_CSMODE_PM(pm) | div16);
+
+	/* Set eSPI mode */
+	if (mode & SPI_CPHA)
+		out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
+			| ESPI_CSMODE_CP_BEGIN_EDGCLK);
+	if (mode & SPI_CPOL)
+		out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
+			| ESPI_CSMODE_CI_INACTIVEHIGH);
+
+	/* Character bit order: msb first */
+	out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
+		| ESPI_CSMODE_REV_MSB_FIRST);
+
+	/* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */
+	out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
+		| ESPI_CSMODE_LEN(7));
+}
+
+void espi_setup_slave(struct fsl_spi_slave *fsl)
+{
+	unsigned int max_hz;
+	sys_info_t sysinfo;
+	unsigned long spibrg = 0;
+	unsigned long spi_freq = 0;
+	unsigned char pm = 0;
+
+	max_hz = fsl->speed_hz;
+
+	get_sys_info(&sysinfo);
+	spibrg = sysinfo.freq_systembus / 2;
+	fsl->div16 = 0;
+	if ((spibrg / max_hz) > 32) {
+		fsl->div16 = ESPI_CSMODE_DIV16;
+		pm = spibrg / (max_hz * 16 * 2);
+		if (pm > 16) {
+			pm = 16;
+			debug("max_hz is too low: %d Hz, %ld Hz is used.\n",
+			      max_hz, spibrg / (32 * 16));
+		}
+	} else {
+		pm = spibrg / (max_hz * 2);
+	}
+	if (pm)
+		pm--;
+	fsl->pm = pm;
+
+	if (fsl->div16)
+		spi_freq = spibrg / ((pm + 1) * 2 * 16);
+	else
+		spi_freq = spibrg / ((pm + 1) * 2);
+
+	/* set tx_timeout to 10 times of one espi FIFO entry go out */
+	fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT
+				* 10), spi_freq);/* Set eSPI BRG clock source */
+}
+
+#if !CONFIG_IS_ENABLED(DM_SPI)
 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 {
 	return bus == 0 && cs < ESPI_MAX_CS_NUM;
 }
 
-void spi_cs_activate(struct spi_slave *slave)
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+				  unsigned int max_hz, unsigned int mode)
+{
+	struct fsl_spi_slave *fsl;
+
+	if (!spi_cs_is_valid(bus, cs))
+		return NULL;
+
+	fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);
+	if (!fsl)
+		return NULL;
+
+	fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
+	fsl->mode = mode;
+	fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
+	fsl->speed_hz = max_hz;
+
+	espi_setup_slave(fsl);
+
+	return &fsl->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
 {
 	struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
-	ccsr_espi_t *espi = fsl->espi;
-	unsigned int com = 0;
-	size_t data_len = fsl->data_len;
 
-	com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF));
-	com |= ESPI_COM_CS(slave->cs);
-	com |= ESPI_COM_TRANLEN(data_len - 1);
-	out_be32(&espi->com, com);
+	free(fsl);
 }
 
-void spi_cs_deactivate(struct spi_slave *slave)
+int spi_claim_bus(struct spi_slave *slave)
 {
 	struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
-	ccsr_espi_t *espi = fsl->espi;
 
-	/* clear the RXCNT and TXCNT */
-	out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN));
-	out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN);
+	espi_claim_bus(fsl, slave->cs);
+
+	return 0;
 }
+
+void spi_release_bus(struct spi_slave *slave)
+{
+	struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
+
+	espi_release_bus(fsl);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+	     void *din, unsigned long flags)
+{
+	struct fsl_spi_slave *fsl = (struct fsl_spi_slave *)slave;
+
+	return espi_xfer(fsl, slave->cs, bitlen, dout, din, flags);
+}
+#else
+static void __espi_set_speed(struct fsl_spi_slave *fsl)
+{
+	espi_setup_slave(fsl);
+
+	/* Set eSPI BRG clock source */
+	out_be32(&fsl->espi->csmode[fsl->cs],
+		 in_be32(&fsl->espi->csmode[fsl->cs])
+			 | ESPI_CSMODE_PM(fsl->pm) | fsl->div16);
+}
+
+static void __espi_set_mode(struct fsl_spi_slave *fsl)
+{
+	/* Set eSPI mode */
+	if (fsl->mode & SPI_CPHA)
+		out_be32(&fsl->espi->csmode[fsl->cs],
+			 in_be32(&fsl->espi->csmode[fsl->cs])
+				| ESPI_CSMODE_CP_BEGIN_EDGCLK);
+	if (fsl->mode & SPI_CPOL)
+		out_be32(&fsl->espi->csmode[fsl->cs],
+			 in_be32(&fsl->espi->csmode[fsl->cs])
+				| ESPI_CSMODE_CI_INACTIVEHIGH);
+}
+
+static int fsl_espi_claim_bus(struct udevice *dev)
+{
+	struct udevice *bus = dev->parent;
+	struct fsl_spi_slave  *fsl =  dev_get_priv(bus);
+
+	espi_claim_bus(fsl, fsl->cs);
+
+	return 0;
+}
+
+static int fsl_espi_release_bus(struct udevice *dev)
+{
+	struct udevice *bus = dev->parent;
+	struct fsl_spi_slave *fsl = dev_get_priv(bus);
+
+	espi_release_bus(fsl);
+
+	return 0;
+}
+
+static int fsl_espi_xfer(struct udevice *dev, unsigned int bitlen,
+			 const void *dout, void *din, unsigned long flags)
+{
+	struct udevice *bus = dev->parent;
+	struct fsl_spi_slave *fsl = dev_get_priv(bus);
+
+	return espi_xfer(fsl, fsl->cs, bitlen, dout, din, flags);
+}
+
+static int fsl_espi_set_speed(struct udevice *bus, uint speed)
+{
+	struct fsl_spi_slave *fsl = dev_get_priv(bus);
+
+	debug("%s speed %u\n", __func__, speed);
+	fsl->speed_hz = speed;
+
+	__espi_set_speed(fsl);
+
+	return 0;
+}
+
+static int fsl_espi_set_mode(struct udevice *bus, uint mode)
+{
+	struct fsl_spi_slave *fsl = dev_get_priv(bus);
+
+	debug("%s mode %u\n", __func__, mode);
+	fsl->mode = mode;
+
+	__espi_set_mode(fsl);
+
+	return 0;
+}
+
+static int fsl_espi_child_pre_probe(struct udevice *dev)
+{
+	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+	struct udevice *bus = dev->parent;
+	struct fsl_spi_slave *fsl = dev_get_priv(bus);
+
+	debug("%s cs %u\n", __func__, slave_plat->cs);
+	fsl->cs = slave_plat->cs;
+
+	return 0;
+}
+
+static int fsl_espi_probe(struct udevice *bus)
+{
+	struct fsl_espi_platdata *plat = dev_get_platdata(bus);
+	struct fsl_spi_slave *fsl = dev_get_priv(bus);
+
+	fsl->espi = (ccsr_espi_t *)((u32)plat->regs_addr);
+	fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
+	fsl->speed_hz = plat->speed_hz;
+
+	debug("%s probe done, bus-num %d.\n", bus->name, bus->seq);
+
+	return 0;
+}
+
+static const struct dm_spi_ops fsl_espi_ops = {
+	.claim_bus	= fsl_espi_claim_bus,
+	.release_bus	= fsl_espi_release_bus,
+	.xfer		= fsl_espi_xfer,
+	.set_speed	= fsl_espi_set_speed,
+	.set_mode	= fsl_espi_set_mode,
+};
+
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+static int fsl_espi_ofdata_to_platdata(struct udevice *bus)
+{
+	fdt_addr_t addr;
+	struct fsl_espi_platdata   *plat = bus->platdata;
+	const void *blob = gd->fdt_blob;
+	int node = dev_of_offset(bus);
+
+	addr = dev_read_addr(bus);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	plat->regs_addr = lower_32_bits(addr);
+	plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
+					FSL_ESPI_DEFAULT_SCK_FREQ);
+
+	debug("ESPI: regs=%p, max-frequency=%d\n",
+	      &plat->regs_addr, plat->speed_hz);
+
+	return 0;
+}
+
+static const struct udevice_id fsl_espi_ids[] = {
+	{ .compatible = "fsl,mpc8536-espi" },
+	{ }
+};
+#endif
+
+U_BOOT_DRIVER(fsl_espi) = {
+	.name	= "fsl_espi",
+	.id	= UCLASS_SPI,
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+	.of_match = fsl_espi_ids,
+	.ofdata_to_platdata = fsl_espi_ofdata_to_platdata,
+#endif
+	.ops	= &fsl_espi_ops,
+	.platdata_auto_alloc_size = sizeof(struct fsl_espi_platdata),
+	.priv_auto_alloc_size = sizeof(struct fsl_spi_slave),
+	.probe	= fsl_espi_probe,
+	.child_pre_probe = fsl_espi_child_pre_probe,
+};
+#endif
diff --git a/include/dm/platform_data/fsl_espi.h b/include/dm/platform_data/fsl_espi.h
new file mode 100644
index 0000000000..812933f51c
--- /dev/null
+++ b/include/dm/platform_data/fsl_espi.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __fsl_espi_h
+#define __fsl_espi_h
+
+struct fsl_espi_platdata {
+	uint flags;
+	uint speed_hz;
+	uint num_chipselect;
+	fdt_addr_t regs_addr;
+};
+
+#endif /* __fsl_espi_h */
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 02/36] powerpc: dts: t2080: add espi controller node support
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
  2020-06-02 13:34 ` [PATCHv2 01/36] dm: spi: Convert Freescale ESPI driver to driver model Zhiqiang Hou
@ 2020-06-02 13:34 ` Zhiqiang Hou
  2020-06-02 13:34 ` [PATCHv2 03/36] powerpc: dts: t2080qds: add espi slave nodes support Zhiqiang Hou
                   ` (33 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:34 UTC (permalink / raw)
  To: u-boot

From: Chuanhua Han <chuanhua.han@nxp.com>

Add espi controller node to support t2080.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 arch/powerpc/dts/t2080.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/powerpc/dts/t2080.dtsi b/arch/powerpc/dts/t2080.dtsi
index a9e9b404f6..7e446b18df 100644
--- a/arch/powerpc/dts/t2080.dtsi
+++ b/arch/powerpc/dts/t2080.dtsi
@@ -69,6 +69,16 @@
 			voltage-ranges = <1800 1800 3300 3300>;
 		};
 
+		espi0: spi at 110000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,mpc8536-espi";
+			reg = <0x110000 0x1000>;
+			interrupts = <53 0x2 0 0>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
+
 		usb0: usb at 210000 {
 			compatible = "fsl-usb2-mph";
 			reg = <0x210000 0x1000>;
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 03/36] powerpc: dts: t2080qds: add espi slave nodes support
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
  2020-06-02 13:34 ` [PATCHv2 01/36] dm: spi: Convert Freescale ESPI driver to driver model Zhiqiang Hou
  2020-06-02 13:34 ` [PATCHv2 02/36] powerpc: dts: t2080: add espi controller node support Zhiqiang Hou
@ 2020-06-02 13:34 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 04/36] configs: enable espi device module in T2080QDS Zhiqiang Hou
                   ` (32 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:34 UTC (permalink / raw)
  To: u-boot

From: Chuanhua Han <chuanhua.han@nxp.com>

Add espi slave nodes  to support t2080qds.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 arch/powerpc/dts/t2080qds.dts | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/powerpc/dts/t2080qds.dts b/arch/powerpc/dts/t2080qds.dts
index 1819a081dd..f9e786b239 100644
--- a/arch/powerpc/dts/t2080qds.dts
+++ b/arch/powerpc/dts/t2080qds.dts
@@ -14,4 +14,37 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 	interrupt-parent = <&mpic>;
+
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
+&espi0 {
+
+	status = "okay";
+	flash at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q128a11", "jedec,spi-nor"; /* 16MB */
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+	};
+
+	flash at 1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "sst,sst25wf040", "jedec,spi-nor";
+		reg = <1>;
+		spi-max-frequency = <10000000>;
+	};
+
+	flash at 2 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "eon,en25s64", "jedec,spi-nor";
+		reg = <2>;
+		spi-max-frequency = <10000000>;
+	};
+
 };
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 04/36] configs: enable espi device module in T2080QDS
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (2 preceding siblings ...)
  2020-06-02 13:34 ` [PATCHv2 03/36] powerpc: dts: t2080qds: add espi slave nodes support Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 05/36] dts: P1020: Add ESPI DT nodes Zhiqiang Hou
                   ` (31 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Chuanhua Han <chuanhua.han@nxp.com>

This patch is to enable  espi DM for T2080QDS in uboot

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 configs/T2080QDS_NAND_defconfig           | 2 ++
 configs/T2080QDS_SDCARD_defconfig         | 2 ++
 configs/T2080QDS_SECURE_BOOT_defconfig    | 2 ++
 configs/T2080QDS_SPIFLASH_defconfig       | 2 ++
 configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 2 ++
 configs/T2080QDS_defconfig                | 2 ++
 6 files changed, 12 insertions(+)

diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index 52255ed120..0b506fd14f 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -81,3 +81,5 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index ba57ea33b1..e8ec495ec6 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -78,3 +78,5 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index 9b3f709c87..9d7472e228 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -68,3 +68,5 @@ CONFIG_USB_STORAGE=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index 5aa45f5a89..c91711017a 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -81,3 +81,5 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index 4958435ef4..98070993c5 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -58,3 +58,5 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index 602bf577e0..e9d5cd04f5 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -66,3 +66,5 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 05/36] dts: P1020: Add ESPI DT nodes
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (3 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 04/36] configs: enable espi device module in T2080QDS Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 06/36] dts: P1020RDB: Add ESPI slave device node Zhiqiang Hou
                   ` (30 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Add ESPI controller DT node for P1020.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 arch/powerpc/dts/p1020-post.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi
index 1dce8e86e9..65b844e5d0 100644
--- a/arch/powerpc/dts/p1020-post.dtsi
+++ b/arch/powerpc/dts/p1020-post.dtsi
@@ -44,6 +44,15 @@
 		clock-frequency = <0>;
 	};
 
+	espi0: spi at 7000 {
+		compatible = "fsl,mpc8536-espi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x7000 0x1000>;
+		fsl,espi-num-chipselects = <4>;
+		status = "disabled";
+	};
+
 	/include/ "pq3-i2c-0.dtsi"
 	/include/ "pq3-i2c-1.dtsi"
 };
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 06/36] dts: P1020RDB: Add ESPI slave device node
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (4 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 05/36] dts: P1020: Add ESPI DT nodes Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 07/36] configs: P1020RDB: Enable ESPI driver Zhiqiang Hou
                   ` (29 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Add ESPI slave node for P1020RDB.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 arch/powerpc/dts/p1020rdb-pc.dts     | 15 +++++++++++++++
 arch/powerpc/dts/p1020rdb-pc_36b.dts | 15 +++++++++++++++
 arch/powerpc/dts/p1020rdb-pd.dts     | 15 +++++++++++++++
 3 files changed, 45 insertions(+)

diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts
index 7ebaa619df..4193af10c9 100644
--- a/arch/powerpc/dts/p1020rdb-pc.dts
+++ b/arch/powerpc/dts/p1020rdb-pc.dts
@@ -30,6 +30,21 @@
 		ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000   /* downstream I/O */
 			  0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
 	};
+
+	aliases {
+		spi0 = &espi0;
+	};
 };
 
 /include/ "p1020-post.dtsi"
+
+&espi0 {
+	status = "okay";
+	flash at 0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
+};
diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts b/arch/powerpc/dts/p1020rdb-pc_36b.dts
index c0e5ef4cf4..5a20e60d96 100644
--- a/arch/powerpc/dts/p1020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts
@@ -30,6 +30,21 @@
 		ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000   /* downstream I/O */
 			  0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
 	};
+
+	aliases {
+		spi0 = &espi0;
+	};
 };
 
 /include/ "p1020-post.dtsi"
+
+&espi0 {
+	status = "okay";
+	flash at 0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
+};
diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts
index 21174a09be..6e319f0ef0 100644
--- a/arch/powerpc/dts/p1020rdb-pd.dts
+++ b/arch/powerpc/dts/p1020rdb-pd.dts
@@ -30,6 +30,21 @@
 		ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000   /* downstream I/O */
 			  0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
 	};
+
+	aliases {
+		spi0 = &espi0;
+	};
 };
 
 /include/ "p1020-post.dtsi"
+
+&espi0 {
+	status = "okay";
+	flash at 0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
+};
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 07/36] configs: P1020RDB: Enable ESPI driver
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (5 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 06/36] dts: P1020RDB: Add ESPI slave device node Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 08/36] dts: P2020: Add ESPI DT nodes Zhiqiang Hou
                   ` (28 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Enable the DM ESPI driver in P1020RDB defconfig.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 configs/P1020RDB-PC_36BIT_NAND_defconfig     | 2 ++
 configs/P1020RDB-PC_36BIT_SDCARD_defconfig   | 2 ++
 configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 2 ++
 configs/P1020RDB-PC_36BIT_defconfig          | 2 ++
 configs/P1020RDB-PC_NAND_defconfig           | 2 ++
 configs/P1020RDB-PC_SDCARD_defconfig         | 2 ++
 configs/P1020RDB-PC_SPIFLASH_defconfig       | 2 ++
 configs/P1020RDB-PC_defconfig                | 2 ++
 configs/P1020RDB-PD_NAND_defconfig           | 2 ++
 configs/P1020RDB-PD_SDCARD_defconfig         | 2 ++
 configs/P1020RDB-PD_SPIFLASH_defconfig       | 2 ++
 configs/P1020RDB-PD_defconfig                | 2 ++
 12 files changed, 24 insertions(+)

diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index 6ee52fe5e7..5ee48fd2ac 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -48,6 +48,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index 489b91d8e7..e89e287f25 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -44,6 +44,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index 4a8e4e3726..ba147e7d66 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -46,6 +46,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index f9a4b735ca..0b34b615ed 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -33,6 +33,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index 5c8231cba2..e0f7ccdce2 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -47,6 +47,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index ad2bb90a49..412077866d 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -43,6 +43,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index b8055e49b0..3f27bcdfe5 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -45,6 +45,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index a71985374e..e865776f54 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -32,6 +32,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index 0043fd5f66..d06709df65 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -50,6 +50,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index cb0a8aec65..98d1533248 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -46,6 +46,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index 35e60ca856..25ef996407 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -48,6 +48,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index d7f19c3d96..c7208fc620 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -35,6 +35,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 08/36] dts: P2020: Add ESPI DT nodes
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (6 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 07/36] configs: P1020RDB: Enable ESPI driver Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 09/36] dts: P2020RDB: Add ESPI slave device node Zhiqiang Hou
                   ` (27 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Add ESPI controller DT node for P2020.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 arch/powerpc/dts/p2020-post.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index 4ed093dad4..48989457df 100644
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -38,6 +38,15 @@
 		clock-frequency = <0>;
 	};
 
+	espi0: spi at 7000 {
+		compatible = "fsl,mpc8536-espi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x7000 0x1000>;
+		fsl,espi-num-chipselects = <4>;
+		status = "disabled";
+	};
+
 	/include/ "pq3-i2c-0.dtsi"
 	/include/ "pq3-i2c-1.dtsi"
 };
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 09/36] dts: P2020RDB: Add ESPI slave device node
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (7 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 08/36] dts: P2020: Add ESPI DT nodes Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 10/36] configs: P2020RDB: Enable ESPI driver Zhiqiang Hou
                   ` (26 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Add ESPI slave node for P2020RDB.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 arch/powerpc/dts/p2020rdb-pc.dts     | 15 +++++++++++++++
 arch/powerpc/dts/p2020rdb-pc_36b.dts | 15 +++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts
index 08befd4c59..5ae278cbfc 100644
--- a/arch/powerpc/dts/p2020rdb-pc.dts
+++ b/arch/powerpc/dts/p2020rdb-pc.dts
@@ -35,6 +35,21 @@
 		ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000   /* downstream I/O */
 			  0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
 	};
+
+	aliases {
+		spi0 = &espi0;
+	};
 };
 
 /include/ "p2020-post.dtsi"
+
+&espi0 {
+	status = "okay";
+	flash at 0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
+};
diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts
index 04b2519e1a..542fffc33e 100644
--- a/arch/powerpc/dts/p2020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts
@@ -35,6 +35,21 @@
 		ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000   /* downstream I/O */
 			  0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
 	};
+
+	aliases {
+		spi0 = &espi0;
+	};
 };
 
 /include/ "p2020-post.dtsi"
+
+&espi0 {
+	status = "okay";
+	flash at 0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
+};
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 10/36] configs: P2020RDB: Enable ESPI driver
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (8 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 09/36] dts: P2020RDB: Add ESPI slave device node Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 11/36] dts: P2041: Add ESPI DT nodes Zhiqiang Hou
                   ` (25 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Enable the DM ESPI driver in P2020RDB defconfig.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 configs/P2020RDB-PC_36BIT_NAND_defconfig     | 2 ++
 configs/P2020RDB-PC_36BIT_SDCARD_defconfig   | 2 ++
 configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 2 ++
 configs/P2020RDB-PC_36BIT_defconfig          | 2 ++
 configs/P2020RDB-PC_NAND_defconfig           | 2 ++
 configs/P2020RDB-PC_SDCARD_defconfig         | 2 ++
 configs/P2020RDB-PC_SPIFLASH_defconfig       | 2 ++
 configs/P2020RDB-PC_defconfig                | 2 ++
 8 files changed, 16 insertions(+)

diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index 3e6ea64ee3..487ed34916 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -52,6 +52,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index 187cbee0d6..e63bfe9588 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -48,6 +48,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index 88c9224001..a2079f9bc2 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -50,6 +50,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index 88e24c30ba..a409d1879b 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -37,6 +37,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index dda34dd43e..e774def659 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -51,6 +51,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index c2b6ad5f32..2553fb74d9 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -47,6 +47,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index 3ec208ee00..0d642724e2 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -49,6 +49,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index 0f0a6ad810..11287517a8 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -36,6 +36,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 11/36] dts: P2041: Add ESPI DT nodes
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (9 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 10/36] configs: P2020RDB: Enable ESPI driver Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 12/36] dts: P2041RDB: Add ESPI slave device node Zhiqiang Hou
                   ` (24 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Add ESPI controller DT node for P2041.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 arch/powerpc/dts/p2041.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi
index 95931e299d..8abc4a5ea9 100644
--- a/arch/powerpc/dts/p2041.dtsi
+++ b/arch/powerpc/dts/p2041.dtsi
@@ -40,6 +40,15 @@
 			reg = <3>;
 			fsl,portid-mapping = <0x10000000>;
 		};
+
+		espi0: spi at 110000 {
+			compatible = "fsl,mpc8536-espi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x110000 0x1000>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
 	};
 
 	soc: soc at ffe000000 {
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 12/36] dts: P2041RDB: Add ESPI slave device node
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (10 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 11/36] dts: P2041: Add ESPI DT nodes Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 13/36] configs: P2041RDB: Enable ESPI driver Zhiqiang Hou
                   ` (23 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Add ESPI slave node for P2041RDB.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 arch/powerpc/dts/p2041rdb.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/powerpc/dts/p2041rdb.dts b/arch/powerpc/dts/p2041rdb.dts
index 6e9d9c058a..505c74d620 100644
--- a/arch/powerpc/dts/p2041rdb.dts
+++ b/arch/powerpc/dts/p2041rdb.dts
@@ -15,4 +15,18 @@
 	#size-cells = <2>;
 	interrupt-parent = <&mpic>;
 
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
+&espi0 {
+	status = "okay";
+	flash at 0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
 };
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 13/36] configs: P2041RDB: Enable ESPI driver
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (11 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 12/36] dts: P2041RDB: Add ESPI slave device node Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 14/36] dts: P3041: Add ESPI DT nodes Zhiqiang Hou
                   ` (22 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Enable the DM ESPI driver in P2041RDB defconfig.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 configs/P2041RDB_NAND_defconfig     | 2 ++
 configs/P2041RDB_SDCARD_defconfig   | 2 ++
 configs/P2041RDB_SPIFLASH_defconfig | 2 ++
 configs/P2041RDB_defconfig          | 2 ++
 4 files changed, 8 insertions(+)

diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index 13b20dd1c6..24c8012f6f 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -31,6 +31,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index d99c15342d..c62583360a 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -31,6 +31,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index 78a2a97064..8d27dee5ca 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -32,6 +32,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 0b9625e91e..bc9f04536e 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -30,6 +30,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 14/36] dts: P3041: Add ESPI DT nodes
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (12 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 13/36] configs: P2041RDB: Enable ESPI driver Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 15/36] dts: P3041DS: Add ESPI slave device node Zhiqiang Hou
                   ` (21 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Add ESPI controller DT node for P3041.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 arch/powerpc/dts/p3041.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/powerpc/dts/p3041.dtsi b/arch/powerpc/dts/p3041.dtsi
index 3152683b84..f6a50aaaae 100644
--- a/arch/powerpc/dts/p3041.dtsi
+++ b/arch/powerpc/dts/p3041.dtsi
@@ -40,6 +40,15 @@
 			reg = <3>;
 			fsl,portid-mapping = <0x10000000>;
 		};
+
+		espi0: spi at 110000 {
+			compatible = "fsl,mpc8536-espi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x110000 0x1000>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
 	};
 
 	soc: soc at ffe000000 {
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 15/36] dts: P3041DS: Add ESPI slave device node
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (13 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 14/36] dts: P3041: Add ESPI DT nodes Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 16/36] configs: P3041DS: Enable ESPI driver Zhiqiang Hou
                   ` (20 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Add ESPI slave node for P3041DS.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 arch/powerpc/dts/p3041ds.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/powerpc/dts/p3041ds.dts b/arch/powerpc/dts/p3041ds.dts
index c30bf7ac77..5d1bac2eed 100644
--- a/arch/powerpc/dts/p3041ds.dts
+++ b/arch/powerpc/dts/p3041ds.dts
@@ -15,4 +15,18 @@
 	#size-cells = <2>;
 	interrupt-parent = <&mpic>;
 
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
+&espi0 {
+	status = "okay";
+	flash at 0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
 };
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 16/36] configs: P3041DS: Enable ESPI driver
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (14 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 15/36] dts: P3041DS: Add ESPI slave device node Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 17/36] dts: P4080: Add ESPI DT nodes Zhiqiang Hou
                   ` (19 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Enable the DM ESPI driver in P3041DS defconfig.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 configs/P3041DS_NAND_defconfig     | 2 ++
 configs/P3041DS_SDCARD_defconfig   | 2 ++
 configs/P3041DS_SPIFLASH_defconfig | 2 ++
 configs/P3041DS_defconfig          | 2 ++
 4 files changed, 8 insertions(+)

diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index 55613ccacd..a2002e87aa 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -31,6 +31,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index b52068d050..276bb8c249 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -31,6 +31,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
index 3af52b90e8..23e08bc97c 100644
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig
@@ -32,6 +32,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index cc3234c6b1..f4c234d4e4 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -30,6 +30,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 17/36] dts: P4080: Add ESPI DT nodes
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (15 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 16/36] configs: P3041DS: Enable ESPI driver Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 18/36] dts: P4080DS: Add ESPI slave device node Zhiqiang Hou
                   ` (18 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Add ESPI controller DT node for P4080.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 arch/powerpc/dts/p4080.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/powerpc/dts/p4080.dtsi b/arch/powerpc/dts/p4080.dtsi
index 4a80561e18..9d7d685229 100644
--- a/arch/powerpc/dts/p4080.dtsi
+++ b/arch/powerpc/dts/p4080.dtsi
@@ -60,6 +60,15 @@
 			reg = <7>;
 			fsl,portid-mapping = <0x01000000>;
 		};
+
+		espi0: spi at 110000 {
+			compatible = "fsl,mpc8536-espi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x110000 0x1000>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
 	};
 
 	soc: soc at ffe000000 {
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 18/36] dts: P4080DS: Add ESPI slave device node
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (16 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 17/36] dts: P4080: Add ESPI DT nodes Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 19/36] configs: P4080DS: Enable ESPI driver Zhiqiang Hou
                   ` (17 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Add ESPI slave node for P4080DS.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 arch/powerpc/dts/p4080ds.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/powerpc/dts/p4080ds.dts b/arch/powerpc/dts/p4080ds.dts
index 15a0f66fb6..62a0f9881d 100644
--- a/arch/powerpc/dts/p4080ds.dts
+++ b/arch/powerpc/dts/p4080ds.dts
@@ -15,4 +15,18 @@
 	#size-cells = <2>;
 	interrupt-parent = <&mpic>;
 
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
+&espi0 {
+	status = "okay";
+	flash at 0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
 };
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 19/36] configs: P4080DS: Enable ESPI driver
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (17 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 18/36] dts: P4080DS: Add ESPI slave device node Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 20/36] dts: P5040: Add ESPI DT nodes Zhiqiang Hou
                   ` (16 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Enable the DM ESPI driver in P4080DS defconfig.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 configs/P4080DS_SDCARD_defconfig   | 2 ++
 configs/P4080DS_SPIFLASH_defconfig | 2 ++
 configs/P4080DS_defconfig          | 2 ++
 3 files changed, 6 insertions(+)

diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index 18ad56ac8d..db23cfa41e 100644
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig
@@ -31,6 +31,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p4080ds"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
index 81a513bec9..15510413eb 100644
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig
@@ -32,6 +32,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p4080ds"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index 52db2e06c7..4ffeeb7660 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -30,6 +30,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p4080ds"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 20/36] dts: P5040: Add ESPI DT nodes
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (18 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 19/36] configs: P4080DS: Enable ESPI driver Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 21/36] dts: P5040DS: Add ESPI slave device node Zhiqiang Hou
                   ` (15 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Add ESPI controller DT node for P5040.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 arch/powerpc/dts/p5040.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/powerpc/dts/p5040.dtsi b/arch/powerpc/dts/p5040.dtsi
index 45988574a2..4e618ee4da 100644
--- a/arch/powerpc/dts/p5040.dtsi
+++ b/arch/powerpc/dts/p5040.dtsi
@@ -39,6 +39,15 @@
 			reg = <3>;
 			fsl,portid-mapping = <0x10000000>;
 		};
+
+		espi0: spi at 110000 {
+			compatible = "fsl,mpc8536-espi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x110000 0x1000>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
 	};
 
 	soc: soc at ffe000000 {
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 21/36] dts: P5040DS: Add ESPI slave device node
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (19 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 20/36] dts: P5040: Add ESPI DT nodes Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 22/36] configs: P5040DS: Enable ESPI driver Zhiqiang Hou
                   ` (14 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Add ESPI slave node for P5040DS.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 arch/powerpc/dts/p5040ds.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/powerpc/dts/p5040ds.dts b/arch/powerpc/dts/p5040ds.dts
index 723d31d5fb..0e1308a2ec 100644
--- a/arch/powerpc/dts/p5040ds.dts
+++ b/arch/powerpc/dts/p5040ds.dts
@@ -15,4 +15,18 @@
 	#size-cells = <2>;
 	interrupt-parent = <&mpic>;
 
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
+&espi0 {
+	status = "okay";
+	flash at 0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
 };
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 22/36] configs: P5040DS: Enable ESPI driver
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (20 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 21/36] dts: P5040DS: Add ESPI slave device node Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 23/36] dts: T102x: Add ESPI DT nodes Zhiqiang Hou
                   ` (13 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Enable the DM ESPI driver in P5040DS defconfig.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 configs/P5040DS_NAND_defconfig     | 2 ++
 configs/P5040DS_SDCARD_defconfig   | 2 ++
 configs/P5040DS_SPIFLASH_defconfig | 2 ++
 configs/P5040DS_defconfig          | 2 ++
 4 files changed, 8 insertions(+)

diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index efffb706fb..b841ec234c 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -32,6 +32,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index fdd39acbaf..58b9205075 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -31,6 +31,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
index 3f4642f4e0..8d48d025a9 100644
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig
@@ -32,6 +32,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index d2a2e02dcd..e0f9f8d493 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -30,6 +30,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 23/36] dts: T102x: Add ESPI DT nodes
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (21 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 22/36] configs: P5040DS: Enable ESPI driver Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 24/36] dts: T1024RDB: Add ESPI slave device node Zhiqiang Hou
                   ` (12 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Add ESPI controller DT node for T102x.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 arch/powerpc/dts/t102x.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/powerpc/dts/t102x.dtsi b/arch/powerpc/dts/t102x.dtsi
index 521825d85a..d5af5ca50a 100644
--- a/arch/powerpc/dts/t102x.dtsi
+++ b/arch/powerpc/dts/t102x.dtsi
@@ -29,6 +29,15 @@
 			reg = <1>;
 			#cooling-cells = <2>;
 		};
+
+		espi0: spi at 110000 {
+			compatible = "fsl,mpc8536-espi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x110000 0x1000>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
 	};
 
 	soc: soc at ffe000000 {
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 24/36] dts: T1024RDB: Add ESPI slave device node
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (22 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 23/36] dts: T102x: Add ESPI DT nodes Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 25/36] configs: T1024RDB: Enable ESPI driver Zhiqiang Hou
                   ` (11 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Add ESPI slave node for T1024RDB.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 arch/powerpc/dts/t1024rdb.dts | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/powerpc/dts/t1024rdb.dts b/arch/powerpc/dts/t1024rdb.dts
index 19a6652a23..5a45b1b481 100644
--- a/arch/powerpc/dts/t1024rdb.dts
+++ b/arch/powerpc/dts/t1024rdb.dts
@@ -14,4 +14,19 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 	interrupt-parent = <&mpic>;
+
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
+&espi0 {
+	status = "okay";
+	flash at 0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
 };
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 25/36] configs: T1024RDB: Enable ESPI driver
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (23 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 24/36] dts: T1024RDB: Add ESPI slave device node Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 26/36] dts: T104x: Add ESPI DT nodes Zhiqiang Hou
                   ` (10 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Enable the DM ESPI driver in T1024RDB defconfig.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 configs/T1024RDB_NAND_defconfig     | 2 ++
 configs/T1024RDB_SDCARD_defconfig   | 2 ++
 configs/T1024RDB_SPIFLASH_defconfig | 2 ++
 configs/T1024RDB_defconfig          | 2 ++
 4 files changed, 8 insertions(+)

diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index 9b116548a7..8e247cb74d 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -52,6 +52,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DM_I2C=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index 5e087fe2f3..a53fa3f03f 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -50,6 +50,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DM_I2C=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index 39b4537e71..8b5188637d 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -53,6 +53,8 @@ CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_ADDR=0xFFFC9000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DM_I2C=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index 8ff2fe3f0c..fcf9adc03f 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -38,6 +38,8 @@ CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DM_I2C=y
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 26/36] dts: T104x: Add ESPI DT nodes
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (24 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 25/36] configs: T1024RDB: Enable ESPI driver Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 27/36] dts: T1042D4RDB: Add ESPI slave device node Zhiqiang Hou
                   ` (9 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Add ESPI controller DT node for T104x.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 arch/powerpc/dts/t104x.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/powerpc/dts/t104x.dtsi b/arch/powerpc/dts/t104x.dtsi
index 0a08a69f31..4a81030f11 100644
--- a/arch/powerpc/dts/t104x.dtsi
+++ b/arch/powerpc/dts/t104x.dtsi
@@ -39,6 +39,15 @@
 			reg = <3>;
 			#cooling-cells = <2>;
 		};
+
+		espi0: spi at 110000 {
+			compatible = "fsl,mpc8536-espi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x110000 0x1000>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
 	};
 
 	soc: soc at ffe000000 {
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 27/36] dts: T1042D4RDB: Add ESPI slave device node
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (25 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 26/36] dts: T104x: Add ESPI DT nodes Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 28/36] configs: T1042D4RDB: Enable ESPI driver Zhiqiang Hou
                   ` (8 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Add ESPI slave node for T1042D4RDB.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 arch/powerpc/dts/t1042d4rdb.dts | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/powerpc/dts/t1042d4rdb.dts b/arch/powerpc/dts/t1042d4rdb.dts
index 16a8ed4c79..3584c06aa8 100644
--- a/arch/powerpc/dts/t1042d4rdb.dts
+++ b/arch/powerpc/dts/t1042d4rdb.dts
@@ -14,4 +14,19 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 	interrupt-parent = <&mpic>;
+
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
+&espi0 {
+	status = "okay";
+	flash at 0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
 };
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 28/36] configs: T1042D4RDB: Enable ESPI driver
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (26 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 27/36] dts: T1042D4RDB: Add ESPI slave device node Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 29/36] dts: T2080RDB: Add ESPI slave device node Zhiqiang Hou
                   ` (7 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Enable the DM ESPI driver in T1042D4RDB defconfig.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 configs/T1042D4RDB_NAND_defconfig     | 2 ++
 configs/T1042D4RDB_SDCARD_defconfig   | 2 ++
 configs/T1042D4RDB_SPIFLASH_defconfig | 2 ++
 configs/T1042D4RDB_defconfig          | 2 ++
 4 files changed, 8 insertions(+)

diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index 1602fb890e..7736c971b1 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -50,6 +50,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index a4a31bfd62..c52244e034 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -48,6 +48,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index 697c08dbfa..6b456d1640 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -51,6 +51,8 @@ CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_ADDR=0xFFFC9000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 70ddffb3a7..4f5d9c0b81 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -36,6 +36,8 @@ CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 29/36] dts: T2080RDB: Add ESPI slave device node
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (27 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 28/36] configs: T1042D4RDB: Enable ESPI driver Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 30/36] configs: T2080RDB: Enable ESPI driver Zhiqiang Hou
                   ` (6 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Add ESPI slave node for T2080RDB.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 arch/powerpc/dts/t2080rdb.dts | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/powerpc/dts/t2080rdb.dts b/arch/powerpc/dts/t2080rdb.dts
index 49c1765b29..34ec6a74cb 100644
--- a/arch/powerpc/dts/t2080rdb.dts
+++ b/arch/powerpc/dts/t2080rdb.dts
@@ -14,4 +14,19 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 	interrupt-parent = <&mpic>;
+
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
+&espi0 {
+	status = "okay";
+	flash at 0 {
+		compatible = "jedec,spi-nor"; /* 16MB */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
 };
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 30/36] configs: T2080RDB: Enable ESPI driver
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (28 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 29/36] dts: T2080RDB: Add ESPI slave device node Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 31/36] dts: T4240: Add ESPI DT nodes Zhiqiang Hou
                   ` (5 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Enable the DM ESPI driver in T2080RDB defconfig.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 configs/T2080RDB_NAND_defconfig     | 2 ++
 configs/T2080RDB_SDCARD_defconfig   | 2 ++
 configs/T2080RDB_SPIFLASH_defconfig | 2 ++
 configs/T2080RDB_defconfig          | 2 ++
 4 files changed, 8 insertions(+)

diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index 81baa5dbdd..e349396785 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -50,6 +50,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index a1d7d87b60..397ac2873c 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -48,6 +48,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index c433a922e6..3bea0da750 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -51,6 +51,8 @@ CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_ADDR=0xFFFC9000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index 85e3b64ad3..f9021e5e05 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -36,6 +36,8 @@ CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 31/36] dts: T4240: Add ESPI DT nodes
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (29 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 30/36] configs: T2080RDB: Enable ESPI driver Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 32/36] dts: T4240RDB: Add ESPI slave device node Zhiqiang Hou
                   ` (4 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Add ESPI controller DT node for T4240.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 arch/powerpc/dts/t4240.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/powerpc/dts/t4240.dtsi b/arch/powerpc/dts/t4240.dtsi
index 9b5902fe9e..227e758988 100644
--- a/arch/powerpc/dts/t4240.dtsi
+++ b/arch/powerpc/dts/t4240.dtsi
@@ -79,6 +79,15 @@
 			reg = <22 23>;
 			fsl,portid-mapping = <0x80000000>;
 		};
+
+		espi0: spi at 110000 {
+			compatible = "fsl,mpc8536-espi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x110000 0x1000>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
 	};
 
 	soc: soc at ffe000000 {
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 32/36] dts: T4240RDB: Add ESPI slave device node
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (30 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 31/36] dts: T4240: Add ESPI DT nodes Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 33/36] configs: T4240RDB: Enable ESPI driver Zhiqiang Hou
                   ` (3 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Add ESPI slave node for T4240RDB.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 arch/powerpc/dts/t4240rdb.dts | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/powerpc/dts/t4240rdb.dts b/arch/powerpc/dts/t4240rdb.dts
index f67d7ce2ae..635065a036 100644
--- a/arch/powerpc/dts/t4240rdb.dts
+++ b/arch/powerpc/dts/t4240rdb.dts
@@ -14,4 +14,19 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 	interrupt-parent = <&mpic>;
+
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
+&espi0 {
+	status = "okay";
+	flash at 0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
 };
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 33/36] configs: T4240RDB: Enable ESPI driver
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (31 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 32/36] dts: T4240RDB: Add ESPI slave device node Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 34/36] dts: P1010: Add eSPI controller DT node Zhiqiang Hou
                   ` (2 subsequent siblings)
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Enable the DM ESPI driver in T4240RDB defconfig.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Rebase the patch, no change intended.

 configs/T4240RDB_SDCARD_defconfig | 2 ++
 configs/T4240RDB_defconfig        | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index 14e366358b..a0238599f3 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -41,6 +41,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index dfe8953af7..95388a8cbf 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -29,6 +29,8 @@ CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 34/36] dts: P1010: Add eSPI controller DT node
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (32 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 33/36] configs: T4240RDB: Enable ESPI driver Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 35/36] dts: P1010RDB: Add eSPI slave DT nodes Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 36/36] configs: P1010RDB: Enable eSPI controller and SPI flash DM driver Zhiqiang Hou
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Add eSPI controller DT node for P1010.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - New patch to add support for P1010RDB.

 arch/powerpc/dts/p1010si-post.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/powerpc/dts/p1010si-post.dtsi b/arch/powerpc/dts/p1010si-post.dtsi
index 0289441381..aa04f5f033 100644
--- a/arch/powerpc/dts/p1010si-post.dtsi
+++ b/arch/powerpc/dts/p1010si-post.dtsi
@@ -23,6 +23,16 @@
 		single-cpu-affinity;
 		last-interrupt-source = <255>;
 	};
+
+	espi0: spi at 7000 {
+		compatible = "fsl,mpc8536-espi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x7000 0x1000>;
+		fsl,espi-num-chipselects = <1>;
+		status = "disabled";
+	};
+
 /include/ "pq3-i2c-0.dtsi"
 /include/ "pq3-i2c-1.dtsi"
 };
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 35/36] dts: P1010RDB: Add eSPI slave DT nodes
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (33 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 34/36] dts: P1010: Add eSPI controller DT node Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  2020-06-02 13:35 ` [PATCHv2 36/36] configs: P1010RDB: Enable eSPI controller and SPI flash DM driver Zhiqiang Hou
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Add DT nodes for eSPI slave device SPI flash.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - New patch to add support for P1010RDB.

 arch/powerpc/dts/p1010rdb-pa.dts     |  1 +
 arch/powerpc/dts/p1010rdb-pa_36b.dts |  1 +
 arch/powerpc/dts/p1010rdb.dtsi       | 17 +++++++++++++++++
 3 files changed, 19 insertions(+)

diff --git a/arch/powerpc/dts/p1010rdb-pa.dts b/arch/powerpc/dts/p1010rdb-pa.dts
index c66c4923ac..360d254d91 100644
--- a/arch/powerpc/dts/p1010rdb-pa.dts
+++ b/arch/powerpc/dts/p1010rdb-pa.dts
@@ -15,3 +15,4 @@
 };
 
 /include/ "p1010si-post.dtsi"
+/include/ "p1010rdb.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb-pa_36b.dts b/arch/powerpc/dts/p1010rdb-pa_36b.dts
index b943de7cbb..062086a8c0 100644
--- a/arch/powerpc/dts/p1010rdb-pa_36b.dts
+++ b/arch/powerpc/dts/p1010rdb-pa_36b.dts
@@ -15,3 +15,4 @@
 };
 
 /include/ "p1010si-post.dtsi"
+/include/ "p1010rdb.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb.dtsi b/arch/powerpc/dts/p1010rdb.dtsi
index 4f58ee2446..20bd570299 100644
--- a/arch/powerpc/dts/p1010rdb.dtsi
+++ b/arch/powerpc/dts/p1010rdb.dtsi
@@ -4,6 +4,12 @@
  *
  * Copyright 2020 NXP
  */
+/ {
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
 &soc {
 	i2c at 3000 {
 		rtc at 68 {
@@ -11,4 +17,15 @@
 			reg = <0x68>;
 		};
 	};
+
+	spi at 7000 {
+		status = "okay";
+		flash at 0 {
+			compatible = "jedec,spi-nor";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0>;
+			spi-max-frequency = <10000000>; /* input clock */
+		};
+	};
 };
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 36/36] configs: P1010RDB: Enable eSPI controller and SPI flash DM driver
  2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
                   ` (34 preceding siblings ...)
  2020-06-02 13:35 ` [PATCHv2 35/36] dts: P1010RDB: Add eSPI slave DT nodes Zhiqiang Hou
@ 2020-06-02 13:35 ` Zhiqiang Hou
  35 siblings, 0 replies; 41+ messages in thread
From: Zhiqiang Hou @ 2020-06-02 13:35 UTC (permalink / raw)
  To: u-boot

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Enable the DM_SPI and DM_SPI_FLASH in P1010RDB defconfigs except
SECBOOT defconfigs.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - New patch to add support for P1010RDB.

 configs/P1010RDB-PA_36BIT_NAND_defconfig     | 2 ++
 configs/P1010RDB-PA_36BIT_NOR_defconfig      | 2 ++
 configs/P1010RDB-PA_36BIT_SDCARD_defconfig   | 2 ++
 configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 ++
 configs/P1010RDB-PA_NAND_defconfig           | 2 ++
 configs/P1010RDB-PA_NOR_defconfig            | 2 ++
 configs/P1010RDB-PA_SDCARD_defconfig         | 2 ++
 configs/P1010RDB-PA_SPIFLASH_defconfig       | 2 ++
 configs/P1010RDB-PB_36BIT_NAND_defconfig     | 2 ++
 configs/P1010RDB-PB_36BIT_NOR_defconfig      | 2 ++
 configs/P1010RDB-PB_36BIT_SDCARD_defconfig   | 2 ++
 configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 ++
 configs/P1010RDB-PB_NAND_defconfig           | 2 ++
 configs/P1010RDB-PB_NOR_defconfig            | 2 ++
 configs/P1010RDB-PB_SDCARD_defconfig         | 2 ++
 configs/P1010RDB-PB_SPIFLASH_defconfig       | 2 ++
 16 files changed, 32 insertions(+)

diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index da04cab014..c10f3f3a4f 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -48,6 +48,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index e6edd395e7..dc69fec2f2 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -31,6 +31,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index dcd606b0c2..4674caf4a3 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -43,6 +43,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index c0800c8d7d..ded4db2555 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -45,6 +45,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index 29ba692ca1..6c2b1e8f1b 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -47,6 +47,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index d8f87b5dac..d49c27f9c6 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig
@@ -30,6 +30,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index 9711082529..68f31a0cb3 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -42,6 +42,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index de2ac2235f..d9298a058d 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -44,6 +44,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index 9f4876dd13..436e3b833f 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -48,6 +48,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index e85af32e2c..9d01ce4ed8 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -31,6 +31,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index 45feab4ee4..0d18dbe95f 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -43,6 +43,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index 3cd94f84ea..c78816e9ad 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -45,6 +45,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index ddfe7b43a1..f9953e184d 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -47,6 +47,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index 6011f8a9d8..2c6d28c922 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig
@@ -30,6 +30,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index 65f86fff60..8ae26b0171 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -42,6 +42,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index f71ee19ba6..486f417cf2 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -44,6 +44,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCHv2 01/36] dm: spi: Convert Freescale ESPI driver to driver model
  2020-06-02 13:34 ` [PATCHv2 01/36] dm: spi: Convert Freescale ESPI driver to driver model Zhiqiang Hou
@ 2020-06-02 19:28   ` Jagan Teki
  2020-06-03  2:03     ` Z.q. Hou
  0 siblings, 1 reply; 41+ messages in thread
From: Jagan Teki @ 2020-06-02 19:28 UTC (permalink / raw)
  To: u-boot

On Tue, Jun 2, 2020 at 7:10 PM Zhiqiang Hou <Zhiqiang.Hou@nxp.com> wrote:
>
> From: Chuanhua Han <chuanhua.han@nxp.com>
>
> Modify the Freescale ESPI driver to support the driver model.
> Also resolved the following problems:
>
> ===================== WARNING ======================
> This board does not use CONFIG_DM_SPI. Please update
> the board before v2019.04 for no dm conversion
> and v2019.07 for partially dm converted drivers.
> Failure to update can lead to driver/board removal
> See doc/driver-model/MIGRATION.txt for more info.
> ====================================================
> ===================== WARNING ======================
> This board does not use CONFIG_DM_SPI_FLASH. Please update
> the board to use CONFIG_SPI_FLASH before the v2019.07 release.
> Failure to update by the deadline may result in board removal.
> See doc/driver-model/MIGRATION.txt for more info.
> ====================================================
>
> Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
> Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V2:
>  - Rebase the patch, no change intended.
>
>  drivers/spi/fsl_espi.c              | 444 ++++++++++++++++++++--------
>  include/dm/platform_data/fsl_espi.h |  16 +
>  2 files changed, 337 insertions(+), 123 deletions(-)
>  create mode 100644 include/dm/platform_data/fsl_espi.h
>
> diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
> index 50d194f614..5c76fd962e 100644
> --- a/drivers/spi/fsl_espi.c
> +++ b/drivers/spi/fsl_espi.c
> @@ -3,7 +3,9 @@
>   * eSPI controller driver.
>   *
>   * Copyright 2010-2011 Freescale Semiconductor, Inc.
> + * Copyright 2020 NXP
>   * Author: Mingkai Hu (Mingkai.hu at freescale.com)
> + *        Chuanhua Han (chuanhua.han at nxp.com)
>   */
>
>  #include <common.h>
> @@ -14,10 +16,16 @@
>  #include <malloc.h>
>  #include <spi.h>
>  #include <asm/immap_85xx.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <fdtdec.h>
> +#include <dm/platform_data/fsl_espi.h>
>
>  struct fsl_spi_slave {
>         struct spi_slave slave;
>         ccsr_espi_t     *espi;
> +       u32             speed_hz;
> +       unsigned int    cs;
>         unsigned int    div16;
>         unsigned int    pm;
>         int             tx_timeout;
> @@ -31,6 +39,9 @@ struct fsl_spi_slave {
>  #define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave)
>  #define US_PER_SECOND          1000000UL
>
> +/* default SCK frequency, unit: HZ */
> +#define FSL_ESPI_DEFAULT_SCK_FREQ   10000000
> +
>  #define ESPI_MAX_CS_NUM                4
>  #define ESPI_FIFO_WIDTH_BIT    32
>
> @@ -65,116 +76,27 @@ struct fsl_spi_slave {
>
>  #define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0
>
> -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> -               unsigned int max_hz, unsigned int mode)
> -{
> -       struct fsl_spi_slave *fsl;
> -       sys_info_t sysinfo;
> -       unsigned long spibrg = 0;
> -       unsigned long spi_freq = 0;
> -       unsigned char pm = 0;
> -
> -       if (!spi_cs_is_valid(bus, cs))
> -               return NULL;
> -
> -       fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);
> -       if (!fsl)
> -               return NULL;
> -
> -       fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
> -       fsl->mode = mode;
> -       fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
> -
> -       /* Set eSPI BRG clock source */
> -       get_sys_info(&sysinfo);
> -       spibrg = sysinfo.freq_systembus / 2;
> -       fsl->div16 = 0;
> -       if ((spibrg / max_hz) > 32) {
> -               fsl->div16 = ESPI_CSMODE_DIV16;
> -               pm = spibrg / (max_hz * 16 * 2);
> -               if (pm > 16) {
> -                       pm = 16;
> -                       debug("Requested speed is too low: %d Hz, %ld Hz "
> -                               "is used.\n", max_hz, spibrg / (32 * 16));
> -               }
> -       } else
> -               pm = spibrg / (max_hz * 2);
> -       if (pm)
> -               pm--;
> -       fsl->pm = pm;
> -
> -       if (fsl->div16)
> -               spi_freq = spibrg / ((pm + 1) * 2 * 16);
> -       else
> -               spi_freq = spibrg / ((pm + 1) * 2);
> -
> -       /* set tx_timeout to 10 times of one espi FIFO entry go out */
> -       fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT
> -                               * 10), spi_freq);
> -
> -       return &fsl->slave;
> -}
> -
> -void spi_free_slave(struct spi_slave *slave)
> -{
> -       struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> -       free(fsl);
> -}
> -
> -int spi_claim_bus(struct spi_slave *slave)
> +void fsl_spi_cs_activate(struct spi_slave *slave, uint cs)
>  {
>         struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
>         ccsr_espi_t *espi = fsl->espi;
> -       unsigned char pm = fsl->pm;
> -       unsigned int cs = slave->cs;
> -       unsigned int mode =  fsl->mode;
> -       unsigned int div16 = fsl->div16;
> -       int i;
> -
> -       debug("%s: bus:%i cs:%i\n", __func__, slave->bus, cs);
> -
> -       /* Enable eSPI interface */
> -       out_be32(&espi->mode, ESPI_MODE_RXTHR(3)
> -                       | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN);
> -
> -       out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */
> -       out_be32(&espi->mask, 0x00000000); /* Mask  all eSPI interrupts */
> -
> -       /* Init CS mode interface */
> -       for (i = 0; i < ESPI_MAX_CS_NUM; i++)
> -               out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL);
> -
> -       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) &
> -               ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16
> -               | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK
> -               | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF)));
> -
> -       /* Set eSPI BRG clock source */
> -       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> -               | ESPI_CSMODE_PM(pm) | div16);
> -
> -       /* Set eSPI mode */
> -       if (mode & SPI_CPHA)
> -               out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> -                       | ESPI_CSMODE_CP_BEGIN_EDGCLK);
> -       if (mode & SPI_CPOL)
> -               out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> -                       | ESPI_CSMODE_CI_INACTIVEHIGH);
> -
> -       /* Character bit order: msb first */
> -       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> -               | ESPI_CSMODE_REV_MSB_FIRST);
> -
> -       /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */
> -       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> -               | ESPI_CSMODE_LEN(7));
> +       unsigned int com = 0;
> +       size_t data_len = fsl->data_len;
>
> -       return 0;
> +       com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF));
> +       com |= ESPI_COM_CS(cs);
> +       com |= ESPI_COM_TRANLEN(data_len - 1);
> +       out_be32(&espi->com, com);
>  }
>
> -void spi_release_bus(struct spi_slave *slave)
> +void fsl_spi_cs_deactivate(struct spi_slave *slave)
>  {
> +       struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> +       ccsr_espi_t *espi = fsl->espi;
>
> +       /* clear the RXCNT and TXCNT */
> +       out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN));
> +       out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN);
>  }
>
>  static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout)
> @@ -207,7 +129,8 @@ static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout)
>                 debug("***spi_xfer:...Tx timeout! event = %08x\n", event);
>  }
>
> -static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes)
> +static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din,
> +                      unsigned int bytes)
>  {
>         ccsr_espi_t *espi = fsl->espi;
>         unsigned int tmpdin, rx_times;
> @@ -239,10 +162,17 @@ static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes)
>         return bytes;
>  }
>
> -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
> -               void *data_in, unsigned long flags)
> +void  espi_release_bus(struct fsl_spi_slave *fsl)
>  {
> -       struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> +       /* Disable the SPI hardware */
> +        out_be32(&fsl->espi->mode,
> +                 in_be32(&fsl->espi->mode) & (~ESPI_MODE_EN));
> +}
> +
> +int espi_xfer(struct fsl_spi_slave *fsl,  uint cs, unsigned int bitlen,
> +             const void *data_out, void *data_in, unsigned long flags)
> +{
> +       struct spi_slave *slave = &fsl->slave;
>         ccsr_espi_t *espi = fsl->espi;
>         unsigned int event, rx_bytes;
>         const void *dout = NULL;
> @@ -261,13 +191,14 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
>         max_tran_len = fsl->max_transfer_length;
>         switch (flags) {
>         case SPI_XFER_BEGIN:
> -               cmd_len = fsl->cmd_len = data_len;
> +               cmd_len = data_len;
> +               fsl->cmd_len = cmd_len;
>                 memcpy(cmd_buf, data_out, cmd_len);
>                 return 0;
>         case 0:
>         case SPI_XFER_END:
>                 if (bitlen == 0) {
> -                       spi_cs_deactivate(slave);
> +                       fsl_spi_cs_deactivate(slave);
>                         return 0;
>                 }
>                 buf_len = 2 * cmd_len + min(data_len, (size_t)max_tran_len);
> @@ -307,7 +238,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
>                 num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4);
>                 num_bytes = (tran_len + cmd_len) % 4;
>                 fsl->data_len = tran_len + cmd_len;
> -               spi_cs_activate(slave);
> +               fsl_spi_cs_activate(slave, cs);
>
>                 /* Clear all eSPI events */
>                 out_be32(&espi->event , 0xffffffff);
> @@ -350,37 +281,304 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
>                                 *(int *)buffer += tran_len;
>                         }
>                 }
> -               spi_cs_deactivate(slave);
> +               fsl_spi_cs_deactivate(slave);
>         }
>
>         free(buffer);
>         return 0;
>  }
>
> +void espi_claim_bus(struct fsl_spi_slave *fsl, unsigned int cs)
> +{
> +       ccsr_espi_t *espi = fsl->espi;
> +       unsigned char pm = fsl->pm;
> +       unsigned int mode =  fsl->mode;
> +       unsigned int div16 = fsl->div16;
> +       int i;
> +
> +       /* Enable eSPI interface */
> +       out_be32(&espi->mode, ESPI_MODE_RXTHR(3)
> +                       | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN);
> +
> +       out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */
> +       out_be32(&espi->mask, 0x00000000); /* Mask  all eSPI interrupts */
> +
> +       /* Init CS mode interface */
> +       for (i = 0; i < ESPI_MAX_CS_NUM; i++)
> +               out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL);
> +
> +       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) &
> +               ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16
> +               | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK
> +               | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF)));
> +
> +       /* Set eSPI BRG clock source */
> +       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> +               | ESPI_CSMODE_PM(pm) | div16);
> +
> +       /* Set eSPI mode */
> +       if (mode & SPI_CPHA)
> +               out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> +                       | ESPI_CSMODE_CP_BEGIN_EDGCLK);
> +       if (mode & SPI_CPOL)
> +               out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> +                       | ESPI_CSMODE_CI_INACTIVEHIGH);
> +
> +       /* Character bit order: msb first */
> +       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> +               | ESPI_CSMODE_REV_MSB_FIRST);
> +
> +       /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */
> +       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> +               | ESPI_CSMODE_LEN(7));
> +}
> +
> +void espi_setup_slave(struct fsl_spi_slave *fsl)
> +{
> +       unsigned int max_hz;
> +       sys_info_t sysinfo;
> +       unsigned long spibrg = 0;
> +       unsigned long spi_freq = 0;
> +       unsigned char pm = 0;
> +
> +       max_hz = fsl->speed_hz;
> +
> +       get_sys_info(&sysinfo);
> +       spibrg = sysinfo.freq_systembus / 2;
> +       fsl->div16 = 0;
> +       if ((spibrg / max_hz) > 32) {
> +               fsl->div16 = ESPI_CSMODE_DIV16;
> +               pm = spibrg / (max_hz * 16 * 2);
> +               if (pm > 16) {
> +                       pm = 16;
> +                       debug("max_hz is too low: %d Hz, %ld Hz is used.\n",
> +                             max_hz, spibrg / (32 * 16));
> +               }
> +       } else {
> +               pm = spibrg / (max_hz * 2);
> +       }
> +       if (pm)
> +               pm--;
> +       fsl->pm = pm;
> +
> +       if (fsl->div16)
> +               spi_freq = spibrg / ((pm + 1) * 2 * 16);
> +       else
> +               spi_freq = spibrg / ((pm + 1) * 2);
> +
> +       /* set tx_timeout to 10 times of one espi FIFO entry go out */
> +       fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT
> +                               * 10), spi_freq);/* Set eSPI BRG clock source */
> +}
> +
> +#if !CONFIG_IS_ENABLED(DM_SPI)
>  int spi_cs_is_valid(unsigned int bus, unsigned int cs)
>  {
>         return bus == 0 && cs < ESPI_MAX_CS_NUM;
>  }
>
> -void spi_cs_activate(struct spi_slave *slave)
> +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> +                                 unsigned int max_hz, unsigned int mode)
> +{
> +       struct fsl_spi_slave *fsl;
> +
> +       if (!spi_cs_is_valid(bus, cs))
> +               return NULL;
> +
> +       fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);
> +       if (!fsl)
> +               return NULL;
> +
> +       fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
> +       fsl->mode = mode;
> +       fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
> +       fsl->speed_hz = max_hz;
> +
> +       espi_setup_slave(fsl);
> +
> +       return &fsl->slave;
> +}
> +
> +void spi_free_slave(struct spi_slave *slave)
>  {
>         struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> -       ccsr_espi_t *espi = fsl->espi;
> -       unsigned int com = 0;
> -       size_t data_len = fsl->data_len;
>
> -       com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF));
> -       com |= ESPI_COM_CS(slave->cs);
> -       com |= ESPI_COM_TRANLEN(data_len - 1);
> -       out_be32(&espi->com, com);
> +       free(fsl);
>  }
>
> -void spi_cs_deactivate(struct spi_slave *slave)
> +int spi_claim_bus(struct spi_slave *slave)
>  {
>         struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> -       ccsr_espi_t *espi = fsl->espi;
>
> -       /* clear the RXCNT and TXCNT */
> -       out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN));
> -       out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN);
> +       espi_claim_bus(fsl, slave->cs);
> +
> +       return 0;
>  }
> +
> +void spi_release_bus(struct spi_slave *slave)
> +{
> +       struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> +
> +       espi_release_bus(fsl);
> +}
> +
> +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
> +            void *din, unsigned long flags)
> +{
> +       struct fsl_spi_slave *fsl = (struct fsl_spi_slave *)slave;
> +
> +       return espi_xfer(fsl, slave->cs, bitlen, dout, din, flags);
> +}
> +#else
> +static void __espi_set_speed(struct fsl_spi_slave *fsl)
> +{
> +       espi_setup_slave(fsl);
> +
> +       /* Set eSPI BRG clock source */
> +       out_be32(&fsl->espi->csmode[fsl->cs],
> +                in_be32(&fsl->espi->csmode[fsl->cs])
> +                        | ESPI_CSMODE_PM(fsl->pm) | fsl->div16);
> +}
> +
> +static void __espi_set_mode(struct fsl_spi_slave *fsl)
> +{
> +       /* Set eSPI mode */
> +       if (fsl->mode & SPI_CPHA)
> +               out_be32(&fsl->espi->csmode[fsl->cs],
> +                        in_be32(&fsl->espi->csmode[fsl->cs])
> +                               | ESPI_CSMODE_CP_BEGIN_EDGCLK);
> +       if (fsl->mode & SPI_CPOL)
> +               out_be32(&fsl->espi->csmode[fsl->cs],
> +                        in_be32(&fsl->espi->csmode[fsl->cs])
> +                               | ESPI_CSMODE_CI_INACTIVEHIGH);
> +}
> +
> +static int fsl_espi_claim_bus(struct udevice *dev)
> +{
> +       struct udevice *bus = dev->parent;
> +       struct fsl_spi_slave  *fsl =  dev_get_priv(bus);
> +
> +       espi_claim_bus(fsl, fsl->cs);
> +
> +       return 0;
> +}
> +
> +static int fsl_espi_release_bus(struct udevice *dev)
> +{
> +       struct udevice *bus = dev->parent;
> +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> +
> +       espi_release_bus(fsl);
> +
> +       return 0;
> +}
> +
> +static int fsl_espi_xfer(struct udevice *dev, unsigned int bitlen,
> +                        const void *dout, void *din, unsigned long flags)
> +{
> +       struct udevice *bus = dev->parent;
> +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> +
> +       return espi_xfer(fsl, fsl->cs, bitlen, dout, din, flags);
> +}
> +
> +static int fsl_espi_set_speed(struct udevice *bus, uint speed)
> +{
> +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> +
> +       debug("%s speed %u\n", __func__, speed);
> +       fsl->speed_hz = speed;
> +
> +       __espi_set_speed(fsl);
> +
> +       return 0;
> +}
> +
> +static int fsl_espi_set_mode(struct udevice *bus, uint mode)
> +{
> +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> +
> +       debug("%s mode %u\n", __func__, mode);
> +       fsl->mode = mode;
> +
> +       __espi_set_mode(fsl);
> +
> +       return 0;
> +}
> +
> +static int fsl_espi_child_pre_probe(struct udevice *dev)
> +{
> +       struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
> +       struct udevice *bus = dev->parent;
> +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> +
> +       debug("%s cs %u\n", __func__, slave_plat->cs);
> +       fsl->cs = slave_plat->cs;
> +
> +       return 0;
> +}
> +
> +static int fsl_espi_probe(struct udevice *bus)
> +{
> +       struct fsl_espi_platdata *plat = dev_get_platdata(bus);
> +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> +
> +       fsl->espi = (ccsr_espi_t *)((u32)plat->regs_addr);
> +       fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
> +       fsl->speed_hz = plat->speed_hz;
> +
> +       debug("%s probe done, bus-num %d.\n", bus->name, bus->seq);
> +
> +       return 0;
> +}
> +
> +static const struct dm_spi_ops fsl_espi_ops = {
> +       .claim_bus      = fsl_espi_claim_bus,
> +       .release_bus    = fsl_espi_release_bus,
> +       .xfer           = fsl_espi_xfer,
> +       .set_speed      = fsl_espi_set_speed,
> +       .set_mode       = fsl_espi_set_mode,
> +};
> +
> +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
> +static int fsl_espi_ofdata_to_platdata(struct udevice *bus)
> +{
> +       fdt_addr_t addr;
> +       struct fsl_espi_platdata   *plat = bus->platdata;
> +       const void *blob = gd->fdt_blob;
> +       int node = dev_of_offset(bus);
> +
> +       addr = dev_read_addr(bus);
> +       if (addr == FDT_ADDR_T_NONE)
> +               return -EINVAL;
> +
> +       plat->regs_addr = lower_32_bits(addr);
> +       plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
> +                                       FSL_ESPI_DEFAULT_SCK_FREQ);
> +
> +       debug("ESPI: regs=%p, max-frequency=%d\n",
> +             &plat->regs_addr, plat->speed_hz);
> +
> +       return 0;
> +}
> +
> +static const struct udevice_id fsl_espi_ids[] = {
> +       { .compatible = "fsl,mpc8536-espi" },
> +       { }
> +};
> +#endif
> +
> +U_BOOT_DRIVER(fsl_espi) = {
> +       .name   = "fsl_espi",
> +       .id     = UCLASS_SPI,
> +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
> +       .of_match = fsl_espi_ids,
> +       .ofdata_to_platdata = fsl_espi_ofdata_to_platdata,
> +#endif
> +       .ops    = &fsl_espi_ops,
> +       .platdata_auto_alloc_size = sizeof(struct fsl_espi_platdata),
> +       .priv_auto_alloc_size = sizeof(struct fsl_spi_slave),
> +       .probe  = fsl_espi_probe,
> +       .child_pre_probe = fsl_espi_child_pre_probe,
> +};
> +#endif

It still has nondm code, does it required for SPL due to foot-print
restrictions? How much are the numbers please?

Jagan.

^ permalink raw reply	[flat|nested] 41+ messages in thread
* [PATCHv2 01/36] dm: spi: Convert Freescale ESPI driver to driver model
  2020-06-02 19:28   ` Jagan Teki
@ 2020-06-03  2:03     ` Z.q. Hou
  2020-06-03  7:41       ` Jagan Teki
  0 siblings, 1 reply; 41+ messages in thread
From: Z.q. Hou @ 2020-06-03  2:03 UTC (permalink / raw)
  To: u-boot

Hi Jagan,

Thanks a lot for your comments!

> -----Original Message-----
> From: Jagan Teki <jagan@amarulasolutions.com>
> Sent: 2020?6?3? 3:29
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: U-Boot-Denx <u-boot@lists.denx.de>; Priyanka Jain
> <priyanka.jain@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>; Simon
> Glass <sjg@chromium.org>; Biwen Li <biwen.li@nxp.com>; Bin Meng
> <bmeng.cn@gmail.com>; Jiafei Pan <jiafei.pan@nxp.com>; Chuanhua Han
> <chuanhua.han@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv2 01/36] dm: spi: Convert Freescale ESPI driver to driver
> model
> 
> On Tue, Jun 2, 2020 at 7:10 PM Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
> wrote:
> >
> > From: Chuanhua Han <chuanhua.han@nxp.com>
> >
> > Modify the Freescale ESPI driver to support the driver model.
> > Also resolved the following problems:
> >
> > ===================== WARNING ====================== This
> board does
> > not use CONFIG_DM_SPI. Please update the board before v2019.04 for no
> > dm conversion and v2019.07 for partially dm converted drivers.
> > Failure to update can lead to driver/board removal See
> > doc/driver-model/MIGRATION.txt for more info.
> > ====================================================
> > ===================== WARNING ====================== This
> board does
> > not use CONFIG_DM_SPI_FLASH. Please update the board to use
> > CONFIG_SPI_FLASH before the v2019.07 release.
> > Failure to update by the deadline may result in board removal.
> > See doc/driver-model/MIGRATION.txt for more info.
> > ====================================================
> >
> > Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
> > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > ---
> > V2:
> >  - Rebase the patch, no change intended.
> >
> >  drivers/spi/fsl_espi.c              | 444
> ++++++++++++++++++++--------
> >  include/dm/platform_data/fsl_espi.h |  16 +
> >  2 files changed, 337 insertions(+), 123 deletions(-)  create mode
> > 100644 include/dm/platform_data/fsl_espi.h
> >
> > diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index
> > 50d194f614..5c76fd962e 100644
> > --- a/drivers/spi/fsl_espi.c
> > +++ b/drivers/spi/fsl_espi.c
> > @@ -3,7 +3,9 @@
> >   * eSPI controller driver.
> >   *
> >   * Copyright 2010-2011 Freescale Semiconductor, Inc.
> > + * Copyright 2020 NXP
> >   * Author: Mingkai Hu (Mingkai.hu at freescale.com)
> > + *        Chuanhua Han (chuanhua.han at nxp.com)
> >   */
> >
> >  #include <common.h>
> > @@ -14,10 +16,16 @@
> >  #include <malloc.h>
> >  #include <spi.h>
> >  #include <asm/immap_85xx.h>
> > +#include <dm.h>
> > +#include <errno.h>
> > +#include <fdtdec.h>
> > +#include <dm/platform_data/fsl_espi.h>
> >
> >  struct fsl_spi_slave {
> >         struct spi_slave slave;
> >         ccsr_espi_t     *espi;
> > +       u32             speed_hz;
> > +       unsigned int    cs;
> >         unsigned int    div16;
> >         unsigned int    pm;
> >         int             tx_timeout;
> > @@ -31,6 +39,9 @@ struct fsl_spi_slave {  #define to_fsl_spi_slave(s)
> > container_of(s, struct fsl_spi_slave, slave)
> >  #define US_PER_SECOND          1000000UL
> >
> > +/* default SCK frequency, unit: HZ */
> > +#define FSL_ESPI_DEFAULT_SCK_FREQ   10000000
> > +
> >  #define ESPI_MAX_CS_NUM                4
> >  #define ESPI_FIFO_WIDTH_BIT    32
> >
> > @@ -65,116 +76,27 @@ struct fsl_spi_slave {
> >
> >  #define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0
> >
> > -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> > -               unsigned int max_hz, unsigned int mode)
> > -{
> > -       struct fsl_spi_slave *fsl;
> > -       sys_info_t sysinfo;
> > -       unsigned long spibrg = 0;
> > -       unsigned long spi_freq = 0;
> > -       unsigned char pm = 0;
> > -
> > -       if (!spi_cs_is_valid(bus, cs))
> > -               return NULL;
> > -
> > -       fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);
> > -       if (!fsl)
> > -               return NULL;
> > -
> > -       fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
> > -       fsl->mode = mode;
> > -       fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
> > -
> > -       /* Set eSPI BRG clock source */
> > -       get_sys_info(&sysinfo);
> > -       spibrg = sysinfo.freq_systembus / 2;
> > -       fsl->div16 = 0;
> > -       if ((spibrg / max_hz) > 32) {
> > -               fsl->div16 = ESPI_CSMODE_DIV16;
> > -               pm = spibrg / (max_hz * 16 * 2);
> > -               if (pm > 16) {
> > -                       pm = 16;
> > -                       debug("Requested speed is too low: %d
> Hz, %ld Hz "
> > -                               "is used.\n", max_hz, spibrg / (32 *
> 16));
> > -               }
> > -       } else
> > -               pm = spibrg / (max_hz * 2);
> > -       if (pm)
> > -               pm--;
> > -       fsl->pm = pm;
> > -
> > -       if (fsl->div16)
> > -               spi_freq = spibrg / ((pm + 1) * 2 * 16);
> > -       else
> > -               spi_freq = spibrg / ((pm + 1) * 2);
> > -
> > -       /* set tx_timeout to 10 times of one espi FIFO entry go out */
> > -       fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND *
> ESPI_FIFO_WIDTH_BIT
> > -                               * 10), spi_freq);
> > -
> > -       return &fsl->slave;
> > -}
> > -
> > -void spi_free_slave(struct spi_slave *slave) -{
> > -       struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> > -       free(fsl);
> > -}
> > -
> > -int spi_claim_bus(struct spi_slave *slave)
> > +void fsl_spi_cs_activate(struct spi_slave *slave, uint cs)
> >  {
> >         struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> >         ccsr_espi_t *espi = fsl->espi;
> > -       unsigned char pm = fsl->pm;
> > -       unsigned int cs = slave->cs;
> > -       unsigned int mode =  fsl->mode;
> > -       unsigned int div16 = fsl->div16;
> > -       int i;
> > -
> > -       debug("%s: bus:%i cs:%i\n", __func__, slave->bus, cs);
> > -
> > -       /* Enable eSPI interface */
> > -       out_be32(&espi->mode, ESPI_MODE_RXTHR(3)
> > -                       | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN);
> > -
> > -       out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */
> > -       out_be32(&espi->mask, 0x00000000); /* Mask  all eSPI
> interrupts */
> > -
> > -       /* Init CS mode interface */
> > -       for (i = 0; i < ESPI_MAX_CS_NUM; i++)
> > -               out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL);
> > -
> > -       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) &
> > -               ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16
> > -               | ESPI_CSMODE_CI_INACTIVEHIGH |
> ESPI_CSMODE_CP_BEGIN_EDGCLK
> > -               | ESPI_CSMODE_REV_MSB_FIRST |
> ESPI_CSMODE_LEN(0xF)));
> > -
> > -       /* Set eSPI BRG clock source */
> > -       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> > -               | ESPI_CSMODE_PM(pm) | div16);
> > -
> > -       /* Set eSPI mode */
> > -       if (mode & SPI_CPHA)
> > -               out_be32(&espi->csmode[cs],
> in_be32(&espi->csmode[cs])
> > -                       | ESPI_CSMODE_CP_BEGIN_EDGCLK);
> > -       if (mode & SPI_CPOL)
> > -               out_be32(&espi->csmode[cs],
> in_be32(&espi->csmode[cs])
> > -                       | ESPI_CSMODE_CI_INACTIVEHIGH);
> > -
> > -       /* Character bit order: msb first */
> > -       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> > -               | ESPI_CSMODE_REV_MSB_FIRST);
> > -
> > -       /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */
> > -       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> > -               | ESPI_CSMODE_LEN(7));
> > +       unsigned int com = 0;
> > +       size_t data_len = fsl->data_len;
> >
> > -       return 0;
> > +       com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF));
> > +       com |= ESPI_COM_CS(cs);
> > +       com |= ESPI_COM_TRANLEN(data_len - 1);
> > +       out_be32(&espi->com, com);
> >  }
> >
> > -void spi_release_bus(struct spi_slave *slave)
> > +void fsl_spi_cs_deactivate(struct spi_slave *slave)
> >  {
> > +       struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> > +       ccsr_espi_t *espi = fsl->espi;
> >
> > +       /* clear the RXCNT and TXCNT */
> > +       out_be32(&espi->mode, in_be32(&espi->mode) &
> (~ESPI_MODE_EN));
> > +       out_be32(&espi->mode, in_be32(&espi->mode) |
> ESPI_MODE_EN);
> >  }
> >
> >  static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout)
> > @@ -207,7 +129,8 @@ static void fsl_espi_tx(struct fsl_spi_slave *fsl,
> const void *dout)
> >                 debug("***spi_xfer:...Tx timeout! event = %08x\n",
> > event);  }
> >
> > -static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned
> > int bytes)
> > +static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din,
> > +                      unsigned int bytes)
> >  {
> >         ccsr_espi_t *espi = fsl->espi;
> >         unsigned int tmpdin, rx_times; @@ -239,10 +162,17 @@ static
> > int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes)
> >         return bytes;
> >  }
> >
> > -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void
> *data_out,
> > -               void *data_in, unsigned long flags)
> > +void  espi_release_bus(struct fsl_spi_slave *fsl)
> >  {
> > -       struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> > +       /* Disable the SPI hardware */
> > +        out_be32(&fsl->espi->mode,
> > +                 in_be32(&fsl->espi->mode) & (~ESPI_MODE_EN)); }
> > +
> > +int espi_xfer(struct fsl_spi_slave *fsl,  uint cs, unsigned int bitlen,
> > +             const void *data_out, void *data_in, unsigned long
> > +flags) {
> > +       struct spi_slave *slave = &fsl->slave;
> >         ccsr_espi_t *espi = fsl->espi;
> >         unsigned int event, rx_bytes;
> >         const void *dout = NULL;
> > @@ -261,13 +191,14 @@ int spi_xfer(struct spi_slave *slave, unsigned int
> bitlen, const void *data_out,
> >         max_tran_len = fsl->max_transfer_length;
> >         switch (flags) {
> >         case SPI_XFER_BEGIN:
> > -               cmd_len = fsl->cmd_len = data_len;
> > +               cmd_len = data_len;
> > +               fsl->cmd_len = cmd_len;
> >                 memcpy(cmd_buf, data_out, cmd_len);
> >                 return 0;
> >         case 0:
> >         case SPI_XFER_END:
> >                 if (bitlen == 0) {
> > -                       spi_cs_deactivate(slave);
> > +                       fsl_spi_cs_deactivate(slave);
> >                         return 0;
> >                 }
> >                 buf_len = 2 * cmd_len + min(data_len,
> > (size_t)max_tran_len); @@ -307,7 +238,7 @@ int spi_xfer(struct spi_slave
> *slave, unsigned int bitlen, const void *data_out,
> >                 num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4);
> >                 num_bytes = (tran_len + cmd_len) % 4;
> >                 fsl->data_len = tran_len + cmd_len;
> > -               spi_cs_activate(slave);
> > +               fsl_spi_cs_activate(slave, cs);
> >
> >                 /* Clear all eSPI events */
> >                 out_be32(&espi->event , 0xffffffff); @@ -350,37
> > +281,304 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const
> void *data_out,
> >                                 *(int *)buffer += tran_len;
> >                         }
> >                 }
> > -               spi_cs_deactivate(slave);
> > +               fsl_spi_cs_deactivate(slave);
> >         }
> >
> >         free(buffer);
> >         return 0;
> >  }
> >
> > +void espi_claim_bus(struct fsl_spi_slave *fsl, unsigned int cs) {
> > +       ccsr_espi_t *espi = fsl->espi;
> > +       unsigned char pm = fsl->pm;
> > +       unsigned int mode =  fsl->mode;
> > +       unsigned int div16 = fsl->div16;
> > +       int i;
> > +
> > +       /* Enable eSPI interface */
> > +       out_be32(&espi->mode, ESPI_MODE_RXTHR(3)
> > +                       | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN);
> > +
> > +       out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */
> > +       out_be32(&espi->mask, 0x00000000); /* Mask  all eSPI
> > + interrupts */
> > +
> > +       /* Init CS mode interface */
> > +       for (i = 0; i < ESPI_MAX_CS_NUM; i++)
> > +               out_be32(&espi->csmode[i],
> ESPI_CSMODE_INIT_VAL);
> > +
> > +       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) &
> > +               ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16
> > +               | ESPI_CSMODE_CI_INACTIVEHIGH |
> ESPI_CSMODE_CP_BEGIN_EDGCLK
> > +               | ESPI_CSMODE_REV_MSB_FIRST |
> ESPI_CSMODE_LEN(0xF)));
> > +
> > +       /* Set eSPI BRG clock source */
> > +       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> > +               | ESPI_CSMODE_PM(pm) | div16);
> > +
> > +       /* Set eSPI mode */
> > +       if (mode & SPI_CPHA)
> > +               out_be32(&espi->csmode[cs],
> in_be32(&espi->csmode[cs])
> > +                       | ESPI_CSMODE_CP_BEGIN_EDGCLK);
> > +       if (mode & SPI_CPOL)
> > +               out_be32(&espi->csmode[cs],
> in_be32(&espi->csmode[cs])
> > +                       | ESPI_CSMODE_CI_INACTIVEHIGH);
> > +
> > +       /* Character bit order: msb first */
> > +       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> > +               | ESPI_CSMODE_REV_MSB_FIRST);
> > +
> > +       /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */
> > +       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> > +               | ESPI_CSMODE_LEN(7)); }
> > +
> > +void espi_setup_slave(struct fsl_spi_slave *fsl) {
> > +       unsigned int max_hz;
> > +       sys_info_t sysinfo;
> > +       unsigned long spibrg = 0;
> > +       unsigned long spi_freq = 0;
> > +       unsigned char pm = 0;
> > +
> > +       max_hz = fsl->speed_hz;
> > +
> > +       get_sys_info(&sysinfo);
> > +       spibrg = sysinfo.freq_systembus / 2;
> > +       fsl->div16 = 0;
> > +       if ((spibrg / max_hz) > 32) {
> > +               fsl->div16 = ESPI_CSMODE_DIV16;
> > +               pm = spibrg / (max_hz * 16 * 2);
> > +               if (pm > 16) {
> > +                       pm = 16;
> > +                       debug("max_hz is too low: %d Hz, %ld Hz is
> used.\n",
> > +                             max_hz, spibrg / (32 * 16));
> > +               }
> > +       } else {
> > +               pm = spibrg / (max_hz * 2);
> > +       }
> > +       if (pm)
> > +               pm--;
> > +       fsl->pm = pm;
> > +
> > +       if (fsl->div16)
> > +               spi_freq = spibrg / ((pm + 1) * 2 * 16);
> > +       else
> > +               spi_freq = spibrg / ((pm + 1) * 2);
> > +
> > +       /* set tx_timeout to 10 times of one espi FIFO entry go out */
> > +       fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND *
> ESPI_FIFO_WIDTH_BIT
> > +                               * 10), spi_freq);/* Set eSPI BRG
> clock
> > +source */ }
> > +
> > +#if !CONFIG_IS_ENABLED(DM_SPI)
> >  int spi_cs_is_valid(unsigned int bus, unsigned int cs)  {
> >         return bus == 0 && cs < ESPI_MAX_CS_NUM;  }
> >
> > -void spi_cs_activate(struct spi_slave *slave)
> > +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> > +                                 unsigned int max_hz, unsigned
> int
> > +mode) {
> > +       struct fsl_spi_slave *fsl;
> > +
> > +       if (!spi_cs_is_valid(bus, cs))
> > +               return NULL;
> > +
> > +       fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);
> > +       if (!fsl)
> > +               return NULL;
> > +
> > +       fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
> > +       fsl->mode = mode;
> > +       fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
> > +       fsl->speed_hz = max_hz;
> > +
> > +       espi_setup_slave(fsl);
> > +
> > +       return &fsl->slave;
> > +}
> > +
> > +void spi_free_slave(struct spi_slave *slave)
> >  {
> >         struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> > -       ccsr_espi_t *espi = fsl->espi;
> > -       unsigned int com = 0;
> > -       size_t data_len = fsl->data_len;
> >
> > -       com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF));
> > -       com |= ESPI_COM_CS(slave->cs);
> > -       com |= ESPI_COM_TRANLEN(data_len - 1);
> > -       out_be32(&espi->com, com);
> > +       free(fsl);
> >  }
> >
> > -void spi_cs_deactivate(struct spi_slave *slave)
> > +int spi_claim_bus(struct spi_slave *slave)
> >  {
> >         struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> > -       ccsr_espi_t *espi = fsl->espi;
> >
> > -       /* clear the RXCNT and TXCNT */
> > -       out_be32(&espi->mode, in_be32(&espi->mode) &
> (~ESPI_MODE_EN));
> > -       out_be32(&espi->mode, in_be32(&espi->mode) |
> ESPI_MODE_EN);
> > +       espi_claim_bus(fsl, slave->cs);
> > +
> > +       return 0;
> >  }
> > +
> > +void spi_release_bus(struct spi_slave *slave) {
> > +       struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> > +
> > +       espi_release_bus(fsl);
> > +}
> > +
> > +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
> > +            void *din, unsigned long flags) {
> > +       struct fsl_spi_slave *fsl = (struct fsl_spi_slave *)slave;
> > +
> > +       return espi_xfer(fsl, slave->cs, bitlen, dout, din, flags); }
> > +#else static void __espi_set_speed(struct fsl_spi_slave *fsl) {
> > +       espi_setup_slave(fsl);
> > +
> > +       /* Set eSPI BRG clock source */
> > +       out_be32(&fsl->espi->csmode[fsl->cs],
> > +                in_be32(&fsl->espi->csmode[fsl->cs])
> > +                        | ESPI_CSMODE_PM(fsl->pm) | fsl->div16); }
> > +
> > +static void __espi_set_mode(struct fsl_spi_slave *fsl) {
> > +       /* Set eSPI mode */
> > +       if (fsl->mode & SPI_CPHA)
> > +               out_be32(&fsl->espi->csmode[fsl->cs],
> > +                        in_be32(&fsl->espi->csmode[fsl->cs])
> > +                               |
> ESPI_CSMODE_CP_BEGIN_EDGCLK);
> > +       if (fsl->mode & SPI_CPOL)
> > +               out_be32(&fsl->espi->csmode[fsl->cs],
> > +                        in_be32(&fsl->espi->csmode[fsl->cs])
> > +                               |
> ESPI_CSMODE_CI_INACTIVEHIGH); }
> > +
> > +static int fsl_espi_claim_bus(struct udevice *dev) {
> > +       struct udevice *bus = dev->parent;
> > +       struct fsl_spi_slave  *fsl =  dev_get_priv(bus);
> > +
> > +       espi_claim_bus(fsl, fsl->cs);
> > +
> > +       return 0;
> > +}
> > +
> > +static int fsl_espi_release_bus(struct udevice *dev) {
> > +       struct udevice *bus = dev->parent;
> > +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> > +
> > +       espi_release_bus(fsl);
> > +
> > +       return 0;
> > +}
> > +
> > +static int fsl_espi_xfer(struct udevice *dev, unsigned int bitlen,
> > +                        const void *dout, void *din, unsigned long
> > +flags) {
> > +       struct udevice *bus = dev->parent;
> > +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> > +
> > +       return espi_xfer(fsl, fsl->cs, bitlen, dout, din, flags); }
> > +
> > +static int fsl_espi_set_speed(struct udevice *bus, uint speed) {
> > +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> > +
> > +       debug("%s speed %u\n", __func__, speed);
> > +       fsl->speed_hz = speed;
> > +
> > +       __espi_set_speed(fsl);
> > +
> > +       return 0;
> > +}
> > +
> > +static int fsl_espi_set_mode(struct udevice *bus, uint mode) {
> > +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> > +
> > +       debug("%s mode %u\n", __func__, mode);
> > +       fsl->mode = mode;
> > +
> > +       __espi_set_mode(fsl);
> > +
> > +       return 0;
> > +}
> > +
> > +static int fsl_espi_child_pre_probe(struct udevice *dev) {
> > +       struct dm_spi_slave_platdata *slave_plat =
> dev_get_parent_platdata(dev);
> > +       struct udevice *bus = dev->parent;
> > +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> > +
> > +       debug("%s cs %u\n", __func__, slave_plat->cs);
> > +       fsl->cs = slave_plat->cs;
> > +
> > +       return 0;
> > +}
> > +
> > +static int fsl_espi_probe(struct udevice *bus) {
> > +       struct fsl_espi_platdata *plat = dev_get_platdata(bus);
> > +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> > +
> > +       fsl->espi = (ccsr_espi_t *)((u32)plat->regs_addr);
> > +       fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
> > +       fsl->speed_hz = plat->speed_hz;
> > +
> > +       debug("%s probe done, bus-num %d.\n", bus->name, bus->seq);
> > +
> > +       return 0;
> > +}
> > +
> > +static const struct dm_spi_ops fsl_espi_ops = {
> > +       .claim_bus      = fsl_espi_claim_bus,
> > +       .release_bus    = fsl_espi_release_bus,
> > +       .xfer           = fsl_espi_xfer,
> > +       .set_speed      = fsl_espi_set_speed,
> > +       .set_mode       = fsl_espi_set_mode,
> > +};
> > +
> > +#if CONFIG_IS_ENABLED(OF_CONTROL)
> && !CONFIG_IS_ENABLED(OF_PLATDATA)
> > +static int fsl_espi_ofdata_to_platdata(struct udevice *bus) {
> > +       fdt_addr_t addr;
> > +       struct fsl_espi_platdata   *plat = bus->platdata;
> > +       const void *blob = gd->fdt_blob;
> > +       int node = dev_of_offset(bus);
> > +
> > +       addr = dev_read_addr(bus);
> > +       if (addr == FDT_ADDR_T_NONE)
> > +               return -EINVAL;
> > +
> > +       plat->regs_addr = lower_32_bits(addr);
> > +       plat->speed_hz = fdtdec_get_int(blob, node,
> "spi-max-frequency",
> > +
> FSL_ESPI_DEFAULT_SCK_FREQ);
> > +
> > +       debug("ESPI: regs=%p, max-frequency=%d\n",
> > +             &plat->regs_addr, plat->speed_hz);
> > +
> > +       return 0;
> > +}
> > +
> > +static const struct udevice_id fsl_espi_ids[] = {
> > +       { .compatible = "fsl,mpc8536-espi" },
> > +       { }
> > +};
> > +#endif
> > +
> > +U_BOOT_DRIVER(fsl_espi) = {
> > +       .name   = "fsl_espi",
> > +       .id     = UCLASS_SPI,
> > +#if CONFIG_IS_ENABLED(OF_CONTROL)
> && !CONFIG_IS_ENABLED(OF_PLATDATA)
> > +       .of_match = fsl_espi_ids,
> > +       .ofdata_to_platdata = fsl_espi_ofdata_to_platdata, #endif
> > +       .ops    = &fsl_espi_ops,
> > +       .platdata_auto_alloc_size = sizeof(struct fsl_espi_platdata),
> > +       .priv_auto_alloc_size = sizeof(struct fsl_spi_slave),
> > +       .probe  = fsl_espi_probe,
> > +       .child_pre_probe = fsl_espi_child_pre_probe, }; #endif
> 
> It still has nondm code, does it required for SPL due to foot-print restrictions?
> How much are the numbers please?

As the SPL is non-DM on these platforms, the SPL of SPI flash boot still needs these non-DM code.
What does the 'foot-print restrictions' mean? I don't know the background, since I just take over this task.

Thanks,
Zhiqiang

> 
> Jagan.

^ permalink raw reply	[flat|nested] 41+ messages in thread
* [PATCHv2 01/36] dm: spi: Convert Freescale ESPI driver to driver model
  2020-06-03  2:03     ` Z.q. Hou
@ 2020-06-03  7:41       ` Jagan Teki
  2020-06-04  2:40         ` Z.q. Hou
  0 siblings, 1 reply; 41+ messages in thread
From: Jagan Teki @ 2020-06-03  7:41 UTC (permalink / raw)
  To: u-boot

On Wed, Jun 3, 2020 at 7:33 AM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
>
> Hi Jagan,
>
> Thanks a lot for your comments!
>
> > -----Original Message-----
> > From: Jagan Teki <jagan@amarulasolutions.com>
> > Sent: 2020?6?3? 3:29
> > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > Cc: U-Boot-Denx <u-boot@lists.denx.de>; Priyanka Jain
> > <priyanka.jain@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>; Simon
> > Glass <sjg@chromium.org>; Biwen Li <biwen.li@nxp.com>; Bin Meng
> > <bmeng.cn@gmail.com>; Jiafei Pan <jiafei.pan@nxp.com>; Chuanhua Han
> > <chuanhua.han@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > Subject: Re: [PATCHv2 01/36] dm: spi: Convert Freescale ESPI driver to driver
> > model
> >
> > On Tue, Jun 2, 2020 at 7:10 PM Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
> > wrote:
> > >
> > > From: Chuanhua Han <chuanhua.han@nxp.com>
> > >
> > > Modify the Freescale ESPI driver to support the driver model.
> > > Also resolved the following problems:
> > >
> > > ===================== WARNING ====================== This
> > board does
> > > not use CONFIG_DM_SPI. Please update the board before v2019.04 for no
> > > dm conversion and v2019.07 for partially dm converted drivers.
> > > Failure to update can lead to driver/board removal See
> > > doc/driver-model/MIGRATION.txt for more info.
> > > ====================================================
> > > ===================== WARNING ====================== This
> > board does
> > > not use CONFIG_DM_SPI_FLASH. Please update the board to use
> > > CONFIG_SPI_FLASH before the v2019.07 release.
> > > Failure to update by the deadline may result in board removal.
> > > See doc/driver-model/MIGRATION.txt for more info.
> > > ====================================================
> > >
> > > Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
> > > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > ---
> > > V2:
> > >  - Rebase the patch, no change intended.
> > >
> > >  drivers/spi/fsl_espi.c              | 444
> > ++++++++++++++++++++--------
> > >  include/dm/platform_data/fsl_espi.h |  16 +
> > >  2 files changed, 337 insertions(+), 123 deletions(-)  create mode
> > > 100644 include/dm/platform_data/fsl_espi.h
> > >
> > > diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index
> > > 50d194f614..5c76fd962e 100644
> > > --- a/drivers/spi/fsl_espi.c
> > > +++ b/drivers/spi/fsl_espi.c
> > > @@ -3,7 +3,9 @@
> > >   * eSPI controller driver.
> > >   *
> > >   * Copyright 2010-2011 Freescale Semiconductor, Inc.
> > > + * Copyright 2020 NXP
> > >   * Author: Mingkai Hu (Mingkai.hu at freescale.com)
> > > + *        Chuanhua Han (chuanhua.han at nxp.com)
> > >   */
> > >
> > >  #include <common.h>
> > > @@ -14,10 +16,16 @@
> > >  #include <malloc.h>
> > >  #include <spi.h>
> > >  #include <asm/immap_85xx.h>
> > > +#include <dm.h>
> > > +#include <errno.h>
> > > +#include <fdtdec.h>
> > > +#include <dm/platform_data/fsl_espi.h>
> > >
> > >  struct fsl_spi_slave {
> > >         struct spi_slave slave;
> > >         ccsr_espi_t     *espi;
> > > +       u32             speed_hz;
> > > +       unsigned int    cs;
> > >         unsigned int    div16;
> > >         unsigned int    pm;
> > >         int             tx_timeout;
> > > @@ -31,6 +39,9 @@ struct fsl_spi_slave {  #define to_fsl_spi_slave(s)
> > > container_of(s, struct fsl_spi_slave, slave)
> > >  #define US_PER_SECOND          1000000UL
> > >
> > > +/* default SCK frequency, unit: HZ */
> > > +#define FSL_ESPI_DEFAULT_SCK_FREQ   10000000
> > > +
> > >  #define ESPI_MAX_CS_NUM                4
> > >  #define ESPI_FIFO_WIDTH_BIT    32
> > >
> > > @@ -65,116 +76,27 @@ struct fsl_spi_slave {
> > >
> > >  #define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0
> > >
> > > -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> > > -               unsigned int max_hz, unsigned int mode)
> > > -{
> > > -       struct fsl_spi_slave *fsl;
> > > -       sys_info_t sysinfo;
> > > -       unsigned long spibrg = 0;
> > > -       unsigned long spi_freq = 0;
> > > -       unsigned char pm = 0;
> > > -
> > > -       if (!spi_cs_is_valid(bus, cs))
> > > -               return NULL;
> > > -
> > > -       fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);
> > > -       if (!fsl)
> > > -               return NULL;
> > > -
> > > -       fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
> > > -       fsl->mode = mode;
> > > -       fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
> > > -
> > > -       /* Set eSPI BRG clock source */
> > > -       get_sys_info(&sysinfo);
> > > -       spibrg = sysinfo.freq_systembus / 2;
> > > -       fsl->div16 = 0;
> > > -       if ((spibrg / max_hz) > 32) {
> > > -               fsl->div16 = ESPI_CSMODE_DIV16;
> > > -               pm = spibrg / (max_hz * 16 * 2);
> > > -               if (pm > 16) {
> > > -                       pm = 16;
> > > -                       debug("Requested speed is too low: %d
> > Hz, %ld Hz "
> > > -                               "is used.\n", max_hz, spibrg / (32 *
> > 16));
> > > -               }
> > > -       } else
> > > -               pm = spibrg / (max_hz * 2);
> > > -       if (pm)
> > > -               pm--;
> > > -       fsl->pm = pm;
> > > -
> > > -       if (fsl->div16)
> > > -               spi_freq = spibrg / ((pm + 1) * 2 * 16);
> > > -       else
> > > -               spi_freq = spibrg / ((pm + 1) * 2);
> > > -
> > > -       /* set tx_timeout to 10 times of one espi FIFO entry go out */
> > > -       fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND *
> > ESPI_FIFO_WIDTH_BIT
> > > -                               * 10), spi_freq);
> > > -
> > > -       return &fsl->slave;
> > > -}
> > > -
> > > -void spi_free_slave(struct spi_slave *slave) -{
> > > -       struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> > > -       free(fsl);
> > > -}
> > > -
> > > -int spi_claim_bus(struct spi_slave *slave)
> > > +void fsl_spi_cs_activate(struct spi_slave *slave, uint cs)
> > >  {
> > >         struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> > >         ccsr_espi_t *espi = fsl->espi;
> > > -       unsigned char pm = fsl->pm;
> > > -       unsigned int cs = slave->cs;
> > > -       unsigned int mode =  fsl->mode;
> > > -       unsigned int div16 = fsl->div16;
> > > -       int i;
> > > -
> > > -       debug("%s: bus:%i cs:%i\n", __func__, slave->bus, cs);
> > > -
> > > -       /* Enable eSPI interface */
> > > -       out_be32(&espi->mode, ESPI_MODE_RXTHR(3)
> > > -                       | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN);
> > > -
> > > -       out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */
> > > -       out_be32(&espi->mask, 0x00000000); /* Mask  all eSPI
> > interrupts */
> > > -
> > > -       /* Init CS mode interface */
> > > -       for (i = 0; i < ESPI_MAX_CS_NUM; i++)
> > > -               out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL);
> > > -
> > > -       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) &
> > > -               ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16
> > > -               | ESPI_CSMODE_CI_INACTIVEHIGH |
> > ESPI_CSMODE_CP_BEGIN_EDGCLK
> > > -               | ESPI_CSMODE_REV_MSB_FIRST |
> > ESPI_CSMODE_LEN(0xF)));
> > > -
> > > -       /* Set eSPI BRG clock source */
> > > -       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> > > -               | ESPI_CSMODE_PM(pm) | div16);
> > > -
> > > -       /* Set eSPI mode */
> > > -       if (mode & SPI_CPHA)
> > > -               out_be32(&espi->csmode[cs],
> > in_be32(&espi->csmode[cs])
> > > -                       | ESPI_CSMODE_CP_BEGIN_EDGCLK);
> > > -       if (mode & SPI_CPOL)
> > > -               out_be32(&espi->csmode[cs],
> > in_be32(&espi->csmode[cs])
> > > -                       | ESPI_CSMODE_CI_INACTIVEHIGH);
> > > -
> > > -       /* Character bit order: msb first */
> > > -       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> > > -               | ESPI_CSMODE_REV_MSB_FIRST);
> > > -
> > > -       /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */
> > > -       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> > > -               | ESPI_CSMODE_LEN(7));
> > > +       unsigned int com = 0;
> > > +       size_t data_len = fsl->data_len;
> > >
> > > -       return 0;
> > > +       com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF));
> > > +       com |= ESPI_COM_CS(cs);
> > > +       com |= ESPI_COM_TRANLEN(data_len - 1);
> > > +       out_be32(&espi->com, com);
> > >  }
> > >
> > > -void spi_release_bus(struct spi_slave *slave)
> > > +void fsl_spi_cs_deactivate(struct spi_slave *slave)
> > >  {
> > > +       struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> > > +       ccsr_espi_t *espi = fsl->espi;
> > >
> > > +       /* clear the RXCNT and TXCNT */
> > > +       out_be32(&espi->mode, in_be32(&espi->mode) &
> > (~ESPI_MODE_EN));
> > > +       out_be32(&espi->mode, in_be32(&espi->mode) |
> > ESPI_MODE_EN);
> > >  }
> > >
> > >  static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout)
> > > @@ -207,7 +129,8 @@ static void fsl_espi_tx(struct fsl_spi_slave *fsl,
> > const void *dout)
> > >                 debug("***spi_xfer:...Tx timeout! event = %08x\n",
> > > event);  }
> > >
> > > -static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned
> > > int bytes)
> > > +static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din,
> > > +                      unsigned int bytes)
> > >  {
> > >         ccsr_espi_t *espi = fsl->espi;
> > >         unsigned int tmpdin, rx_times; @@ -239,10 +162,17 @@ static
> > > int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes)
> > >         return bytes;
> > >  }
> > >
> > > -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void
> > *data_out,
> > > -               void *data_in, unsigned long flags)
> > > +void  espi_release_bus(struct fsl_spi_slave *fsl)
> > >  {
> > > -       struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> > > +       /* Disable the SPI hardware */
> > > +        out_be32(&fsl->espi->mode,
> > > +                 in_be32(&fsl->espi->mode) & (~ESPI_MODE_EN)); }
> > > +
> > > +int espi_xfer(struct fsl_spi_slave *fsl,  uint cs, unsigned int bitlen,
> > > +             const void *data_out, void *data_in, unsigned long
> > > +flags) {
> > > +       struct spi_slave *slave = &fsl->slave;
> > >         ccsr_espi_t *espi = fsl->espi;
> > >         unsigned int event, rx_bytes;
> > >         const void *dout = NULL;
> > > @@ -261,13 +191,14 @@ int spi_xfer(struct spi_slave *slave, unsigned int
> > bitlen, const void *data_out,
> > >         max_tran_len = fsl->max_transfer_length;
> > >         switch (flags) {
> > >         case SPI_XFER_BEGIN:
> > > -               cmd_len = fsl->cmd_len = data_len;
> > > +               cmd_len = data_len;
> > > +               fsl->cmd_len = cmd_len;
> > >                 memcpy(cmd_buf, data_out, cmd_len);
> > >                 return 0;
> > >         case 0:
> > >         case SPI_XFER_END:
> > >                 if (bitlen == 0) {
> > > -                       spi_cs_deactivate(slave);
> > > +                       fsl_spi_cs_deactivate(slave);
> > >                         return 0;
> > >                 }
> > >                 buf_len = 2 * cmd_len + min(data_len,
> > > (size_t)max_tran_len); @@ -307,7 +238,7 @@ int spi_xfer(struct spi_slave
> > *slave, unsigned int bitlen, const void *data_out,
> > >                 num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4);
> > >                 num_bytes = (tran_len + cmd_len) % 4;
> > >                 fsl->data_len = tran_len + cmd_len;
> > > -               spi_cs_activate(slave);
> > > +               fsl_spi_cs_activate(slave, cs);
> > >
> > >                 /* Clear all eSPI events */
> > >                 out_be32(&espi->event , 0xffffffff); @@ -350,37
> > > +281,304 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const
> > void *data_out,
> > >                                 *(int *)buffer += tran_len;
> > >                         }
> > >                 }
> > > -               spi_cs_deactivate(slave);
> > > +               fsl_spi_cs_deactivate(slave);
> > >         }
> > >
> > >         free(buffer);
> > >         return 0;
> > >  }
> > >
> > > +void espi_claim_bus(struct fsl_spi_slave *fsl, unsigned int cs) {
> > > +       ccsr_espi_t *espi = fsl->espi;
> > > +       unsigned char pm = fsl->pm;
> > > +       unsigned int mode =  fsl->mode;
> > > +       unsigned int div16 = fsl->div16;
> > > +       int i;
> > > +
> > > +       /* Enable eSPI interface */
> > > +       out_be32(&espi->mode, ESPI_MODE_RXTHR(3)
> > > +                       | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN);
> > > +
> > > +       out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */
> > > +       out_be32(&espi->mask, 0x00000000); /* Mask  all eSPI
> > > + interrupts */
> > > +
> > > +       /* Init CS mode interface */
> > > +       for (i = 0; i < ESPI_MAX_CS_NUM; i++)
> > > +               out_be32(&espi->csmode[i],
> > ESPI_CSMODE_INIT_VAL);
> > > +
> > > +       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) &
> > > +               ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16
> > > +               | ESPI_CSMODE_CI_INACTIVEHIGH |
> > ESPI_CSMODE_CP_BEGIN_EDGCLK
> > > +               | ESPI_CSMODE_REV_MSB_FIRST |
> > ESPI_CSMODE_LEN(0xF)));
> > > +
> > > +       /* Set eSPI BRG clock source */
> > > +       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> > > +               | ESPI_CSMODE_PM(pm) | div16);
> > > +
> > > +       /* Set eSPI mode */
> > > +       if (mode & SPI_CPHA)
> > > +               out_be32(&espi->csmode[cs],
> > in_be32(&espi->csmode[cs])
> > > +                       | ESPI_CSMODE_CP_BEGIN_EDGCLK);
> > > +       if (mode & SPI_CPOL)
> > > +               out_be32(&espi->csmode[cs],
> > in_be32(&espi->csmode[cs])
> > > +                       | ESPI_CSMODE_CI_INACTIVEHIGH);
> > > +
> > > +       /* Character bit order: msb first */
> > > +       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> > > +               | ESPI_CSMODE_REV_MSB_FIRST);
> > > +
> > > +       /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */
> > > +       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> > > +               | ESPI_CSMODE_LEN(7)); }
> > > +
> > > +void espi_setup_slave(struct fsl_spi_slave *fsl) {
> > > +       unsigned int max_hz;
> > > +       sys_info_t sysinfo;
> > > +       unsigned long spibrg = 0;
> > > +       unsigned long spi_freq = 0;
> > > +       unsigned char pm = 0;
> > > +
> > > +       max_hz = fsl->speed_hz;
> > > +
> > > +       get_sys_info(&sysinfo);
> > > +       spibrg = sysinfo.freq_systembus / 2;
> > > +       fsl->div16 = 0;
> > > +       if ((spibrg / max_hz) > 32) {
> > > +               fsl->div16 = ESPI_CSMODE_DIV16;
> > > +               pm = spibrg / (max_hz * 16 * 2);
> > > +               if (pm > 16) {
> > > +                       pm = 16;
> > > +                       debug("max_hz is too low: %d Hz, %ld Hz is
> > used.\n",
> > > +                             max_hz, spibrg / (32 * 16));
> > > +               }
> > > +       } else {
> > > +               pm = spibrg / (max_hz * 2);
> > > +       }
> > > +       if (pm)
> > > +               pm--;
> > > +       fsl->pm = pm;
> > > +
> > > +       if (fsl->div16)
> > > +               spi_freq = spibrg / ((pm + 1) * 2 * 16);
> > > +       else
> > > +               spi_freq = spibrg / ((pm + 1) * 2);
> > > +
> > > +       /* set tx_timeout to 10 times of one espi FIFO entry go out */
> > > +       fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND *
> > ESPI_FIFO_WIDTH_BIT
> > > +                               * 10), spi_freq);/* Set eSPI BRG
> > clock
> > > +source */ }
> > > +
> > > +#if !CONFIG_IS_ENABLED(DM_SPI)
> > >  int spi_cs_is_valid(unsigned int bus, unsigned int cs)  {
> > >         return bus == 0 && cs < ESPI_MAX_CS_NUM;  }
> > >
> > > -void spi_cs_activate(struct spi_slave *slave)
> > > +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> > > +                                 unsigned int max_hz, unsigned
> > int
> > > +mode) {
> > > +       struct fsl_spi_slave *fsl;
> > > +
> > > +       if (!spi_cs_is_valid(bus, cs))
> > > +               return NULL;
> > > +
> > > +       fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);
> > > +       if (!fsl)
> > > +               return NULL;
> > > +
> > > +       fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
> > > +       fsl->mode = mode;
> > > +       fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
> > > +       fsl->speed_hz = max_hz;
> > > +
> > > +       espi_setup_slave(fsl);
> > > +
> > > +       return &fsl->slave;
> > > +}
> > > +
> > > +void spi_free_slave(struct spi_slave *slave)
> > >  {
> > >         struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> > > -       ccsr_espi_t *espi = fsl->espi;
> > > -       unsigned int com = 0;
> > > -       size_t data_len = fsl->data_len;
> > >
> > > -       com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF));
> > > -       com |= ESPI_COM_CS(slave->cs);
> > > -       com |= ESPI_COM_TRANLEN(data_len - 1);
> > > -       out_be32(&espi->com, com);
> > > +       free(fsl);
> > >  }
> > >
> > > -void spi_cs_deactivate(struct spi_slave *slave)
> > > +int spi_claim_bus(struct spi_slave *slave)
> > >  {
> > >         struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> > > -       ccsr_espi_t *espi = fsl->espi;
> > >
> > > -       /* clear the RXCNT and TXCNT */
> > > -       out_be32(&espi->mode, in_be32(&espi->mode) &
> > (~ESPI_MODE_EN));
> > > -       out_be32(&espi->mode, in_be32(&espi->mode) |
> > ESPI_MODE_EN);
> > > +       espi_claim_bus(fsl, slave->cs);
> > > +
> > > +       return 0;
> > >  }
> > > +
> > > +void spi_release_bus(struct spi_slave *slave) {
> > > +       struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> > > +
> > > +       espi_release_bus(fsl);
> > > +}
> > > +
> > > +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
> > > +            void *din, unsigned long flags) {
> > > +       struct fsl_spi_slave *fsl = (struct fsl_spi_slave *)slave;
> > > +
> > > +       return espi_xfer(fsl, slave->cs, bitlen, dout, din, flags); }
> > > +#else static void __espi_set_speed(struct fsl_spi_slave *fsl) {
> > > +       espi_setup_slave(fsl);
> > > +
> > > +       /* Set eSPI BRG clock source */
> > > +       out_be32(&fsl->espi->csmode[fsl->cs],
> > > +                in_be32(&fsl->espi->csmode[fsl->cs])
> > > +                        | ESPI_CSMODE_PM(fsl->pm) | fsl->div16); }
> > > +
> > > +static void __espi_set_mode(struct fsl_spi_slave *fsl) {
> > > +       /* Set eSPI mode */
> > > +       if (fsl->mode & SPI_CPHA)
> > > +               out_be32(&fsl->espi->csmode[fsl->cs],
> > > +                        in_be32(&fsl->espi->csmode[fsl->cs])
> > > +                               |
> > ESPI_CSMODE_CP_BEGIN_EDGCLK);
> > > +       if (fsl->mode & SPI_CPOL)
> > > +               out_be32(&fsl->espi->csmode[fsl->cs],
> > > +                        in_be32(&fsl->espi->csmode[fsl->cs])
> > > +                               |
> > ESPI_CSMODE_CI_INACTIVEHIGH); }
> > > +
> > > +static int fsl_espi_claim_bus(struct udevice *dev) {
> > > +       struct udevice *bus = dev->parent;
> > > +       struct fsl_spi_slave  *fsl =  dev_get_priv(bus);
> > > +
> > > +       espi_claim_bus(fsl, fsl->cs);
> > > +
> > > +       return 0;
> > > +}
> > > +
> > > +static int fsl_espi_release_bus(struct udevice *dev) {
> > > +       struct udevice *bus = dev->parent;
> > > +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> > > +
> > > +       espi_release_bus(fsl);
> > > +
> > > +       return 0;
> > > +}
> > > +
> > > +static int fsl_espi_xfer(struct udevice *dev, unsigned int bitlen,
> > > +                        const void *dout, void *din, unsigned long
> > > +flags) {
> > > +       struct udevice *bus = dev->parent;
> > > +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> > > +
> > > +       return espi_xfer(fsl, fsl->cs, bitlen, dout, din, flags); }
> > > +
> > > +static int fsl_espi_set_speed(struct udevice *bus, uint speed) {
> > > +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> > > +
> > > +       debug("%s speed %u\n", __func__, speed);
> > > +       fsl->speed_hz = speed;
> > > +
> > > +       __espi_set_speed(fsl);
> > > +
> > > +       return 0;
> > > +}
> > > +
> > > +static int fsl_espi_set_mode(struct udevice *bus, uint mode) {
> > > +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> > > +
> > > +       debug("%s mode %u\n", __func__, mode);
> > > +       fsl->mode = mode;
> > > +
> > > +       __espi_set_mode(fsl);
> > > +
> > > +       return 0;
> > > +}
> > > +
> > > +static int fsl_espi_child_pre_probe(struct udevice *dev) {
> > > +       struct dm_spi_slave_platdata *slave_plat =
> > dev_get_parent_platdata(dev);
> > > +       struct udevice *bus = dev->parent;
> > > +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> > > +
> > > +       debug("%s cs %u\n", __func__, slave_plat->cs);
> > > +       fsl->cs = slave_plat->cs;
> > > +
> > > +       return 0;
> > > +}
> > > +
> > > +static int fsl_espi_probe(struct udevice *bus) {
> > > +       struct fsl_espi_platdata *plat = dev_get_platdata(bus);
> > > +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> > > +
> > > +       fsl->espi = (ccsr_espi_t *)((u32)plat->regs_addr);
> > > +       fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
> > > +       fsl->speed_hz = plat->speed_hz;
> > > +
> > > +       debug("%s probe done, bus-num %d.\n", bus->name, bus->seq);
> > > +
> > > +       return 0;
> > > +}
> > > +
> > > +static const struct dm_spi_ops fsl_espi_ops = {
> > > +       .claim_bus      = fsl_espi_claim_bus,
> > > +       .release_bus    = fsl_espi_release_bus,
> > > +       .xfer           = fsl_espi_xfer,
> > > +       .set_speed      = fsl_espi_set_speed,
> > > +       .set_mode       = fsl_espi_set_mode,
> > > +};
> > > +
> > > +#if CONFIG_IS_ENABLED(OF_CONTROL)
> > && !CONFIG_IS_ENABLED(OF_PLATDATA)
> > > +static int fsl_espi_ofdata_to_platdata(struct udevice *bus) {
> > > +       fdt_addr_t addr;
> > > +       struct fsl_espi_platdata   *plat = bus->platdata;
> > > +       const void *blob = gd->fdt_blob;
> > > +       int node = dev_of_offset(bus);
> > > +
> > > +       addr = dev_read_addr(bus);
> > > +       if (addr == FDT_ADDR_T_NONE)
> > > +               return -EINVAL;
> > > +
> > > +       plat->regs_addr = lower_32_bits(addr);
> > > +       plat->speed_hz = fdtdec_get_int(blob, node,
> > "spi-max-frequency",
> > > +
> > FSL_ESPI_DEFAULT_SCK_FREQ);
> > > +
> > > +       debug("ESPI: regs=%p, max-frequency=%d\n",
> > > +             &plat->regs_addr, plat->speed_hz);
> > > +
> > > +       return 0;
> > > +}
> > > +
> > > +static const struct udevice_id fsl_espi_ids[] = {
> > > +       { .compatible = "fsl,mpc8536-espi" },
> > > +       { }
> > > +};
> > > +#endif
> > > +
> > > +U_BOOT_DRIVER(fsl_espi) = {
> > > +       .name   = "fsl_espi",
> > > +       .id     = UCLASS_SPI,
> > > +#if CONFIG_IS_ENABLED(OF_CONTROL)
> > && !CONFIG_IS_ENABLED(OF_PLATDATA)
> > > +       .of_match = fsl_espi_ids,
> > > +       .ofdata_to_platdata = fsl_espi_ofdata_to_platdata, #endif
> > > +       .ops    = &fsl_espi_ops,
> > > +       .platdata_auto_alloc_size = sizeof(struct fsl_espi_platdata),
> > > +       .priv_auto_alloc_size = sizeof(struct fsl_spi_slave),
> > > +       .probe  = fsl_espi_probe,
> > > +       .child_pre_probe = fsl_espi_child_pre_probe, }; #endif
> >
> > It still has nondm code, does it required for SPL due to foot-print restrictions?
> > How much are the numbers please?
>
> As the SPL is non-DM on these platforms, the SPL of SPI flash boot still needs these non-DM code.
> What does the 'foot-print restrictions' mean? I don't know the background, since I just take over this task.

foot-print here mean size of the binary. what if the driver has only
DM code with DM_SPI_FLASH?

Jagan.

^ permalink raw reply	[flat|nested] 41+ messages in thread
* [PATCHv2 01/36] dm: spi: Convert Freescale ESPI driver to driver model
  2020-06-03  7:41       ` Jagan Teki
@ 2020-06-04  2:40         ` Z.q. Hou
  0 siblings, 0 replies; 41+ messages in thread
From: Z.q. Hou @ 2020-06-04  2:40 UTC (permalink / raw)
  To: u-boot

Hi Jagan,

Thanks for your comments!

> -----Original Message-----
> From: Jagan Teki [mailto:jagan at amarulasolutions.com]
> Sent: 2020?6?3? 15:41
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: U-Boot-Denx <u-boot@lists.denx.de>; Priyanka Jain
> <priyanka.jain@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>; Simon
> Glass <sjg@chromium.org>; Biwen Li <biwen.li@nxp.com>; Bin Meng
> <bmeng.cn@gmail.com>; Jiafei Pan <jiafei.pan@nxp.com>; Chuanhua Han
> <chuanhua.han@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv2 01/36] dm: spi: Convert Freescale ESPI driver to driver
> model
> 
> On Wed, Jun 3, 2020 at 7:33 AM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> >
> > Hi Jagan,
> >
> > Thanks a lot for your comments!
> >
> > > -----Original Message-----
> > > From: Jagan Teki <jagan@amarulasolutions.com>
> > > Sent: 2020?6?3? 3:29
> > > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > > Cc: U-Boot-Denx <u-boot@lists.denx.de>; Priyanka Jain
> > > <priyanka.jain@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> > > Simon Glass <sjg@chromium.org>; Biwen Li <biwen.li@nxp.com>; Bin
> > > Meng <bmeng.cn@gmail.com>; Jiafei Pan <jiafei.pan@nxp.com>;
> Chuanhua
> > > Han <chuanhua.han@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > > Subject: Re: [PATCHv2 01/36] dm: spi: Convert Freescale ESPI driver
> > > to driver model
> > >
> > > On Tue, Jun 2, 2020 at 7:10 PM Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
> > > wrote:
> > > >
> > > > From: Chuanhua Han <chuanhua.han@nxp.com>
> > > >
> > > > Modify the Freescale ESPI driver to support the driver model.
> > > > Also resolved the following problems:
> > > >
> > > > ===================== WARNING ====================== This
> > > board does
> > > > not use CONFIG_DM_SPI. Please update the board before v2019.04 for
> > > > no dm conversion and v2019.07 for partially dm converted drivers.
> > > > Failure to update can lead to driver/board removal See
> > > > doc/driver-model/MIGRATION.txt for more info.
> > > > ====================================================
> > > > ===================== WARNING ====================== This
> > > board does
> > > > not use CONFIG_DM_SPI_FLASH. Please update the board to use
> > > > CONFIG_SPI_FLASH before the v2019.07 release.
> > > > Failure to update by the deadline may result in board removal.
> > > > See doc/driver-model/MIGRATION.txt for more info.
> > > > ====================================================
> > > >
> > > > Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
> > > > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > ---
> > > > V2:
> > > >  - Rebase the patch, no change intended.
> > > >
> > > >  drivers/spi/fsl_espi.c              | 444
> > > ++++++++++++++++++++--------
> > > >  include/dm/platform_data/fsl_espi.h |  16 +
> > > >  2 files changed, 337 insertions(+), 123 deletions(-)  create mode
> > > > 100644 include/dm/platform_data/fsl_espi.h
> > > >
> > > > diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index
> > > > 50d194f614..5c76fd962e 100644
> > > > --- a/drivers/spi/fsl_espi.c
> > > > +++ b/drivers/spi/fsl_espi.c
> > > > @@ -3,7 +3,9 @@
> > > >   * eSPI controller driver.
> > > >   *
> > > >   * Copyright 2010-2011 Freescale Semiconductor, Inc.
> > > > + * Copyright 2020 NXP
> > > >   * Author: Mingkai Hu (Mingkai.hu at freescale.com)
> > > > + *        Chuanhua Han (chuanhua.han at nxp.com)
> > > >   */
> > > >
> > > >  #include <common.h>
> > > > @@ -14,10 +16,16 @@
> > > >  #include <malloc.h>
> > > >  #include <spi.h>
> > > >  #include <asm/immap_85xx.h>
> > > > +#include <dm.h>
> > > > +#include <errno.h>
> > > > +#include <fdtdec.h>
> > > > +#include <dm/platform_data/fsl_espi.h>
> > > >
> > > >  struct fsl_spi_slave {
> > > >         struct spi_slave slave;
> > > >         ccsr_espi_t     *espi;
> > > > +       u32             speed_hz;
> > > > +       unsigned int    cs;
> > > >         unsigned int    div16;
> > > >         unsigned int    pm;
> > > >         int             tx_timeout;
> > > > @@ -31,6 +39,9 @@ struct fsl_spi_slave {  #define
> > > > to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave)
> > > >  #define US_PER_SECOND          1000000UL
> > > >
> > > > +/* default SCK frequency, unit: HZ */
> > > > +#define FSL_ESPI_DEFAULT_SCK_FREQ   10000000
> > > > +
> > > >  #define ESPI_MAX_CS_NUM                4
> > > >  #define ESPI_FIFO_WIDTH_BIT    32
> > > >
> > > > @@ -65,116 +76,27 @@ struct fsl_spi_slave {
> > > >
> > > >  #define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0
> > > >
> > > > -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> > > > -               unsigned int max_hz, unsigned int mode)
> > > > -{
> > > > -       struct fsl_spi_slave *fsl;
> > > > -       sys_info_t sysinfo;
> > > > -       unsigned long spibrg = 0;
> > > > -       unsigned long spi_freq = 0;
> > > > -       unsigned char pm = 0;
> > > > -
> > > > -       if (!spi_cs_is_valid(bus, cs))
> > > > -               return NULL;
> > > > -
> > > > -       fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);
> > > > -       if (!fsl)
> > > > -               return NULL;
> > > > -
> > > > -       fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
> > > > -       fsl->mode = mode;
> > > > -       fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
> > > > -
> > > > -       /* Set eSPI BRG clock source */
> > > > -       get_sys_info(&sysinfo);
> > > > -       spibrg = sysinfo.freq_systembus / 2;
> > > > -       fsl->div16 = 0;
> > > > -       if ((spibrg / max_hz) > 32) {
> > > > -               fsl->div16 = ESPI_CSMODE_DIV16;
> > > > -               pm = spibrg / (max_hz * 16 * 2);
> > > > -               if (pm > 16) {
> > > > -                       pm = 16;
> > > > -                       debug("Requested speed is too low: %d
> > > Hz, %ld Hz "
> > > > -                               "is used.\n", max_hz, spibrg / (32
> *
> > > 16));
> > > > -               }
> > > > -       } else
> > > > -               pm = spibrg / (max_hz * 2);
> > > > -       if (pm)
> > > > -               pm--;
> > > > -       fsl->pm = pm;
> > > > -
> > > > -       if (fsl->div16)
> > > > -               spi_freq = spibrg / ((pm + 1) * 2 * 16);
> > > > -       else
> > > > -               spi_freq = spibrg / ((pm + 1) * 2);
> > > > -
> > > > -       /* set tx_timeout to 10 times of one espi FIFO entry go out */
> > > > -       fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND *
> > > ESPI_FIFO_WIDTH_BIT
> > > > -                               * 10), spi_freq);
> > > > -
> > > > -       return &fsl->slave;
> > > > -}
> > > > -
> > > > -void spi_free_slave(struct spi_slave *slave) -{
> > > > -       struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> > > > -       free(fsl);
> > > > -}
> > > > -
> > > > -int spi_claim_bus(struct spi_slave *slave)
> > > > +void fsl_spi_cs_activate(struct spi_slave *slave, uint cs)
> > > >  {
> > > >         struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> > > >         ccsr_espi_t *espi = fsl->espi;
> > > > -       unsigned char pm = fsl->pm;
> > > > -       unsigned int cs = slave->cs;
> > > > -       unsigned int mode =  fsl->mode;
> > > > -       unsigned int div16 = fsl->div16;
> > > > -       int i;
> > > > -
> > > > -       debug("%s: bus:%i cs:%i\n", __func__, slave->bus, cs);
> > > > -
> > > > -       /* Enable eSPI interface */
> > > > -       out_be32(&espi->mode, ESPI_MODE_RXTHR(3)
> > > > -                       | ESPI_MODE_TXTHR(4) |
> ESPI_MODE_EN);
> > > > -
> > > > -       out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */
> > > > -       out_be32(&espi->mask, 0x00000000); /* Mask  all eSPI
> > > interrupts */
> > > > -
> > > > -       /* Init CS mode interface */
> > > > -       for (i = 0; i < ESPI_MAX_CS_NUM; i++)
> > > > -               out_be32(&espi->csmode[i],
> ESPI_CSMODE_INIT_VAL);
> > > > -
> > > > -       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) &
> > > > -               ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16
> > > > -               | ESPI_CSMODE_CI_INACTIVEHIGH |
> > > ESPI_CSMODE_CP_BEGIN_EDGCLK
> > > > -               | ESPI_CSMODE_REV_MSB_FIRST |
> > > ESPI_CSMODE_LEN(0xF)));
> > > > -
> > > > -       /* Set eSPI BRG clock source */
> > > > -       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> > > > -               | ESPI_CSMODE_PM(pm) | div16);
> > > > -
> > > > -       /* Set eSPI mode */
> > > > -       if (mode & SPI_CPHA)
> > > > -               out_be32(&espi->csmode[cs],
> > > in_be32(&espi->csmode[cs])
> > > > -                       | ESPI_CSMODE_CP_BEGIN_EDGCLK);
> > > > -       if (mode & SPI_CPOL)
> > > > -               out_be32(&espi->csmode[cs],
> > > in_be32(&espi->csmode[cs])
> > > > -                       | ESPI_CSMODE_CI_INACTIVEHIGH);
> > > > -
> > > > -       /* Character bit order: msb first */
> > > > -       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> > > > -               | ESPI_CSMODE_REV_MSB_FIRST);
> > > > -
> > > > -       /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits
> */
> > > > -       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> > > > -               | ESPI_CSMODE_LEN(7));
> > > > +       unsigned int com = 0;
> > > > +       size_t data_len = fsl->data_len;
> > > >
> > > > -       return 0;
> > > > +       com &= ~(ESPI_COM_CS(0x3) |
> ESPI_COM_TRANLEN(0xFFFF));
> > > > +       com |= ESPI_COM_CS(cs);
> > > > +       com |= ESPI_COM_TRANLEN(data_len - 1);
> > > > +       out_be32(&espi->com, com);
> > > >  }
> > > >
> > > > -void spi_release_bus(struct spi_slave *slave)
> > > > +void fsl_spi_cs_deactivate(struct spi_slave *slave)
> > > >  {
> > > > +       struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> > > > +       ccsr_espi_t *espi = fsl->espi;
> > > >
> > > > +       /* clear the RXCNT and TXCNT */
> > > > +       out_be32(&espi->mode, in_be32(&espi->mode) &
> > > (~ESPI_MODE_EN));
> > > > +       out_be32(&espi->mode, in_be32(&espi->mode) |
> > > ESPI_MODE_EN);
> > > >  }
> > > >
> > > >  static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void
> > > > *dout) @@ -207,7 +129,8 @@ static void fsl_espi_tx(struct
> > > > fsl_spi_slave *fsl,
> > > const void *dout)
> > > >                 debug("***spi_xfer:...Tx timeout! event = %08x\n",
> > > > event);  }
> > > >
> > > > -static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din,
> > > > unsigned int bytes)
> > > > +static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din,
> > > > +                      unsigned int bytes)
> > > >  {
> > > >         ccsr_espi_t *espi = fsl->espi;
> > > >         unsigned int tmpdin, rx_times; @@ -239,10 +162,17 @@
> > > > static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int
> bytes)
> > > >         return bytes;
> > > >  }
> > > >
> > > > -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const
> > > > void
> > > *data_out,
> > > > -               void *data_in, unsigned long flags)
> > > > +void  espi_release_bus(struct fsl_spi_slave *fsl)
> > > >  {
> > > > -       struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> > > > +       /* Disable the SPI hardware */
> > > > +        out_be32(&fsl->espi->mode,
> > > > +                 in_be32(&fsl->espi->mode) &
> (~ESPI_MODE_EN)); }
> > > > +
> > > > +int espi_xfer(struct fsl_spi_slave *fsl,  uint cs, unsigned int bitlen,
> > > > +             const void *data_out, void *data_in, unsigned long
> > > > +flags) {
> > > > +       struct spi_slave *slave = &fsl->slave;
> > > >         ccsr_espi_t *espi = fsl->espi;
> > > >         unsigned int event, rx_bytes;
> > > >         const void *dout = NULL;
> > > > @@ -261,13 +191,14 @@ int spi_xfer(struct spi_slave *slave,
> > > > unsigned int
> > > bitlen, const void *data_out,
> > > >         max_tran_len = fsl->max_transfer_length;
> > > >         switch (flags) {
> > > >         case SPI_XFER_BEGIN:
> > > > -               cmd_len = fsl->cmd_len = data_len;
> > > > +               cmd_len = data_len;
> > > > +               fsl->cmd_len = cmd_len;
> > > >                 memcpy(cmd_buf, data_out, cmd_len);
> > > >                 return 0;
> > > >         case 0:
> > > >         case SPI_XFER_END:
> > > >                 if (bitlen == 0) {
> > > > -                       spi_cs_deactivate(slave);
> > > > +                       fsl_spi_cs_deactivate(slave);
> > > >                         return 0;
> > > >                 }
> > > >                 buf_len = 2 * cmd_len + min(data_len,
> > > > (size_t)max_tran_len); @@ -307,7 +238,7 @@ int spi_xfer(struct
> > > > spi_slave
> > > *slave, unsigned int bitlen, const void *data_out,
> > > >                 num_blks = DIV_ROUND_UP(tran_len + cmd_len,
> 4);
> > > >                 num_bytes = (tran_len + cmd_len) % 4;
> > > >                 fsl->data_len = tran_len + cmd_len;
> > > > -               spi_cs_activate(slave);
> > > > +               fsl_spi_cs_activate(slave, cs);
> > > >
> > > >                 /* Clear all eSPI events */
> > > >                 out_be32(&espi->event , 0xffffffff); @@ -350,37
> > > > +281,304 @@ int spi_xfer(struct spi_slave *slave, unsigned int
> > > > +bitlen, const
> > > void *data_out,
> > > >                                 *(int *)buffer += tran_len;
> > > >                         }
> > > >                 }
> > > > -               spi_cs_deactivate(slave);
> > > > +               fsl_spi_cs_deactivate(slave);
> > > >         }
> > > >
> > > >         free(buffer);
> > > >         return 0;
> > > >  }
> > > >
> > > > +void espi_claim_bus(struct fsl_spi_slave *fsl, unsigned int cs) {
> > > > +       ccsr_espi_t *espi = fsl->espi;
> > > > +       unsigned char pm = fsl->pm;
> > > > +       unsigned int mode =  fsl->mode;
> > > > +       unsigned int div16 = fsl->div16;
> > > > +       int i;
> > > > +
> > > > +       /* Enable eSPI interface */
> > > > +       out_be32(&espi->mode, ESPI_MODE_RXTHR(3)
> > > > +                       | ESPI_MODE_TXTHR(4) |
> ESPI_MODE_EN);
> > > > +
> > > > +       out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */
> > > > +       out_be32(&espi->mask, 0x00000000); /* Mask  all eSPI
> > > > + interrupts */
> > > > +
> > > > +       /* Init CS mode interface */
> > > > +       for (i = 0; i < ESPI_MAX_CS_NUM; i++)
> > > > +               out_be32(&espi->csmode[i],
> > > ESPI_CSMODE_INIT_VAL);
> > > > +
> > > > +       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) &
> > > > +               ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16
> > > > +               | ESPI_CSMODE_CI_INACTIVEHIGH |
> > > ESPI_CSMODE_CP_BEGIN_EDGCLK
> > > > +               | ESPI_CSMODE_REV_MSB_FIRST |
> > > ESPI_CSMODE_LEN(0xF)));
> > > > +
> > > > +       /* Set eSPI BRG clock source */
> > > > +       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> > > > +               | ESPI_CSMODE_PM(pm) | div16);
> > > > +
> > > > +       /* Set eSPI mode */
> > > > +       if (mode & SPI_CPHA)
> > > > +               out_be32(&espi->csmode[cs],
> > > in_be32(&espi->csmode[cs])
> > > > +                       | ESPI_CSMODE_CP_BEGIN_EDGCLK);
> > > > +       if (mode & SPI_CPOL)
> > > > +               out_be32(&espi->csmode[cs],
> > > in_be32(&espi->csmode[cs])
> > > > +                       | ESPI_CSMODE_CI_INACTIVEHIGH);
> > > > +
> > > > +       /* Character bit order: msb first */
> > > > +       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> > > > +               | ESPI_CSMODE_REV_MSB_FIRST);
> > > > +
> > > > +       /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits
> */
> > > > +       out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
> > > > +               | ESPI_CSMODE_LEN(7)); }
> > > > +
> > > > +void espi_setup_slave(struct fsl_spi_slave *fsl) {
> > > > +       unsigned int max_hz;
> > > > +       sys_info_t sysinfo;
> > > > +       unsigned long spibrg = 0;
> > > > +       unsigned long spi_freq = 0;
> > > > +       unsigned char pm = 0;
> > > > +
> > > > +       max_hz = fsl->speed_hz;
> > > > +
> > > > +       get_sys_info(&sysinfo);
> > > > +       spibrg = sysinfo.freq_systembus / 2;
> > > > +       fsl->div16 = 0;
> > > > +       if ((spibrg / max_hz) > 32) {
> > > > +               fsl->div16 = ESPI_CSMODE_DIV16;
> > > > +               pm = spibrg / (max_hz * 16 * 2);
> > > > +               if (pm > 16) {
> > > > +                       pm = 16;
> > > > +                       debug("max_hz is too low: %d Hz, %ld Hz
> is
> > > used.\n",
> > > > +                             max_hz, spibrg / (32 * 16));
> > > > +               }
> > > > +       } else {
> > > > +               pm = spibrg / (max_hz * 2);
> > > > +       }
> > > > +       if (pm)
> > > > +               pm--;
> > > > +       fsl->pm = pm;
> > > > +
> > > > +       if (fsl->div16)
> > > > +               spi_freq = spibrg / ((pm + 1) * 2 * 16);
> > > > +       else
> > > > +               spi_freq = spibrg / ((pm + 1) * 2);
> > > > +
> > > > +       /* set tx_timeout to 10 times of one espi FIFO entry go out */
> > > > +       fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND *
> > > ESPI_FIFO_WIDTH_BIT
> > > > +                               * 10), spi_freq);/* Set eSPI BRG
> > > clock
> > > > +source */ }
> > > > +
> > > > +#if !CONFIG_IS_ENABLED(DM_SPI)
> > > >  int spi_cs_is_valid(unsigned int bus, unsigned int cs)  {
> > > >         return bus == 0 && cs < ESPI_MAX_CS_NUM;  }
> > > >
> > > > -void spi_cs_activate(struct spi_slave *slave)
> > > > +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> > > > +                                 unsigned int max_hz,
> unsigned
> > > int
> > > > +mode) {
> > > > +       struct fsl_spi_slave *fsl;
> > > > +
> > > > +       if (!spi_cs_is_valid(bus, cs))
> > > > +               return NULL;
> > > > +
> > > > +       fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);
> > > > +       if (!fsl)
> > > > +               return NULL;
> > > > +
> > > > +       fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
> > > > +       fsl->mode = mode;
> > > > +       fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
> > > > +       fsl->speed_hz = max_hz;
> > > > +
> > > > +       espi_setup_slave(fsl);
> > > > +
> > > > +       return &fsl->slave;
> > > > +}
> > > > +
> > > > +void spi_free_slave(struct spi_slave *slave)
> > > >  {
> > > >         struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> > > > -       ccsr_espi_t *espi = fsl->espi;
> > > > -       unsigned int com = 0;
> > > > -       size_t data_len = fsl->data_len;
> > > >
> > > > -       com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF));
> > > > -       com |= ESPI_COM_CS(slave->cs);
> > > > -       com |= ESPI_COM_TRANLEN(data_len - 1);
> > > > -       out_be32(&espi->com, com);
> > > > +       free(fsl);
> > > >  }
> > > >
> > > > -void spi_cs_deactivate(struct spi_slave *slave)
> > > > +int spi_claim_bus(struct spi_slave *slave)
> > > >  {
> > > >         struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> > > > -       ccsr_espi_t *espi = fsl->espi;
> > > >
> > > > -       /* clear the RXCNT and TXCNT */
> > > > -       out_be32(&espi->mode, in_be32(&espi->mode) &
> > > (~ESPI_MODE_EN));
> > > > -       out_be32(&espi->mode, in_be32(&espi->mode) |
> > > ESPI_MODE_EN);
> > > > +       espi_claim_bus(fsl, slave->cs);
> > > > +
> > > > +       return 0;
> > > >  }
> > > > +
> > > > +void spi_release_bus(struct spi_slave *slave) {
> > > > +       struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> > > > +
> > > > +       espi_release_bus(fsl);
> > > > +}
> > > > +
> > > > +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void
> *dout,
> > > > +            void *din, unsigned long flags) {
> > > > +       struct fsl_spi_slave *fsl = (struct fsl_spi_slave *)slave;
> > > > +
> > > > +       return espi_xfer(fsl, slave->cs, bitlen, dout, din,
> > > > +flags); } #else static void __espi_set_speed(struct fsl_spi_slave *fsl) {
> > > > +       espi_setup_slave(fsl);
> > > > +
> > > > +       /* Set eSPI BRG clock source */
> > > > +       out_be32(&fsl->espi->csmode[fsl->cs],
> > > > +                in_be32(&fsl->espi->csmode[fsl->cs])
> > > > +                        | ESPI_CSMODE_PM(fsl->pm) |
> fsl->div16);
> > > > + }
> > > > +
> > > > +static void __espi_set_mode(struct fsl_spi_slave *fsl) {
> > > > +       /* Set eSPI mode */
> > > > +       if (fsl->mode & SPI_CPHA)
> > > > +               out_be32(&fsl->espi->csmode[fsl->cs],
> > > > +                        in_be32(&fsl->espi->csmode[fsl->cs])
> > > > +                               |
> > > ESPI_CSMODE_CP_BEGIN_EDGCLK);
> > > > +       if (fsl->mode & SPI_CPOL)
> > > > +               out_be32(&fsl->espi->csmode[fsl->cs],
> > > > +                        in_be32(&fsl->espi->csmode[fsl->cs])
> > > > +                               |
> > > ESPI_CSMODE_CI_INACTIVEHIGH); }
> > > > +
> > > > +static int fsl_espi_claim_bus(struct udevice *dev) {
> > > > +       struct udevice *bus = dev->parent;
> > > > +       struct fsl_spi_slave  *fsl =  dev_get_priv(bus);
> > > > +
> > > > +       espi_claim_bus(fsl, fsl->cs);
> > > > +
> > > > +       return 0;
> > > > +}
> > > > +
> > > > +static int fsl_espi_release_bus(struct udevice *dev) {
> > > > +       struct udevice *bus = dev->parent;
> > > > +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> > > > +
> > > > +       espi_release_bus(fsl);
> > > > +
> > > > +       return 0;
> > > > +}
> > > > +
> > > > +static int fsl_espi_xfer(struct udevice *dev, unsigned int bitlen,
> > > > +                        const void *dout, void *din, unsigned
> > > > +long
> > > > +flags) {
> > > > +       struct udevice *bus = dev->parent;
> > > > +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> > > > +
> > > > +       return espi_xfer(fsl, fsl->cs, bitlen, dout, din, flags);
> > > > + }
> > > > +
> > > > +static int fsl_espi_set_speed(struct udevice *bus, uint speed) {
> > > > +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> > > > +
> > > > +       debug("%s speed %u\n", __func__, speed);
> > > > +       fsl->speed_hz = speed;
> > > > +
> > > > +       __espi_set_speed(fsl);
> > > > +
> > > > +       return 0;
> > > > +}
> > > > +
> > > > +static int fsl_espi_set_mode(struct udevice *bus, uint mode) {
> > > > +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> > > > +
> > > > +       debug("%s mode %u\n", __func__, mode);
> > > > +       fsl->mode = mode;
> > > > +
> > > > +       __espi_set_mode(fsl);
> > > > +
> > > > +       return 0;
> > > > +}
> > > > +
> > > > +static int fsl_espi_child_pre_probe(struct udevice *dev) {
> > > > +       struct dm_spi_slave_platdata *slave_plat =
> > > dev_get_parent_platdata(dev);
> > > > +       struct udevice *bus = dev->parent;
> > > > +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> > > > +
> > > > +       debug("%s cs %u\n", __func__, slave_plat->cs);
> > > > +       fsl->cs = slave_plat->cs;
> > > > +
> > > > +       return 0;
> > > > +}
> > > > +
> > > > +static int fsl_espi_probe(struct udevice *bus) {
> > > > +       struct fsl_espi_platdata *plat = dev_get_platdata(bus);
> > > > +       struct fsl_spi_slave *fsl = dev_get_priv(bus);
> > > > +
> > > > +       fsl->espi = (ccsr_espi_t *)((u32)plat->regs_addr);
> > > > +       fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
> > > > +       fsl->speed_hz = plat->speed_hz;
> > > > +
> > > > +       debug("%s probe done, bus-num %d.\n", bus->name,
> > > > + bus->seq);
> > > > +
> > > > +       return 0;
> > > > +}
> > > > +
> > > > +static const struct dm_spi_ops fsl_espi_ops = {
> > > > +       .claim_bus      = fsl_espi_claim_bus,
> > > > +       .release_bus    = fsl_espi_release_bus,
> > > > +       .xfer           = fsl_espi_xfer,
> > > > +       .set_speed      = fsl_espi_set_speed,
> > > > +       .set_mode       = fsl_espi_set_mode,
> > > > +};
> > > > +
> > > > +#if CONFIG_IS_ENABLED(OF_CONTROL)
> > > && !CONFIG_IS_ENABLED(OF_PLATDATA)
> > > > +static int fsl_espi_ofdata_to_platdata(struct udevice *bus) {
> > > > +       fdt_addr_t addr;
> > > > +       struct fsl_espi_platdata   *plat = bus->platdata;
> > > > +       const void *blob = gd->fdt_blob;
> > > > +       int node = dev_of_offset(bus);
> > > > +
> > > > +       addr = dev_read_addr(bus);
> > > > +       if (addr == FDT_ADDR_T_NONE)
> > > > +               return -EINVAL;
> > > > +
> > > > +       plat->regs_addr = lower_32_bits(addr);
> > > > +       plat->speed_hz = fdtdec_get_int(blob, node,
> > > "spi-max-frequency",
> > > > +
> > > FSL_ESPI_DEFAULT_SCK_FREQ);
> > > > +
> > > > +       debug("ESPI: regs=%p, max-frequency=%d\n",
> > > > +             &plat->regs_addr, plat->speed_hz);
> > > > +
> > > > +       return 0;
> > > > +}
> > > > +
> > > > +static const struct udevice_id fsl_espi_ids[] = {
> > > > +       { .compatible = "fsl,mpc8536-espi" },
> > > > +       { }
> > > > +};
> > > > +#endif
> > > > +
> > > > +U_BOOT_DRIVER(fsl_espi) = {
> > > > +       .name   = "fsl_espi",
> > > > +       .id     = UCLASS_SPI,
> > > > +#if CONFIG_IS_ENABLED(OF_CONTROL)
> > > && !CONFIG_IS_ENABLED(OF_PLATDATA)
> > > > +       .of_match = fsl_espi_ids,
> > > > +       .ofdata_to_platdata = fsl_espi_ofdata_to_platdata, #endif
> > > > +       .ops    = &fsl_espi_ops,
> > > > +       .platdata_auto_alloc_size = sizeof(struct fsl_espi_platdata),
> > > > +       .priv_auto_alloc_size = sizeof(struct fsl_spi_slave),
> > > > +       .probe  = fsl_espi_probe,
> > > > +       .child_pre_probe = fsl_espi_child_pre_probe, }; #endif
> > >
> > > It still has nondm code, does it required for SPL due to foot-print
> restrictions?
> > > How much are the numbers please?
> >
> > As the SPL is non-DM on these platforms, the SPL of SPI flash boot still needs
> these non-DM code.
> > What does the 'foot-print restrictions' mean? I don't know the background,
> since I just take over this task.
> 
> foot-print here mean size of the binary. what if the driver has only DM code
> with DM_SPI_FLASH?

Thanks a lot for the clarification, the defined CONFIG_SPL_MAX_SIZE values are
different on FSL PowerPC platforms, the least is 4KB on some P1 and P2 boards,
I don't know if the size is the restriction, no one is working on the SPL DM
conversion so far.

As the DM_SPI_FLASH depends DM&&DM_SPI, I don't think the non-DM SPL will
Work with only DM code in SPI flash driver. 

Thanks,
Zhiqiang

> 
> Jagan.

^ permalink raw reply	[flat|nested] 41+ messages in thread
end of thread, other threads:[~2020-06-04  2:40 UTC | newest]

Thread overview: 41+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-02 13:34 [PATCHv2 00/36] spi: fsl-espi: Convert eSPI driver to DM Zhiqiang Hou
2020-06-02 13:34 ` [PATCHv2 01/36] dm: spi: Convert Freescale ESPI driver to driver model Zhiqiang Hou
2020-06-02 19:28   ` Jagan Teki
2020-06-03  2:03     ` Z.q. Hou
2020-06-03  7:41       ` Jagan Teki
2020-06-04  2:40         ` Z.q. Hou
2020-06-02 13:34 ` [PATCHv2 02/36] powerpc: dts: t2080: add espi controller node support Zhiqiang Hou
2020-06-02 13:34 ` [PATCHv2 03/36] powerpc: dts: t2080qds: add espi slave nodes support Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 04/36] configs: enable espi device module in T2080QDS Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 05/36] dts: P1020: Add ESPI DT nodes Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 06/36] dts: P1020RDB: Add ESPI slave device node Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 07/36] configs: P1020RDB: Enable ESPI driver Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 08/36] dts: P2020: Add ESPI DT nodes Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 09/36] dts: P2020RDB: Add ESPI slave device node Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 10/36] configs: P2020RDB: Enable ESPI driver Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 11/36] dts: P2041: Add ESPI DT nodes Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 12/36] dts: P2041RDB: Add ESPI slave device node Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 13/36] configs: P2041RDB: Enable ESPI driver Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 14/36] dts: P3041: Add ESPI DT nodes Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 15/36] dts: P3041DS: Add ESPI slave device node Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 16/36] configs: P3041DS: Enable ESPI driver Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 17/36] dts: P4080: Add ESPI DT nodes Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 18/36] dts: P4080DS: Add ESPI slave device node Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 19/36] configs: P4080DS: Enable ESPI driver Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 20/36] dts: P5040: Add ESPI DT nodes Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 21/36] dts: P5040DS: Add ESPI slave device node Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 22/36] configs: P5040DS: Enable ESPI driver Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 23/36] dts: T102x: Add ESPI DT nodes Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 24/36] dts: T1024RDB: Add ESPI slave device node Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 25/36] configs: T1024RDB: Enable ESPI driver Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 26/36] dts: T104x: Add ESPI DT nodes Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 27/36] dts: T1042D4RDB: Add ESPI slave device node Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 28/36] configs: T1042D4RDB: Enable ESPI driver Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 29/36] dts: T2080RDB: Add ESPI slave device node Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 30/36] configs: T2080RDB: Enable ESPI driver Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 31/36] dts: T4240: Add ESPI DT nodes Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 32/36] dts: T4240RDB: Add ESPI slave device node Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 33/36] configs: T4240RDB: Enable ESPI driver Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 34/36] dts: P1010: Add eSPI controller DT node Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 35/36] dts: P1010RDB: Add eSPI slave DT nodes Zhiqiang Hou
2020-06-02 13:35 ` [PATCHv2 36/36] configs: P1010RDB: Enable eSPI controller and SPI flash DM driver Zhiqiang Hou

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