* [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again
@ 2020-06-11 16:05 Chris Wilson
2020-06-11 16:29 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (7 more replies)
0 siblings, 8 replies; 15+ messages in thread
From: Chris Wilson @ 2020-06-11 16:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
gen3 does not fully flush MI stores to memory on MI_FLUSH, such that a
subsequent read from e.g. the sampler can bypass the store and read the
stale value from memory. This is a serious issue when we are using MI
stores to rewrite the batches for relocation, as it means that the batch
is reading from random user/kernel memory. While it is particularly
sensitive [and detectable] for relocations, reading stale data at any
time is a worry.
Having started with a small number of delaying stores and doubling until
no more incoherency was seen over a few hours (with and without
background memory pressure), 32 was the magic number.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2018
References: a889580c087a ("drm/i915: Flush GPU relocs harder for gen3")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
So gen3 requires a delay after to flush the previous stores, gen5 is
assuming it requires a delay between the seqno and the
MI_USER_INTERRUPT. Here I've made gen5 reuse the gen3 approach, but I
need to verify that it still holds.
---
drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 39 +++++++++---------------
1 file changed, 15 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
index 3fb0dc1fb910..342c476ec872 100644
--- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
@@ -142,19 +142,26 @@ int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode)
return 0;
}
-u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs)
+static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs, int count)
{
GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
*cs++ = MI_FLUSH;
+ *cs++ = MI_NOOP;
+
+ while (count--) {
+ *cs++ = MI_STORE_DWORD_INDEX;
+ *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32);
+ *cs++ = rq->fence.seqno;
+ *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;
+ }
*cs++ = MI_STORE_DWORD_INDEX;
*cs++ = I915_GEM_HWS_SEQNO_ADDR;
*cs++ = rq->fence.seqno;
*cs++ = MI_USER_INTERRUPT;
- *cs++ = MI_NOOP;
rq->tail = intel_ring_offset(rq, cs);
assert_ring_tail_valid(rq->ring, rq->tail);
@@ -162,31 +169,15 @@ u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs)
return cs;
}
-#define GEN5_WA_STORES 8 /* must be at least 1! */
-u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs)
+u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs)
{
- int i;
-
- GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
- GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
-
- *cs++ = MI_FLUSH;
-
- BUILD_BUG_ON(GEN5_WA_STORES < 1);
- for (i = 0; i < GEN5_WA_STORES; i++) {
- *cs++ = MI_STORE_DWORD_INDEX;
- *cs++ = I915_GEM_HWS_SEQNO_ADDR;
- *cs++ = rq->fence.seqno;
- }
-
- *cs++ = MI_USER_INTERRUPT;
-
- rq->tail = intel_ring_offset(rq, cs);
- assert_ring_tail_valid(rq->ring, rq->tail);
+ return __gen2_emit_breadcrumb(rq, cs, 32);
+}
- return cs;
+u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs)
+{
+ return __gen2_emit_breadcrumb(rq, cs, 8);
}
-#undef GEN5_WA_STORES
/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
#define I830_BATCH_LIMIT SZ_256K
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Flush gen3 relocs harder, again
2020-06-11 16:05 [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again Chris Wilson
@ 2020-06-11 16:29 ` Patchwork
2020-06-11 16:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (6 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2020-06-11 16:29 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gt: Flush gen3 relocs harder, again
URL : https://patchwork.freedesktop.org/series/78230/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c941a56c4805 drm/i915/gt: Flush gen3 relocs harder, again
-:19: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit a889580c087a ("drm/i915: Flush GPU relocs harder for gen3")'
#19:
References: a889580c087a ("drm/i915: Flush GPU relocs harder for gen3")
total: 1 errors, 0 warnings, 0 checks, 65 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Flush gen3 relocs harder, again
2020-06-11 16:05 [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again Chris Wilson
2020-06-11 16:29 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2020-06-11 16:50 ` Patchwork
2020-06-11 21:28 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
` (5 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2020-06-11 16:50 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gt: Flush gen3 relocs harder, again
URL : https://patchwork.freedesktop.org/series/78230/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8618 -> Patchwork_17928
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/index.html
Known issues
------------
Here are the changes found in Patchwork_17928 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
- fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
#### Possible fixes ####
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-tgl-u2: [DMESG-WARN][7] ([i915#402]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-u2/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/fi-tgl-u2/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
#### Warnings ####
* igt@kms_flip@basic-flip-vs-modeset@a-dp1:
- fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92]) -> [DMESG-WARN][10] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset@a-dp1.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset@a-dp1.html
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +5 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569
[i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192
[i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193
[i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (50 -> 43)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_8618 -> Patchwork_17928
CI-20190529: 20190529
CI_DRM_8618: 88841e30e7f8c60ff464be277e5b8fef49ebaea0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5703: c33471b4aa0a0ae9dd42202048e7037a661e0574 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17928: c941a56c4805f053450c96e0c4366f90289b14d3 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c941a56c4805 drm/i915/gt: Flush gen3 relocs harder, again
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Flush gen3 relocs harder, again
2020-06-11 16:05 [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again Chris Wilson
2020-06-11 16:29 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2020-06-11 16:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-06-11 21:28 ` Patchwork
2020-06-12 9:14 ` [Intel-gfx] [PATCH] " Mika Kuoppala
` (4 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2020-06-11 21:28 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gt: Flush gen3 relocs harder, again
URL : https://patchwork.freedesktop.org/series/78230/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8618_full -> Patchwork_17928_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_17928_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_whisper@basic-fds-forked-all:
- shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-glk1/igt@gem_exec_whisper@basic-fds-forked-all.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-glk8/igt@gem_exec_whisper@basic-fds-forked-all.html
* igt@gem_mmap_wc@write-cpu-read-wc:
- shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#95]) +21 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl2/igt@gem_mmap_wc@write-cpu-read-wc.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-apl1/igt@gem_mmap_wc@write-cpu-read-wc.html
- shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#93] / [i915#95]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl7/igt@gem_mmap_wc@write-cpu-read-wc.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-kbl4/igt@gem_mmap_wc@write-cpu-read-wc.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-0:
- shard-glk: [PASS][7] -> [DMESG-FAIL][8] ([i915#118] / [i915#95])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-glk1/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-glk8/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-apl4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#180])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-apl4/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [PASS][13] -> [FAIL][14] ([i915#79])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-fences@a-edp1:
- shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +5 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl3/igt@kms_flip@flip-vs-fences@a-edp1.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-skl1/igt@kms_flip@flip-vs-fences@a-edp1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl6/igt@kms_flip@flip-vs-suspend@a-dp1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-kbl7/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
- shard-skl: [PASS][19] -> [DMESG-FAIL][20] ([i915#1982])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
* igt@kms_flip_tiling@flip-yf-tiled:
- shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl2/igt@kms_flip_tiling@flip-yf-tiled.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-kbl7/igt@kms_flip_tiling@flip-yf-tiled.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-gtt:
- shard-skl: [PASS][23] -> [FAIL][24] ([i915#49])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-gtt.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-skl9/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-gtt.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][25] -> [DMESG-FAIL][26] ([fdo#108145] / [i915#1982])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_multiple@atomic-pipe-c-tiling-none:
- shard-tglb: [PASS][27] -> [DMESG-WARN][28] ([i915#402])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-tglb5/igt@kms_plane_multiple@atomic-pipe-c-tiling-none.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-tglb1/igt@kms_plane_multiple@atomic-pipe-c-tiling-none.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-iclb1/igt@kms_psr@psr2_cursor_plane_move.html
#### Possible fixes ####
* igt@gem_exec_await@wide-contexts:
- shard-kbl: [DMESG-WARN][31] ([i915#93] / [i915#95]) -> [PASS][32] +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl4/igt@gem_exec_await@wide-contexts.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-kbl3/igt@gem_exec_await@wide-contexts.html
* igt@gem_exec_reloc@basic-wc-read:
- shard-apl: [DMESG-WARN][33] ([i915#95]) -> [PASS][34] +23 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl1/igt@gem_exec_reloc@basic-wc-read.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-apl3/igt@gem_exec_reloc@basic-wc-read.html
* igt@i915_module_load@reload:
- shard-tglb: [DMESG-WARN][35] ([i915#402]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-tglb1/igt@i915_module_load@reload.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-tglb3/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@system-suspend-modeset:
- shard-skl: [INCOMPLETE][37] ([i915#151] / [i915#69]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl9/igt@i915_pm_rpm@system-suspend-modeset.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-skl5/igt@i915_pm_rpm@system-suspend-modeset.html
* igt@i915_selftest@perf@request:
- shard-tglb: [INCOMPLETE][39] ([i915#1823]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-tglb7/igt@i915_selftest@perf@request.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-tglb8/igt@i915_selftest@perf@request.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-0:
- shard-glk: [DMESG-FAIL][41] ([i915#118] / [i915#95]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-glk8/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-glk5/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +8 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen:
- shard-apl: [FAIL][45] ([i915#54]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl3/igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-apl4/igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2:
- shard-glk: [FAIL][47] ([i915#79]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-glk5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-apl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [FAIL][51] ([i915#1928]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][53] ([i915#1188]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane@plane-panning-top-left-pipe-c-planes:
- shard-skl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] +8 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl1/igt@kms_plane@plane-panning-top-left-pipe-c-planes.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-skl3/igt@kms_plane@plane-panning-top-left-pipe-c-planes.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][57] ([fdo#109441]) -> [PASS][58] +3 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-iclb5/igt@kms_psr@psr2_cursor_render.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
* igt@kms_setmode@basic:
- shard-skl: [FAIL][59] ([i915#31]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl2/igt@kms_setmode@basic.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-skl8/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-c-wait-busy-hang:
- shard-apl: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +2 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl8/igt@kms_vblank@pipe-c-wait-busy-hang.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-apl6/igt@kms_vblank@pipe-c-wait-busy-hang.html
#### Warnings ####
* igt@gem_exec_reloc@basic-concurrent16:
- shard-apl: [INCOMPLETE][63] ([i915#1635] / [i915#1958] / [i915#95]) -> [INCOMPLETE][64] ([i915#1635] / [i915#1958])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl2/igt@gem_exec_reloc@basic-concurrent16.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-apl6/igt@gem_exec_reloc@basic-concurrent16.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [FAIL][65] ([i915#1515]) -> [WARN][66] ([i915#1515])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-iclb7/igt@i915_pm_rc6_residency@rc6-idle.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-iclb3/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_content_protection@atomic:
- shard-apl: [DMESG-FAIL][67] ([fdo#110321] / [i915#95]) -> [TIMEOUT][68] ([i915#1319])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl6/igt@kms_content_protection@atomic.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-apl2/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: [FAIL][69] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][70] ([i915#1319] / [i915#1635]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl2/igt@kms_content_protection@atomic-dpms.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-apl7/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@legacy:
- shard-kbl: [TIMEOUT][71] ([i915#1319] / [i915#1958]) -> [TIMEOUT][72] ([i915#1319])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl4/igt@kms_content_protection@legacy.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-kbl3/igt@kms_content_protection@legacy.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-skl: [FAIL][73] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][74] ([fdo#108145] / [i915#1982])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1823]: https://gitlab.freedesktop.org/drm/intel/issues/1823
[i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928
[i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_8618 -> Patchwork_17928
CI-20190529: 20190529
CI_DRM_8618: 88841e30e7f8c60ff464be277e5b8fef49ebaea0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5703: c33471b4aa0a0ae9dd42202048e7037a661e0574 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17928: c941a56c4805f053450c96e0c4366f90289b14d3 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again
2020-06-11 16:05 [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again Chris Wilson
` (2 preceding siblings ...)
2020-06-11 21:28 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2020-06-12 9:14 ` Mika Kuoppala
2020-06-12 9:23 ` Chris Wilson
2020-06-12 12:39 ` Chris Wilson
` (3 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Mika Kuoppala @ 2020-06-12 9:14 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Chris Wilson
Chris Wilson <chris@chris-wilson.co.uk> writes:
> gen3 does not fully flush MI stores to memory on MI_FLUSH, such that a
> subsequent read from e.g. the sampler can bypass the store and read the
> stale value from memory. This is a serious issue when we are using MI
> stores to rewrite the batches for relocation, as it means that the batch
> is reading from random user/kernel memory. While it is particularly
> sensitive [and detectable] for relocations, reading stale data at any
> time is a worry.
>
> Having started with a small number of delaying stores and doubling until
> no more incoherency was seen over a few hours (with and without
> background memory pressure), 32 was the magic number.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2018
> References: a889580c087a ("drm/i915: Flush GPU relocs harder for gen3")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> So gen3 requires a delay after to flush the previous stores, gen5 is
> assuming it requires a delay between the seqno and the
> MI_USER_INTERRUPT. Here I've made gen5 reuse the gen3 approach, but I
> need to verify that it still holds.
> ---
> drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 39 +++++++++---------------
> 1 file changed, 15 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> index 3fb0dc1fb910..342c476ec872 100644
> --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> @@ -142,19 +142,26 @@ int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode)
> return 0;
> }
>
> -u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> +static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs, int count)
> {
> GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
> GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
>
> *cs++ = MI_FLUSH;
> + *cs++ = MI_NOOP;
> +
> + while (count--) {
> + *cs++ = MI_STORE_DWORD_INDEX;
> + *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32);
> + *cs++ = rq->fence.seqno;
> + *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;
Why would you avoid write flush here?
-Mika
> + }
>
> *cs++ = MI_STORE_DWORD_INDEX;
> *cs++ = I915_GEM_HWS_SEQNO_ADDR;
> *cs++ = rq->fence.seqno;
>
> *cs++ = MI_USER_INTERRUPT;
> - *cs++ = MI_NOOP;
>
> rq->tail = intel_ring_offset(rq, cs);
> assert_ring_tail_valid(rq->ring, rq->tail);
> @@ -162,31 +169,15 @@ u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> return cs;
> }
>
> -#define GEN5_WA_STORES 8 /* must be at least 1! */
> -u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> +u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> {
> - int i;
> -
> - GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
> - GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
> -
> - *cs++ = MI_FLUSH;
> -
> - BUILD_BUG_ON(GEN5_WA_STORES < 1);
> - for (i = 0; i < GEN5_WA_STORES; i++) {
> - *cs++ = MI_STORE_DWORD_INDEX;
> - *cs++ = I915_GEM_HWS_SEQNO_ADDR;
> - *cs++ = rq->fence.seqno;
> - }
> -
> - *cs++ = MI_USER_INTERRUPT;
> -
> - rq->tail = intel_ring_offset(rq, cs);
> - assert_ring_tail_valid(rq->ring, rq->tail);
> + return __gen2_emit_breadcrumb(rq, cs, 32);
> +}
>
> - return cs;
> +u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> +{
> + return __gen2_emit_breadcrumb(rq, cs, 8);
> }
> -#undef GEN5_WA_STORES
>
> /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
> #define I830_BATCH_LIMIT SZ_256K
> --
> 2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again
2020-06-12 9:14 ` [Intel-gfx] [PATCH] " Mika Kuoppala
@ 2020-06-12 9:23 ` Chris Wilson
2020-06-12 9:40 ` Chris Wilson
0 siblings, 1 reply; 15+ messages in thread
From: Chris Wilson @ 2020-06-12 9:23 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2020-06-12 10:14:55)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > gen3 does not fully flush MI stores to memory on MI_FLUSH, such that a
> > subsequent read from e.g. the sampler can bypass the store and read the
> > stale value from memory. This is a serious issue when we are using MI
> > stores to rewrite the batches for relocation, as it means that the batch
> > is reading from random user/kernel memory. While it is particularly
> > sensitive [and detectable] for relocations, reading stale data at any
> > time is a worry.
> >
> > Having started with a small number of delaying stores and doubling until
> > no more incoherency was seen over a few hours (with and without
> > background memory pressure), 32 was the magic number.
> >
> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2018
> > References: a889580c087a ("drm/i915: Flush GPU relocs harder for gen3")
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > ---
> > So gen3 requires a delay after to flush the previous stores, gen5 is
> > assuming it requires a delay between the seqno and the
> > MI_USER_INTERRUPT. Here I've made gen5 reuse the gen3 approach, but I
> > need to verify that it still holds.
> > ---
> > drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 39 +++++++++---------------
> > 1 file changed, 15 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> > index 3fb0dc1fb910..342c476ec872 100644
> > --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> > @@ -142,19 +142,26 @@ int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode)
> > return 0;
> > }
> >
> > -u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> > +static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs, int count)
> > {
> > GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
> > GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
> >
> > *cs++ = MI_FLUSH;
> > + *cs++ = MI_NOOP;
> > +
> > + while (count--) {
> > + *cs++ = MI_STORE_DWORD_INDEX;
> > + *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32);
> > + *cs++ = rq->fence.seqno;
> > + *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;
>
> Why would you avoid write flush here?
It's a flush of the render caches; all I'm using it for here is a delay.
As evidenced, MI_FLUSH does not flush the stores by itself.
32 is an awful lot of papering. I should note that for gen5 not only did
we have the delay in the breadcrumb but also in the invalidation. Maybe
that would help for gen3
-Chris
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again
2020-06-12 9:23 ` Chris Wilson
@ 2020-06-12 9:40 ` Chris Wilson
0 siblings, 0 replies; 15+ messages in thread
From: Chris Wilson @ 2020-06-12 9:40 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Chris Wilson (2020-06-12 10:23:30)
> Quoting Mika Kuoppala (2020-06-12 10:14:55)
> > Chris Wilson <chris@chris-wilson.co.uk> writes:
> >
> > > gen3 does not fully flush MI stores to memory on MI_FLUSH, such that a
> > > subsequent read from e.g. the sampler can bypass the store and read the
> > > stale value from memory. This is a serious issue when we are using MI
> > > stores to rewrite the batches for relocation, as it means that the batch
> > > is reading from random user/kernel memory. While it is particularly
> > > sensitive [and detectable] for relocations, reading stale data at any
> > > time is a worry.
> > >
> > > Having started with a small number of delaying stores and doubling until
> > > no more incoherency was seen over a few hours (with and without
> > > background memory pressure), 32 was the magic number.
> > >
> > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2018
> > > References: a889580c087a ("drm/i915: Flush GPU relocs harder for gen3")
> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > > ---
> > > So gen3 requires a delay after to flush the previous stores, gen5 is
> > > assuming it requires a delay between the seqno and the
> > > MI_USER_INTERRUPT. Here I've made gen5 reuse the gen3 approach, but I
> > > need to verify that it still holds.
> > > ---
> > > drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 39 +++++++++---------------
> > > 1 file changed, 15 insertions(+), 24 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> > > index 3fb0dc1fb910..342c476ec872 100644
> > > --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> > > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> > > @@ -142,19 +142,26 @@ int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode)
> > > return 0;
> > > }
> > >
> > > -u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> > > +static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs, int count)
> > > {
> > > GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
> > > GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
> > >
> > > *cs++ = MI_FLUSH;
> > > + *cs++ = MI_NOOP;
> > > +
> > > + while (count--) {
> > > + *cs++ = MI_STORE_DWORD_INDEX;
> > > + *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32);
> > > + *cs++ = rq->fence.seqno;
> > > + *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;
> >
> > Why would you avoid write flush here?
>
> It's a flush of the render caches; all I'm using it for here is a delay.
> As evidenced, MI_FLUSH does not flush the stores by itself.
>
> 32 is an awful lot of papering. I should note that for gen5 not only did
> we have the delay in the breadcrumb but also in the invalidation. Maybe
> that would help for gen3
Well that was easy. Splitting the w/a between the breadcrumb and the
invalidate does not help to reduce the burden [the number of stores
required to make the incoherency go away] of the w/a.
-Chris
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again
2020-06-11 16:05 [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again Chris Wilson
` (3 preceding siblings ...)
2020-06-12 9:14 ` [Intel-gfx] [PATCH] " Mika Kuoppala
@ 2020-06-12 12:39 ` Chris Wilson
2020-06-12 22:05 ` Mika Kuoppala
2020-06-12 13:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Flush gen3 relocs harder, again (rev2) Patchwork
` (2 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Chris Wilson @ 2020-06-12 12:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
gen3 does not fully flush MI stores to memory on MI_FLUSH, such that a
subsequent read from e.g. the sampler can bypass the store and read the
stale value from memory. This is a serious issue when we are using MI
stores to rewrite the batches for relocation, as it means that the batch
is reading from random user/kernel memory. While it is particularly
sensitive [and detectable] for relocations, reading stale data at any
time is a worry.
Having started with a small number of delaying stores and doubling until
no more incoherency was seen over a few hours (with and without
background memory pressure), 32 was the magic number.
v2: Follow more closer with the gen5 w/a and include some
post-invalidate flushes as well.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2018
References: a889580c087a ("drm/i915: Flush GPU relocs harder for gen3")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 61 ++++++++++--------------
1 file changed, 25 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
index 3fb0dc1fb910..5400d657f334 100644
--- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
@@ -13,28 +13,25 @@
int gen2_emit_flush(struct i915_request *rq, u32 mode)
{
- unsigned int num_store_dw;
+ unsigned int num_store_dw = 12;
u32 cmd, *cs;
cmd = MI_FLUSH;
- num_store_dw = 0;
if (mode & EMIT_INVALIDATE)
cmd |= MI_READ_FLUSH;
- if (mode & EMIT_FLUSH)
- num_store_dw = 4;
- cs = intel_ring_begin(rq, 2 + 3 * num_store_dw);
+ cs = intel_ring_begin(rq, 2 + 4 * num_store_dw);
if (IS_ERR(cs))
return PTR_ERR(cs);
*cs++ = cmd;
while (num_store_dw--) {
- *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
- *cs++ = intel_gt_scratch_offset(rq->engine->gt,
- INTEL_GT_SCRATCH_FIELD_DEFAULT);
- *cs++ = 0;
+ *cs++ = MI_STORE_DWORD_INDEX;
+ *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32);
+ *cs++ = rq->fence.seqno - 1;
+ *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;
}
- *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;
+ *cs++ = cmd;
intel_ring_advance(rq, cs);
@@ -142,38 +139,21 @@ int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode)
return 0;
}
-u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs)
+static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs,
+ int flush, int post)
{
GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
*cs++ = MI_FLUSH;
- *cs++ = MI_STORE_DWORD_INDEX;
- *cs++ = I915_GEM_HWS_SEQNO_ADDR;
- *cs++ = rq->fence.seqno;
-
- *cs++ = MI_USER_INTERRUPT;
- *cs++ = MI_NOOP;
-
- rq->tail = intel_ring_offset(rq, cs);
- assert_ring_tail_valid(rq->ring, rq->tail);
-
- return cs;
-}
-
-#define GEN5_WA_STORES 8 /* must be at least 1! */
-u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs)
-{
- int i;
-
- GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
- GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
-
- *cs++ = MI_FLUSH;
+ while (flush--) {
+ *cs++ = MI_STORE_DWORD_INDEX;
+ *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32);
+ *cs++ = rq->fence.seqno;
+ }
- BUILD_BUG_ON(GEN5_WA_STORES < 1);
- for (i = 0; i < GEN5_WA_STORES; i++) {
+ while (post--) {
*cs++ = MI_STORE_DWORD_INDEX;
*cs++ = I915_GEM_HWS_SEQNO_ADDR;
*cs++ = rq->fence.seqno;
@@ -186,7 +166,16 @@ u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs)
return cs;
}
-#undef GEN5_WA_STORES
+
+u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs)
+{
+ return __gen2_emit_breadcrumb(rq, cs, 16, 8);
+}
+
+u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs)
+{
+ return __gen2_emit_breadcrumb(rq, cs, 8, 8);
+}
/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
#define I830_BATCH_LIMIT SZ_256K
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Flush gen3 relocs harder, again (rev2)
2020-06-11 16:05 [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again Chris Wilson
` (4 preceding siblings ...)
2020-06-12 12:39 ` Chris Wilson
@ 2020-06-12 13:07 ` Patchwork
2020-06-12 13:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-06-12 15:28 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
7 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2020-06-12 13:07 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gt: Flush gen3 relocs harder, again (rev2)
URL : https://patchwork.freedesktop.org/series/78230/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e754040f8747 drm/i915/gt: Flush gen3 relocs harder, again
-:22: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit a889580c087a ("drm/i915: Flush GPU relocs harder for gen3")'
#22:
References: a889580c087a ("drm/i915: Flush GPU relocs harder for gen3")
total: 1 errors, 0 warnings, 0 checks, 98 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Flush gen3 relocs harder, again (rev2)
2020-06-11 16:05 [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again Chris Wilson
` (5 preceding siblings ...)
2020-06-12 13:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Flush gen3 relocs harder, again (rev2) Patchwork
@ 2020-06-12 13:30 ` Patchwork
2020-06-12 15:28 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
7 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2020-06-12 13:30 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gt: Flush gen3 relocs harder, again (rev2)
URL : https://patchwork.freedesktop.org/series/78230/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8621 -> Patchwork_17938
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/index.html
Known issues
------------
Here are the changes found in Patchwork_17938 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload:
- fi-byt-n2820: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-byt-n2820/igt@i915_module_load@reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/fi-byt-n2820/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6700k2: [PASS][5] -> [INCOMPLETE][6] ([i915#151])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-skl-6700k2/igt@i915_pm_rpm@module-reload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/fi-skl-6700k2/igt@i915_pm_rpm@module-reload.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-icl-y: [DMESG-FAIL][7] ([i915#1993]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-y/igt@i915_selftest@live@execlists.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/fi-icl-y/igt@i915_selftest@live@execlists.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-kefka: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-icl-guc: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-guc/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/fi-icl-guc/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +4 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#1993]: https://gitlab.freedesktop.org/drm/intel/issues/1993
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (49 -> 43)
------------------------------
Additional (1): fi-tgl-u2
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_8621 -> Patchwork_17938
CI-20190529: 20190529
CI_DRM_8621: acd803311fbd1e6adc38d10ca382a60c6c190be9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5708: f66c71e29de50bae880bc81ceb0517d4e3e2dfd8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17938: e754040f87476d5c11086ff3064211105297c0fa @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e754040f8747 drm/i915/gt: Flush gen3 relocs harder, again
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Flush gen3 relocs harder, again (rev2)
2020-06-11 16:05 [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again Chris Wilson
` (6 preceding siblings ...)
2020-06-12 13:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-06-12 15:28 ` Patchwork
7 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2020-06-12 15:28 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gt: Flush gen3 relocs harder, again (rev2)
URL : https://patchwork.freedesktop.org/series/78230/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8621_full -> Patchwork_17938_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_17938_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +5 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl4/igt@gem_ctx_isolation@preservation-s3@rcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-apl6/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* igt@gem_exec_reloc@basic-concurrent0:
- shard-apl: [PASS][3] -> [FAIL][4] ([i915#1930])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl7/igt@gem_exec_reloc@basic-concurrent0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-apl7/igt@gem_exec_reloc@basic-concurrent0.html
* igt@gem_exec_schedule@smoketest-all:
- shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-glk4/igt@gem_exec_schedule@smoketest-all.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-glk6/igt@gem_exec_schedule@smoketest-all.html
* igt@i915_module_load@reload:
- shard-tglb: [PASS][7] -> [DMESG-WARN][8] ([i915#402]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb6/igt@i915_module_load@reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-tglb1/igt@i915_module_load@reload.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-180:
- shard-glk: [PASS][9] -> [DMESG-FAIL][10] ([i915#118] / [i915#95]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-glk5/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-glk8/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
* igt@kms_cursor_crc@pipe-b-cursor-128x42-onscreen:
- shard-skl: [PASS][11] -> [FAIL][12] ([i915#54]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-128x42-onscreen.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-128x42-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_flip@plain-flip-fb-recreate@c-edp1:
- shard-skl: [PASS][15] -> [FAIL][16] ([i915#1928])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl7/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-skl6/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu:
- shard-tglb: [PASS][17] -> [DMESG-WARN][18] ([i915#1982])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][19] -> [FAIL][20] ([i915#1188])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl3/igt@kms_hdr@bpc-switch-suspend.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-skl2/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [i915#265]) +4 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_sprite_render:
- shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-iclb8/igt@kms_psr@psr2_sprite_render.html
* igt@kms_universal_plane@disable-primary-vs-flip-pipe-c:
- shard-skl: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) +9 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl9/igt@kms_universal_plane@disable-primary-vs-flip-pipe-c.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-skl1/igt@kms_universal_plane@disable-primary-vs-flip-pipe-c.html
* igt@kms_vblank@pipe-c-accuracy-idle:
- shard-glk: [PASS][27] -> [FAIL][28] ([i915#43])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-glk9/igt@kms_vblank@pipe-c-accuracy-idle.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-glk6/igt@kms_vblank@pipe-c-accuracy-idle.html
* igt@kms_vblank@pipe-c-ts-continuation-idle-hang:
- shard-apl: [PASS][29] -> [DMESG-WARN][30] ([i915#1982])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl1/igt@kms_vblank@pipe-c-ts-continuation-idle-hang.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-apl8/igt@kms_vblank@pipe-c-ts-continuation-idle-hang.html
* igt@perf@blocking-parameterized:
- shard-hsw: [PASS][31] -> [FAIL][32] ([i915#1542]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-hsw2/igt@perf@blocking-parameterized.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-hsw6/igt@perf@blocking-parameterized.html
* igt@syncobj_wait@single-wait-for-submit-unsubmitted:
- shard-apl: [PASS][33] -> [DMESG-WARN][34] ([i915#95]) +13 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl3/igt@syncobj_wait@single-wait-for-submit-unsubmitted.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-apl4/igt@syncobj_wait@single-wait-for-submit-unsubmitted.html
#### Possible fixes ####
* igt@gem_exec_schedule@implicit-read-write@bcs0:
- shard-snb: [INCOMPLETE][35] ([i915#82]) -> [PASS][36] +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb1/igt@gem_exec_schedule@implicit-read-write@bcs0.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-snb5/igt@gem_exec_schedule@implicit-read-write@bcs0.html
* igt@i915_selftest@perf@request:
- shard-tglb: [DMESG-FAIL][37] ([i915#1823]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb5/igt@i915_selftest@perf@request.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-tglb5/igt@i915_selftest@perf@request.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40] +2 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-apl8/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge:
- shard-skl: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +7 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl6/igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-skl4/igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
- shard-apl: [DMESG-WARN][43] ([i915#95]) -> [PASS][44] +16 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl1/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-apl3/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
* igt@kms_cursor_legacy@pipe-c-torture-bo:
- shard-hsw: [DMESG-WARN][45] ([i915#128]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-hsw4/igt@kms_cursor_legacy@pipe-c-torture-bo.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-hsw1/igt@kms_cursor_legacy@pipe-c-torture-bo.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][47] ([i915#180]) -> [PASS][48] +11 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][49] ([i915#1188]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-skl5/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-skl: [INCOMPLETE][51] ([i915#69]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-skl5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [SKIP][53] ([fdo#109441]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb4/igt@kms_psr@psr2_cursor_blt.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
* igt@perf@blocking-parameterized:
- shard-iclb: [FAIL][55] ([i915#1542]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb8/igt@perf@blocking-parameterized.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-iclb1/igt@perf@blocking-parameterized.html
* igt@perf_pmu@module-unload:
- shard-tglb: [DMESG-WARN][57] ([i915#402]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb2/igt@perf_pmu@module-unload.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-tglb2/igt@perf_pmu@module-unload.html
#### Warnings ####
* igt@kms_content_protection@atomic:
- shard-apl: [DMESG-FAIL][59] ([fdo#110321]) -> [TIMEOUT][60] ([i915#1319] / [i915#1635]) +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl2/igt@kms_content_protection@atomic.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-apl3/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@legacy:
- shard-apl: [TIMEOUT][61] ([i915#1319]) -> [TIMEOUT][62] ([i915#1319] / [i915#1635])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl8/igt@kms_content_protection@legacy.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-apl2/igt@kms_content_protection@legacy.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [DMESG-WARN][63] ([i915#180] / [i915#95]) -> [DMESG-WARN][64] ([i915#95])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-apl8/igt@kms_frontbuffer_tracking@fbc-suspend.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1823]: https://gitlab.freedesktop.org/drm/intel/issues/1823
[i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928
[i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#43]: https://gitlab.freedesktop.org/drm/intel/issues/43
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_8621 -> Patchwork_17938
CI-20190529: 20190529
CI_DRM_8621: acd803311fbd1e6adc38d10ca382a60c6c190be9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5708: f66c71e29de50bae880bc81ceb0517d4e3e2dfd8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17938: e754040f87476d5c11086ff3064211105297c0fa @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again
2020-06-12 12:39 ` Chris Wilson
@ 2020-06-12 22:05 ` Mika Kuoppala
2020-06-12 22:10 ` Chris Wilson
0 siblings, 1 reply; 15+ messages in thread
From: Mika Kuoppala @ 2020-06-12 22:05 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Chris Wilson
Chris Wilson <chris@chris-wilson.co.uk> writes:
> gen3 does not fully flush MI stores to memory on MI_FLUSH, such that a
> subsequent read from e.g. the sampler can bypass the store and read the
> stale value from memory. This is a serious issue when we are using MI
> stores to rewrite the batches for relocation, as it means that the batch
> is reading from random user/kernel memory. While it is particularly
> sensitive [and detectable] for relocations, reading stale data at any
> time is a worry.
>
> Having started with a small number of delaying stores and doubling until
> no more incoherency was seen over a few hours (with and without
> background memory pressure), 32 was the magic number.
>
> v2: Follow more closer with the gen5 w/a and include some
> post-invalidate flushes as well.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2018
> References: a889580c087a ("drm/i915: Flush GPU relocs harder for gen3")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 61 ++++++++++--------------
> 1 file changed, 25 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> index 3fb0dc1fb910..5400d657f334 100644
> --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> @@ -13,28 +13,25 @@
>
> int gen2_emit_flush(struct i915_request *rq, u32 mode)
> {
> - unsigned int num_store_dw;
> + unsigned int num_store_dw = 12;
> u32 cmd, *cs;
>
> cmd = MI_FLUSH;
> - num_store_dw = 0;
> if (mode & EMIT_INVALIDATE)
> cmd |= MI_READ_FLUSH;
> - if (mode & EMIT_FLUSH)
> - num_store_dw = 4;
>
> - cs = intel_ring_begin(rq, 2 + 3 * num_store_dw);
> + cs = intel_ring_begin(rq, 2 + 4 * num_store_dw);
> if (IS_ERR(cs))
> return PTR_ERR(cs);
>
> *cs++ = cmd;
> while (num_store_dw--) {
> - *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
> - *cs++ = intel_gt_scratch_offset(rq->engine->gt,
> - INTEL_GT_SCRATCH_FIELD_DEFAULT);
> - *cs++ = 0;
> + *cs++ = MI_STORE_DWORD_INDEX;
> + *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32);
> + *cs++ = rq->fence.seqno - 1;
> + *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;
> }
> - *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;
> + *cs++ = cmd;
>
> intel_ring_advance(rq, cs);
>
> @@ -142,38 +139,21 @@ int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode)
> return 0;
> }
>
> -u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> +static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs,
> + int flush, int post)
> {
> GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
> GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
>
> *cs++ = MI_FLUSH;
>
> - *cs++ = MI_STORE_DWORD_INDEX;
> - *cs++ = I915_GEM_HWS_SEQNO_ADDR;
> - *cs++ = rq->fence.seqno;
> -
> - *cs++ = MI_USER_INTERRUPT;
How can you throw the interrupt part out?
-Mika
> - *cs++ = MI_NOOP;
> -
> - rq->tail = intel_ring_offset(rq, cs);
> - assert_ring_tail_valid(rq->ring, rq->tail);
> -
> - return cs;
> -}
> -
> -#define GEN5_WA_STORES 8 /* must be at least 1! */
> -u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> -{
> - int i;
> -
> - GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
> - GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
> -
> - *cs++ = MI_FLUSH;
> + while (flush--) {
> + *cs++ = MI_STORE_DWORD_INDEX;
> + *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32);
> + *cs++ = rq->fence.seqno;
> + }
>
> - BUILD_BUG_ON(GEN5_WA_STORES < 1);
> - for (i = 0; i < GEN5_WA_STORES; i++) {
> + while (post--) {
> *cs++ = MI_STORE_DWORD_INDEX;
> *cs++ = I915_GEM_HWS_SEQNO_ADDR;
> *cs++ = rq->fence.seqno;
> @@ -186,7 +166,16 @@ u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs)
>
> return cs;
> }
> -#undef GEN5_WA_STORES
> +
> +u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> +{
> + return __gen2_emit_breadcrumb(rq, cs, 16, 8);
> +}
> +
> +u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> +{
> + return __gen2_emit_breadcrumb(rq, cs, 8, 8);
> +}
>
> /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
> #define I830_BATCH_LIMIT SZ_256K
> --
> 2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again
2020-06-12 22:05 ` Mika Kuoppala
@ 2020-06-12 22:10 ` Chris Wilson
2020-06-13 8:44 ` Mika Kuoppala
0 siblings, 1 reply; 15+ messages in thread
From: Chris Wilson @ 2020-06-12 22:10 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2020-06-12 23:05:18)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > gen3 does not fully flush MI stores to memory on MI_FLUSH, such that a
> > subsequent read from e.g. the sampler can bypass the store and read the
> > stale value from memory. This is a serious issue when we are using MI
> > stores to rewrite the batches for relocation, as it means that the batch
> > is reading from random user/kernel memory. While it is particularly
> > sensitive [and detectable] for relocations, reading stale data at any
> > time is a worry.
> >
> > Having started with a small number of delaying stores and doubling until
> > no more incoherency was seen over a few hours (with and without
> > background memory pressure), 32 was the magic number.
> >
> > v2: Follow more closer with the gen5 w/a and include some
> > post-invalidate flushes as well.
> >
> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2018
> > References: a889580c087a ("drm/i915: Flush GPU relocs harder for gen3")
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 61 ++++++++++--------------
> > 1 file changed, 25 insertions(+), 36 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> > index 3fb0dc1fb910..5400d657f334 100644
> > --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> > @@ -13,28 +13,25 @@
> >
> > int gen2_emit_flush(struct i915_request *rq, u32 mode)
> > {
> > - unsigned int num_store_dw;
> > + unsigned int num_store_dw = 12;
> > u32 cmd, *cs;
> >
> > cmd = MI_FLUSH;
> > - num_store_dw = 0;
> > if (mode & EMIT_INVALIDATE)
> > cmd |= MI_READ_FLUSH;
> > - if (mode & EMIT_FLUSH)
> > - num_store_dw = 4;
> >
> > - cs = intel_ring_begin(rq, 2 + 3 * num_store_dw);
> > + cs = intel_ring_begin(rq, 2 + 4 * num_store_dw);
> > if (IS_ERR(cs))
> > return PTR_ERR(cs);
> >
> > *cs++ = cmd;
> > while (num_store_dw--) {
> > - *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
> > - *cs++ = intel_gt_scratch_offset(rq->engine->gt,
> > - INTEL_GT_SCRATCH_FIELD_DEFAULT);
> > - *cs++ = 0;
> > + *cs++ = MI_STORE_DWORD_INDEX;
> > + *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32);
> > + *cs++ = rq->fence.seqno - 1;
> > + *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;
> > }
> > - *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;
> > + *cs++ = cmd;
> >
> > intel_ring_advance(rq, cs);
> >
> > @@ -142,38 +139,21 @@ int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode)
> > return 0;
> > }
> >
> > -u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> > +static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs,
> > + int flush, int post)
> > {
> > GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
> > GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
> >
> > *cs++ = MI_FLUSH;
> >
> > - *cs++ = MI_STORE_DWORD_INDEX;
> > - *cs++ = I915_GEM_HWS_SEQNO_ADDR;
> > - *cs++ = rq->fence.seqno;
> > -
> > - *cs++ = MI_USER_INTERRUPT;
>
> How can you throw the interrupt part out?
Diff being confusing. gen3_emit_breadcrumb and gen5_emit_breadcrumb
merged together.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again
2020-06-12 22:10 ` Chris Wilson
@ 2020-06-13 8:44 ` Mika Kuoppala
2020-06-13 9:17 ` Chris Wilson
0 siblings, 1 reply; 15+ messages in thread
From: Mika Kuoppala @ 2020-06-13 8:44 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Quoting Mika Kuoppala (2020-06-12 23:05:18)
>> Chris Wilson <chris@chris-wilson.co.uk> writes:
>>
>> > gen3 does not fully flush MI stores to memory on MI_FLUSH, such that a
>> > subsequent read from e.g. the sampler can bypass the store and read the
>> > stale value from memory. This is a serious issue when we are using MI
>> > stores to rewrite the batches for relocation, as it means that the batch
>> > is reading from random user/kernel memory. While it is particularly
>> > sensitive [and detectable] for relocations, reading stale data at any
>> > time is a worry.
>> >
>> > Having started with a small number of delaying stores and doubling until
>> > no more incoherency was seen over a few hours (with and without
>> > background memory pressure), 32 was the magic number.
>> >
>> > v2: Follow more closer with the gen5 w/a and include some
>> > post-invalidate flushes as well.
>> >
>> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2018
>> > References: a889580c087a ("drm/i915: Flush GPU relocs harder for gen3")
>> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> > ---
>> > drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 61 ++++++++++--------------
>> > 1 file changed, 25 insertions(+), 36 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
>> > index 3fb0dc1fb910..5400d657f334 100644
>> > --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
>> > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
>> > @@ -13,28 +13,25 @@
>> >
>> > int gen2_emit_flush(struct i915_request *rq, u32 mode)
>> > {
>> > - unsigned int num_store_dw;
>> > + unsigned int num_store_dw = 12;
>> > u32 cmd, *cs;
>> >
>> > cmd = MI_FLUSH;
>> > - num_store_dw = 0;
>> > if (mode & EMIT_INVALIDATE)
>> > cmd |= MI_READ_FLUSH;
>> > - if (mode & EMIT_FLUSH)
>> > - num_store_dw = 4;
>> >
>> > - cs = intel_ring_begin(rq, 2 + 3 * num_store_dw);
>> > + cs = intel_ring_begin(rq, 2 + 4 * num_store_dw);
>> > if (IS_ERR(cs))
>> > return PTR_ERR(cs);
>> >
>> > *cs++ = cmd;
>> > while (num_store_dw--) {
>> > - *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
>> > - *cs++ = intel_gt_scratch_offset(rq->engine->gt,
>> > - INTEL_GT_SCRATCH_FIELD_DEFAULT);
>> > - *cs++ = 0;
>> > + *cs++ = MI_STORE_DWORD_INDEX;
>> > + *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32);
>> > + *cs++ = rq->fence.seqno - 1;
>> > + *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;
>> > }
>> > - *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;
>> > + *cs++ = cmd;
>> >
>> > intel_ring_advance(rq, cs);
>> >
>> > @@ -142,38 +139,21 @@ int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode)
>> > return 0;
>> > }
>> >
>> > -u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs)
>> > +static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs,
>> > + int flush, int post)
>> > {
>> > GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
>> > GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
>> >
>> > *cs++ = MI_FLUSH;
>> >
>> > - *cs++ = MI_STORE_DWORD_INDEX;
>> > - *cs++ = I915_GEM_HWS_SEQNO_ADDR;
>> > - *cs++ = rq->fence.seqno;
>> > -
>> > - *cs++ = MI_USER_INTERRUPT;
>>
>> How can you throw the interrupt part out?
>
> Diff being confusing. gen3_emit_breadcrumb and gen5_emit_breadcrumb
> merged together.
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again
2020-06-13 8:44 ` Mika Kuoppala
@ 2020-06-13 9:17 ` Chris Wilson
0 siblings, 0 replies; 15+ messages in thread
From: Chris Wilson @ 2020-06-13 9:17 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2020-06-13 09:44:39)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > Quoting Mika Kuoppala (2020-06-12 23:05:18)
> >> Chris Wilson <chris@chris-wilson.co.uk> writes:
> >>
> >> > gen3 does not fully flush MI stores to memory on MI_FLUSH, such that a
> >> > subsequent read from e.g. the sampler can bypass the store and read the
> >> > stale value from memory. This is a serious issue when we are using MI
> >> > stores to rewrite the batches for relocation, as it means that the batch
> >> > is reading from random user/kernel memory. While it is particularly
> >> > sensitive [and detectable] for relocations, reading stale data at any
> >> > time is a worry.
> >> >
> >> > Having started with a small number of delaying stores and doubling until
> >> > no more incoherency was seen over a few hours (with and without
> >> > background memory pressure), 32 was the magic number.
> >> >
> >> > v2: Follow more closer with the gen5 w/a and include some
> >> > post-invalidate flushes as well.
> >> >
> >> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2018
> >> > References: a889580c087a ("drm/i915: Flush GPU relocs harder for gen3")
> >> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> >> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> >> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> >> > ---
> >> > drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 61 ++++++++++--------------
> >> > 1 file changed, 25 insertions(+), 36 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> >> > index 3fb0dc1fb910..5400d657f334 100644
> >> > --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> >> > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> >> > @@ -13,28 +13,25 @@
> >> >
> >> > int gen2_emit_flush(struct i915_request *rq, u32 mode)
> >> > {
> >> > - unsigned int num_store_dw;
> >> > + unsigned int num_store_dw = 12;
> >> > u32 cmd, *cs;
> >> >
> >> > cmd = MI_FLUSH;
> >> > - num_store_dw = 0;
> >> > if (mode & EMIT_INVALIDATE)
> >> > cmd |= MI_READ_FLUSH;
> >> > - if (mode & EMIT_FLUSH)
> >> > - num_store_dw = 4;
> >> >
> >> > - cs = intel_ring_begin(rq, 2 + 3 * num_store_dw);
> >> > + cs = intel_ring_begin(rq, 2 + 4 * num_store_dw);
> >> > if (IS_ERR(cs))
> >> > return PTR_ERR(cs);
> >> >
> >> > *cs++ = cmd;
> >> > while (num_store_dw--) {
> >> > - *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
> >> > - *cs++ = intel_gt_scratch_offset(rq->engine->gt,
> >> > - INTEL_GT_SCRATCH_FIELD_DEFAULT);
> >> > - *cs++ = 0;
> >> > + *cs++ = MI_STORE_DWORD_INDEX;
> >> > + *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32);
> >> > + *cs++ = rq->fence.seqno - 1;
> >> > + *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;
> >> > }
> >> > - *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;
> >> > + *cs++ = cmd;
> >> >
> >> > intel_ring_advance(rq, cs);
> >> >
> >> > @@ -142,38 +139,21 @@ int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode)
> >> > return 0;
> >> > }
> >> >
> >> > -u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> >> > +static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs,
> >> > + int flush, int post)
> >> > {
> >> > GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
> >> > GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
> >> >
> >> > *cs++ = MI_FLUSH;
> >> >
> >> > - *cs++ = MI_STORE_DWORD_INDEX;
> >> > - *cs++ = I915_GEM_HWS_SEQNO_ADDR;
> >> > - *cs++ = rq->fence.seqno;
> >> > -
> >> > - *cs++ = MI_USER_INTERRUPT;
> >>
> >> How can you throw the interrupt part out?
> >
> > Diff being confusing. gen3_emit_breadcrumb and gen5_emit_breadcrumb
> > merged together.
>
> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
It failed eventually, so unfortunately it's still just paper. However
increasing the MTBF by a few orders of magnitude should be enough to
stop CI complaining on every idle run.
-Chris
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^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2020-06-13 9:17 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-11 16:05 [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again Chris Wilson
2020-06-11 16:29 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2020-06-11 16:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-06-11 21:28 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-06-12 9:14 ` [Intel-gfx] [PATCH] " Mika Kuoppala
2020-06-12 9:23 ` Chris Wilson
2020-06-12 9:40 ` Chris Wilson
2020-06-12 12:39 ` Chris Wilson
2020-06-12 22:05 ` Mika Kuoppala
2020-06-12 22:10 ` Chris Wilson
2020-06-13 8:44 ` Mika Kuoppala
2020-06-13 9:17 ` Chris Wilson
2020-06-12 13:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Flush gen3 relocs harder, again (rev2) Patchwork
2020-06-12 13:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-06-12 15:28 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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