All of lore.kernel.org
 help / color / mirror / Atom feed
From: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
To: u-boot@lists.denx.de
Subject: [PATCHv3 14/15] dts: powerpc: p2020rdb: Add eTSEC DT nodes
Date: Fri, 12 Jun 2020 23:17:34 +0800	[thread overview]
Message-ID: <20200612151735.49048-15-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20200612151735.49048-1-Zhiqiang.Hou@nxp.com>

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

P2020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
    eTSEC1: Connected to RGMII PHY VSC7385
    eTSEC2: Connected to SGMII PHY VSC8221
    eTSEC3: Connected to SGMII PHY AR8021

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
 - Rebase the patch, no change intended.

 arch/powerpc/dts/p2020-post.dtsi         | 10 ++++
 arch/powerpc/dts/p2020rdb-pc.dts         |  1 +
 arch/powerpc/dts/p2020rdb-pc.dtsi        | 59 ++++++++++++++++++++++++
 arch/powerpc/dts/p2020rdb-pc_36b.dts     |  1 +
 arch/powerpc/dts/pq3-etsec1-0.dtsi       | 28 +++++++++++
 arch/powerpc/dts/pq3-etsec1-1.dtsi       | 28 +++++++++++
 arch/powerpc/dts/pq3-etsec1-2.dtsi       | 28 +++++++++++
 arch/powerpc/dts/pq3-etsec1-3.dtsi       | 28 +++++++++++
 arch/powerpc/dts/pq3-etsec1-timer-0.dtsi | 13 ++++++
 9 files changed, 196 insertions(+)
 create mode 100644 arch/powerpc/dts/p2020rdb-pc.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec1-0.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec1-1.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec1-2.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec1-3.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec1-timer-0.dtsi

diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index 4ed093dad4..af79705eba 100644
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -40,6 +40,16 @@
 
 	/include/ "pq3-i2c-0.dtsi"
 	/include/ "pq3-i2c-1.dtsi"
+
+/include/ "pq3-etsec1-0.dtsi"
+/include/ "pq3-etsec1-timer-0.dtsi"
+
+	ptp_clock at 24e00 {
+		interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>;
+	};
+
+/include/ "pq3-etsec1-1.dtsi"
+/include/ "pq3-etsec1-2.dtsi"
 };
 
 /* PCIe controller base address 0x8000 */
diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts
index 08befd4c59..f3f6be1080 100644
--- a/arch/powerpc/dts/p2020rdb-pc.dts
+++ b/arch/powerpc/dts/p2020rdb-pc.dts
@@ -37,4 +37,5 @@
 	};
 };
 
+/include/ "p2020rdb-pc.dtsi"
 /include/ "p2020-post.dtsi"
diff --git a/arch/powerpc/dts/p2020rdb-pc.dtsi b/arch/powerpc/dts/p2020rdb-pc.dtsi
new file mode 100644
index 0000000000..9abd700999
--- /dev/null
+++ b/arch/powerpc/dts/p2020rdb-pc.dtsi
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+&soc {
+	mdio at 24520 {
+		phy0: ethernet-phy at 0 {
+			interrupts = <3 1 0 0>;
+			reg = <0x0>;
+			};
+		phy1: ethernet-phy at 1 {
+			interrupts = <2 1 0 0>;
+			reg = <0x1>;
+			};
+	};
+
+	mdio at 25520 {
+		tbi0: tbi-phy at 11 {
+			reg = <0x11>;
+			device_type = "tbi-phy";
+		};
+	};
+
+	mdio at 26520 {
+		status = "disabled";
+	};
+
+	ptp_clock at 24e00 {
+		fsl,tclk-period	= <5>;
+		fsl,tmr-prsc	= <2>;
+		fsl,tmr-add	= <0xaaaaaaab>;
+		fsl,tmr-fiper1	= <999999995>;
+		fsl,tmr-fiper2	= <99990>;
+		fsl,max-adj	= <299999999>;
+	};
+
+	enet0: ethernet at 24000 {
+		phy-connection-type = "rgmii-id";
+		fixed-link {
+			speed = <1000>;
+			full-duplex;
+		};
+	};
+
+	enet1: ethernet at 25000 {
+		tbi-handle = <&tbi0>;
+		phy-handle = <&phy0>;
+		phy-connection-type = "sgmii";
+	};
+
+	enet2: ethernet at 26000 {
+		phy-handle = <&phy1>;
+		phy-connection-type = "rgmii-id";
+	};
+};
diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts
index 04b2519e1a..6d983b7d71 100644
--- a/arch/powerpc/dts/p2020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts
@@ -37,4 +37,5 @@
 	};
 };
 
+/include/ "p2020rdb-pc.dtsi"
 /include/ "p2020-post.dtsi"
diff --git a/arch/powerpc/dts/pq3-etsec1-0.dtsi b/arch/powerpc/dts/pq3-etsec1-0.dtsi
new file mode 100644
index 0000000000..8800243f34
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-0.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet at 24000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cell-index = <0>;
+	device_type = "network";
+	model = "eTSEC";
+	compatible = "gianfar";
+	reg = <0x24000 0x1000>;
+	ranges = <0x0 0x24000 0x1000>;
+	fsl,magic-packet;
+	local-mac-address = [ 00 00 00 00 00 00 ];
+	interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
+};
+
+mdio at 24520 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "fsl,gianfar-mdio";
+	reg = <0x24520 0x20>;
+};
diff --git a/arch/powerpc/dts/pq3-etsec1-1.dtsi b/arch/powerpc/dts/pq3-etsec1-1.dtsi
new file mode 100644
index 0000000000..2bc62d1a57
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-1.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x25000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet at 25000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cell-index = <1>;
+	device_type = "network";
+	model = "eTSEC";
+	compatible = "gianfar";
+	reg = <0x25000 0x1000>;
+	ranges = <0x0 0x25000 0x1000>;
+	fsl,magic-packet;
+	local-mac-address = [ 00 00 00 00 00 00 ];
+	interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
+};
+
+mdio at 25520 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "fsl,gianfar-tbi";
+	reg = <0x25520 0x20>;
+};
diff --git a/arch/powerpc/dts/pq3-etsec1-2.dtsi b/arch/powerpc/dts/pq3-etsec1-2.dtsi
new file mode 100644
index 0000000000..d45865fe03
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-2.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x26000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet at 26000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cell-index = <2>;
+	device_type = "network";
+	model = "eTSEC";
+	compatible = "gianfar";
+	reg = <0x26000 0x1000>;
+	ranges = <0x0 0x26000 0x1000>;
+	fsl,magic-packet;
+	local-mac-address = [ 00 00 00 00 00 00 ];
+	interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
+};
+
+mdio at 26520 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "fsl,gianfar-tbi";
+	reg = <0x26520 0x20>;
+};
diff --git a/arch/powerpc/dts/pq3-etsec1-3.dtsi b/arch/powerpc/dts/pq3-etsec1-3.dtsi
new file mode 100644
index 0000000000..853a27359d
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-3.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x27000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet at 27000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cell-index = <3>;
+	device_type = "network";
+	model = "eTSEC";
+	compatible = "gianfar";
+	reg = <0x27000 0x1000>;
+	ranges = <0x0 0x27000 0x1000>;
+	fsl,magic-packet;
+	local-mac-address = [ 00 00 00 00 00 00 ];
+	interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>;
+};
+
+mdio at 27520 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "fsl,gianfar-tbi";
+	reg = <0x27520 0x20>;
+};
diff --git a/arch/powerpc/dts/pq3-etsec1-timer-0.dtsi b/arch/powerpc/dts/pq3-etsec1-timer-0.dtsi
new file mode 100644
index 0000000000..19b37aca1d
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-timer-0.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC Timer (IEEE 1588) device tree stub [ @ offsets 0x24e00 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ptp_clock at 24e00 {
+	compatible = "fsl,etsec-ptp";
+	reg = <0x24e00 0xb0>;
+	interrupts = <68 2 0 0 69 2 0 0>;
+};
-- 
2.25.1

  parent reply	other threads:[~2020-06-12 15:17 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-12 15:17 [PATCHv3 00/13] powerpc: covert p1010, p1020 and p2020 RDB board to DM_ETH Zhiqiang Hou
2020-06-12 15:17 ` [PATCHv3 01/15] net: fsl_mdio: Change to use virtual address Zhiqiang Hou
2020-06-12 20:28   ` Vladimir Oltean
2020-06-15  8:54     ` Z.q. Hou
2020-06-12 15:17 ` [PATCHv3 02/15] net: fsl_mdio: Correct the MII management register block address Zhiqiang Hou
2020-06-12 15:17 ` [PATCHv3 03/15] net: tsec: convert to use DM_MDIO when DM_ETH enabled Zhiqiang Hou
2020-06-12 20:31   ` Vladimir Oltean
2020-06-15  8:56     ` Z.q. Hou
2020-06-12 15:17 ` [PATCHv3 04/15] net: tsec: Add the compatible string "gianfar" support Zhiqiang Hou
2020-06-12 20:40   ` Vladimir Oltean
2020-06-15  8:56     ` Z.q. Hou
2020-06-12 15:17 ` [PATCHv3 05/15] powerpc: mpc8xxx: Don't compile cpu_eth_init() when DM_ETH enabled Zhiqiang Hou
2020-06-12 15:17 ` [PATCHv3 06/15] fsl: p1_p2_rdb: Move vsc7835 firmware uploading to board_early_init_r() Zhiqiang Hou
2020-06-12 20:36   ` Vladimir Oltean
2020-06-15  8:56     ` Z.q. Hou
2020-06-12 15:17 ` [PATCHv3 07/15] configs: p1_p2_rdb: Add the default address of vsc7385 firmware Zhiqiang Hou
2020-06-12 15:17 ` [PATCHv3 08/15] dts: powerpc: p1020rdb: Add eTSEC DT nodes Zhiqiang Hou
2020-06-12 20:15   ` Vladimir Oltean
2020-06-15  8:50     ` Z.q. Hou
2020-06-12 15:17 ` [PATCHv3 09/15] powerpc: p1_p2_rdb: Don't compile board_eth_init() when DM_ETH enabled Zhiqiang Hou
2020-06-12 15:17 ` [PATCHv3 10/15] configs: P1020RDB: Enable DM_ETH config Zhiqiang Hou
2020-06-12 15:17 ` [PATCHv3 11/15] dts: powerpc: p1010rdb: Add eTSEC DT nodes Zhiqiang Hou
2020-06-12 15:17 ` [PATCHv3 12/15] powerpc: p1010rdb: Compile legacy ethernet init function when no DM_ETH Zhiqiang Hou
2020-06-12 20:24   ` Vladimir Oltean
2020-06-15  8:54     ` Z.q. Hou
2020-06-12 15:17 ` [PATCHv3 13/15] configs: P1010RDB: Enable DM_ETH config Zhiqiang Hou
2020-06-12 20:20   ` Vladimir Oltean
2020-06-15  8:53     ` Z.q. Hou
2020-06-12 15:17 ` Zhiqiang Hou [this message]
2020-06-12 15:17 ` [PATCHv3 15/15] configs: P2020RDB: " Zhiqiang Hou
2020-06-12 20:17   ` Vladimir Oltean
2020-06-15  8:51     ` Z.q. Hou

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200612151735.49048-15-Zhiqiang.Hou@nxp.com \
    --to=zhiqiang.hou@nxp.com \
    --cc=u-boot@lists.denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.