[PATCH v2 0/2] target/mips: Add two groups of loongson-ext instructions

[PATCH v2 0/2] target/mips: Add two groups of loongson-ext instructions

[Jiaxun Yang]

This is the sucessor of:
"Basic TCG Loongson-3A1000 Support"

Thanks!

Jiaxun Yang (2):
  target/mips: Add loongson-ext lsdc2 group of instructions
  target/mips: Add loongson-ext lswc2 group of instrustions

 target/mips/translate.c | 437 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 437 insertions(+)

-- 
2.27.0.rc2

[PATCH v2 1/2] target/mips: Add loongson-ext lsdc2 group of instructions

[Jiaxun Yang]

LDC2/SDC2 opcodes have been rewritten as "load & store with offset"
group of instructions by loongson-ext ASE.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/mips/translate.c | 179 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 179 insertions(+)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9fad58ea2c..5d2accf3e4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -460,6 +460,24 @@ enum {
     R6_OPC_SCD         = 0x27 | OPC_SPECIAL3,
 };
 
+/* Loongson EXT LDC2/SDC2 opcodes */
+#define MASK_LOONGSON_LSDC2(op)           (MASK_OP_MAJOR(op) | (op & 0x7))
+
+enum {
+    OPC_GSLBX      = 0x0 | OPC_LDC2,
+    OPC_GSLHX      = 0x1 | OPC_LDC2,
+    OPC_GSLWX      = 0x2 | OPC_LDC2,
+    OPC_GSLDX      = 0x3 | OPC_LDC2,
+    OPC_GSLWXC1    = 0x6 | OPC_LDC2,
+    OPC_GSLDXC1    = 0x7 | OPC_LDC2,
+    OPC_GSSBX      = 0x0 | OPC_SDC2,
+    OPC_GSSHX      = 0x1 | OPC_SDC2,
+    OPC_GSSWX      = 0x2 | OPC_SDC2,
+    OPC_GSSDX      = 0x3 | OPC_SDC2,
+    OPC_GSSWXC1    = 0x6 | OPC_SDC2,
+    OPC_GSSDXC1    = 0x7 | OPC_SDC2,
+};
+
 /* BSHFL opcodes */
 #define MASK_BSHFL(op)              (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 
@@ -5910,6 +5928,165 @@ no_rd:
     tcg_temp_free_i64(t1);
 }
 
+/* Loongson EXT LDC2/SDC2 */
+static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
+                                int rs, int rd)
+{
+    int offset = (int8_t)(ctx->opcode >> 3);
+    uint32_t opc = MASK_LOONGSON_LSDC2(ctx->opcode);
+    TCGv t0, t1;
+    TCGv_i32 fp0;
+
+    /* Pre-conditions */
+    switch (opc) {
+    case OPC_GSLBX:
+    case OPC_GSLHX:
+    case OPC_GSLWX:
+    case OPC_GSLDX:
+        /* prefetch, implement as NOP */
+        if (rt == 0) {
+            return;
+        }
+        break;
+    case OPC_GSSBX:
+    case OPC_GSSHX:
+    case OPC_GSSWX:
+    case OPC_GSSDX:
+        break;
+    case OPC_GSLWXC1:
+#if defined(TARGET_MIPS64)
+    case OPC_GSLDXC1:
+#endif
+        check_cp1_enabled(ctx);
+        /* prefetch, implement as NOP */
+        if (rt == 0) {
+            return;
+        }
+        break;
+    case OPC_GSSWXC1:
+#if defined(TARGET_MIPS64)
+    case OPC_GSSDXC1:
+#endif
+        check_cp1_enabled(ctx);
+        break;
+    default:
+        MIPS_INVAL("loongson_lsdc2");
+        generate_exception_end(ctx, EXCP_RI);
+        return;
+        break;
+    }
+
+    t0 = tcg_temp_new();
+
+    gen_base_offset_addr(ctx, t0, rs, offset);
+    gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+
+    switch (opc) {
+    case OPC_GSLBX:
+        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB);
+        gen_store_gpr(t0, rt);
+        break;
+    case OPC_GSLHX:
+        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW |
+                            ctx->default_tcg_memop_mask);
+        gen_store_gpr(t0, rt);
+        break;
+    case OPC_GSLWX:
+        gen_base_offset_addr(ctx, t0, rs, offset);
+        if (rd) {
+            gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+        }
+        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL |
+                            ctx->default_tcg_memop_mask);
+        gen_store_gpr(t0, rt);
+        break;
+#if defined(TARGET_MIPS64)
+    case OPC_GSLDX:
+        gen_base_offset_addr(ctx, t0, rs, offset);
+        if (rd) {
+            gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+        }
+        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
+                            ctx->default_tcg_memop_mask);
+        gen_store_gpr(t0, rt);
+        break;
+#endif
+    case OPC_GSLWXC1:
+        check_cp1_enabled(ctx);
+        gen_base_offset_addr(ctx, t0, rs, offset);
+        if (rd) {
+            gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+        }
+        fp0 = tcg_temp_new_i32();
+        tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL |
+                            ctx->default_tcg_memop_mask);
+        gen_store_fpr32(ctx, fp0, rt);
+        tcg_temp_free_i32(fp0);
+        break;
+#if defined(TARGET_MIPS64)
+    case OPC_GSLDXC1:
+        check_cp1_enabled(ctx);
+        gen_base_offset_addr(ctx, t0, rs, offset);
+        if (rd) {
+            gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+        }
+        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
+                            ctx->default_tcg_memop_mask);
+        gen_store_fpr64(ctx, t0, rt);
+        break;
+#endif
+    case OPC_GSSBX:
+        t1 = tcg_temp_new();
+        gen_load_gpr(t1, rt);
+        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_SB);
+        tcg_temp_free(t1);
+        break;
+    case OPC_GSSHX:
+        t1 = tcg_temp_new();
+        gen_load_gpr(t1, rt);
+        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW |
+                            ctx->default_tcg_memop_mask);
+        tcg_temp_free(t1);
+        break;
+    case OPC_GSSWX:
+        t1 = tcg_temp_new();
+        gen_load_gpr(t1, rt);
+        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+                            ctx->default_tcg_memop_mask);
+        tcg_temp_free(t1);
+        break;
+#if defined(TARGET_MIPS64)
+    case OPC_GSSDX:
+        t1 = tcg_temp_new();
+        gen_load_gpr(t1, rt);
+        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+                            ctx->default_tcg_memop_mask);
+        tcg_temp_free(t1);
+        break;
+#endif
+    case OPC_GSSWXC1:
+        fp0 = tcg_temp_new_i32();
+        gen_load_fpr32(ctx, fp0, rt);
+        tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL |
+                            ctx->default_tcg_memop_mask);
+        tcg_temp_free_i32(fp0);
+        break;
+#if defined(TARGET_MIPS64)
+    case OPC_GSSDXC1:
+        t1 = tcg_temp_new();
+        gen_load_fpr64(ctx, t1, rt);
+        tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TEQ |
+                            ctx->default_tcg_memop_mask);
+        tcg_temp_free(t1);
+        break;
+#endif
+    default:
+        break;
+    }
+
+    tcg_temp_free(t0);
+}
+
 /* Traps */
 static void gen_trap(DisasContext *ctx, uint32_t opc,
                      int rs, int rt, int16_t imm)
@@ -30799,6 +30976,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
                 /* OPC_JIC, OPC_JIALC */
                 gen_compute_compact_branch(ctx, op, 0, rt, imm);
             }
+        } else if (ctx->insn_flags & ASE_LEXT) {
+            gen_loongson_lsdc2(ctx, rt, rs, rd);
         } else {
             /* OPC_LWC2, OPC_SWC2 */
             /* COP2: Not implemented. */
-- 
2.27.0.rc2

[PATCH v2 2/2] target/mips: Add loongson-ext lswc2 group of instrustions

[Jiaxun Yang]

LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE
as "load/store quad word" and "shifted load/store" groups of
instructions.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/mips/translate.c | 258 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 258 insertions(+)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 5d2accf3e4..12349a1593 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -460,6 +460,30 @@ enum {
     R6_OPC_SCD         = 0x27 | OPC_SPECIAL3,
 };
 
+/* Loongson EXT load/store quad word opcodes */
+#define MASK_LOONGSON_GSLSQ(op)           (MASK_OP_MAJOR(op) | (op & 0x8020))
+enum {
+    OPC_GSLQ        = 0x0020 | OPC_LWC2,
+    OPC_GSLQC1      = 0x8020 | OPC_LWC2,
+    OPC_GSSHFL      = OPC_LWC2,
+    OPC_GSSQ        = 0x0020 | OPC_SWC2,
+    OPC_GSSQC1      = 0x8020 | OPC_SWC2,
+    OPC_GSSHFS      = OPC_SWC2,
+};
+
+/* Loongson EXT shifted load/store opcodes */
+#define MASK_LOONGSON_GSSHFLS(op)         (MASK_OP_MAJOR(op) | (op & 0xc03f))
+enum {
+    OPC_GSLWLC1     = 0x4 | OPC_GSSHFL,
+    OPC_GSLWRC1     = 0x5 | OPC_GSSHFL,
+    OPC_GSLDLC1     = 0x6 | OPC_GSSHFL,
+    OPC_GSLDRC1     = 0x7 | OPC_GSSHFL,
+    OPC_GSSWLC1     = 0x4 | OPC_GSSHFS,
+    OPC_GSSWRC1     = 0x5 | OPC_GSSHFS,
+    OPC_GSSDLC1     = 0x6 | OPC_GSSHFS,
+    OPC_GSSDRC1     = 0x7 | OPC_GSSHFS,
+};
+
 /* Loongson EXT LDC2/SDC2 opcodes */
 #define MASK_LOONGSON_LSDC2(op)           (MASK_OP_MAJOR(op) | (op & 0x7))
 
@@ -5928,6 +5952,238 @@ no_rd:
     tcg_temp_free_i64(t1);
 }
 
+static void gen_loongson_lswc2(DisasContext *ctx, int rt,
+                                int rs, int rd)
+{
+    TCGv t0, t1, t2;
+    TCGv_i32 fp0;
+    int lsq_offset = ((int)((ctx->opcode >> 6) & 0x1ff) << 23) >> 19;
+    int lsq_rt1 = ctx->opcode & 0x1f;
+    int shf_offset = (int8_t)(ctx->opcode >> 6);
+
+    t0 = tcg_temp_new();
+
+    switch (MASK_LOONGSON_GSLSQ(ctx->opcode)) {
+#if defined(TARGET_MIPS64)
+    case OPC_GSLQ:
+        gen_base_offset_addr(ctx, t0, rs, lsq_offset);
+        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
+                            ctx->default_tcg_memop_mask);
+        gen_store_gpr(t0, rt);
+        gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
+        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
+                            ctx->default_tcg_memop_mask);
+        gen_store_gpr(t0, lsq_rt1);
+        break;
+    case OPC_GSLQC1:
+        check_cp1_enabled(ctx);
+        gen_base_offset_addr(ctx, t0, rs, lsq_offset);
+        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
+                            ctx->default_tcg_memop_mask);
+        gen_store_fpr64(ctx, t0, rt);
+        gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
+        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
+                            ctx->default_tcg_memop_mask);
+        gen_store_fpr64(ctx, t0, lsq_rt1);
+        break;
+    case OPC_GSSQ:
+        t1 = tcg_temp_new();
+        gen_base_offset_addr(ctx, t0, rs, lsq_offset);
+        gen_load_gpr(t1, rt);
+        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+                            ctx->default_tcg_memop_mask);
+        gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
+        gen_load_gpr(t1, lsq_rt1);
+        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+                            ctx->default_tcg_memop_mask);
+        tcg_temp_free(t1);
+        break;
+    case OPC_GSSQC1:
+        check_cp1_enabled(ctx);
+        t1 = tcg_temp_new();
+        gen_base_offset_addr(ctx, t0, rs, lsq_offset);
+        gen_load_fpr64(ctx, t1, rt);
+        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+                            ctx->default_tcg_memop_mask);
+        gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
+        gen_load_fpr64(ctx, t1, lsq_rt1);
+        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+                            ctx->default_tcg_memop_mask);
+        tcg_temp_free(t1);
+        break;
+#endif
+    case OPC_GSSHFL:
+        switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) {
+        case OPC_GSLWLC1:
+            check_cp1_enabled(ctx);
+            gen_base_offset_addr(ctx, t0, rs, shf_offset);
+            t1 = tcg_temp_new();
+            tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
+            tcg_gen_andi_tl(t1, t0, 3);
+#ifndef TARGET_WORDS_BIGENDIAN
+            tcg_gen_xori_tl(t1, t1, 3);
+#endif
+            tcg_gen_shli_tl(t1, t1, 3);
+            tcg_gen_andi_tl(t0, t0, ~3);
+            tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
+            tcg_gen_shl_tl(t0, t0, t1);
+            t2 = tcg_const_tl(-1);
+            tcg_gen_shl_tl(t2, t2, t1);
+            fp0 = tcg_temp_new_i32();
+            gen_load_fpr32(ctx, fp0, rt);
+            tcg_gen_ext_i32_tl(t1, fp0);
+            tcg_gen_andc_tl(t1, t1, t2);
+            tcg_temp_free(t2);
+            tcg_gen_or_tl(t0, t0, t1);
+            tcg_temp_free(t1);
+#if defined(TARGET_MIPS64)
+            tcg_gen_extrl_i64_i32(fp0, t0);
+#else
+            tcg_gen_ext32s_tl(fp0, t0);
+#endif
+            gen_store_fpr32(ctx, fp0, rt);
+            tcg_temp_free_i32(fp0);
+            break;
+        case OPC_GSLWRC1:
+            check_cp1_enabled(ctx);
+            gen_base_offset_addr(ctx, t0, rs, shf_offset);
+            t1 = tcg_temp_new();
+            tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
+            tcg_gen_andi_tl(t1, t0, 3);
+#ifdef TARGET_WORDS_BIGENDIAN
+            tcg_gen_xori_tl(t1, t1, 3);
+#endif
+            tcg_gen_shli_tl(t1, t1, 3);
+            tcg_gen_andi_tl(t0, t0, ~3);
+            tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
+            tcg_gen_shr_tl(t0, t0, t1);
+            tcg_gen_xori_tl(t1, t1, 31);
+            t2 = tcg_const_tl(0xfffffffeull);
+            tcg_gen_shl_tl(t2, t2, t1);
+            fp0 = tcg_temp_new_i32();
+            gen_load_fpr32(ctx, fp0, rt);
+            tcg_gen_ext_i32_tl(t1, fp0);
+            tcg_gen_and_tl(t1, t1, t2);
+            tcg_temp_free(t2);
+            tcg_gen_or_tl(t0, t0, t1);
+            tcg_temp_free(t1);
+#if defined(TARGET_MIPS64)
+            tcg_gen_extrl_i64_i32(fp0, t0);
+#else
+            tcg_gen_ext32s_tl(fp0, t0);
+#endif
+            gen_store_fpr32(ctx, fp0, rt);
+            tcg_temp_free_i32(fp0);
+            break;
+#if defined(TARGET_MIPS64)
+        case OPC_GSLDLC1:
+            check_cp1_enabled(ctx);
+            gen_base_offset_addr(ctx, t0, rs, shf_offset);
+            t1 = tcg_temp_new();
+            tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
+            tcg_gen_andi_tl(t1, t0, 7);
+#ifndef TARGET_WORDS_BIGENDIAN
+            tcg_gen_xori_tl(t1, t1, 7);
+#endif
+            tcg_gen_shli_tl(t1, t1, 3);
+            tcg_gen_andi_tl(t0, t0, ~7);
+            tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
+            tcg_gen_shl_tl(t0, t0, t1);
+            t2 = tcg_const_tl(-1);
+            tcg_gen_shl_tl(t2, t2, t1);
+            gen_load_fpr64(ctx, t1, rt);
+            tcg_gen_andc_tl(t1, t1, t2);
+            tcg_temp_free(t2);
+            tcg_gen_or_tl(t0, t0, t1);
+            tcg_temp_free(t1);
+            gen_store_fpr64(ctx, t0, rt);
+            break;
+        case OPC_GSLDRC1:
+            check_cp1_enabled(ctx);
+            gen_base_offset_addr(ctx, t0, rs, shf_offset);
+            t1 = tcg_temp_new();
+            tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
+            tcg_gen_andi_tl(t1, t0, 7);
+#ifdef TARGET_WORDS_BIGENDIAN
+            tcg_gen_xori_tl(t1, t1, 7);
+#endif
+            tcg_gen_shli_tl(t1, t1, 3);
+            tcg_gen_andi_tl(t0, t0, ~7);
+            tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
+            tcg_gen_shr_tl(t0, t0, t1);
+            tcg_gen_xori_tl(t1, t1, 63);
+            t2 = tcg_const_tl(0xfffffffffffffffeull);
+            tcg_gen_shl_tl(t2, t2, t1);
+            gen_load_fpr64(ctx, t1, rt);
+            tcg_gen_and_tl(t1, t1, t2);
+            tcg_temp_free(t2);
+            tcg_gen_or_tl(t0, t0, t1);
+            tcg_temp_free(t1);
+            gen_store_fpr64(ctx, t0, rt);
+            break;
+#endif
+        default:
+            MIPS_INVAL("loongson_gsshfl");
+            generate_exception_end(ctx, EXCP_RI);
+            break;
+        }
+        break;
+    case OPC_GSSHFS:
+        switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) {
+        case OPC_GSSWLC1:
+            check_cp1_enabled(ctx);
+            t1 = tcg_temp_new();
+            gen_base_offset_addr(ctx, t0, rs, shf_offset);
+            fp0 = tcg_temp_new_i32();
+            gen_load_fpr32(ctx, fp0, rt);
+            tcg_gen_ext_i32_tl(t1, fp0);
+            gen_helper_0e2i(swl, t1, t0, ctx->mem_idx);
+            tcg_temp_free_i32(fp0);
+            tcg_temp_free(t1);
+            break;
+        case OPC_GSSWRC1:
+            check_cp1_enabled(ctx);
+            t1 = tcg_temp_new();
+            gen_base_offset_addr(ctx, t0, rs, shf_offset);
+            fp0 = tcg_temp_new_i32();
+            gen_load_fpr32(ctx, fp0, rt);
+            tcg_gen_ext_i32_tl(t1, fp0);
+            gen_helper_0e2i(swr, t1, t0, ctx->mem_idx);
+            tcg_temp_free_i32(fp0);
+            tcg_temp_free(t1);
+            break;
+#if defined(TARGET_MIPS64)
+        case OPC_GSSDLC1:
+            check_cp1_enabled(ctx);
+            t1 = tcg_temp_new();
+            gen_base_offset_addr(ctx, t0, rs, shf_offset);
+            gen_load_fpr64(ctx, t1, rt);
+            gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx);
+            tcg_temp_free(t1);
+            break;
+        case OPC_GSSDRC1:
+            check_cp1_enabled(ctx);
+            t1 = tcg_temp_new();
+            gen_base_offset_addr(ctx, t0, rs, shf_offset);
+            gen_load_fpr64(ctx, t1, rt);
+            gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx);
+            tcg_temp_free(t1);
+            break;
+#endif
+        default:
+            MIPS_INVAL("loongson_gsshfs");
+            generate_exception_end(ctx, EXCP_RI);
+            break;
+        }
+        break;
+    default:
+        MIPS_INVAL("loongson_gslsq");
+        generate_exception_end(ctx, EXCP_RI);
+        break;
+    }
+    tcg_temp_free(t0);
+}
+
 /* Loongson EXT LDC2/SDC2 */
 static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
                                 int rs, int rd)
@@ -30959,6 +31215,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
             /* OPC_BC, OPC_BALC */
             gen_compute_compact_branch(ctx, op, 0, 0,
                                        sextract32(ctx->opcode << 2, 0, 28));
+        } else if (ctx->insn_flags & ASE_LEXT) {
+            gen_loongson_lswc2(ctx, rt, rs, rd);
         } else {
             /* OPC_LWC2, OPC_SWC2 */
             /* COP2: Not implemented. */
-- 
2.27.0.rc2

[PATCH v2 0/2] target/mips: Add two groups of loongson-ext instructions

[Aleksandar Markovic]

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уторак, 16. јун 2020., Jiaxun Yang <jiaxun.yang@flygoat.com> је написао/ла:

> This is the sucessor of:
> "Basic TCG Loongson-3A1000 Support"
>
> Thanks!
>
>
Hi, Jiaxun.

Thanks for providing updated version of the series.

I wonder, given so many "#if defined(TARGET_MIPS64)" lines in this series,
what would be the 32-bit processors that support Loongson EXT ASE?

Thanks,
Aleksandar



> Jiaxun Yang (2):
>   target/mips: Add loongson-ext lsdc2 group of instructions
>   target/mips: Add loongson-ext lswc2 group of instrustions
>
>
Also, a spelling mistake in the second title.


>  target/mips/translate.c | 437 ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 437 insertions(+)
>
> --
> 2.27.0.rc2
>
>

[-- Attachment #2: Type: text/html, Size: 1405 bytes --]

Re: [PATCH v2 0/2] target/mips: Add two groups of loongson-ext instructions

[Jiaxun Yang]

在 2020/6/16 18:38, Aleksandar Markovic 写道:
> 
> 
> уторак, 16. јун 2020., Jiaxun Yang <jiaxun.yang@flygoat.com 
> <mailto:jiaxun.yang@flygoat.com>> је написао/ла:
> 
>     This is the sucessor of:
>     "Basic TCG Loongson-3A1000 Support"
> 
>     Thanks!
> 
> 
> Hi, Jiaxun.
> 
> Thanks for providing updated version of the series.
> 
> I wonder, given so many "#if defined(TARGET_MIPS64)" lines in this 
> series, what would be the 32-bit processors that support Loongson EXT ASE?

Loongson GS232 core which can be found in Loongson-1A/B/C should support it.
Although I have no intension to work on QEMU support of these processors.

> 
> Thanks,
> Aleksandar
> 
>     Jiaxun Yang (2):
>        target/mips: Add loongson-ext lsdc2 group of instructions
>        target/mips: Add loongson-ext lswc2 group of instrustions
> 
> 
> Also, a spelling mistake in the second title.

Ahh, My bad....

> 
>       target/mips/translate.c | 437 ++++++++++++++++++++++++++++++++++++++++
>       1 file changed, 437 insertions(+)
> 
>     -- 
>     2.27.0.rc2
> 

-- 
- Jiaxun

Re: [PATCH v2 0/2] target/mips: Add two groups of loongson-ext instructions

[Aleksandar Markovic]

[-- Attachment #1: Type: text/plain, Size: 2191 bytes --]

уторак, 16. јун 2020., Jiaxun Yang <jiaxun.yang@flygoat.com> је написао/ла:

>
>
> 在 2020/6/16 18:38, Aleksandar Markovic 写道:
>
>>
>>
>> уторак, 16. јун 2020., Jiaxun Yang <jiaxun.yang@flygoat.com <mailto:
>> jiaxun.yang@flygoat.com>> је написао/ла:
>>
>>     This is the sucessor of:
>>     "Basic TCG Loongson-3A1000 Support"
>>
>>     Thanks!
>>
>>
>> Hi, Jiaxun.
>>
>> Thanks for providing updated version of the series.
>>
>> I wonder, given so many "#if defined(TARGET_MIPS64)" lines in this
>> series, what would be the 32-bit processors that support Loongson EXT ASE?
>>
>
> Loongson GS232 core which can be found in Loongson-1A/B/C should support
> it.
> Although I have no intension to work on QEMU support of these processors.
>
>
...And, for the sake of accuracy, you nevertheless included the correct
implementation (for both 32-bir and 64-bit). That is very good. I would do
the same, if I were you.

However, there is a problem. We can't upstream (at least not in QEMU for
MIPS) anything without the proper documentation.

So, please provide the links or attach the supporting files to the cover
letter in v2. You already did something similar in some of your previous
series and patches. I am perfectly fine with machine translation from
Chinese.

For example, you need to provide, among other things, docs describing EXT
support in GS 232 cores. We can't just make assumptions, or trust your
word. These sources of information should be repeated for all versions (v2,
v3,...) of the series, in their cover letters.

I salute your series, but it needs much more justification.

Yours,
Aleksandar



>
>> Thanks,
>> Aleksandar
>>
>>     Jiaxun Yang (2):
>>        target/mips: Add loongson-ext lsdc2 group of instructions
>>        target/mips: Add loongson-ext lswc2 group of instrustions
>>
>>
>> Also, a spelling mistake in the second title.
>>
>
> Ahh, My bad....
>
>
>>       target/mips/translate.c | 437 ++++++++++++++++++++++++++++++
>> ++++++++++
>>       1 file changed, 437 insertions(+)
>>
>>     --     2.27.0.rc2
>>
>>
> --
> - Jiaxun
>

[-- Attachment #2: Type: text/html, Size: 3243 bytes --]

Re: [PATCH v2 0/2] target/mips: Add two groups of loongson-ext instructions

[Jiaxun Yang]

在 2020/6/16 22:41, Aleksandar Markovic 写道:
> 
> 
> уторак, 16. јун 2020., Jiaxun Yang <jiaxun.yang@flygoat.com 
> <mailto:jiaxun.yang@flygoat.com>> је написао/ла:
> 
> 
> 
>     在 2020/6/16 18:38, Aleksandar Markovic 写道:
> 
> 
> 
>         уторак, 16. јун 2020., Jiaxun Yang <jiaxun.yang@flygoat.com
>         <mailto:jiaxun.yang@flygoat.com> <mailto:jiaxun.yang@flygoat.com
>         <mailto:jiaxun.yang@flygoat.com>>> је написао/ла:
> 
>              This is the sucessor of:
>              "Basic TCG Loongson-3A1000 Support"
> 
>              Thanks!
> 
> 
>         Hi, Jiaxun.
> 
>         Thanks for providing updated version of the series.
> 
>         I wonder, given so many "#if defined(TARGET_MIPS64)" lines in
>         this series, what would be the 32-bit processors that support
>         Loongson EXT ASE?
> 
> 
>     Loongson GS232 core which can be found in Loongson-1A/B/C should
>     support it.
>     Although I have no intension to work on QEMU support of these
>     processors.
> 
> 
> ...And, for the sake of accuracy, you nevertheless included the correct 
> implementation (for both 32-bir and 64-bit). That is very good. I would 
> do the same, if I were you.
> 
> However, there is a problem. We can't upstream (at least not in QEMU for 
> MIPS) anything without the proper documentation.
> 
> So, please provide the links or attach the supporting files to the cover 
> letter in v2. You already did something similar in some of your previous 
> series and patches. I am perfectly fine with machine translation from 
> Chinese.
> 
> For example, you need to provide, among other things, docs describing 
> EXT support in GS 232 cores. We can't just make assumptions, or trust 
> your word. These sources of information should be repeated for all 
> versions (v2, v3,...) of the series, in their cover letters.

I'll attach necessary information about these instructions in next 
version, however, there is no public document avilable for GS232 core.
That's why I'm not intend to upstream it for now.

Should I keep these code as is? Ot just filter all Loongson EXT out for 
MIPS32.

Thanks.

> 
> I salute your series, but it needs much more justification.
> 
> Yours,
> Aleksandar
> 
> 
>         Thanks,
>         Aleksandar
> 
>              Jiaxun Yang (2):
>                 target/mips: Add loongson-ext lsdc2 group of instructions
>                 target/mips: Add loongson-ext lswc2 group of instrustions
> 
> 
>         Also, a spelling mistake in the second title.
> 
> 
>     Ahh, My bad....
> 
> 
>                target/mips/translate.c | 437
>         ++++++++++++++++++++++++++++++++++++++++
>                1 file changed, 437 insertions(+)
> 
>              --     2.27.0.rc2
> 
> 
>     -- 
>     - Jiaxun
> 

-- 
- Jiaxun

Re: [PATCH v2 0/2] target/mips: Add two groups of loongson-ext instructions

[Aleksandar Markovic]

[-- Attachment #1: Type: text/plain, Size: 4131 bytes --]

среда, 17. јун 2020., Jiaxun Yang <jiaxun.yang@flygoat.com> је написао/ла:

>
>
> 在 2020/6/16 22:41, Aleksandar Markovic 写道:
>
>>
>>
>> уторак, 16. јун 2020., Jiaxun Yang <jiaxun.yang@flygoat.com <mailto:
>> jiaxun.yang@flygoat.com>> је написао/ла:
>>
>>
>>
>>     在 2020/6/16 18:38, Aleksandar Markovic 写道:
>>
>>
>>
>>         уторак, 16. јун 2020., Jiaxun Yang <jiaxun.yang@flygoat.com
>>         <mailto:jiaxun.yang@flygoat.com> <mailto:jiaxun.yang@flygoat.com
>>         <mailto:jiaxun.yang@flygoat.com>>> је написао/ла:
>>
>>              This is the sucessor of:
>>              "Basic TCG Loongson-3A1000 Support"
>>
>>              Thanks!
>>
>>
>>         Hi, Jiaxun.
>>
>>         Thanks for providing updated version of the series.
>>
>>         I wonder, given so many "#if defined(TARGET_MIPS64)" lines in
>>         this series, what would be the 32-bit processors that support
>>         Loongson EXT ASE?
>>
>>
>>     Loongson GS232 core which can be found in Loongson-1A/B/C should
>>     support it.
>>     Although I have no intension to work on QEMU support of these
>>     processors.
>>
>>
>> ...And, for the sake of accuracy, you nevertheless included the correct
>> implementation (for both 32-bir and 64-bit). That is very good. I would do
>> the same, if I were you.
>>
>> However, there is a problem. We can't upstream (at least not in QEMU for
>> MIPS) anything without the proper documentation.
>>
>> So, please provide the links or attach the supporting files to the cover
>> letter in v2. You already did something similar in some of your previous
>> series and patches. I am perfectly fine with machine translation from
>> Chinese.
>>
>> For example, you need to provide, among other things, docs describing EXT
>> support in GS 232 cores. We can't just make assumptions, or trust your
>> word. These sources of information should be repeated for all versions (v2,
>> v3,...) of the series, in their cover letters.
>>
>
> I'll attach necessary information about these instructions in next
> version, however, there is no public document avilable for GS232 core.
> That's why I'm not intend to upstream it for now.
>
> Should I keep these code as is? Ot just filter all Loongson EXT out for
> MIPS32.
>
>
Sorry for late response, Jiaxun, I got carried away with other things.

I am not sure, I simply don't have access to the appropriate info. at this
moment, I'd say you can keep (for now) the "ifdef"-ed code for handling
32-bit, since it will never be actually used.

But, how do you know the code is correct, if there is no doc? How do you
know about specifics of 32-bit ext? Is it just guessing, or more than that?
Mention the source of information in commit messages, if any. Or say this
is just a guess.

A short comment should be added about handling for 32-bit just before the
main functions that handle Loongson EXT, just like Richard did for those
instructions from LMMI that he could not find proper documentation.

Also, can you mention what is achieved by having EXT in QEMU? What
Longson-related scenarion would work, that previously (currently) would not?

Thanks for this nice series, and all valuable efforts, hopefully we will
resolve documentation issue in comming days or weeks.

Aleksandar





> Thanks.
>
>
>> I salute your series, but it needs much more justification.
>>
>> Yours,
>> Aleksandar
>>
>>
>>         Thanks,
>>         Aleksandar
>>
>>              Jiaxun Yang (2):
>>                 target/mips: Add loongson-ext lsdc2 group of instructions
>>                 target/mips: Add loongson-ext lswc2 group of instrustions
>>
>>
>>         Also, a spelling mistake in the second title.
>>
>>
>>     Ahh, My bad....
>>
>>
>>                target/mips/translate.c | 437
>>         ++++++++++++++++++++++++++++++++++++++++
>>                1 file changed, 437 insertions(+)
>>
>>              --     2.27.0.rc2
>>
>>
>>     --     - Jiaxun
>>
>>
> --
> - Jiaxun
>

[-- Attachment #2: Type: text/html, Size: 5563 bytes --]

Re: [PATCH v2 0/2] target/mips: Add two groups of loongson-ext instructions

[Jiaxun Yang]

在 2020/6/18 20:00, Aleksandar Markovic 写道:
> 
> 
> среда, 17. јун 2020., Jiaxun Yang <jiaxun.yang@flygoat.com 
> <mailto:jiaxun.yang@flygoat.com>> је написао/ла:
> 
> 
> 
>     在 2020/6/16 22:41, Aleksandar Markovic 写道:
> 
> 
> 
>         уторак, 16. јун 2020., Jiaxun Yang <jiaxun.yang@flygoat.com
>         <mailto:jiaxun.yang@flygoat.com> <mailto:jiaxun.yang@flygoat.com
>         <mailto:jiaxun.yang@flygoat.com>>> је написао/ла:
> 
> 
> 
>              在 2020/6/16 18:38, Aleksandar Markovic 写道:
> 
> 
> 
>                  уторак, 16. јун 2020., Jiaxun Yang
>         <jiaxun.yang@flygoat.com <mailto:jiaxun.yang@flygoat.com>
>                  <mailto:jiaxun.yang@flygoat.com
>         <mailto:jiaxun.yang@flygoat.com>>
>         <mailto:jiaxun.yang@flygoat.com <mailto:jiaxun.yang@flygoat.com>
>                  <mailto:jiaxun.yang@flygoat.com
>         <mailto:jiaxun.yang@flygoat.com>>>> је написао/ла:
> 
>                       This is the sucessor of:
>                       "Basic TCG Loongson-3A1000 Support"
> 
>                       Thanks!
> 
> 
>                  Hi, Jiaxun.
> 
>                  Thanks for providing updated version of the series.
> 
>                  I wonder, given so many "#if defined(TARGET_MIPS64)"
>         lines in
>                  this series, what would be the 32-bit processors that
>         support
>                  Loongson EXT ASE?
> 
> 
>              Loongson GS232 core which can be found in Loongson-1A/B/C
>         should
>              support it.
>              Although I have no intension to work on QEMU support of these
>              processors.
> 
> 
>         ...And, for the sake of accuracy, you nevertheless included the
>         correct implementation (for both 32-bir and 64-bit). That is
>         very good. I would do the same, if I were you.
> 
>         However, there is a problem. We can't upstream (at least not in
>         QEMU for MIPS) anything without the proper documentation.
> 
>         So, please provide the links or attach the supporting files to
>         the cover letter in v2. You already did something similar in
>         some of your previous series and patches. I am perfectly fine
>         with machine translation from Chinese.
> 
>         For example, you need to provide, among other things, docs
>         describing EXT support in GS 232 cores. We can't just make
>         assumptions, or trust your word. These sources of information
>         should be repeated for all versions (v2, v3,...) of the series,
>         in their cover letters.
> 
> 
>     I'll attach necessary information about these instructions in next
>     version, however, there is no public document avilable for GS232 core.
>     That's why I'm not intend to upstream it for now.
> 
>     Should I keep these code as is? Ot just filter all Loongson EXT out
>     for MIPS32.
> 
> 
> Sorry for late response, Jiaxun, I got carried away with other things.
> 
> I am not sure, I simply don't have access to the appropriate info. at 
> this moment, I'd say you can keep (for now) the "ifdef"-ed code for 
> handling 32-bit, since it will never be actually used.
> 
> But, how do you know the code is correct, if there is no doc? How do you 
> know about specifics of 32-bit ext? Is it just guessing, or more than 
> that? Mention the source of information in commit messages, if any. Or  > say this is just a guess.

By guess and experiments on real hardware....

> 
> A short comment should be added about handling for 32-bit just before 
> the main functions that handle Loongson EXT, just like Richard did for 
> those instructions from LMMI that he could not find proper documentation.

Will do.

> 
> Also, can you mention what is achieved by having EXT in QEMU? What 
> Longson-related scenarion would work, that previously (currently) would not?
>

As most applications targeting Loongson processor including Kernel are 
compiled -march=loongson3a CFLAG, without supoorting these instructions 
these applications can never run properly.

I'll mention them in next version of cover letter. Probably tomorrow.

> Thanks for this nice series, and all valuable efforts, hopefully we will 
> resolve documentation issue in comming days or weeks.

Thanks, and wish you all health!

> 
> Aleksandar
> 
> 
> 
>     Thanks.
> 
> 
>         I salute your series, but it needs much more justification.
> 
>         Yours,
>         Aleksandar
> 
> 
>                  Thanks,
>                  Aleksandar
> 
>                       Jiaxun Yang (2):
>                          target/mips: Add loongson-ext lsdc2 group of
>         instructions
>                          target/mips: Add loongson-ext lswc2 group of
>         instrustions
> 
> 
>                  Also, a spelling mistake in the second title.
> 
> 
>              Ahh, My bad....
> 
> 
>                         target/mips/translate.c | 437
>                  ++++++++++++++++++++++++++++++++++++++++
>                         1 file changed, 437 insertions(+)
> 
>                       --     2.27.0.rc2
> 
> 
>              --     - Jiaxun
> 
> 
>     -- 
>     - Jiaxun
> 

-- 
- Jiaxun