All of lore.kernel.org
 help / color / mirror / Atom feed
From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 11/32] drm/i915/dg1: Add fake PCH
Date: Wed, 17 Jun 2020 17:42:19 -0700	[thread overview]
Message-ID: <20200618004240.16263-12-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com>

DG1 has the south engine display on the same PCI device. Ideally we
could use HAS_PCH_SPLIT(), but that macro is misused all across the
code base to rather signify a range of gens. So add a fake one for DG1
to be used where needed.

Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/intel_pch.c | 6 ++++++
 drivers/gpu/drm/i915/intel_pch.h | 4 ++++
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index c668e99eb2e46..6c97192e9ca87 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -188,6 +188,12 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
 {
 	struct pci_dev *pch = NULL;
 
+	/* DG1 has south engine display on the same PCI device */
+	if (IS_DG1(dev_priv)) {
+		dev_priv->pch_type = PCH_DG1;
+		return;
+	}
+
 	/*
 	 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 	 * make graphics device passthrough work easy for VMM, that only
diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
index 3053d1ce398b1..06d2cd50af0b9 100644
--- a/drivers/gpu/drm/i915/intel_pch.h
+++ b/drivers/gpu/drm/i915/intel_pch.h
@@ -26,6 +26,9 @@ enum intel_pch {
 	PCH_JSP,	/* Jasper Lake PCH */
 	PCH_MCC,        /* Mule Creek Canyon PCH */
 	PCH_TGP,	/* Tiger Lake PCH */
+
+	/* Fake PCHs, functionality handled on the same PCI dev */
+	PCH_DG1 = 1024,
 };
 
 #define INTEL_PCH_DEVICE_ID_MASK		0xff80
@@ -56,6 +59,7 @@ enum intel_pch {
 
 #define INTEL_PCH_TYPE(dev_priv)		((dev_priv)->pch_type)
 #define INTEL_PCH_ID(dev_priv)			((dev_priv)->pch_id)
+#define HAS_PCH_DG1(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
 #define HAS_PCH_JSP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
 #define HAS_PCH_MCC(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
 #define HAS_PCH_TGP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2020-06-18  0:42 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-18  0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 01/32] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout Lucas De Marchi
2020-06-23 23:40   ` Souza, Jose
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 02/32] drm/i915/rkl: Add DPLL4 support Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 03/32] drm/i915/rkl: Handle HTI Lucas De Marchi
2020-06-23 23:56   ` Souza, Jose
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 04/32] drm/i915/rkl: Add initial workarounds Lucas De Marchi
2020-06-24  0:13   ` Souza, Jose
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 05/32] drm/i915/rkl: Add Wa_14011224835 for PHY B initialization Lucas De Marchi
2020-06-24  0:07   ` Souza, Jose
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 06/32] drm/i915: Add has_master_unit_irq flag Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 07/32] drm/i915/dg1: add initial DG-1 definitions Lucas De Marchi
2020-06-22  7:51   ` Daniel Vetter
2020-06-22  9:55     ` Jani Nikula
2020-06-23  4:54       ` Dave Airlie
2020-06-23  6:17         ` Daniel Vetter
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 08/32] drm/i915/dg1: Add DG1 PCI IDs Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 09/32] drm/i915/dg1: add support for the master unit interrupt Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 10/32] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming Lucas De Marchi
2020-06-18  0:42 ` Lucas De Marchi [this message]
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 12/32] drm/i915/dg1: Initialize RAWCLK properly Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 13/32] drm/i915/dg1: Define MOCS table for DG1 Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 14/32] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 15/32] drm/i915/dg1: Increase mmio size to 4MB Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 16/32] drm/i915/dg1: Wait for pcode/uncore handshake at startup Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 17/32] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 18/32] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 19/32] drm/i915/dg1: Enable DPLL " Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 20/32] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
2020-06-22 18:35   ` Imre Deak
2020-06-22 20:43     ` Lucas De Marchi
2020-06-22 20:54       ` Imre Deak
2020-06-22 21:59         ` Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 21/32] drm/i915/dg1: invert HPD pins Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 22/32] drm/i915/dg1: gmbus pin mapping Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 23/32] drm/i915/dg1: Enable first 2 ports for DG1 Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 24/32] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 25/32] drm/i915/dg1: Update comp master/slave relationships for PHYs Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 26/32] drm/i915/dg1: Update voltage swing tables for DP Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 27/32] drm/i915/dg1: provide port/phy mapping for vbt Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 28/32] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 29/32] drm/i915/dg1: enable PORT C/D aka D/E Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 30/32] drm/i915/dg1: Load DMC Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 31/32] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
2020-06-18  0:42 ` [Intel-gfx] [PATCH v2 32/32] drm/i915/dg1: DG1 does not support DC6 Lucas De Marchi
2020-06-18  0:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 (rev2) Patchwork
2020-06-18  0:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-06-18  1:18 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200618004240.16263-12-lucas.demarchi@intel.com \
    --to=lucas.demarchi@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.