* [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status
@ 2020-06-18 0:01 Manasi Navare
2020-06-18 0:01 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/dp: Wait or poll with timeout for DDI BUF non idle after enable Manasi Navare
` (4 more replies)
0 siblings, 5 replies; 15+ messages in thread
From: Manasi Navare @ 2020-06-18 0:01 UTC (permalink / raw)
To: intel-gfx
Modify the helper to add a fixed delay or poll with timeout
based on platform specification in bothe enable and disable
cases so check for either Idle bit set (DDI_BUF_CTL is idle
for disable case) or check for Idle bit = 0 (non idle for
DDI BUF enable case)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++++++++++++++---------
1 file changed, 21 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ca7bb2294d2b..e4738c3b6d44 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1182,18 +1182,26 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
}
static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
- enum port port)
+ enum port port, bool idle)
{
- i915_reg_t reg = DDI_BUF_CTL(port);
- int i;
-
- for (i = 0; i < 16; i++) {
- udelay(1);
- if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE)
- return;
+ if (idle) {
+ if (IS_BROXTON(dev_priv))
+ udelay(16);
+ else
+ if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
+ DDI_BUF_IS_IDLE), 16))
+ drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n",
+ port_name(port));
+ } else {
+ if (INTEL_GEN(dev_priv) < 10)
+ udelay(600);
+ else
+ if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
+ DDI_BUF_IS_IDLE), 600))
+ drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n",
+ port_name(port));
}
- drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n",
- port_name(port));
+
}
static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
@@ -1373,7 +1381,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
- intel_wait_ddi_buf_idle(dev_priv, PORT_E);
+ intel_wait_ddi_buf_idle(dev_priv, PORT_E, true);
/* Reset FDI_RX_MISC pwrdn lanes */
temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
@@ -3495,7 +3503,7 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
intel_ddi_disable_fec_state(encoder, crtc_state);
if (wait)
- intel_wait_ddi_buf_idle(dev_priv, port);
+ intel_wait_ddi_buf_idle(dev_priv, port, true);
}
static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
@@ -4004,7 +4012,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
if (wait)
- intel_wait_ddi_buf_idle(dev_priv, port);
+ intel_wait_ddi_buf_idle(dev_priv, port, true);
}
dp_tp_ctl = DP_TP_CTL_ENABLE |
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH v2 2/2] drm/i915/dp: Wait or poll with timeout for DDI BUF non idle after enable
2020-06-18 0:01 [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status Manasi Navare
@ 2020-06-18 0:01 ` Manasi Navare
2020-06-18 0:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 15+ messages in thread
From: Manasi Navare @ 2020-06-18 0:01 UTC (permalink / raw)
To: intel-gfx
Based on the platform, Bspec expects us to wait or poll with
timeout for DDI BUF IDLE bit to be set to 0 (non idle)
afetr enabling DDI_BUF_CTL. Use the existing wait_for_buf_idle()
to do this.
v2:
* Based on platform, fixed delay or poll (Ville)
* Use a helper to do this (Imre, Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index e4738c3b6d44..788c2be8fa73 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4031,7 +4031,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
- udelay(600);
+ intel_wait_ddi_buf_idle(dev_priv, port, false);
}
static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status
2020-06-18 0:01 [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status Manasi Navare
2020-06-18 0:01 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/dp: Wait or poll with timeout for DDI BUF non idle after enable Manasi Navare
@ 2020-06-18 0:31 ` Patchwork
2020-06-18 0:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2020-06-18 0:31 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status
URL : https://patchwork.freedesktop.org/series/78500/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
42dd12bb148b drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status
-:39: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst
#39: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1189:
+ udelay(16);
-:47: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst
#47: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1197:
+ udelay(600);
total: 0 errors, 0 warnings, 2 checks, 60 lines checked
ed2c62fe315d drm/i915/dp: Wait or poll with timeout for DDI BUF non idle after enable
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status
2020-06-18 0:01 [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status Manasi Navare
2020-06-18 0:01 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/dp: Wait or poll with timeout for DDI BUF non idle after enable Manasi Navare
2020-06-18 0:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status Patchwork
@ 2020-06-18 0:51 ` Patchwork
2020-06-18 1:55 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-06-22 15:49 ` [Intel-gfx] [PATCH v2 1/2] " Imre Deak
4 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2020-06-18 0:51 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status
URL : https://patchwork.freedesktop.org/series/78500/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8639 -> Patchwork_17984
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/index.html
Known issues
------------
Here are the changes found in Patchwork_17984 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
* igt@i915_module_load@reload:
- fi-tgl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-u2/igt@i915_module_load@reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-tgl-u2/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-byt-j1900: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-bsw-n3050: [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-bsw-n3050/igt@i915_pm_rpm@module-reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-bsw-n3050/igt@i915_pm_rpm@module-reload.html
- fi-glk-dsi: [PASS][9] -> [DMESG-WARN][10] ([i915#1982])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-glk-dsi/igt@i915_pm_rpm@module-reload.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-glk-dsi/igt@i915_pm_rpm@module-reload.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- fi-icl-u2: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
#### Possible fixes ####
* igt@i915_pm_backlight@basic-brightness:
- fi-whl-u: [DMESG-WARN][13] ([i915#95]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-whl-u/igt@i915_pm_backlight@basic-brightness.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-whl-u/igt@i915_pm_backlight@basic-brightness.html
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt@kms_busy@basic@flip.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-kbl-x1275/igt@kms_busy@basic@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- {fi-tgl-dsi}: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-dsi/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-tgl-dsi/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-icl-guc: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-guc/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-icl-guc/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- {fi-tgl-dsi}: [INCOMPLETE][21] -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-dsi/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-tgl-dsi/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
* igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
- fi-icl-u2: [DMESG-WARN][23] ([i915#1982]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
#### Warnings ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [SKIP][25] ([fdo#109271]) -> [DMESG-FAIL][26] ([i915#62] / [i915#95])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
- fi-kbl-x1275: [DMESG-WARN][27] ([i915#62] / [i915#92]) -> [DMESG-WARN][28] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-x1275: [DMESG-WARN][29] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][30] ([i915#62] / [i915#92]) +2 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (48 -> 41)
------------------------------
Missing (7): fi-ilk-m540 fi-cml-s fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper
Build changes
-------------
* Linux: CI_DRM_8639 -> Patchwork_17984
CI-20190529: 20190529
CI_DRM_8639: 47584e59cf51ec499d68a4cefbaf447448ce2894 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17984: ed2c62fe315d12edf14a8de352d0ccf3c0ea9780 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ed2c62fe315d drm/i915/dp: Wait or poll with timeout for DDI BUF non idle after enable
42dd12bb148b drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status
2020-06-18 0:01 [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status Manasi Navare
` (2 preceding siblings ...)
2020-06-18 0:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-06-18 1:55 ` Patchwork
2020-06-22 15:49 ` [Intel-gfx] [PATCH v2 1/2] " Imre Deak
4 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2020-06-18 1:55 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status
URL : https://patchwork.freedesktop.org/series/78500/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8639_full -> Patchwork_17984_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_17984_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@process:
- shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#93] / [i915#95]) +3 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl7/igt@gem_ctx_persistence@process.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-kbl3/igt@gem_ctx_persistence@process.html
* igt@gem_exec_schedule@implicit-read-write@rcs0:
- shard-snb: [PASS][3] -> [INCOMPLETE][4] ([i915#82]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb2/igt@gem_exec_schedule@implicit-read-write@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-snb5/igt@gem_exec_schedule@implicit-read-write@rcs0.html
* igt@gem_exec_suspend@basic:
- shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-glk4/igt@gem_exec_suspend@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-glk4/igt@gem_exec_suspend@basic.html
* igt@kms_big_fb@linear-64bpp-rotate-180:
- shard-glk: [PASS][7] -> [DMESG-FAIL][8] ([i915#118] / [i915#95])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-glk7/igt@kms_big_fb@linear-64bpp-rotate-180.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-glk8/igt@kms_big_fb@linear-64bpp-rotate-180.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-hsw: [PASS][9] -> [FAIL][10] ([i915#57])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-hsw2/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#1928])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-glk5/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-glk2/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +5 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip_tiling@flip-changes-tiling:
- shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +12 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl7/igt@kms_flip_tiling@flip-changes-tiling.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-skl7/igt@kms_flip_tiling@flip-changes-tiling.html
* igt@kms_flip_tiling@flip-changes-tiling-y:
- shard-apl: [PASS][17] -> [DMESG-FAIL][18] ([i915#95])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl3/igt@kms_flip_tiling@flip-changes-tiling-y.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-apl2/igt@kms_flip_tiling@flip-changes-tiling-y.html
* igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary:
- shard-iclb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [i915#265]) +2 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_properties@connector-properties-legacy:
- shard-iclb: [PASS][23] -> [DMESG-WARN][24] ([i915#1226])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb4/igt@kms_properties@connector-properties-legacy.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-iclb4/igt@kms_properties@connector-properties-legacy.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) +2 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-iclb7/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_vblank@pipe-b-wait-busy-hang:
- shard-apl: [PASS][27] -> [DMESG-WARN][28] ([i915#1982])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl7/igt@kms_vblank@pipe-b-wait-busy-hang.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-apl6/igt@kms_vblank@pipe-b-wait-busy-hang.html
* igt@perf@blocking-parameterized:
- shard-iclb: [PASS][29] -> [FAIL][30] ([i915#1542])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb5/igt@perf@blocking-parameterized.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-iclb7/igt@perf@blocking-parameterized.html
* igt@perf@invalid-create-userspace-config:
- shard-apl: [PASS][31] -> [DMESG-WARN][32] ([i915#95]) +10 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl4/igt@perf@invalid-create-userspace-config.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-apl8/igt@perf@invalid-create-userspace-config.html
#### Possible fixes ####
* igt@gem_exec_gttfill@all:
- shard-glk: [DMESG-WARN][33] ([i915#118] / [i915#95]) -> [PASS][34] +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-glk4/igt@gem_exec_gttfill@all.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-glk8/igt@gem_exec_gttfill@all.html
* igt@gem_tiled_blits@basic:
- shard-snb: [TIMEOUT][35] ([i915#1958]) -> [PASS][36] +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb4/igt@gem_tiled_blits@basic.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-snb1/igt@gem_tiled_blits@basic.html
* igt@gem_tiled_swapping@non-threaded:
- shard-apl: [DMESG-WARN][37] ([i915#183]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl2/igt@gem_tiled_swapping@non-threaded.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-apl3/igt@gem_tiled_swapping@non-threaded.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- shard-apl: [DMESG-WARN][39] ([i915#95]) -> [PASS][40] +9 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl1/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-apl3/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-tglb: [DMESG-WARN][41] ([i915#402]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-tglb5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-tglb2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +6 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl4/igt@kms_flip@flip-vs-suspend@c-dp1.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-kbl1/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
- shard-skl: [FAIL][45] ([i915#1928]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
- shard-kbl: [DMESG-WARN][47] ([i915#93] / [i915#95]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-tglb: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][51] ([i915#1188]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl9/igt@kms_hdr@bpc-switch-suspend.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane@plane-position-covered-pipe-b-planes:
- shard-skl: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] +4 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl6/igt@kms_plane@plane-position-covered-pipe-b-planes.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-skl4/igt@kms_plane@plane-position-covered-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][55] ([fdo#108145] / [i915#265]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_scaling@pipe-a-scaler-with-rotation:
- shard-apl: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl6/igt@kms_plane_scaling@pipe-a-scaler-with-rotation.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-apl4/igt@kms_plane_scaling@pipe-a-scaler-with-rotation.html
* igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping:
- shard-iclb: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb3/igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-iclb6/igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62] +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb7/igt@kms_psr@psr2_cursor_render.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
* igt@perf_pmu@semaphore-busy@rcs0:
- shard-kbl: [FAIL][63] ([i915#1820]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl7/igt@perf_pmu@semaphore-busy@rcs0.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-kbl3/igt@perf_pmu@semaphore-busy@rcs0.html
#### Warnings ####
* igt@gem_exec_reloc@basic-concurrent16:
- shard-snb: [TIMEOUT][65] ([i915#1958]) -> [FAIL][66] ([i915#1930])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb4/igt@gem_exec_reloc@basic-concurrent16.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-snb1/igt@gem_exec_reloc@basic-concurrent16.html
* igt@gen7_exec_parse@chained-batch:
- shard-snb: [TIMEOUT][67] ([i915#1958]) -> [SKIP][68] ([fdo#109271]) +2 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb4/igt@gen7_exec_parse@chained-batch.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-snb1/igt@gen7_exec_parse@chained-batch.html
* igt@kms_color_chamelium@pipe-b-ctm-max:
- shard-snb: [TIMEOUT][69] ([i915#1958]) -> [SKIP][70] ([fdo#109271] / [fdo#111827])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb4/igt@kms_color_chamelium@pipe-b-ctm-max.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-snb1/igt@kms_color_chamelium@pipe-b-ctm-max.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [DMESG-WARN][71] ([i915#93] / [i915#95]) -> [DMESG-WARN][72] ([i915#180] / [i915#93] / [i915#95])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-suspend.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-skl: [FAIL][73] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][74] ([fdo#108145] / [i915#1982])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820
[i915#183]: https://gitlab.freedesktop.org/drm/intel/issues/183
[i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928
[i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930
[i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#57]: https://gitlab.freedesktop.org/drm/intel/issues/57
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_8639 -> Patchwork_17984
CI-20190529: 20190529
CI_DRM_8639: 47584e59cf51ec499d68a4cefbaf447448ce2894 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17984: ed2c62fe315d12edf14a8de352d0ccf3c0ea9780 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status
2020-06-18 0:01 [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status Manasi Navare
` (3 preceding siblings ...)
2020-06-18 1:55 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2020-06-22 15:49 ` Imre Deak
2020-06-22 17:06 ` Ville Syrjälä
2020-06-23 19:42 ` Manasi Navare
4 siblings, 2 replies; 15+ messages in thread
From: Imre Deak @ 2020-06-22 15:49 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Wed, Jun 17, 2020 at 05:01:23PM -0700, Manasi Navare wrote:
> Modify the helper to add a fixed delay or poll with timeout
> based on platform specification in bothe enable and disable
> cases so check for either Idle bit set (DDI_BUF_CTL is idle
> for disable case) or check for Idle bit = 0 (non idle for
> DDI BUF enable case)
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++++++++++++++---------
> 1 file changed, 21 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index ca7bb2294d2b..e4738c3b6d44 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1182,18 +1182,26 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
> }
>
> static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
> - enum port port)
maybe intel_ddi_wait_for_ddi_buf(i915, port, active) ?
> + enum port port, bool idle)
> {
> - i915_reg_t reg = DDI_BUF_CTL(port);
> - int i;
> -
> - for (i = 0; i < 16; i++) {
> - udelay(1);
> - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE)
> - return;
> + if (idle) {
> + if (IS_BROXTON(dev_priv))
> + udelay(16);
> + else
> + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
> + DDI_BUF_IS_IDLE), 16))
> + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n",
> + port_name(port));
> + } else {
> + if (INTEL_GEN(dev_priv) < 10)
> + udelay(600);
> + else
> + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
> + DDI_BUF_IS_IDLE), 600))
> + drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n",
> + port_name(port));
> }
> - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n",
> - port_name(port));
> +
since we can only guarantee a minimum delay or timeout, imo it could be just:
if (BXT && !active || GEN <= 9 && active) {
usleep_range(600, 1000);
return;
}
if (wait_for_us(!(read(BUF_CTL) & IS_IDLE) == active, 600))
drm_err("Port %c: Timeout waiting for DDI BUF to get %s\n",
port, active ? "active" : "idle"));
> }
>
> static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
> @@ -1373,7 +1381,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
> intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
> intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
>
> - intel_wait_ddi_buf_idle(dev_priv, PORT_E);
> + intel_wait_ddi_buf_idle(dev_priv, PORT_E, true);
>
> /* Reset FDI_RX_MISC pwrdn lanes */
> temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
> @@ -3495,7 +3503,7 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
> intel_ddi_disable_fec_state(encoder, crtc_state);
>
> if (wait)
> - intel_wait_ddi_buf_idle(dev_priv, port);
> + intel_wait_ddi_buf_idle(dev_priv, port, true);
> }
>
> static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
> @@ -4004,7 +4012,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
> intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
>
> if (wait)
> - intel_wait_ddi_buf_idle(dev_priv, port);
> + intel_wait_ddi_buf_idle(dev_priv, port, true);
> }
>
> dp_tp_ctl = DP_TP_CTL_ENABLE |
The DSI code could also use the new helper.
> --
> 2.19.1
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status
2020-06-22 15:49 ` [Intel-gfx] [PATCH v2 1/2] " Imre Deak
@ 2020-06-22 17:06 ` Ville Syrjälä
2020-06-23 19:26 ` Manasi Navare
2020-06-23 19:42 ` Manasi Navare
1 sibling, 1 reply; 15+ messages in thread
From: Ville Syrjälä @ 2020-06-22 17:06 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Mon, Jun 22, 2020 at 06:49:26PM +0300, Imre Deak wrote:
> On Wed, Jun 17, 2020 at 05:01:23PM -0700, Manasi Navare wrote:
> > Modify the helper to add a fixed delay or poll with timeout
> > based on platform specification in bothe enable and disable
> > cases so check for either Idle bit set (DDI_BUF_CTL is idle
> > for disable case) or check for Idle bit = 0 (non idle for
> > DDI BUF enable case)
> >
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++++++++++++++---------
> > 1 file changed, 21 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index ca7bb2294d2b..e4738c3b6d44 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -1182,18 +1182,26 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
> > }
> >
> > static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
> > - enum port port)
>
> maybe intel_ddi_wait_for_ddi_buf(i915, port, active) ?
I'd just make it two functions. Avoids that stupid boolean
parameter.
>
> > + enum port port, bool idle)
> > {
> > - i915_reg_t reg = DDI_BUF_CTL(port);
> > - int i;
> > -
> > - for (i = 0; i < 16; i++) {
> > - udelay(1);
> > - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE)
> > - return;
> > + if (idle) {
> > + if (IS_BROXTON(dev_priv))
> > + udelay(16);
> > + else
> > + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
> > + DDI_BUF_IS_IDLE), 16))
> > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n",
> > + port_name(port));
> > + } else {
> > + if (INTEL_GEN(dev_priv) < 10)
> > + udelay(600);
> > + else
> > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
> > + DDI_BUF_IS_IDLE), 600))
> > + drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n",
> > + port_name(port));
> > }
> > - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n",
> > - port_name(port));
> > +
>
> since we can only guarantee a minimum delay or timeout, imo it could be just:
>
> if (BXT && !active || GEN <= 9 && active) {
> usleep_range(600, 1000);
> return;
> }
>
> if (wait_for_us(!(read(BUF_CTL) & IS_IDLE) == active, 600))
> drm_err("Port %c: Timeout waiting for DDI BUF to get %s\n",
> port, active ? "active" : "idle"));
>
>
> > }
> >
> > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
> > @@ -1373,7 +1381,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
> > intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
> > intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
> >
> > - intel_wait_ddi_buf_idle(dev_priv, PORT_E);
> > + intel_wait_ddi_buf_idle(dev_priv, PORT_E, true);
> >
> > /* Reset FDI_RX_MISC pwrdn lanes */
> > temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
> > @@ -3495,7 +3503,7 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
> > intel_ddi_disable_fec_state(encoder, crtc_state);
> >
> > if (wait)
> > - intel_wait_ddi_buf_idle(dev_priv, port);
> > + intel_wait_ddi_buf_idle(dev_priv, port, true);
> > }
> >
> > static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
> > @@ -4004,7 +4012,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
> > intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
> >
> > if (wait)
> > - intel_wait_ddi_buf_idle(dev_priv, port);
> > + intel_wait_ddi_buf_idle(dev_priv, port, true);
> > }
> >
> > dp_tp_ctl = DP_TP_CTL_ENABLE |
>
> The DSI code could also use the new helper.
>
> > --
> > 2.19.1
> >
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status
2020-06-22 17:06 ` Ville Syrjälä
@ 2020-06-23 19:26 ` Manasi Navare
0 siblings, 0 replies; 15+ messages in thread
From: Manasi Navare @ 2020-06-23 19:26 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Jun 22, 2020 at 08:06:51PM +0300, Ville Syrjälä wrote:
> On Mon, Jun 22, 2020 at 06:49:26PM +0300, Imre Deak wrote:
> > On Wed, Jun 17, 2020 at 05:01:23PM -0700, Manasi Navare wrote:
> > > Modify the helper to add a fixed delay or poll with timeout
> > > based on platform specification in bothe enable and disable
> > > cases so check for either Idle bit set (DDI_BUF_CTL is idle
> > > for disable case) or check for Idle bit = 0 (non idle for
> > > DDI BUF enable case)
> > >
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Cc: Imre Deak <imre.deak@intel.com>
> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++++++++++++++---------
> > > 1 file changed, 21 insertions(+), 13 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index ca7bb2294d2b..e4738c3b6d44 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -1182,18 +1182,26 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
> > > }
> > >
> > > static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
> > > - enum port port)
> >
> > maybe intel_ddi_wait_for_ddi_buf(i915, port, active) ?
>
> I'd just make it two functions. Avoids that stupid boolean
> parameter.
Just have 2 functions: 1. intel_ddi_wait_for_ddi_buf_idle()
2. intel_ddi_wait_for_ddi_buf_active or _non_idle()?
Hmm but wouldnt it be more readable if we pass that bool and use
the same function?
Manasi
>
> >
> > > + enum port port, bool idle)
> > > {
> > > - i915_reg_t reg = DDI_BUF_CTL(port);
> > > - int i;
> > > -
> > > - for (i = 0; i < 16; i++) {
> > > - udelay(1);
> > > - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE)
> > > - return;
> > > + if (idle) {
> > > + if (IS_BROXTON(dev_priv))
> > > + udelay(16);
> > > + else
> > > + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
> > > + DDI_BUF_IS_IDLE), 16))
> > > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n",
> > > + port_name(port));
> > > + } else {
> > > + if (INTEL_GEN(dev_priv) < 10)
> > > + udelay(600);
> > > + else
> > > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
> > > + DDI_BUF_IS_IDLE), 600))
> > > + drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n",
> > > + port_name(port));
> > > }
> > > - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n",
> > > - port_name(port));
> > > +
> >
> > since we can only guarantee a minimum delay or timeout, imo it could be just:
> >
> > if (BXT && !active || GEN <= 9 && active) {
> > usleep_range(600, 1000);
> > return;
> > }
> >
> > if (wait_for_us(!(read(BUF_CTL) & IS_IDLE) == active, 600))
> > drm_err("Port %c: Timeout waiting for DDI BUF to get %s\n",
> > port, active ? "active" : "idle"));
> >
> >
> > > }
> > >
> > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
> > > @@ -1373,7 +1381,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
> > > intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
> > > intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
> > >
> > > - intel_wait_ddi_buf_idle(dev_priv, PORT_E);
> > > + intel_wait_ddi_buf_idle(dev_priv, PORT_E, true);
> > >
> > > /* Reset FDI_RX_MISC pwrdn lanes */
> > > temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
> > > @@ -3495,7 +3503,7 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
> > > intel_ddi_disable_fec_state(encoder, crtc_state);
> > >
> > > if (wait)
> > > - intel_wait_ddi_buf_idle(dev_priv, port);
> > > + intel_wait_ddi_buf_idle(dev_priv, port, true);
> > > }
> > >
> > > static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
> > > @@ -4004,7 +4012,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
> > > intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
> > >
> > > if (wait)
> > > - intel_wait_ddi_buf_idle(dev_priv, port);
> > > + intel_wait_ddi_buf_idle(dev_priv, port, true);
> > > }
> > >
> > > dp_tp_ctl = DP_TP_CTL_ENABLE |
> >
> > The DSI code could also use the new helper.
> >
> > > --
> > > 2.19.1
> > >
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status
2020-06-22 15:49 ` [Intel-gfx] [PATCH v2 1/2] " Imre Deak
2020-06-22 17:06 ` Ville Syrjälä
@ 2020-06-23 19:42 ` Manasi Navare
2020-06-23 19:57 ` Imre Deak
1 sibling, 1 reply; 15+ messages in thread
From: Manasi Navare @ 2020-06-23 19:42 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Mon, Jun 22, 2020 at 06:49:26PM +0300, Imre Deak wrote:
> On Wed, Jun 17, 2020 at 05:01:23PM -0700, Manasi Navare wrote:
> > Modify the helper to add a fixed delay or poll with timeout
> > based on platform specification in bothe enable and disable
> > cases so check for either Idle bit set (DDI_BUF_CTL is idle
> > for disable case) or check for Idle bit = 0 (non idle for
> > DDI BUF enable case)
> >
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++++++++++++++---------
> > 1 file changed, 21 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index ca7bb2294d2b..e4738c3b6d44 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -1182,18 +1182,26 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
> > }
> >
> > static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
> > - enum port port)
>
> maybe intel_ddi_wait_for_ddi_buf(i915, port, active) ?
So here you mean active which is true if we are checking during enable for non_idle
and vice versa for disable, active will be false or checking for idel state?
>
> > + enum port port, bool idle)
> > {
> > - i915_reg_t reg = DDI_BUF_CTL(port);
> > - int i;
> > -
> > - for (i = 0; i < 16; i++) {
> > - udelay(1);
> > - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE)
> > - return;
> > + if (idle) {
> > + if (IS_BROXTON(dev_priv))
> > + udelay(16);
> > + else
> > + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
> > + DDI_BUF_IS_IDLE), 16))
> > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n",
> > + port_name(port));
> > + } else {
> > + if (INTEL_GEN(dev_priv) < 10)
> > + udelay(600);
> > + else
> > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
> > + DDI_BUF_IS_IDLE), 600))
> > + drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n",
> > + port_name(port));
> > }
> > - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n",
> > - port_name(port));
> > +
>
> since we can only guarantee a minimum delay or timeout, imo it could be just:
>
> if (BXT && !active || GEN <= 9 && active) {
> usleep_range(600, 1000);
> return;
Didnt quite understand this logic, for BXT & !active which is BXT and idle, it shd be fixed delay of just 16usecs
or if it is !BXT and !active then we wait with a timeout
also for gen <=9 and active, it shd be fixed delay of 600 and greater than or = 10 and active should
be a timeout
Manasi
> }
>
> if (wait_for_us(!(read(BUF_CTL) & IS_IDLE) == active, 600))
> drm_err("Port %c: Timeout waiting for DDI BUF to get %s\n",
> port, active ? "active" : "idle"));
>
>
> > }
> >
> > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
> > @@ -1373,7 +1381,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
> > intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
> > intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
> >
> > - intel_wait_ddi_buf_idle(dev_priv, PORT_E);
> > + intel_wait_ddi_buf_idle(dev_priv, PORT_E, true);
> >
> > /* Reset FDI_RX_MISC pwrdn lanes */
> > temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
> > @@ -3495,7 +3503,7 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
> > intel_ddi_disable_fec_state(encoder, crtc_state);
> >
> > if (wait)
> > - intel_wait_ddi_buf_idle(dev_priv, port);
> > + intel_wait_ddi_buf_idle(dev_priv, port, true);
> > }
> >
> > static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
> > @@ -4004,7 +4012,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
> > intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
> >
> > if (wait)
> > - intel_wait_ddi_buf_idle(dev_priv, port);
> > + intel_wait_ddi_buf_idle(dev_priv, port, true);
> > }
> >
> > dp_tp_ctl = DP_TP_CTL_ENABLE |
>
> The DSI code could also use the new helper.
>
> > --
> > 2.19.1
> >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status
2020-06-23 19:42 ` Manasi Navare
@ 2020-06-23 19:57 ` Imre Deak
2020-06-23 20:32 ` Manasi Navare
0 siblings, 1 reply; 15+ messages in thread
From: Imre Deak @ 2020-06-23 19:57 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Tue, Jun 23, 2020 at 12:42:00PM -0700, Manasi Navare wrote:
> On Mon, Jun 22, 2020 at 06:49:26PM +0300, Imre Deak wrote:
> > On Wed, Jun 17, 2020 at 05:01:23PM -0700, Manasi Navare wrote:
> > > Modify the helper to add a fixed delay or poll with timeout
> > > based on platform specification in bothe enable and disable
> > > cases so check for either Idle bit set (DDI_BUF_CTL is idle
> > > for disable case) or check for Idle bit = 0 (non idle for
> > > DDI BUF enable case)
> > >
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Cc: Imre Deak <imre.deak@intel.com>
> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++++++++++++++---------
> > > 1 file changed, 21 insertions(+), 13 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index ca7bb2294d2b..e4738c3b6d44 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -1182,18 +1182,26 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
> > > }
> > >
> > > static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
> > > - enum port port)
> >
> > maybe intel_ddi_wait_for_ddi_buf(i915, port, active) ?
>
> So here you mean active which is true if we are checking during enable for non_idle
> and vice versa for disable, active will be false or checking for idel state?
Maybe just use Ville's idea with two functions instead.
>
> >
> > > + enum port port, bool idle)
> > > {
> > > - i915_reg_t reg = DDI_BUF_CTL(port);
> > > - int i;
> > > -
> > > - for (i = 0; i < 16; i++) {
> > > - udelay(1);
> > > - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE)
> > > - return;
> > > + if (idle) {
> > > + if (IS_BROXTON(dev_priv))
> > > + udelay(16);
> > > + else
> > > + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
> > > + DDI_BUF_IS_IDLE), 16))
> > > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n",
> > > + port_name(port));
> > > + } else {
> > > + if (INTEL_GEN(dev_priv) < 10)
> > > + udelay(600);
> > > + else
> > > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
> > > + DDI_BUF_IS_IDLE), 600))
> > > + drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n",
> > > + port_name(port));
> > > }
> > > - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n",
> > > - port_name(port));
> > > +
> >
> > since we can only guarantee a minimum delay or timeout, imo it could be just:
> >
> > if (BXT && !active || GEN <= 9 && active) {
> > usleep_range(600, 1000);
> > return;
>
> Didnt quite understand this logic, for BXT & !active which is BXT and
> idle, it shd be fixed delay of just 16usecs
> or if it is !BXT and !active then we wait with a timeout
> also for gen <=9 and active, it shd be fixed delay of 600
> and greater than or = 10 and active should be a timeout
yes, the above would match what I provided. The fixed delay for all
platforms would be a minimum 600usec delay. You can't guarantee that the
delay would be only 16usec in any case, so using 600 usec on BXT too
would be ok.
> Manasi
>
> > }
> >
> > if (wait_for_us(!(read(BUF_CTL) & IS_IDLE) == active, 600))
> > drm_err("Port %c: Timeout waiting for DDI BUF to get %s\n",
> > port, active ? "active" : "idle"));
> >
> >
> > > }
> > >
> > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
> > > @@ -1373,7 +1381,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
> > > intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
> > > intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
> > >
> > > - intel_wait_ddi_buf_idle(dev_priv, PORT_E);
> > > + intel_wait_ddi_buf_idle(dev_priv, PORT_E, true);
> > >
> > > /* Reset FDI_RX_MISC pwrdn lanes */
> > > temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
> > > @@ -3495,7 +3503,7 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
> > > intel_ddi_disable_fec_state(encoder, crtc_state);
> > >
> > > if (wait)
> > > - intel_wait_ddi_buf_idle(dev_priv, port);
> > > + intel_wait_ddi_buf_idle(dev_priv, port, true);
> > > }
> > >
> > > static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
> > > @@ -4004,7 +4012,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
> > > intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
> > >
> > > if (wait)
> > > - intel_wait_ddi_buf_idle(dev_priv, port);
> > > + intel_wait_ddi_buf_idle(dev_priv, port, true);
> > > }
> > >
> > > dp_tp_ctl = DP_TP_CTL_ENABLE |
> >
> > The DSI code could also use the new helper.
> >
> > > --
> > > 2.19.1
> > >
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status
2020-06-23 19:57 ` Imre Deak
@ 2020-06-23 20:32 ` Manasi Navare
2020-06-23 20:50 ` Imre Deak
0 siblings, 1 reply; 15+ messages in thread
From: Manasi Navare @ 2020-06-23 20:32 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Tue, Jun 23, 2020 at 10:57:10PM +0300, Imre Deak wrote:
> On Tue, Jun 23, 2020 at 12:42:00PM -0700, Manasi Navare wrote:
> > On Mon, Jun 22, 2020 at 06:49:26PM +0300, Imre Deak wrote:
> > > On Wed, Jun 17, 2020 at 05:01:23PM -0700, Manasi Navare wrote:
> > > > Modify the helper to add a fixed delay or poll with timeout
> > > > based on platform specification in bothe enable and disable
> > > > cases so check for either Idle bit set (DDI_BUF_CTL is idle
> > > > for disable case) or check for Idle bit = 0 (non idle for
> > > > DDI BUF enable case)
> > > >
> > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > Cc: Imre Deak <imre.deak@intel.com>
> > > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++++++++++++++---------
> > > > 1 file changed, 21 insertions(+), 13 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > index ca7bb2294d2b..e4738c3b6d44 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > @@ -1182,18 +1182,26 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
> > > > }
> > > >
> > > > static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
> > > > - enum port port)
> > >
> > > maybe intel_ddi_wait_for_ddi_buf(i915, port, active) ?
> >
> > So here you mean active which is true if we are checking during enable for non_idle
> > and vice versa for disable, active will be false or checking for idel state?
>
> Maybe just use Ville's idea with two functions instead.
>
> >
> > >
> > > > + enum port port, bool idle)
> > > > {
> > > > - i915_reg_t reg = DDI_BUF_CTL(port);
> > > > - int i;
> > > > -
> > > > - for (i = 0; i < 16; i++) {
> > > > - udelay(1);
> > > > - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE)
> > > > - return;
> > > > + if (idle) {
> > > > + if (IS_BROXTON(dev_priv))
> > > > + udelay(16);
> > > > + else
> > > > + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
> > > > + DDI_BUF_IS_IDLE), 16))
> > > > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n",
> > > > + port_name(port));
> > > > + } else {
> > > > + if (INTEL_GEN(dev_priv) < 10)
> > > > + udelay(600);
> > > > + else
> > > > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
> > > > + DDI_BUF_IS_IDLE), 600))
> > > > + drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n",
> > > > + port_name(port));
> > > > }
> > > > - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n",
> > > > - port_name(port));
> > > > +
> > >
> > > since we can only guarantee a minimum delay or timeout, imo it could be just:
> > >
> > > if (BXT && !active || GEN <= 9 && active) {
> > > usleep_range(600, 1000);
> > > return;
> >
>
> > Didnt quite understand this logic, for BXT & !active which is BXT and
> > idle, it shd be fixed delay of just 16usecs
> > or if it is !BXT and !active then we wait with a timeout
> > also for gen <=9 and active, it shd be fixed delay of 600
> > and greater than or = 10 and active should be a timeout
>
> yes, the above would match what I provided. The fixed delay for all
> platforms would be a minimum 600usec delay. You can't guarantee that the
> delay would be only 16usec in any case, so using 600 usec on BXT too
> would be ok.
still dont quite get it, how is usleep_range (600, 1000) providing a fixed delay?
Now if we split ino 2 functs, one for disable, for that:
if (BXT)
usleep_range(600, 1000)
else
wait_for_us(check if Idle bit set)
so in both functions, for the timeout part we still use the wait_for_us helper right?
Manasi
>
> > Manasi
> >
> > > }
> > >
> > > if (wait_for_us(!(read(BUF_CTL) & IS_IDLE) == active, 600))
> > > drm_err("Port %c: Timeout waiting for DDI BUF to get %s\n",
> > > port, active ? "active" : "idle"));
> > >
> > >
> > > > }
> > > >
> > > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
> > > > @@ -1373,7 +1381,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
> > > > intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
> > > > intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
> > > >
> > > > - intel_wait_ddi_buf_idle(dev_priv, PORT_E);
> > > > + intel_wait_ddi_buf_idle(dev_priv, PORT_E, true);
> > > >
> > > > /* Reset FDI_RX_MISC pwrdn lanes */
> > > > temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
> > > > @@ -3495,7 +3503,7 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
> > > > intel_ddi_disable_fec_state(encoder, crtc_state);
> > > >
> > > > if (wait)
> > > > - intel_wait_ddi_buf_idle(dev_priv, port);
> > > > + intel_wait_ddi_buf_idle(dev_priv, port, true);
> > > > }
> > > >
> > > > static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
> > > > @@ -4004,7 +4012,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
> > > > intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
> > > >
> > > > if (wait)
> > > > - intel_wait_ddi_buf_idle(dev_priv, port);
> > > > + intel_wait_ddi_buf_idle(dev_priv, port, true);
> > > > }
> > > >
> > > > dp_tp_ctl = DP_TP_CTL_ENABLE |
> > >
> > > The DSI code could also use the new helper.
> > >
> > > > --
> > > > 2.19.1
> > > >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status
2020-06-23 20:32 ` Manasi Navare
@ 2020-06-23 20:50 ` Imre Deak
2020-06-23 22:19 ` Manasi Navare
0 siblings, 1 reply; 15+ messages in thread
From: Imre Deak @ 2020-06-23 20:50 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Tue, Jun 23, 2020 at 01:32:50PM -0700, Manasi Navare wrote:
> still dont quite get it, how is usleep_range (600, 1000) providing a fixed delay?
Not sure what you mean. udelay is busy looping, while usleep_range
sleeps instead. How to chose between udelay/usleep_range please read
Documentation/timers/timers-howto.rst
> Now if we split ino 2 functs, one for disable, for that:
>
> if (BXT)
> usleep_range(600, 1000)
> else
> wait_for_us(check if Idle bit set)
>
> so in both functions, for the timeout part we still use the wait_for_us helper right?
with two functions it would get:
intel_ddi_wait_for_ddi_buf_active(i915, port)
{
if (GEN <= 9) {
usleep_range(600, 1000);
return;
}
if (wait_for_us(!(read(BUF_CTL) & IS_IDLE), 600))
drm_err("Port %c: Timeout waiting for DDI BUF to get active\n", port));
}
intel_ddi_wait_for_ddi_buf_idle(i915, port)
{
if (BXT) {
udelay(16);
return;
}
if (wait_for_us(read(BUF_CTL) & IS_IDLE, 600))
drm_err("Port %c: Timeout waiting for DDI BUF to get idle\n", port));
}
--Imre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status
2020-06-23 20:50 ` Imre Deak
@ 2020-06-23 22:19 ` Manasi Navare
2020-06-23 22:50 ` Imre Deak
0 siblings, 1 reply; 15+ messages in thread
From: Manasi Navare @ 2020-06-23 22:19 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Tue, Jun 23, 2020 at 11:50:27PM +0300, Imre Deak wrote:
> On Tue, Jun 23, 2020 at 01:32:50PM -0700, Manasi Navare wrote:
> > still dont quite get it, how is usleep_range (600, 1000) providing a fixed delay?
>
> Not sure what you mean. udelay is busy looping, while usleep_range
> sleeps instead. How to chose between udelay/usleep_range please read
>
> Documentation/timers/timers-howto.rst
>
Yes thanks for pointing me to the documentation.
I guess I thought you were suggesting to use just usleep_range for both
fixed delay and delay with timeout so got confused.
> > Now if we split ino 2 functs, one for disable, for that:
> >
> > if (BXT)
> > usleep_range(600, 1000)
> > else
> > wait_for_us(check if Idle bit set)
> >
> > so in both functions, for the timeout part we still use the wait_for_us helper right?
>
> with two functions it would get:
>
> intel_ddi_wait_for_ddi_buf_active(i915, port)
> {
> if (GEN <= 9) {
> usleep_range(600, 1000);
The doumentation however does suggest that we use udelay to avoid the overhead
of setting up hrtimers needed for usleep_range in atomic context. But then
checkpatch also suggests using usleep_range, why is that?
so still not clear in the context of i915 how we decide where to use jiffie based
delay through udelay and when to use hrtimers (usleep)?
Manasi
> return;
> }
>
> if (wait_for_us(!(read(BUF_CTL) & IS_IDLE), 600))
> drm_err("Port %c: Timeout waiting for DDI BUF to get active\n", port));
> }
>
> intel_ddi_wait_for_ddi_buf_idle(i915, port)
> {
> if (BXT) {
> udelay(16);
> return;
> }
>
> if (wait_for_us(read(BUF_CTL) & IS_IDLE, 600))
> drm_err("Port %c: Timeout waiting for DDI BUF to get idle\n", port));
> }
>
> --Imre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status
2020-06-23 22:19 ` Manasi Navare
@ 2020-06-23 22:50 ` Imre Deak
2020-06-23 22:59 ` Manasi Navare
0 siblings, 1 reply; 15+ messages in thread
From: Imre Deak @ 2020-06-23 22:50 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Tue, Jun 23, 2020 at 03:19:41PM -0700, Manasi Navare wrote:
> On Tue, Jun 23, 2020 at 11:50:27PM +0300, Imre Deak wrote:
> > On Tue, Jun 23, 2020 at 01:32:50PM -0700, Manasi Navare wrote:
> >
> > with two functions it would get:
> >
> > intel_ddi_wait_for_ddi_buf_active(i915, port)
> > {
> > if (GEN <= 9) {
> > usleep_range(600, 1000);
>
> The doumentation however does suggest that we use udelay to avoid the overhead
> of setting up hrtimers needed for usleep_range in atomic context.
The relevant part here is "NON-ATOMIC CONTEXT":
SLEEPING FOR "A FEW" USECS ( < ~10us? ):
* Use udelay
- Why not usleep?
On slower systems, (embedded, OR perhaps a speed-
stepped PC!) the overhead of setting up the hrtimers
for usleep *may* not be worth it. Such an evaluation
will obviously depend on your specific situation, but
it is something to be aware of.
SLEEPING FOR ~USECS OR SMALL MSECS ( 10us - 20ms):
* Use usleep_range
So, can use udelay() for 16usec and should use usleep_range() for 600 usec.
> But then checkpatch also suggests using usleep_range, why is that?
>
> so still not clear in the context of i915 how we decide where to use jiffie based
> delay through udelay and when to use hrtimers (usleep)?
The above document should be followed.
>
> Manasi
>
>
> > return;
> > }
> >
> > if (wait_for_us(!(read(BUF_CTL) & IS_IDLE), 600))
> > drm_err("Port %c: Timeout waiting for DDI BUF to get active\n", port));
> > }
> >
> > intel_ddi_wait_for_ddi_buf_idle(i915, port)
> > {
> > if (BXT) {
> > udelay(16);
> > return;
> > }
> >
> > if (wait_for_us(read(BUF_CTL) & IS_IDLE, 600))
> > drm_err("Port %c: Timeout waiting for DDI BUF to get idle\n", port));
> > }
> >
> > --Imre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status
2020-06-23 22:50 ` Imre Deak
@ 2020-06-23 22:59 ` Manasi Navare
0 siblings, 0 replies; 15+ messages in thread
From: Manasi Navare @ 2020-06-23 22:59 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Wed, Jun 24, 2020 at 01:50:06AM +0300, Imre Deak wrote:
> On Tue, Jun 23, 2020 at 03:19:41PM -0700, Manasi Navare wrote:
> > On Tue, Jun 23, 2020 at 11:50:27PM +0300, Imre Deak wrote:
> > > On Tue, Jun 23, 2020 at 01:32:50PM -0700, Manasi Navare wrote:
> > >
> > > with two functions it would get:
> > >
> > > intel_ddi_wait_for_ddi_buf_active(i915, port)
> > > {
> > > if (GEN <= 9) {
> > > usleep_range(600, 1000);
> >
> > The doumentation however does suggest that we use udelay to avoid the overhead
> > of setting up hrtimers needed for usleep_range in atomic context.
>
> The relevant part here is "NON-ATOMIC CONTEXT":
>
> SLEEPING FOR "A FEW" USECS ( < ~10us? ):
> * Use udelay
>
> - Why not usleep?
> On slower systems, (embedded, OR perhaps a speed-
> stepped PC!) the overhead of setting up the hrtimers
> for usleep *may* not be worth it. Such an evaluation
> will obviously depend on your specific situation, but
> it is something to be aware of.
>
> SLEEPING FOR ~USECS OR SMALL MSECS ( 10us - 20ms):
> * Use usleep_range
>
> So, can use udelay() for 16usec and should use usleep_range() for 600 usec.
Got it thanks will update and send the next rev
Regards
Manasi
>
> > But then checkpatch also suggests using usleep_range, why is that?
> >
> > so still not clear in the context of i915 how we decide where to use jiffie based
> > delay through udelay and when to use hrtimers (usleep)?
>
> The above document should be followed.
>
> >
> > Manasi
> >
> >
> > > return;
> > > }
> > >
> > > if (wait_for_us(!(read(BUF_CTL) & IS_IDLE), 600))
> > > drm_err("Port %c: Timeout waiting for DDI BUF to get active\n", port));
> > > }
> > >
> > > intel_ddi_wait_for_ddi_buf_idle(i915, port)
> > > {
> > > if (BXT) {
> > > udelay(16);
> > > return;
> > > }
> > >
> > > if (wait_for_us(read(BUF_CTL) & IS_IDLE, 600))
> > > drm_err("Port %c: Timeout waiting for DDI BUF to get idle\n", port));
> > > }
> > >
> > > --Imre
_______________________________________________
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2020-06-23 22:57 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-18 0:01 [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status Manasi Navare
2020-06-18 0:01 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/dp: Wait or poll with timeout for DDI BUF non idle after enable Manasi Navare
2020-06-18 0:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status Patchwork
2020-06-18 0:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-06-18 1:55 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-06-22 15:49 ` [Intel-gfx] [PATCH v2 1/2] " Imre Deak
2020-06-22 17:06 ` Ville Syrjälä
2020-06-23 19:26 ` Manasi Navare
2020-06-23 19:42 ` Manasi Navare
2020-06-23 19:57 ` Imre Deak
2020-06-23 20:32 ` Manasi Navare
2020-06-23 20:50 ` Imre Deak
2020-06-23 22:19 ` Manasi Navare
2020-06-23 22:50 ` Imre Deak
2020-06-23 22:59 ` Manasi Navare
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