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From: Lijun Pan <ljp@linux.ibm.com>
To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Cc: Lijun Pan <ljp@linux.ibm.com>,
	richard.henderson@linaro.org, david@gibson.dropbear.id.au
Subject: [PATCH v3 2/8] target/ppc: add byte-reverse br[dwh] instructions
Date: Thu, 25 Jun 2020 12:00:12 -0500	[thread overview]
Message-ID: <20200625170018.64265-3-ljp@linux.ibm.com> (raw)
In-Reply-To: <20200625170018.64265-1-ljp@linux.ibm.com>

POWER ISA 3.1 introduces following byte-reverse instructions:
brd: Byte-Reverse Doubleword X-form
brw: Byte-Reverse Word X-form
brh: Byte-Reverse Halfword X-form

Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
v3: fix the store issue in br[dwh]
    simplify brw implementation
    add "if defined(TARGET_PPC64)"

 target/ppc/translate.c | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4ce3d664b5..6634b38f3a 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6971,7 +6971,45 @@ static void gen_dform3D(DisasContext *ctx)
     return gen_invalid(ctx);
 }
 
+/* brd */
+static void gen_brd(DisasContext *ctx)
+{
+    tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
+}
+
+/* brw */
+static void gen_brw(DisasContext *ctx)
+{
+    tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
+    tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32);
+
+}
+
+/* brh */
+static void gen_brh(DisasContext *ctx)
+{
+    TCGv_i64 t0 = tcg_temp_new_i64();
+    TCGv_i64 t1 = tcg_temp_new_i64();
+    TCGv_i64 t2 = tcg_temp_new_i64();
+
+    tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull);
+    tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8);
+    tcg_gen_and_i64(t2, t1, t0);
+    tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0);
+    tcg_gen_shli_i64(t1, t1, 8);
+    tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2);
+
+    tcg_temp_free_i64(t0);
+    tcg_temp_free_i64(t1);
+    tcg_temp_free_i64(t2);
+}
+
 static opcode_t opcodes[] = {
+#if defined(TARGET_PPC64)
+GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310),
+GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310),
+GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310),
+#endif
 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
-- 
2.23.0



  parent reply	other threads:[~2020-06-25 17:04 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-25 17:00 [PATCH v3 0/8] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
2020-06-25 17:00 ` [PATCH v3 1/8] target/ppc: Introduce Power ISA 3.1 flag Lijun Pan
2020-06-25 17:40   ` Richard Henderson
2020-06-25 21:12     ` Lijun Pan
2020-06-26  3:40       ` Richard Henderson
2020-06-25 17:00 ` Lijun Pan [this message]
2020-06-25 17:42   ` [PATCH v3 2/8] target/ppc: add byte-reverse br[dwh] instructions Richard Henderson
2020-06-25 21:13     ` Lijun Pan
2020-06-25 17:00 ` [PATCH v3 3/8] target/ppc: convert vmuluwm to tcg_gen_gvec_mul Lijun Pan
2020-06-25 17:52   ` Richard Henderson
2020-06-25 17:00 ` [PATCH v3 4/8] target/ppc: add vmulld instruction Lijun Pan
2020-06-25 18:25   ` Richard Henderson
2020-06-25 21:13     ` Lijun Pan
2020-06-26  3:52       ` Richard Henderson
2020-06-25 17:00 ` [PATCH v3 5/8] target/ppc: add vmulh{su}w instructions Lijun Pan
2020-06-25 18:26   ` Richard Henderson
2020-06-25 17:00 ` [PATCH v3 6/8] fix the prototype of muls64/mulu64 Lijun Pan
2020-06-25 18:28   ` Richard Henderson
2020-06-25 17:00 ` [PATCH v3 7/8] target/ppc: add vmulh{su}d instructions Lijun Pan
2020-06-25 18:32   ` Richard Henderson
2020-06-25 17:00 ` [PATCH v3 8/8] target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions Lijun Pan
2020-06-25 18:37   ` Richard Henderson
2020-06-25 21:15     ` Lijun Pan
2020-06-26  3:53       ` Richard Henderson
2020-06-26  4:31         ` David Gibson

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