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From: Richard Henderson <richard.henderson@linaro.org>
To: Lijun Pan <ljp@linux.ibm.com>,
	qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Cc: david@gibson.dropbear.id.au
Subject: Re: [PATCH v3 8/8] target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions
Date: Thu, 25 Jun 2020 11:37:57 -0700	[thread overview]
Message-ID: <4561adf0-2be1-e9c3-49d8-9de8c414ec40@linaro.org> (raw)
In-Reply-To: <20200625170018.64265-9-ljp@linux.ibm.com>

On 6/25/20 10:00 AM, Lijun Pan wrote:
> +#define VDIV_MOD_DO(name, op, element, sign, bit)                       \
> +    void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)       \
> +    {                                                                   \
> +        int i;                                                          \
> +                                                                        \
> +                                                                        \
> +        for (i = 0; i < ARRAY_SIZE(r->element); i++) {                  \
> +            if (unlikely((b->element[i] == 0) ||                        \
> +                (sign &&                                                \
> +                (b->element[i] == UINT##bit##_MAX) &&                   \
> +                (a->element[i] == INT##bit##_MIN))))                    \
> +                continue;                                               \
> +            r->element[i] = a->element[i] op b->element[i];             \
> +        }                                                               \
> +    }

Missing braces for the if.  Extra blank line before the for.

I see that the ISA document says divide-by-zero produces an undefined result,
so leaving the previous contents does seem to be within the letter of the law.

However... Are you able to test what real hardware produces?  It would be nice
(but not required) to match if it is simple to do so.

Whichever way we go with the undefined result, this deserves a comment.


r~


  reply	other threads:[~2020-06-25 18:41 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-25 17:00 [PATCH v3 0/8] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
2020-06-25 17:00 ` [PATCH v3 1/8] target/ppc: Introduce Power ISA 3.1 flag Lijun Pan
2020-06-25 17:40   ` Richard Henderson
2020-06-25 21:12     ` Lijun Pan
2020-06-26  3:40       ` Richard Henderson
2020-06-25 17:00 ` [PATCH v3 2/8] target/ppc: add byte-reverse br[dwh] instructions Lijun Pan
2020-06-25 17:42   ` Richard Henderson
2020-06-25 21:13     ` Lijun Pan
2020-06-25 17:00 ` [PATCH v3 3/8] target/ppc: convert vmuluwm to tcg_gen_gvec_mul Lijun Pan
2020-06-25 17:52   ` Richard Henderson
2020-06-25 17:00 ` [PATCH v3 4/8] target/ppc: add vmulld instruction Lijun Pan
2020-06-25 18:25   ` Richard Henderson
2020-06-25 21:13     ` Lijun Pan
2020-06-26  3:52       ` Richard Henderson
2020-06-25 17:00 ` [PATCH v3 5/8] target/ppc: add vmulh{su}w instructions Lijun Pan
2020-06-25 18:26   ` Richard Henderson
2020-06-25 17:00 ` [PATCH v3 6/8] fix the prototype of muls64/mulu64 Lijun Pan
2020-06-25 18:28   ` Richard Henderson
2020-06-25 17:00 ` [PATCH v3 7/8] target/ppc: add vmulh{su}d instructions Lijun Pan
2020-06-25 18:32   ` Richard Henderson
2020-06-25 17:00 ` [PATCH v3 8/8] target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions Lijun Pan
2020-06-25 18:37   ` Richard Henderson [this message]
2020-06-25 21:15     ` Lijun Pan
2020-06-26  3:53       ` Richard Henderson
2020-06-26  4:31         ` David Gibson

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