* [igt-dev] [PATCH i-g-t v11 0/4] dd api_intel_bb test
@ 2020-06-30 14:50 Zbigniew Kempczyński
2020-06-30 14:50 ` [igt-dev] [PATCH i-g-t v11 1/4] lib/intel_batchbuffer: Extend intel_bb Zbigniew Kempczyński
` (5 more replies)
0 siblings, 6 replies; 7+ messages in thread
From: Zbigniew Kempczyński @ 2020-06-30 14:50 UTC (permalink / raw)
To: igt-dev
Slowly as London bus move toward say goodbye to libdrm in the
rendercopy tests.
Seriously - add some new functions in intel_buf/intel_bb and
verify most of them work properly and doesn't affect gem_gpgpu_fill,
gem_media_fill and i915_pm_sseu which were previously migrated.
v2: fix mapping
v3: skip test where no context are available
v4: cover gens <=4, 5, and 6+ separately
v5: differentiate flush (MI_FLUSH <= gen4 and MI_FLUSH_DW >= gen5)
add intentionally failing test to skip full run
v6: add igt_info to print out ring, remove failing test
v7: fix buffer leak, reset relocation count
v8: ensure bb alignment is modulo 8, fix offsets validation
in api_intel_bb test
v9: remove flush code, change bb constraints to fill fully bb,
adding reference counting (for future tests updates),
adding full-batch test which verifies filling fully bb
v10: synchronizing on bb (executed as async)
v11: skip intel-bb-blit on gen2/3, add api_intel_bb to
fast-feedback
Zbigniew Kempczyński (4):
lib/intel_batchbuffer: Extend intel_bb
lib/intel_bufops: Add new functions and intel_buf fields
tests/api_intel_bb: Add intel_bb API test
intel-ci/fast-feedback: add api_intel_bb tests
lib/intel_batchbuffer.c | 370 +++++++++++++++-
lib/intel_batchbuffer.h | 79 +++-
lib/intel_bufops.c | 135 +++++-
lib/intel_bufops.h | 24 +-
tests/i915/api_intel_bb.c | 613 ++++++++++++++++++++++++++
tests/intel-ci/fast-feedback.testlist | 9 +
tests/meson.build | 1 +
7 files changed, 1196 insertions(+), 35 deletions(-)
create mode 100644 tests/i915/api_intel_bb.c
--
2.26.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 7+ messages in thread
* [igt-dev] [PATCH i-g-t v11 1/4] lib/intel_batchbuffer: Extend intel_bb
2020-06-30 14:50 [igt-dev] [PATCH i-g-t v11 0/4] dd api_intel_bb test Zbigniew Kempczyński
@ 2020-06-30 14:50 ` Zbigniew Kempczyński
2020-06-30 14:50 ` [igt-dev] [PATCH i-g-t v11 2/4] lib/intel_bufops: Add new functions and intel_buf fields Zbigniew Kempczyński
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Zbigniew Kempczyński @ 2020-06-30 14:50 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
As we're going toward removing libdrm from rendercopy tests some
additional code in intel_bb is required. So add new functions
and fix memory issues in the reset path.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_batchbuffer.c | 370 +++++++++++++++++++++++++++++++++++++---
lib/intel_batchbuffer.h | 79 ++++++++-
2 files changed, 424 insertions(+), 25 deletions(-)
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 2a882627..bd792331 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -1045,8 +1045,6 @@ void igt_blitter_fast_copy(struct intel_batchbuffer *batch,
intel_batchbuffer_flush(batch);
}
-#undef CHECK_RANGE
-
/**
* igt_get_render_copyfunc:
* @devid: pci device id
@@ -1211,7 +1209,8 @@ static void __reallocate_objects(struct intel_bb *ibb)
*
* Pointer the intel_bb, asserts on failure.
*/
-struct intel_bb *intel_bb_create(int i915, uint32_t size)
+static struct intel_bb *
+__intel_bb_create(int i915, uint32_t size, bool do_relocs)
{
struct intel_bb *ibb = calloc(1, sizeof(*ibb));
uint64_t gtt_size;
@@ -1221,6 +1220,7 @@ struct intel_bb *intel_bb_create(int i915, uint32_t size)
ibb->i915 = i915;
ibb->devid = intel_get_drm_devid(i915);
ibb->gen = intel_gen(ibb->devid);
+ ibb->enforce_relocs = do_relocs;
ibb->handle = gem_create(i915, size);
ibb->size = size;
ibb->batch = calloc(1, size);
@@ -1238,9 +1238,42 @@ struct intel_bb *intel_bb_create(int i915, uint32_t size)
__reallocate_objects(ibb);
intel_bb_add_object(ibb, ibb->handle, 0, false);
+ ibb->refcount = 1;
+
return ibb;
}
+/**
+ * intel_bb_create:
+ * @i915: drm fd
+ * @size: size of the batchbuffer
+ *
+ * Returns:
+ *
+ * Pointer the intel_bb, asserts on failure.
+ */
+struct intel_bb *intel_bb_create(int i915, uint32_t size)
+{
+ return __intel_bb_create(i915, size, false);
+}
+
+/**
+ * intel_bb_create_with_relocs:
+ * @i915: drm fd
+ * @size: size of the batchbuffer
+ *
+ * Disable passing or randomizing addresses. This will lead to relocations
+ * when objects are not previously pinned.
+ *
+ * Returns:
+ *
+ * Pointer the intel_bb, asserts on failure.
+ */
+struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size)
+{
+ return __intel_bb_create(i915, size, true);
+}
+
/*
* tdestroy() calls free function for each node, but we spread tree
* on objects array, so do nothing.
@@ -1250,24 +1283,32 @@ static void __do_nothing(void *node)
(void) node;
}
-static void __intel_bb_destroy_objects(struct intel_bb *ibb)
+static void __intel_bb_destroy_relocations(struct intel_bb *ibb)
{
uint32_t i;
/* Free relocations */
- for (i = 0; i < ibb->num_objects; i++)
+ for (i = 0; i < ibb->num_objects; i++) {
free(from_user_pointer(ibb->objects[i].relocs_ptr));
+ ibb->objects[i].relocs_ptr = to_user_pointer(NULL);
+ ibb->objects[i].relocation_count = 0;
+ }
- free(ibb->objects);
- tdestroy(ibb->root, __do_nothing);
+ ibb->relocs = NULL;
+ ibb->num_relocs = 0;
+ ibb->allocated_relocs = 0;
+}
+static void __intel_bb_destroy_objects(struct intel_bb *ibb)
+{
+ free(ibb->objects);
ibb->objects = NULL;
+
+ tdestroy(ibb->root, __do_nothing);
ibb->root = NULL;
+
ibb->num_objects = 0;
- ibb->num_relocs = 0;
ibb->allocated_objects = 0;
- ibb->allocated_relocs = 0;
- ibb->ptr = ibb->batch;
}
/**
@@ -1280,6 +1321,10 @@ void intel_bb_destroy(struct intel_bb *ibb)
{
igt_assert(ibb);
+ ibb->refcount--;
+ igt_assert_f(ibb->refcount == 0, "Trying to destroy referenced bb!");
+
+ __intel_bb_destroy_relocations(ibb);
__intel_bb_destroy_objects(ibb);
gem_close(ibb->i915, ibb->handle);
@@ -1291,10 +1336,19 @@ void intel_bb_destroy(struct intel_bb *ibb)
* @ibb: pointer to intel_bb
* @purge_objects_cache: if true destroy internal execobj and relocs + cache
*
- * Recreate batch bo.
+ * Recreate batch bo when there's no additional reference.
*/
void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
{
+ if (purge_objects_cache && ibb->refcount > 1)
+ igt_warn("Cannot purge objects cache on bb, refcount > 1!");
+
+ /* Someone keeps reference, just exit */
+ if (ibb->refcount > 1)
+ return;
+
+ __intel_bb_destroy_relocations(ibb);
+
if (purge_objects_cache) {
__intel_bb_destroy_objects(ibb);
__reallocate_objects(ibb);
@@ -1305,6 +1359,61 @@ void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
intel_bb_add_object(ibb, ibb->handle, 0, false);
ibb->ptr = ibb->batch;
+ memset(ibb->batch, 0, ibb->size);
+}
+
+/*
+ * intel_bb_sync:
+ * @ibb: pointer to intel_bb
+ *
+ * Waits for bb completion.
+ */
+void intel_bb_sync(struct intel_bb *ibb)
+{
+ gem_sync(ibb->i915, ibb->handle);
+}
+
+/*
+ * intel_bb_print:
+ * @ibb: pointer to intel_bb
+ *
+ * Prints batch to stdout.
+ */
+void intel_bb_print(struct intel_bb *ibb)
+{
+ igt_info("drm fd: %d, gen: %d, devid: %u, debug: %d\n",
+ ibb->i915, ibb->gen, ibb->devid, ibb->debug);
+ igt_info("handle: %u, size: %u, batch: %p, ptr: %p\n",
+ ibb->handle, ibb->size, ibb->batch, ibb->ptr);
+ igt_info("prng: %u, gtt_size: %" PRIu64 ", supports 48bit: %d\n",
+ ibb->prng, ibb->gtt_size, ibb->supports_48b_address);
+ igt_info("ctx: %u\n", ibb->ctx);
+ igt_info("root: %p\n", ibb->root);
+ igt_info("objects: %p, num_objects: %u, allocated obj: %u\n",
+ ibb->objects, ibb->num_objects, ibb->allocated_objects);
+ igt_info("relocs: %p, num_relocs: %u, allocated_relocs: %u\n----\n",
+ ibb->relocs, ibb->num_relocs, ibb->allocated_relocs);
+}
+
+/*
+ * intel_bb_dump:
+ * @ibb: pointer to intel_bb
+ * @filename: name to which write bb
+ *
+ * Dump batch bo to file.
+ */
+void intel_bb_dump(struct intel_bb *ibb, const char *filename)
+{
+ FILE *out;
+ void *ptr;
+
+ ptr = gem_mmap__device_coherent(ibb->i915, ibb->handle, 0, ibb->size,
+ PROT_READ);
+ out = fopen(filename, "wb");
+ igt_assert(out);
+ fwrite(ptr, ibb->size, 1, out);
+ fclose(out);
+ munmap(ptr, ibb->size);
}
/**
@@ -1361,7 +1470,9 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle,
object = *found;
/* Assign address once */
- if (object->offset == 0) {
+ if (ibb->enforce_relocs)
+ object->offset = 0;
+ else if (object->offset == 0) {
if (offset) {
object->offset = offset;
} else {
@@ -1382,6 +1493,23 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle,
return object;
}
+static bool intel_bb_object_set_fence(struct intel_bb *ibb, uint32_t handle)
+{
+ struct drm_i915_gem_exec_object2 object = { .handle = handle };
+ struct drm_i915_gem_exec_object2 **found;
+
+ found = tfind((void *) &object, &ibb->root, __compare_objects);
+ if (!found) {
+ igt_warn("Trying to set fence on not found handle: %u\n",
+ handle);
+ return false;
+ }
+
+ (*found)->flags |= EXEC_OBJECT_NEEDS_FENCE;
+
+ return true;
+}
+
/*
* intel_bb_add_reloc:
* @ibb: pointer to intel_bb
@@ -1431,9 +1559,10 @@ static uint64_t intel_bb_add_reloc(struct intel_bb *ibb,
igt_debug("add reloc: handle: %u, r/w: 0x%x/0x%x, "
"delta: 0x%" PRIx64 ", "
"offset: 0x%" PRIx64 ", "
- "poffset: 0x%" PRIx64 "\n",
+ "poffset: %p\n",
handle, read_domains, write_domain,
- delta, offset, presumed_offset);
+ delta, offset,
+ from_user_pointer(relocs[i].presumed_offset));
return object->offset;
}
@@ -1479,6 +1608,23 @@ uint64_t intel_bb_emit_reloc(struct intel_bb *ibb,
return address;
}
+uint64_t intel_bb_emit_reloc_fenced(struct intel_bb *ibb,
+ uint32_t handle,
+ uint32_t read_domains,
+ uint32_t write_domain,
+ uint64_t delta,
+ uint64_t presumed_offset)
+{
+ uint64_t address;
+
+ address = intel_bb_emit_reloc(ibb, handle, read_domains, write_domain,
+ delta, presumed_offset);
+
+ intel_bb_object_set_fence(ibb, handle);
+
+ return address;
+}
+
/**
* intel_bb_offset_reloc:
* @ibb: pointer to intel_bb
@@ -1509,7 +1655,22 @@ uint64_t intel_bb_offset_reloc(struct intel_bb *ibb,
0, offset, presumed_offset);
}
-static void intel_bb_dump_execbuf(struct drm_i915_gem_execbuffer2 *execbuf)
+uint64_t intel_bb_offset_reloc_with_delta(struct intel_bb *ibb,
+ uint32_t handle,
+ uint32_t read_domains,
+ uint32_t write_domain,
+ uint32_t delta,
+ uint32_t offset,
+ uint64_t presumed_offset)
+{
+ igt_assert(ibb);
+
+ return intel_bb_add_reloc(ibb, handle, read_domains, write_domain,
+ delta, offset, presumed_offset);
+}
+
+static void intel_bb_dump_execbuf(struct intel_bb *ibb,
+ struct drm_i915_gem_execbuffer2 *execbuf)
{
struct drm_i915_gem_exec_object2 *objects;
struct drm_i915_gem_relocation_entry *relocs, *reloc;
@@ -1535,7 +1696,8 @@ static void intel_bb_dump_execbuf(struct drm_i915_gem_execbuffer2 *execbuf)
i, objects->handle, objects->relocation_count,
relocs,
objects->alignment,
- objects->offset, objects->flags,
+ objects->offset & (ibb->gtt_size - 1),
+ objects->flags,
objects->rsvd1, objects->rsvd2);
if (objects->relocation_count) {
igt_info("\texecbuf relocs:\n");
@@ -1548,7 +1710,7 @@ static void intel_bb_dump_execbuf(struct drm_i915_gem_execbuffer2 *execbuf)
"write_domain: 0x%x\n",
j, reloc->target_handle,
reloc->offset, reloc->delta,
- reloc->presumed_offset,
+ reloc->presumed_offset & (ibb->gtt_size - 1),
reloc->read_domains,
reloc->write_domain);
}
@@ -1609,14 +1771,16 @@ int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
execbuf.flags = flags | I915_EXEC_BATCH_FIRST;
ret = __gem_execbuf(ibb->i915, &execbuf);
- if (ret)
+ if (ret) {
+ intel_bb_dump_execbuf(ibb, &execbuf);
return ret;
+ }
if (sync || ibb->debug)
gem_sync(ibb->i915, ibb->handle);
if (ibb->debug) {
- intel_bb_dump_execbuf(&execbuf);
+ intel_bb_dump_execbuf(ibb, &execbuf);
if (intel_bb_debug_tree) {
igt_info("\nTree:\n");
twalk(ibb->root, print_node);
@@ -1679,7 +1843,7 @@ uint64_t intel_bb_get_object_offset(struct intel_bb *ibb, uint32_t handle)
if (!found)
return 0;
- return (*found)->offset;
+ return (*found)->offset & (ibb->gtt_size - 1);
}
/**
@@ -1706,8 +1870,172 @@ bool intel_bb_object_offset_to_buf(struct intel_bb *ibb, struct intel_buf *buf)
return false;
}
- buf->addr.offset = (*found)->offset;
+ buf->addr.offset = (*found)->offset & (ibb->gtt_size - 1);
buf->addr.ctx = ibb->ctx;
return true;
}
+
+/*
+ * intel_bb_emit_bbe:
+ * @ibb: batchbuffer
+ *
+ * Outputs MI_BATCH_BUFFER_END and ensures batch is properly aligned.
+ */
+uint32_t intel_bb_emit_bbe(struct intel_bb *ibb)
+{
+ /* Mark the end of the buffer. */
+ intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+ intel_bb_ptr_align(ibb, 8);
+
+ return intel_bb_offset(ibb);
+}
+
+/*
+ * intel_bb_flush_with_context_ring:
+ * @ibb: batchbuffer
+ * @ctx: context id
+ * @ring: ring
+ *
+ * Submits the batch for execution on the @ring engine with the supplied
+ * hardware context @ctx.
+ */
+static void intel_bb_flush_with_context_ring(struct intel_bb *ibb,
+ uint32_t ctx, uint32_t ring)
+{
+ intel_bb_exec_with_context(ibb, intel_bb_offset(ibb), ctx,
+ ring | I915_EXEC_NO_RELOC,
+ false);
+ intel_bb_reset(ibb, false);
+}
+
+void intel_bb_flush_render(struct intel_bb *ibb)
+{
+ uint32_t ring = I915_EXEC_RENDER;
+
+ intel_bb_flush_with_context_ring(ibb, ibb->ctx, ring);
+}
+
+void intel_bb_flush_blit(struct intel_bb *ibb)
+{
+ uint32_t ring = I915_EXEC_DEFAULT;
+
+ if (HAS_BLT_RING(ibb->devid))
+ ring = I915_EXEC_BLT;
+
+ intel_bb_flush_with_context_ring(ibb, ibb->ctx, ring);
+}
+
+uint32_t intel_bb_copy_data(struct intel_bb *ibb,
+ const void *data, unsigned int bytes,
+ uint32_t align)
+{
+ uint32_t *subdata, offset;
+
+ igt_assert((bytes & 3) == 0);
+
+ intel_bb_ptr_align(ibb, align);
+ offset = intel_bb_offset(ibb);
+ igt_assert(offset + bytes < ibb->size);
+
+ subdata = intel_bb_ptr(ibb);
+ memcpy(subdata, data, bytes);
+ intel_bb_ptr_add(ibb, bytes);
+
+ return offset;
+}
+
+void intel_bb_blit_start(struct intel_bb *ibb, uint32_t flags)
+{
+ intel_bb_out(ibb, XY_SRC_COPY_BLT_CMD |
+ XY_SRC_COPY_BLT_WRITE_ALPHA |
+ XY_SRC_COPY_BLT_WRITE_RGB |
+ (flags) |
+ (6 + 2*(ibb->gen >= 8)));
+}
+
+void intel_bb_emit_blt_copy(struct intel_bb *ibb,
+ struct intel_buf *src,
+ int src_x1, int src_y1, int src_pitch,
+ struct intel_buf *dst,
+ int dst_x1, int dst_y1, int dst_pitch,
+ int width, int height, int bpp)
+{
+ const int gen = ibb->gen;
+ uint32_t cmd_bits = 0;
+ uint32_t br13_bits;
+
+ igt_assert(bpp*(src_x1 + width) <= 8*src_pitch);
+ igt_assert(bpp*(dst_x1 + width) <= 8*dst_pitch);
+ igt_assert(src_pitch * (src_y1 + height) <= src->size);
+ igt_assert(dst_pitch * (dst_y1 + height) <= dst->size);
+
+ if (gen >= 4 && src->tiling != I915_TILING_NONE) {
+ src_pitch /= 4;
+ cmd_bits |= XY_SRC_COPY_BLT_SRC_TILED;
+ }
+
+ if (gen >= 4 && dst->tiling != I915_TILING_NONE) {
+ dst_pitch /= 4;
+ cmd_bits |= XY_SRC_COPY_BLT_DST_TILED;
+ }
+
+ CHECK_RANGE(src_x1); CHECK_RANGE(src_y1);
+ CHECK_RANGE(dst_x1); CHECK_RANGE(dst_y1);
+ CHECK_RANGE(width); CHECK_RANGE(height);
+ CHECK_RANGE(src_x1 + width); CHECK_RANGE(src_y1 + height);
+ CHECK_RANGE(dst_x1 + width); CHECK_RANGE(dst_y1 + height);
+ CHECK_RANGE(src_pitch); CHECK_RANGE(dst_pitch);
+
+ br13_bits = 0;
+ switch (bpp) {
+ case 8:
+ break;
+ case 16: /* supporting only RGB565, not ARGB1555 */
+ br13_bits |= 1 << 24;
+ break;
+ case 32:
+ br13_bits |= 3 << 24;
+ cmd_bits |= XY_SRC_COPY_BLT_WRITE_ALPHA |
+ XY_SRC_COPY_BLT_WRITE_RGB;
+ break;
+ default:
+ igt_fail(IGT_EXIT_FAILURE);
+ }
+
+ intel_bb_blit_start(ibb, cmd_bits);
+ intel_bb_out(ibb, (br13_bits) |
+ (0xcc << 16) | /* copy ROP */
+ dst_pitch);
+ intel_bb_out(ibb, (dst_y1 << 16) | dst_x1); /* dst x1,y1 */
+ intel_bb_out(ibb, ((dst_y1 + height) << 16) | (dst_x1 + width)); /* dst x2,y2 */
+ intel_bb_emit_reloc_fenced(ibb, dst->handle,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ 0, dst->addr.offset);
+ intel_bb_out(ibb, (src_y1 << 16) | src_x1); /* src x1,y1 */
+ intel_bb_out(ibb, src_pitch);
+ intel_bb_emit_reloc_fenced(ibb, src->handle,
+ I915_GEM_DOMAIN_RENDER, 0,
+ 0, src->addr.offset);
+
+ if (gen >= 6 && src->handle == dst->handle) {
+ intel_bb_out(ibb, XY_SETUP_CLIP_BLT_CMD);
+ intel_bb_out(ibb, 0);
+ intel_bb_out(ibb, 0);
+ }
+
+}
+
+void intel_bb_blt_copy(struct intel_bb *ibb,
+ struct intel_buf *src,
+ int src_x1, int src_y1, int src_pitch,
+ struct intel_buf *dst,
+ int dst_x1, int dst_y1, int dst_pitch,
+ int width, int height, int bpp)
+{
+ intel_bb_emit_blt_copy(ibb, src, src_x1, src_y1, src_pitch,
+ dst, dst_x1, dst_y1, dst_pitch,
+ width, height, bpp);
+ intel_bb_emit_bbe(ibb);
+ intel_bb_flush_blit(ibb);
+}
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 0649fc22..5c36a9aa 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -433,6 +433,7 @@ struct intel_bb {
int i915;
int gen;
bool debug;
+ bool enforce_relocs;
uint32_t devid;
uint32_t handle;
uint32_t size;
@@ -454,12 +455,34 @@ struct intel_bb {
struct drm_i915_gem_relocation_entry *relocs;
uint32_t num_relocs;
uint32_t allocated_relocs;
+
+ /*
+ * BO recreate in reset path only when refcount == 0
+ * Currently we don't need to use atomics because intel_bb
+ * is not thread-safe.
+ */
+ int32_t refcount;
};
struct intel_bb *intel_bb_create(int i915, uint32_t size);
-
+struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size);
void intel_bb_destroy(struct intel_bb *ibb);
+
+static inline void intel_bb_ref(struct intel_bb *ibb)
+{
+ ibb->refcount++;
+}
+
+static inline void intel_bb_unref(struct intel_bb *ibb)
+{
+ igt_assert_f(ibb->refcount > 0, "intel_bb refcount is 0!");
+ ibb->refcount--;
+}
+
void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache);
+void intel_bb_sync(struct intel_bb *ibb);
+void intel_bb_print(struct intel_bb *ibb);
+void intel_bb_dump(struct intel_bb *ibb, const char *filename);
void intel_bb_set_debug(struct intel_bb *ibb, bool debug);
static inline uint32_t intel_bb_offset(struct intel_bb *ibb)
@@ -471,7 +494,7 @@ static inline void intel_bb_ptr_set(struct intel_bb *ibb, uint32_t offset)
{
ibb->ptr = (void *) ((uint8_t *) ibb->batch + offset);
- igt_assert(intel_bb_offset(ibb) < ibb->size);
+ igt_assert(intel_bb_offset(ibb) <= ibb->size);
}
static inline void intel_bb_ptr_add(struct intel_bb *ibb, uint32_t offset)
@@ -479,10 +502,22 @@ static inline void intel_bb_ptr_add(struct intel_bb *ibb, uint32_t offset)
intel_bb_ptr_set(ibb, intel_bb_offset(ibb) + offset);
}
-static inline void intel_bb_ptr_align(struct intel_bb *ibb,
+static inline uint32_t intel_bb_ptr_add_return_prev_offset(struct intel_bb *ibb,
+ uint32_t offset)
+{
+ uint32_t previous_offset = intel_bb_offset(ibb);
+
+ intel_bb_ptr_set(ibb, previous_offset + offset);
+
+ return previous_offset;
+}
+
+static inline void *intel_bb_ptr_align(struct intel_bb *ibb,
uint32_t alignment)
{
intel_bb_ptr_set(ibb, ALIGN(intel_bb_offset(ibb), alignment));
+
+ return (void *) ibb->ptr;
}
static inline void *intel_bb_ptr(struct intel_bb *ibb)
@@ -495,7 +530,7 @@ static inline void intel_bb_out(struct intel_bb *ibb, uint32_t dword)
*ibb->ptr = dword;
ibb->ptr++;
- igt_assert(intel_bb_offset(ibb) < ibb->size);
+ igt_assert(intel_bb_offset(ibb) <= ibb->size);
}
@@ -510,6 +545,13 @@ uint64_t intel_bb_emit_reloc(struct intel_bb *ibb,
uint64_t delta,
uint64_t presumed_offset);
+uint64_t intel_bb_emit_reloc_fenced(struct intel_bb *ibb,
+ uint32_t handle,
+ uint32_t read_domains,
+ uint32_t write_domain,
+ uint64_t delta,
+ uint64_t presumed_offset);
+
uint64_t intel_bb_offset_reloc(struct intel_bb *ibb,
uint32_t handle,
uint32_t read_domains,
@@ -517,6 +559,14 @@ uint64_t intel_bb_offset_reloc(struct intel_bb *ibb,
uint32_t offset,
uint64_t presumed_offset);
+uint64_t intel_bb_offset_reloc_with_delta(struct intel_bb *ibb,
+ uint32_t handle,
+ uint32_t read_domains,
+ uint32_t write_domain,
+ uint32_t delta,
+ uint32_t offset,
+ uint64_t presumed_offset);
+
int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
uint32_t ctx, uint64_t flags, bool sync);
@@ -529,4 +579,25 @@ void intel_bb_exec_with_context(struct intel_bb *ibb, uint32_t end_offset,
uint64_t intel_bb_get_object_offset(struct intel_bb *ibb, uint32_t handle);
bool intel_bb_object_offset_to_buf(struct intel_bb *ibb, struct intel_buf *buf);
+uint32_t intel_bb_emit_bbe(struct intel_bb *ibb);
+void intel_bb_flush_render(struct intel_bb *ibb);
+void intel_bb_flush_blit(struct intel_bb *ibb);
+
+uint32_t intel_bb_copy_data(struct intel_bb *ibb,
+ const void *data, unsigned int bytes,
+ uint32_t align);
+
+void intel_bb_blit_start(struct intel_bb *ibb, uint32_t flags);
+void intel_bb_emit_blt_copy(struct intel_bb *ibb,
+ struct intel_buf *src,
+ int src_x1, int src_y1, int src_pitch,
+ struct intel_buf *dst,
+ int dst_x1, int dst_y1, int dst_pitch,
+ int width, int height, int bpp);
+void intel_bb_blt_copy(struct intel_bb *ibb,
+ struct intel_buf *src,
+ int src_x1, int src_y1, int src_pitch,
+ struct intel_buf *dst,
+ int dst_x1, int dst_y1, int dst_pitch,
+ int width, int height, int bpp);
#endif
--
2.26.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [igt-dev] [PATCH i-g-t v11 2/4] lib/intel_bufops: Add new functions and intel_buf fields
2020-06-30 14:50 [igt-dev] [PATCH i-g-t v11 0/4] dd api_intel_bb test Zbigniew Kempczyński
2020-06-30 14:50 ` [igt-dev] [PATCH i-g-t v11 1/4] lib/intel_batchbuffer: Extend intel_bb Zbigniew Kempczyński
@ 2020-06-30 14:50 ` Zbigniew Kempczyński
2020-06-30 14:50 ` [igt-dev] [PATCH i-g-t v11 3/4] tests/api_intel_bb: Add intel_bb API test Zbigniew Kempczyński
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Zbigniew Kempczyński @ 2020-06-30 14:50 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
This is minor step toward removing libdrm from rendercopy. Lets
add new functions and structure fields to verify we don't introduce
regressions in already migrated code.
Some utility functions - write buf/aux (ccs) to png were added.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_bufops.c | 135 ++++++++++++++++++++++++++++++++++++++++++---
lib/intel_bufops.h | 24 +++++++-
2 files changed, 149 insertions(+), 10 deletions(-)
diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
index 0337b638..13d01396 100644
--- a/lib/intel_bufops.c
+++ b/lib/intel_bufops.c
@@ -23,6 +23,7 @@
*/
#include <sys/ioctl.h>
+#include <cairo.h>
#include "igt.h"
#include "igt_x86.h"
#include "intel_bufops.h"
@@ -174,10 +175,14 @@ static bool __get_tiling(int fd, uint32_t handle, uint32_t *tiling,
}
static int __set_tiling(int fd, uint32_t handle, uint32_t tiling,
- uint32_t stride)
+ uint32_t stride,
+ uint32_t *ret_tiling, uint32_t *ret_swizzle)
{
+ struct drm_i915_gem_set_tiling st;
+
+ memset(&st, 0, sizeof(st));
do {
- struct drm_i915_gem_set_tiling st;
+
int err;
st.handle = handle;
@@ -188,13 +193,22 @@ static int __set_tiling(int fd, uint32_t handle, uint32_t tiling,
if (ioctl(fd, DRM_IOCTL_I915_GEM_SET_TILING, &st))
err = -errno;
errno = 0;
- if (err != -EINTR)
+ if (err != -EINTR) {
+ if (ret_tiling)
+ *ret_tiling = st.tiling_mode;
+
+ if (ret_swizzle)
+ *ret_swizzle = st.swizzle_mode;
+
return err;
+ }
} while (1);
}
static void set_hw_tiled(struct buf_ops *bops, struct intel_buf *buf)
{
+ uint32_t ret_tiling, ret_swizzle;
+
if (buf->tiling != I915_TILING_X && buf->tiling != I915_TILING_Y)
return;
@@ -202,8 +216,12 @@ static void set_hw_tiled(struct buf_ops *bops, struct intel_buf *buf)
return;
igt_assert_eq(__set_tiling(bops->fd,
- buf->handle, buf->tiling, buf->stride),
+ buf->handle, buf->tiling, buf->stride,
+ &ret_tiling, &ret_swizzle),
0);
+
+ igt_assert(ret_tiling == buf->tiling);
+ buf->swizzle_mode = ret_swizzle;
}
static unsigned long swizzle_bit(unsigned int bit, unsigned long offset)
@@ -697,7 +715,6 @@ static void __intel_buf_init(struct buf_ops *bops,
igt_require(bops->intel_gen >= 9);
igt_assert(req_tiling == I915_TILING_Y ||
req_tiling == I915_TILING_Yf);
-
/*
* On GEN12+ we align the main surface to 4 * 4 main surface
* tiles, which is 64kB. These 16 tiles are mapped by 4 AUX
@@ -724,7 +741,6 @@ static void __intel_buf_init(struct buf_ops *bops,
buf->aux.stride = aux_width;
size = buf->aux.offset + aux_width * aux_height;
-
} else {
if (buf->tiling) {
devid = intel_get_drm_devid(bops->fd);
@@ -826,6 +842,98 @@ void intel_buf_init_using_handle(struct buf_ops *bops,
req_tiling, compression);
}
+struct intel_buf *intel_buf_create(struct buf_ops *bops,
+ int width, int height,
+ int bpp, int alignment,
+ uint32_t req_tiling, uint32_t compression)
+{
+ struct intel_buf *buf;
+
+ igt_assert(bops);
+
+ buf = calloc(1, sizeof(*buf));
+ igt_assert(buf);
+
+ intel_buf_init(bops, buf, width, height, bpp, alignment,
+ req_tiling, compression);
+
+ return buf;
+}
+
+void intel_buf_destroy(struct intel_buf *buf)
+{
+ igt_assert(buf);
+
+ intel_buf_close(buf->bops, buf);
+ free(buf);
+}
+
+void intel_buf_print(const struct intel_buf *buf)
+{
+ igt_info("[name: %s]\n", buf->name);
+ igt_info("[%u]: w: %u, h: %u, stride: %u, size: %u, bo-size: %u, "
+ "bpp: %u, tiling: %u, compress: %u\n",
+ buf->handle, intel_buf_width(buf), intel_buf_height(buf),
+ buf->stride, buf->size,
+ intel_buf_bo_size(buf), buf->bpp,
+ buf->tiling, buf->compression);
+ igt_info(" aux <offset: %u, stride: %u, w: %u, h: %u> cc <offset: %u>\n",
+ buf->aux.offset,
+ intel_buf_aux_width(buf->bops->intel_gen, buf),
+ intel_buf_aux_height(buf->bops->intel_gen, buf),
+ buf->aux.stride, buf->cc.offset);
+ igt_info(" addr <offset: %p, ctx: %u>\n",
+ from_user_pointer(buf->addr.offset), buf->addr.ctx);
+}
+
+const char *intel_buf_set_name(struct intel_buf *buf, const char *name)
+{
+ return strncpy(buf->name, name, INTEL_BUF_NAME_MAXSIZE);
+}
+
+static void __intel_buf_write_to_png(struct buf_ops *bops,
+ struct intel_buf *buf,
+ const char *filename,
+ bool write_aux)
+{
+ cairo_surface_t *surface;
+ cairo_status_t ret;
+ void *linear;
+ int format, width, height, stride, offset;
+ int gen = bops->intel_gen;
+
+ igt_assert_eq(posix_memalign(&linear, 16, intel_buf_bo_size(buf)), 0);
+
+ format = write_aux ? CAIRO_FORMAT_A8 : CAIRO_FORMAT_RGB24;
+ width = write_aux ? intel_buf_aux_width(gen, buf) : intel_buf_width(buf);
+ height = write_aux ? intel_buf_aux_height(gen, buf) : intel_buf_height(buf);
+ stride = write_aux ? buf->aux.stride : buf->stride;
+ offset = write_aux ? buf->aux.offset : 0;
+
+ intel_buf_to_linear(bops, buf, linear);
+
+ surface = cairo_image_surface_create_for_data((uint8_t *) linear + offset,
+ format, width, height,
+ stride);
+ ret = cairo_surface_write_to_png(surface, filename);
+ igt_assert(ret == CAIRO_STATUS_SUCCESS);
+ cairo_surface_destroy(surface);
+
+ free(linear);
+}
+
+void intel_buf_write_to_png(struct intel_buf *buf, const char *filename)
+{
+ __intel_buf_write_to_png(buf->bops, buf, filename, false);
+}
+
+void intel_buf_write_aux_to_png(struct intel_buf *buf, const char *filename)
+{
+ igt_assert(buf->compression);
+
+ __intel_buf_write_to_png(buf->bops, buf, filename, true);
+}
+
#define DEFAULT_BUFOPS(__gen_start, __gen_end) \
.gen_start = __gen_start, \
.gen_end = __gen_end, \
@@ -876,7 +984,7 @@ static bool probe_hw_tiling(struct buf_ops *bops, uint32_t tiling)
handle = gem_create(bops->fd, size);
/* Single shot, if no fences are available we fail immediately */
- ret = __set_tiling(bops->fd, handle, tiling, stride);
+ ret = __set_tiling(bops->fd, handle, tiling, stride, NULL, NULL);
if (ret)
goto end;
@@ -956,6 +1064,15 @@ static void idempotency_selftest(struct buf_ops *bops, uint32_t tiling)
buf_ops_set_software_tiling(bops, tiling, false);
}
+int intel_buf_bo_size(const struct intel_buf *buf)
+{
+ int offset = CCS_OFFSET(buf) ?: buf->size;
+ int ccs_size = buf->compression ?
+ CCS_SIZE(buf->bops->intel_gen, buf) : 0;
+
+ return offset + ccs_size;
+}
+
/**
* buf_ops_create
* @fd: device filedescriptor
@@ -1061,12 +1178,12 @@ void buf_ops_destroy(struct buf_ops *bops)
}
/**
- * buf_ops_getfd
+ * buf_ops_get_fd
* @bops: pointer to buf_ops
*
* Returns: drm fd
*/
-int buf_ops_getfd(struct buf_ops *bops)
+int buf_ops_get_fd(struct buf_ops *bops)
{
igt_assert(bops);
diff --git a/lib/intel_bufops.h b/lib/intel_bufops.h
index 95217cfe..ab19d916 100644
--- a/lib/intel_bufops.h
+++ b/lib/intel_bufops.h
@@ -6,6 +6,7 @@
struct buf_ops;
+#define INTEL_BUF_NAME_MAXSIZE 32
struct intel_buf {
struct buf_ops *bops;
uint32_t handle;
@@ -14,14 +15,21 @@ struct intel_buf {
uint32_t bpp;
uint32_t size;
uint32_t compression;
+ uint32_t swizzle_mode;
struct {
uint32_t offset;
uint32_t stride;
} aux;
+ struct {
+ uint32_t offset;
+ } cc;
struct {
uint64_t offset;
uint32_t ctx;
} addr;
+
+ /* For debugging purposes */
+ char name[INTEL_BUF_NAME_MAXSIZE + 1];
};
static inline unsigned int intel_buf_width(const struct intel_buf *buf)
@@ -62,9 +70,11 @@ intel_buf_aux_height(int gen, const struct intel_buf *buf)
return DIV_ROUND_UP(intel_buf_height(buf), 512) * 32;
}
+int intel_buf_bo_size(const struct intel_buf *buf);
+
struct buf_ops *buf_ops_create(int fd);
void buf_ops_destroy(struct buf_ops *bops);
-int buf_ops_getfd(struct buf_ops *bops);
+int buf_ops_get_fd(struct buf_ops *bops);
bool buf_ops_set_software_tiling(struct buf_ops *bops,
uint32_t tiling,
@@ -90,4 +100,16 @@ void intel_buf_init_using_handle(struct buf_ops *bops,
int width, int height, int bpp, int alignment,
uint32_t req_tiling, uint32_t compression);
+struct intel_buf *intel_buf_create(struct buf_ops *bops,
+ int width, int height,
+ int bpp, int alignment,
+ uint32_t req_tiling, uint32_t compression);
+void intel_buf_destroy(struct intel_buf *buf);
+
+void intel_buf_print(const struct intel_buf *buf);
+const char *intel_buf_set_name(struct intel_buf *buf, const char *name);
+
+void intel_buf_write_to_png(struct intel_buf *buf, const char *filename);
+void intel_buf_write_aux_to_png(struct intel_buf *buf, const char *filename);
+
#endif
--
2.26.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [igt-dev] [PATCH i-g-t v11 3/4] tests/api_intel_bb: Add intel_bb API test
2020-06-30 14:50 [igt-dev] [PATCH i-g-t v11 0/4] dd api_intel_bb test Zbigniew Kempczyński
2020-06-30 14:50 ` [igt-dev] [PATCH i-g-t v11 1/4] lib/intel_batchbuffer: Extend intel_bb Zbigniew Kempczyński
2020-06-30 14:50 ` [igt-dev] [PATCH i-g-t v11 2/4] lib/intel_bufops: Add new functions and intel_buf fields Zbigniew Kempczyński
@ 2020-06-30 14:50 ` Zbigniew Kempczyński
2020-06-30 14:50 ` [igt-dev] [PATCH i-g-t v11 4/4] intel-ci/fast-feedback: add api_intel_bb tests Zbigniew Kempczyński
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Zbigniew Kempczyński @ 2020-06-30 14:50 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
IGT code contains some mechanisms which are quite large and cover
different gens so they deserve own api_* checks.
Starting with api_intel_bb verify intel_bb functions work as expected.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/i915/api_intel_bb.c | 613 ++++++++++++++++++++++++++++++++++++++
tests/meson.build | 1 +
2 files changed, 614 insertions(+)
create mode 100644 tests/i915/api_intel_bb.c
diff --git a/tests/i915/api_intel_bb.c b/tests/i915/api_intel_bb.c
new file mode 100644
index 00000000..dd9630db
--- /dev/null
+++ b/tests/i915/api_intel_bb.c
@@ -0,0 +1,613 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include <unistd.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <cairo.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/ioctl.h>
+#include "intel_bufops.h"
+
+#define PAGE_SIZE 4096
+
+#define WIDTH 64
+#define HEIGHT 64
+#define COLOR_00 0x00
+#define COLOR_33 0x33
+#define COLOR_77 0x77
+#define COLOR_CC 0xcc
+
+IGT_TEST_DESCRIPTION("intel_bb API check.");
+
+enum reloc_objects {
+ RELOC,
+ NORELOC,
+};
+
+enum obj_cache_ops {
+ PURGE_CACHE,
+ KEEP_CACHE,
+};
+
+static bool debug_bb = false;
+static bool write_png = false;
+static bool buf_info = false;
+
+static void *alloc_aligned(uint64_t size)
+{
+ void *p;
+
+ igt_assert_eq(posix_memalign(&p, 16, size), 0);
+
+ return p;
+}
+
+static void fill_buf(struct intel_buf *buf, uint8_t color)
+{
+ uint8_t *ptr;
+ int i915 = buf_ops_get_fd(buf->bops);
+ int i;
+
+ ptr = gem_mmap__device_coherent(i915, buf->handle, 0, buf->size,
+ PROT_WRITE);
+
+ for (i = 0; i < buf->size; i++)
+ ptr[i] = color;
+
+ munmap(ptr, buf->size);
+}
+
+static void check_buf(struct intel_buf *buf, uint8_t color)
+{
+ uint8_t *ptr;
+ int i915 = buf_ops_get_fd(buf->bops);
+ int i;
+
+ ptr = gem_mmap__device_coherent(i915, buf->handle, 0, buf->size,
+ PROT_READ);
+
+ for (i = 0; i < buf->size; i++)
+ igt_assert(ptr[i] == color);
+
+ munmap(ptr, buf->size);
+}
+
+
+static struct intel_buf *
+create_buf(struct buf_ops *bops, int width, int height, uint8_t color)
+{
+ struct intel_buf *buf;
+
+ buf = calloc(1, sizeof(*buf));
+ igt_assert(buf);
+
+ intel_buf_init(bops, buf, width/4, height, 32, 0, I915_TILING_NONE, 0);
+ fill_buf(buf, color);
+
+ return buf;
+}
+
+static void print_buf(struct intel_buf *buf, const char *name)
+{
+ uint8_t *ptr;
+ int i915 = buf_ops_get_fd(buf->bops);
+
+ ptr = gem_mmap__device_coherent(i915, buf->handle, 0, buf->size,
+ PROT_READ);
+ igt_debug("[%s] Buf handle: %d, size: %d, v: 0x%02x\n", name,
+ buf->handle, buf->size, ptr[0]);
+ munmap(ptr, buf->size);
+}
+
+static void simple_bb(struct buf_ops *bops, bool use_context)
+{
+ int i915 = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+ uint32_t ctx;
+
+ if (use_context) {
+ gem_require_contexts(i915);
+ ctx = gem_context_create(i915);
+ }
+
+ ibb = intel_bb_create(i915, PAGE_SIZE);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+ intel_bb_ptr_align(ibb, 8);
+
+ intel_bb_exec(ibb, intel_bb_offset(ibb),
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+
+ /* Check we're safe with reset and no double-free will occur */
+ intel_bb_reset(ibb, true);
+ intel_bb_reset(ibb, false);
+ intel_bb_reset(ibb, true);
+
+ intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+ intel_bb_ptr_align(ibb, 8);
+
+ if (use_context)
+ intel_bb_exec_with_context(ibb, intel_bb_offset(ibb), ctx,
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC,
+ true);
+
+ intel_bb_destroy(ibb);
+ if (use_context)
+ gem_context_destroy(i915, ctx);
+}
+
+static void __emit_blit(struct intel_bb *ibb,
+ struct intel_buf *src, struct intel_buf *dst)
+{
+ bool has_64b_reloc;
+
+ has_64b_reloc = ibb->gen >= 8;
+
+ intel_bb_out(ibb,
+ XY_SRC_COPY_BLT_CMD |
+ XY_SRC_COPY_BLT_WRITE_ALPHA |
+ XY_SRC_COPY_BLT_WRITE_RGB |
+ (6 + 2 * has_64b_reloc));
+ intel_bb_out(ibb, 3 << 24 | 0xcc << 16 | dst->stride);
+ intel_bb_out(ibb, 0);
+ intel_bb_out(ibb, intel_buf_height(dst) << 16 | intel_buf_width(dst));
+ intel_bb_emit_reloc_fenced(ibb, dst->handle,
+ I915_GEM_DOMAIN_RENDER,
+ I915_GEM_DOMAIN_RENDER,
+ 0, 0x0);
+ intel_bb_out(ibb, 0);
+ intel_bb_out(ibb, src->stride);
+ intel_bb_emit_reloc_fenced(ibb, src->handle,
+ I915_GEM_DOMAIN_RENDER, 0,
+ 0, 0x0);
+}
+
+static void blit(struct buf_ops *bops,
+ enum reloc_objects reloc_obj,
+ enum obj_cache_ops cache_op)
+{
+ int i915 = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+ struct intel_buf *src, *dst;
+ uint64_t poff_bb, poff_src, poff_dst;
+ uint64_t poff2_bb, poff2_src, poff2_dst;
+ uint64_t flags = 0;
+ bool purge_cache = cache_op == PURGE_CACHE ? true : false;
+ bool do_relocs = reloc_obj == RELOC ? true : false;
+
+ src = create_buf(bops, WIDTH, HEIGHT, COLOR_CC);
+ dst = create_buf(bops, WIDTH, HEIGHT, COLOR_00);
+
+ if (buf_info) {
+ print_buf(src, "src");
+ print_buf(dst, "dst");
+ }
+
+ if (do_relocs) {
+ ibb = intel_bb_create_with_relocs(i915, PAGE_SIZE);
+ } else {
+ ibb = intel_bb_create(i915, PAGE_SIZE);
+ flags |= I915_EXEC_NO_RELOC;
+ }
+
+ if (ibb->gen >= 6)
+ flags |= I915_EXEC_BLT;
+
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ __emit_blit(ibb, src, dst);
+
+ /* We expect initial addresses are zeroed for relocs */
+ if (reloc_obj == RELOC) {
+ igt_assert(intel_bb_get_object_offset(ibb, ibb->handle) == 0);
+ igt_assert(intel_bb_get_object_offset(ibb, src->handle) == 0);
+ igt_assert(intel_bb_get_object_offset(ibb, dst->handle) == 0);
+ }
+
+ intel_bb_emit_bbe(ibb);
+ igt_debug("exec flags: %" PRIX64 "\n", flags);
+ intel_bb_exec(ibb, intel_bb_offset(ibb), flags, true);
+ check_buf(dst, COLOR_CC);
+
+ poff_bb = intel_bb_get_object_offset(ibb, ibb->handle);
+ poff_src = intel_bb_get_object_offset(ibb, src->handle);
+ poff_dst = intel_bb_get_object_offset(ibb, dst->handle);
+ intel_bb_reset(ibb, purge_cache);
+
+ fill_buf(src, COLOR_77);
+ fill_buf(dst, COLOR_00);
+
+ __emit_blit(ibb, src, dst);
+
+ poff2_bb = intel_bb_get_object_offset(ibb, ibb->handle);
+ poff2_src = intel_bb_get_object_offset(ibb, src->handle);
+ poff2_dst = intel_bb_get_object_offset(ibb, dst->handle);
+
+ igt_debug("purge: %d, relocs: %d\n", purge_cache, do_relocs);
+ igt_debug("bb presumed offset: 0x%lx\n", poff_bb);
+ igt_debug("src presumed offset: 0x%lx\n", poff_src);
+ igt_debug("dst presumed offset: 0x%lx\n", poff_dst);
+ igt_debug("bb2 presumed offset: 0x%lx\n", poff2_bb);
+ igt_debug("src2 presumed offset: 0x%lx\n", poff2_src);
+ igt_debug("dst2 presumed offset: 0x%lx\n", poff2_dst);
+ if (purge_cache) {
+ if (do_relocs) {
+ igt_assert(poff2_bb == 0);
+ igt_assert(poff2_src == 0);
+ igt_assert(poff2_dst == 0);
+ } else {
+ igt_assert(poff_bb != poff2_bb);
+ igt_assert(poff_src != poff2_src);
+ igt_assert(poff_dst != poff2_dst);
+ }
+ } else {
+ if (do_relocs) {
+ uint64_t addrs1 = poff_bb | poff_src | poff_dst;
+ uint64_t addrs2 = poff2_bb | poff2_src | poff2_dst;
+ igt_assert(addrs1 != addrs2);
+ } else {
+ igt_assert(poff_bb == poff2_bb);
+ igt_assert(poff_src == poff2_src);
+ igt_assert(poff_dst == poff2_dst);
+ }
+ }
+
+ intel_bb_emit_bbe(ibb);
+ intel_bb_exec(ibb, intel_bb_offset(ibb), flags, true);
+ check_buf(dst, COLOR_77);
+
+ poff2_src = intel_bb_get_object_offset(ibb, src->handle);
+ poff2_dst = intel_bb_get_object_offset(ibb, dst->handle);
+ igt_assert(poff_src == poff2_src);
+ igt_assert(poff_dst == poff2_dst);
+
+ intel_buf_close(bops, src);
+ intel_buf_close(bops, dst);
+ intel_bb_destroy(ibb);
+}
+
+static void scratch_buf_init(struct buf_ops *bops,
+ struct intel_buf *buf,
+ int width, int height,
+ uint32_t req_tiling,
+ enum i915_compression compression)
+{
+ int bpp = 32;
+
+ intel_buf_init(bops, buf, width, height, bpp, 0,
+ req_tiling, compression);
+
+ igt_assert(intel_buf_width(buf) == width);
+ igt_assert(intel_buf_height(buf) == height);
+}
+
+static void scratch_buf_draw_pattern(struct buf_ops *bops,
+ struct intel_buf *buf,
+ int x, int y, int w, int h,
+ int cx, int cy, int cw, int ch,
+ bool use_alternate_colors)
+{
+ cairo_surface_t *surface;
+ cairo_pattern_t *pat;
+ cairo_t *cr;
+ void *linear;
+
+ linear = alloc_aligned(buf->size);
+
+ surface = cairo_image_surface_create_for_data(linear,
+ CAIRO_FORMAT_RGB24,
+ intel_buf_width(buf),
+ intel_buf_height(buf),
+ buf->stride);
+
+ cr = cairo_create(surface);
+
+ cairo_rectangle(cr, cx, cy, cw, ch);
+ cairo_clip(cr);
+
+ pat = cairo_pattern_create_mesh();
+ cairo_mesh_pattern_begin_patch(pat);
+ cairo_mesh_pattern_move_to(pat, x, y);
+ cairo_mesh_pattern_line_to(pat, x+w, y);
+ cairo_mesh_pattern_line_to(pat, x+w, y+h);
+ cairo_mesh_pattern_line_to(pat, x, y+h);
+ if (use_alternate_colors) {
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 0, 0.0, 1.0, 1.0);
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 1, 1.0, 0.0, 1.0);
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 2, 1.0, 1.0, 0.0);
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 3, 0.0, 0.0, 0.0);
+ } else {
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 0, 1.0, 0.0, 0.0);
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 1, 0.0, 1.0, 0.0);
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 2, 0.0, 0.0, 1.0);
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 3, 1.0, 1.0, 1.0);
+ }
+ cairo_mesh_pattern_end_patch(pat);
+
+ cairo_rectangle(cr, x, y, w, h);
+ cairo_set_source(cr, pat);
+ cairo_fill(cr);
+ cairo_pattern_destroy(pat);
+
+ cairo_destroy(cr);
+
+ cairo_surface_destroy(surface);
+
+ linear_to_intel_buf(bops, buf, linear);
+
+ free(linear);
+}
+
+static bool compare_bufs(struct intel_buf *buf1, struct intel_buf *buf2)
+{
+ void *ptr1, *ptr2;
+ int fd1, fd2, ret;
+
+ igt_assert(buf1->size == buf2->size);
+
+ fd1 = buf_ops_get_fd(buf1->bops);
+ fd2 = buf_ops_get_fd(buf2->bops);
+
+ ptr1 = gem_mmap__device_coherent(fd1, buf1->handle, 0, buf1->size,
+ PROT_READ);
+ ptr2 = gem_mmap__device_coherent(fd2, buf2->handle, 0, buf2->size,
+ PROT_READ);
+ ret = memcmp(ptr1, ptr2, buf1->size);
+
+ munmap(ptr1, buf1->size);
+ munmap(ptr2, buf2->size);
+
+ return ret;
+}
+
+static void do_intel_bb_blit(struct buf_ops *bops)
+{
+ struct intel_bb *ibb;
+ const int width = 1024;
+ const int height = 1024;
+ struct intel_buf src, dst, final;
+ int i915 = buf_ops_get_fd(bops);
+
+ gem_require_blitter(i915);
+
+ /* We'll fix it for gen2/3 later. */
+ igt_require(intel_gen(intel_get_drm_devid(i915)) > 3);
+
+ ibb = intel_bb_create(i915, PAGE_SIZE);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ scratch_buf_init(bops, &src, width, height, I915_TILING_NONE,
+ I915_COMPRESSION_NONE);
+ scratch_buf_init(bops, &dst, width, height, I915_TILING_Y,
+ I915_COMPRESSION_NONE);
+ scratch_buf_init(bops, &final, width, height, I915_TILING_NONE,
+ I915_COMPRESSION_NONE);
+
+ if (buf_info) {
+ intel_buf_print(&src);
+ intel_buf_print(&dst);
+ }
+
+ scratch_buf_draw_pattern(bops, &src,
+ 0, 0, width, height,
+ 0, 0, width, height, 0);
+
+ intel_bb_blt_copy(ibb,
+ &src, 0, 0, src.stride,
+ &dst, 0, 0, dst.stride,
+ intel_buf_width(&dst),
+ intel_buf_height(&dst),
+ dst.bpp);
+
+ intel_bb_blt_copy(ibb,
+ &dst, 0, 0, dst.stride,
+ &final, 0, 0, final.stride,
+ intel_buf_width(&dst),
+ intel_buf_height(&dst),
+ dst.bpp);
+
+ intel_bb_sync(ibb);
+ intel_bb_destroy(ibb);
+
+ if (write_png) {
+ intel_buf_write_to_png(&src, "bb_blit_src_tiling_none.png");
+ intel_buf_write_to_png(&dst, "bb_blit_dst_tiling_y.png");
+ intel_buf_write_to_png(&final, "bb_blit_final_tiling_none.png");
+ }
+
+ igt_assert(compare_bufs(&src, &dst) != 0);
+ igt_assert(compare_bufs(&src, &final) == 0);
+
+ intel_buf_close(bops, &src);
+ intel_buf_close(bops, &dst);
+ intel_buf_close(bops, &final);
+}
+
+
+static void offset_control(struct buf_ops *bops)
+{
+ int i915 = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+ struct intel_buf *src, *dst1, *dst2, *dst3;
+ uint64_t poff_src, poff_dst1, poff_dst2;
+
+ ibb = intel_bb_create(i915, PAGE_SIZE);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ src = create_buf(bops, WIDTH, HEIGHT, COLOR_CC);
+ dst1 = create_buf(bops, WIDTH, HEIGHT, COLOR_00);
+ dst2 = create_buf(bops, WIDTH, HEIGHT, COLOR_77);
+
+ intel_bb_add_object(ibb, src->handle, src->addr.offset, false);
+ intel_bb_add_object(ibb, dst1->handle, dst1->addr.offset, true);
+ intel_bb_add_object(ibb, dst2->handle, dst2->addr.offset, true);
+
+ intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+ intel_bb_ptr_align(ibb, 8);
+
+ intel_bb_exec(ibb, intel_bb_offset(ibb),
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, false);
+
+ if (buf_info) {
+ print_buf(src, "src ");
+ print_buf(dst1, "dst1");
+ print_buf(dst2, "dst2");
+ }
+
+ igt_assert(intel_bb_object_offset_to_buf(ibb, src) == true);
+ igt_assert(intel_bb_object_offset_to_buf(ibb, dst1) == true);
+ igt_assert(intel_bb_object_offset_to_buf(ibb, dst2) == true);
+ poff_src = src->addr.offset;
+ poff_dst1 = dst1->addr.offset;
+ poff_dst2 = dst2->addr.offset;
+ intel_bb_reset(ibb, true);
+
+ dst3 = create_buf(bops, WIDTH, HEIGHT, COLOR_33);
+ intel_bb_add_object(ibb, dst3->handle, dst3->addr.offset, true);
+ intel_bb_add_object(ibb, src->handle, src->addr.offset, false);
+ intel_bb_add_object(ibb, dst1->handle, dst1->addr.offset, true);
+ intel_bb_add_object(ibb, dst2->handle, dst2->addr.offset, true);
+
+ intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+ intel_bb_ptr_align(ibb, 8);
+
+ intel_bb_exec(ibb, intel_bb_offset(ibb),
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, false);
+ intel_bb_sync(ibb);
+
+ igt_assert(intel_bb_object_offset_to_buf(ibb, src) == true);
+ igt_assert(intel_bb_object_offset_to_buf(ibb, dst1) == true);
+ igt_assert(intel_bb_object_offset_to_buf(ibb, dst2) == true);
+ igt_assert(intel_bb_object_offset_to_buf(ibb, dst3) == true);
+ igt_assert(poff_src == src->addr.offset);
+ igt_assert(poff_dst1 == dst1->addr.offset);
+ igt_assert(poff_dst2 == dst2->addr.offset);
+
+ if (buf_info) {
+ print_buf(src, "src ");
+ print_buf(dst1, "dst1");
+ print_buf(dst2, "dst2");
+ }
+
+ intel_bb_destroy(ibb);
+}
+
+static void full_batch(struct buf_ops *bops)
+{
+ int i915 = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+ int i;
+
+ ibb = intel_bb_create(i915, PAGE_SIZE);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ for (i = 0; i < PAGE_SIZE / sizeof(uint32_t) - 1; i++)
+ intel_bb_out(ibb, 0);
+ intel_bb_emit_bbe(ibb);
+
+ igt_assert(intel_bb_offset(ibb) == PAGE_SIZE);
+ intel_bb_exec(ibb, intel_bb_offset(ibb),
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, false);
+
+ intel_bb_destroy(ibb);
+}
+
+static int opt_handler(int opt, int opt_index, void *data)
+{
+ switch (opt) {
+ case 'd':
+ debug_bb = true;
+ break;
+ case 'p':
+ write_png = true;
+ break;
+ case 'i':
+ buf_info = true;
+ break;
+ default:
+ return IGT_OPT_HANDLER_ERROR;
+ }
+
+ return IGT_OPT_HANDLER_SUCCESS;
+}
+
+const char *help_str =
+ " -d\tDebug bb\n"
+ " -p\tWrite surfaces to png\n"
+ " -i\tPrint buffer info\n"
+ ;
+
+igt_main_args("dpi", NULL, help_str, opt_handler, NULL)
+{
+ int i915;
+ struct buf_ops *bops;
+
+ igt_fixture {
+ i915 = drm_open_driver(DRIVER_INTEL);
+ bops = buf_ops_create(i915);
+ }
+
+ igt_subtest("simple-bb")
+ simple_bb(bops, false);
+
+ igt_subtest("simple-bb-ctx")
+ simple_bb(bops, true);
+
+ igt_subtest("blit-noreloc-keep-cache")
+ blit(bops, NORELOC, KEEP_CACHE);
+
+ igt_subtest("blit-reloc-purge-cache")
+ blit(bops, RELOC, PURGE_CACHE);
+
+ igt_subtest("blit-noreloc-purge-cache")
+ blit(bops, NORELOC, PURGE_CACHE);
+
+ igt_subtest("blit-reloc-keep-cache")
+ blit(bops, RELOC, KEEP_CACHE);
+
+ igt_subtest("intel-bb-blit")
+ do_intel_bb_blit(bops);
+
+ igt_subtest("offset-control")
+ offset_control(bops);
+
+ igt_subtest("full-batch")
+ full_batch(bops);
+
+ igt_fixture {
+ buf_ops_destroy(bops);
+ close(i915);
+ }
+}
diff --git a/tests/meson.build b/tests/meson.build
index 28091794..06a47e37 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -103,6 +103,7 @@ test_progs = [
]
i915_progs = [
+ 'api_intel_bb',
'gen3_mixed_blits',
'gen3_render_linear_blits',
'gen3_render_mixed_blits',
--
2.26.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [igt-dev] [PATCH i-g-t v11 4/4] intel-ci/fast-feedback: add api_intel_bb tests
2020-06-30 14:50 [igt-dev] [PATCH i-g-t v11 0/4] dd api_intel_bb test Zbigniew Kempczyński
` (2 preceding siblings ...)
2020-06-30 14:50 ` [igt-dev] [PATCH i-g-t v11 3/4] tests/api_intel_bb: Add intel_bb API test Zbigniew Kempczyński
@ 2020-06-30 14:50 ` Zbigniew Kempczyński
2020-06-30 15:27 ` [igt-dev] ✓ Fi.CI.BAT: success for dd api_intel_bb test Patchwork
2020-06-30 20:12 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 0 replies; 7+ messages in thread
From: Zbigniew Kempczyński @ 2020-06-30 14:50 UTC (permalink / raw)
To: igt-dev; +Cc: Petri Latvala, Chris Wilson
intel_bb has to replace libdrm intel_batchbuffer. We need to know
any changes in its infrastructure doesn't lead to regression.
Add api_intel_bb to BAT to be verified on the very beginning.
Test execution time is very short so it shouldn't be noticable
on CI.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Petri Latvala <petri.latvala@intel.com>
---
tests/intel-ci/fast-feedback.testlist | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-feedback.testlist
index 04f6affc..19e7a79c 100644
--- a/tests/intel-ci/fast-feedback.testlist
+++ b/tests/intel-ci/fast-feedback.testlist
@@ -1,5 +1,14 @@
# Keep alphabetically sorted by default
+igt@api_intel_bb@simple-bb
+igt@api_intel_bb@simple-bb-ctx
+igt@api_intel_bb@blit-noreloc-keep-cache
+igt@api_intel_bb@blit-reloc-purge-cache
+igt@api_intel_bb@blit-noreloc-purge-cache
+igt@api_intel_bb@blit-reloc-keep-cache
+igt@api_intel_bb@intel-bb-blit
+igt@api_intel_bb@offset-control
+igt@api_intel_bb@full-batch
igt@core_auth@basic-auth
igt@debugfs_test@read_all_entries
igt@fbdev@mmap
--
2.26.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for dd api_intel_bb test
2020-06-30 14:50 [igt-dev] [PATCH i-g-t v11 0/4] dd api_intel_bb test Zbigniew Kempczyński
` (3 preceding siblings ...)
2020-06-30 14:50 ` [igt-dev] [PATCH i-g-t v11 4/4] intel-ci/fast-feedback: add api_intel_bb tests Zbigniew Kempczyński
@ 2020-06-30 15:27 ` Patchwork
2020-06-30 20:12 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2020-06-30 15:27 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
== Series Details ==
Series: dd api_intel_bb test
URL : https://patchwork.freedesktop.org/series/78947/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8678 -> IGTPW_4719
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_4719:
### IGT changes ###
#### Possible regressions ####
* {igt@api_intel_bb@intel-bb-blit} (NEW):
- fi-tgl-u2: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/fi-tgl-u2/igt@api_intel_bb@intel-bb-blit.html
New tests
---------
New tests have been introduced between CI_DRM_8678 and IGTPW_4719:
### New IGT tests (9) ###
* igt@api_intel_bb@blit-noreloc-keep-cache:
- Statuses : 35 pass(s)
- Exec time: [0.00, 0.03] s
* igt@api_intel_bb@blit-noreloc-purge-cache:
- Statuses : 35 pass(s)
- Exec time: [0.00, 0.03] s
* igt@api_intel_bb@blit-reloc-keep-cache:
- Statuses : 35 pass(s)
- Exec time: [0.00, 0.03] s
* igt@api_intel_bb@blit-reloc-purge-cache:
- Statuses : 35 pass(s)
- Exec time: [0.00, 0.04] s
* igt@api_intel_bb@full-batch:
- Statuses : 35 pass(s)
- Exec time: [0.0, 0.01] s
* igt@api_intel_bb@intel-bb-blit:
- Statuses : 1 fail(s) 31 pass(s) 3 skip(s)
- Exec time: [0.0, 0.81] s
* igt@api_intel_bb@offset-control:
- Statuses : 35 pass(s)
- Exec time: [0.00, 0.03] s
* igt@api_intel_bb@simple-bb:
- Statuses : 35 pass(s)
- Exec time: [0.00, 0.02] s
* igt@api_intel_bb@simple-bb-ctx:
- Statuses : 32 pass(s) 3 skip(s)
- Exec time: [0.0, 0.03] s
Known issues
------------
Here are the changes found in IGTPW_4719 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s0:
- fi-tgl-u2: [PASS][2] -> [FAIL][3] ([i915#1888])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html
* igt@i915_selftest@live@execlists:
- fi-icl-y: [PASS][4] -> [INCOMPLETE][5] ([i915#1684])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-icl-y/igt@i915_selftest@live@execlists.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/fi-icl-y/igt@i915_selftest@live@execlists.html
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [PASS][6] -> [DMESG-WARN][7] ([i915#62] / [i915#92] / [i915#95])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-x1275/igt@kms_busy@basic@flip.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/fi-kbl-x1275/igt@kms_busy@basic@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-kefka: [PASS][8] -> [DMESG-WARN][9] ([i915#1982])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
- fi-icl-u2: [PASS][10] -> [DMESG-WARN][11] ([i915#1982])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-tgl-u2: [PASS][12] -> [DMESG-WARN][13] ([i915#402])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-tgl-u2/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/fi-tgl-u2/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
#### Possible fixes ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- {fi-tgl-dsi}: [DMESG-WARN][14] ([i915#1982]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-tgl-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/fi-tgl-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html
- fi-bsw-kefka: [DMESG-WARN][16] ([i915#1982]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-glk-dsi: [DMESG-WARN][18] ([i915#1982]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-glk-dsi/igt@i915_pm_rpm@module-reload.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/fi-glk-dsi/igt@i915_pm_rpm@module-reload.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- {fi-kbl-7560u}: [DMESG-WARN][20] ([i915#1982]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- fi-icl-u2: [DMESG-WARN][22] ([i915#1982]) -> [PASS][23] +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
#### Warnings ####
* igt@kms_flip@basic-flip-vs-wf_vblank@a-dp1:
- fi-kbl-x1275: [DMESG-WARN][24] ([i915#62] / [i915#92]) -> [DMESG-WARN][25] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-wf_vblank@a-dp1.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-wf_vblank@a-dp1.html
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-x1275: [DMESG-WARN][26] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][27] ([i915#62] / [i915#92]) +2 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1684]: https://gitlab.freedesktop.org/drm/intel/issues/1684
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (44 -> 37)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5718 -> IGTPW_4719
CI-20190529: 20190529
CI_DRM_8678: 7cafa8aeca728d8abd1bc9d31d2fca60757a00c4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_4719: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/index.html
IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@api_intel_bb@blit-noreloc-keep-cache
+igt@api_intel_bb@blit-noreloc-purge-cache
+igt@api_intel_bb@blit-reloc-keep-cache
+igt@api_intel_bb@blit-reloc-purge-cache
+igt@api_intel_bb@full-batch
+igt@api_intel_bb@intel-bb-blit
+igt@api_intel_bb@offset-control
+igt@api_intel_bb@simple-bb
+igt@api_intel_bb@simple-bb-ctx
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 7+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for dd api_intel_bb test
2020-06-30 14:50 [igt-dev] [PATCH i-g-t v11 0/4] dd api_intel_bb test Zbigniew Kempczyński
` (4 preceding siblings ...)
2020-06-30 15:27 ` [igt-dev] ✓ Fi.CI.BAT: success for dd api_intel_bb test Patchwork
@ 2020-06-30 20:12 ` Patchwork
5 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2020-06-30 20:12 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
== Series Details ==
Series: dd api_intel_bb test
URL : https://patchwork.freedesktop.org/series/78947/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8678_full -> IGTPW_4719_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_4719_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_4719_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_4719_full:
### IGT changes ###
#### Possible regressions ####
* igt@perf_pmu@busy-check-all@bcs0:
- shard-hsw: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-hsw6/igt@perf_pmu@busy-check-all@bcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-hsw4/igt@perf_pmu@busy-check-all@bcs0.html
#### Warnings ####
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt:
- shard-hsw: [SKIP][3] ([fdo#109271]) -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-hsw1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-hsw7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html
New tests
---------
New tests have been introduced between CI_DRM_8678_full and IGTPW_4719_full:
### New IGT tests (9) ###
* igt@api_intel_bb@blit-noreloc-keep-cache:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@api_intel_bb@blit-noreloc-purge-cache:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@api_intel_bb@blit-reloc-keep-cache:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@api_intel_bb@blit-reloc-purge-cache:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@api_intel_bb@full-batch:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@api_intel_bb@intel-bb-blit:
- Statuses : 7 pass(s)
- Exec time: [0.07, 0.18] s
* igt@api_intel_bb@offset-control:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@api_intel_bb@simple-bb:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@api_intel_bb@simple-bb-ctx:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
Known issues
------------
Here are the changes found in IGTPW_4719_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@in-flight-suspend:
- shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl3/igt@gem_eio@in-flight-suspend.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-kbl1/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_fence@invalid-fence-array:
- shard-snb: [PASS][7] -> [TIMEOUT][8] ([i915#1958])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-snb2/igt@gem_exec_fence@invalid-fence-array.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-snb1/igt@gem_exec_fence@invalid-fence-array.html
* igt@gem_exec_whisper@basic-fds:
- shard-glk: [PASS][9] -> [DMESG-WARN][10] ([i915#118] / [i915#95])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk6/igt@gem_exec_whisper@basic-fds.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-glk9/igt@gem_exec_whisper@basic-fds.html
* igt@gem_fence_thrash@bo-write-verify-threaded-none:
- shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#1635] / [i915#95]) +36 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl4/igt@gem_fence_thrash@bo-write-verify-threaded-none.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-apl2/igt@gem_fence_thrash@bo-write-verify-threaded-none.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-tglb: [PASS][13] -> [DMESG-WARN][14] ([i915#402]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb1/igt@i915_module_load@reload-with-fault-injection.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-tglb2/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-0:
- shard-glk: [PASS][15] -> [DMESG-FAIL][16] ([i915#118] / [i915#95])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk3/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-glk8/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-legacy:
- shard-hsw: [PASS][17] -> [TIMEOUT][18] ([i915#1958])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-hsw1/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-hsw7/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic:
- shard-kbl: [PASS][19] -> [DMESG-FAIL][20] ([i915#95]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl6/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-kbl6/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1:
- shard-hsw: [PASS][21] -> [INCOMPLETE][22] ([i915#2055])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-hsw6/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-hsw1/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
- shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#93] / [i915#95]) +35 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-tglb: [PASS][27] -> [DMESG-WARN][28] ([i915#1982]) +4 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-gtt:
- shard-tglb: [PASS][29] -> [SKIP][30] ([i915#668])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-gtt.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-gtt.html
* igt@kms_psr2_su@page_flip:
- shard-tglb: [PASS][31] -> [SKIP][32] ([i915#1911])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb6/igt@kms_psr2_su@page_flip.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-tglb2/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109441]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-iclb1/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_vblank@pipe-b-query-forked-busy:
- shard-apl: [PASS][35] -> [DMESG-WARN][36] ([i915#1982]) +3 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl6/igt@kms_vblank@pipe-b-query-forked-busy.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-apl2/igt@kms_vblank@pipe-b-query-forked-busy.html
* igt@perf@blocking-parameterized:
- shard-tglb: [PASS][37] -> [FAIL][38] ([i915#1542])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb5/igt@perf@blocking-parameterized.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-tglb8/igt@perf@blocking-parameterized.html
* igt@sysfs_timeslice_duration@timeout@vecs0:
- shard-iclb: [PASS][39] -> [FAIL][40] ([i915#1755])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb2/igt@sysfs_timeslice_duration@timeout@vecs0.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-iclb1/igt@sysfs_timeslice_duration@timeout@vecs0.html
- shard-tglb: [PASS][41] -> [FAIL][42] ([i915#1755])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb3/igt@sysfs_timeslice_duration@timeout@vecs0.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-tglb1/igt@sysfs_timeslice_duration@timeout@vecs0.html
#### Possible fixes ####
* igt@gem_exec_balancer@bonded-slice:
- shard-iclb: [INCOMPLETE][43] -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb1/igt@gem_exec_balancer@bonded-slice.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-iclb7/igt@gem_exec_balancer@bonded-slice.html
* igt@gem_exec_whisper@basic-contexts-forked:
- shard-glk: [DMESG-WARN][45] ([i915#118] / [i915#95]) -> [PASS][46] +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk2/igt@gem_exec_whisper@basic-contexts-forked.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-glk2/igt@gem_exec_whisper@basic-contexts-forked.html
* igt@gem_fenced_exec_thrash@no-spare-fences-interruptible:
- shard-snb: [TIMEOUT][47] ([i915#1958]) -> [PASS][48] +2 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-snb1/igt@gem_fenced_exec_thrash@no-spare-fences-interruptible.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-snb6/igt@gem_fenced_exec_thrash@no-spare-fences-interruptible.html
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [DMESG-WARN][49] ([i915#1436] / [i915#716]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl6/igt@gen9_exec_parse@allowed-all.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-apl1/igt@gen9_exec_parse@allowed-all.html
* igt@i915_getparams_basic@basic-eu-total:
- shard-kbl: [DMESG-WARN][51] ([i915#93] / [i915#95]) -> [PASS][52] +39 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl6/igt@i915_getparams_basic@basic-eu-total.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-kbl7/igt@i915_getparams_basic@basic-eu-total.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- shard-apl: [DMESG-WARN][53] ([i915#1635] / [i915#95]) -> [PASS][54] +29 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl1/igt@i915_pm_rpm@modeset-non-lpsp.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-apl4/igt@i915_pm_rpm@modeset-non-lpsp.html
* igt@kms_big_fb@linear-64bpp-rotate-0:
- shard-glk: [DMESG-FAIL][55] ([i915#118] / [i915#95]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk8/igt@kms_big_fb@linear-64bpp-rotate-0.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-glk4/igt@kms_big_fb@linear-64bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen:
- shard-kbl: [DMESG-FAIL][57] ([i915#54] / [i915#95]) -> [PASS][58] +3 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1:
- shard-glk: [FAIL][59] ([i915#79]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][61] ([i915#180]) -> [PASS][62] +8 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-suspend@c-hdmi-a1:
- shard-hsw: [INCOMPLETE][63] ([i915#2055]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-hsw1/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-hsw4/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
* igt@kms_flip@modeset-vs-vblank-race-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][65] ([i915#1982]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl7/igt@kms_flip@modeset-vs-vblank-race-interruptible@a-dp1.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-kbl2/igt@kms_flip@modeset-vs-vblank-race-interruptible@a-dp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack:
- shard-tglb: [DMESG-WARN][67] ([i915#1982]) -> [PASS][68] +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack.html
* igt@kms_lease@lessee_list:
- shard-hsw: [TIMEOUT][69] ([i915#1958]) -> [PASS][70] +3 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-hsw7/igt@kms_lease@lessee_list.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-hsw6/igt@kms_lease@lessee_list.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-glk: [DMESG-WARN][71] ([i915#1982]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-glk7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-mid:
- shard-kbl: [DMESG-FAIL][73] ([fdo#108145] / [i915#95]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-mid.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-kbl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-mid.html
- shard-apl: [DMESG-FAIL][75] ([fdo#108145] / [i915#1635] / [i915#95]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-mid.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-mid.html
* igt@kms_plane_cursor@pipe-a-overlay-size-128:
- shard-kbl: [DMESG-FAIL][77] ([i915#95]) -> [PASS][78] +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl2/igt@kms_plane_cursor@pipe-a-overlay-size-128.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-kbl6/igt@kms_plane_cursor@pipe-a-overlay-size-128.html
- shard-apl: [DMESG-FAIL][79] ([i915#1635] / [i915#95]) -> [PASS][80] +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl2/igt@kms_plane_cursor@pipe-a-overlay-size-128.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-apl1/igt@kms_plane_cursor@pipe-a-overlay-size-128.html
* igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping:
- shard-iclb: [DMESG-WARN][81] ([i915#1982]) -> [PASS][82] +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb3/igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-iclb6/igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [SKIP][83] ([fdo#109441]) -> [PASS][84] +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb1/igt@kms_psr@psr2_cursor_blt.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-tglb: [DMESG-WARN][85] ([i915#402]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb2/igt@kms_psr@psr2_sprite_plane_onoff.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-tglb6/igt@kms_psr@psr2_sprite_plane_onoff.html
* igt@perf_pmu@semaphore-busy@rcs0:
- shard-kbl: [FAIL][87] ([i915#1820]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl7/igt@perf_pmu@semaphore-busy@rcs0.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-kbl1/igt@perf_pmu@semaphore-busy@rcs0.html
#### Warnings ####
* igt@gem_exec_reloc@basic-spin-others@vcs0:
- shard-snb: [WARN][89] ([i915#2021]) -> [WARN][90] ([i915#2036])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-snb6/igt@gem_exec_reloc@basic-spin-others@vcs0.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-snb6/igt@gem_exec_reloc@basic-spin-others@vcs0.html
* igt@kms_chamelium@hdmi-cmp-planar-formats:
- shard-apl: [SKIP][91] ([fdo#109271] / [fdo#111827]) -> [SKIP][92] ([fdo#109271] / [fdo#111827] / [i915#1635]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl1/igt@kms_chamelium@hdmi-cmp-planar-formats.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-apl1/igt@kms_chamelium@hdmi-cmp-planar-formats.html
* igt@kms_color_chamelium@pipe-a-ctm-0-25:
- shard-snb: [SKIP][93] ([fdo#109271] / [fdo#111827]) -> [TIMEOUT][94] ([i915#1958])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-snb2/igt@kms_color_chamelium@pipe-a-ctm-0-25.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-snb1/igt@kms_color_chamelium@pipe-a-ctm-0-25.html
- shard-hsw: [SKIP][95] ([fdo#109271] / [fdo#111827]) -> [TIMEOUT][96] ([i915#1958])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-hsw4/igt@kms_color_chamelium@pipe-a-ctm-0-25.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-hsw7/igt@kms_color_chamelium@pipe-a-ctm-0-25.html
* igt@kms_color_chamelium@pipe-a-ctm-max:
- shard-apl: [SKIP][97] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][98] ([fdo#109271] / [fdo#111827])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl4/igt@kms_color_chamelium@pipe-a-ctm-max.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-apl4/igt@kms_color_chamelium@pipe-a-ctm-max.html
* igt@kms_content_protection@srm:
- shard-kbl: [TIMEOUT][99] ([i915#1319]) -> [TIMEOUT][100] ([i915#1319] / [i915#1958])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl2/igt@kms_content_protection@srm.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-kbl3/igt@kms_content_protection@srm.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled:
- shard-snb: [TIMEOUT][101] ([i915#1958]) -> [SKIP][102] ([fdo#109271]) +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-snb1/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-snb4/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled.html
- shard-hsw: [TIMEOUT][103] ([i915#1958]) -> [SKIP][104] ([fdo#109271])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-hsw7/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-hsw6/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-apl: [SKIP][105] ([fdo#109271]) -> [SKIP][106] ([fdo#109271] / [i915#1635]) +17 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-apl4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [DMESG-WARN][107] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][108] ([i915#93] / [i915#95])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt:
- shard-hsw: [SKIP][109] ([fdo#109271]) -> [TIMEOUT][110] ([i915#1958]) +1 similar issue
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-hsw6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-hsw7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
- shard-snb: [SKIP][111] ([fdo#109271]) -> [TIMEOUT][112] ([i915#1958]) +3 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-snb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-snb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-render:
- shard-apl: [SKIP][113] ([fdo#109271] / [i915#1635]) -> [SKIP][114] ([fdo#109271]) +14 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl8/igt@kms_frontbuffer_tracking@psr-rgb565-draw-render.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-apl1/igt@kms_frontbuffer_tracking@psr-rgb565-draw-render.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-apl: [DMESG-FAIL][115] ([fdo#108145] / [i915#1635] / [i915#95]) -> [FAIL][116] ([fdo#108145] / [i915#265])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl7/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-apl1/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
- shard-kbl: [DMESG-FAIL][117] ([fdo#108145] / [i915#95]) -> [FAIL][118] ([fdo#108145] / [i915#265])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl2/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-kbl2/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-kbl: [FAIL][119] ([i915#265]) -> [DMESG-FAIL][120] ([i915#95])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl2/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-kbl2/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@runner@aborted:
- shard-apl: ([FAIL][121], [FAIL][122]) ([fdo#109271] / [i915#1635] / [i915#716]) -> [FAIL][123] ([i915#1635])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl8/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl6/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/shard-apl3/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820
[i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911
[i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2021]: https://gitlab.freedesktop.org/drm/intel/issues/2021
[i915#2036]: https://gitlab.freedesktop.org/drm/intel/issues/2036
[i915#2055]: https://gitlab.freedesktop.org/drm/intel/issues/2055
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 8)
------------------------------
Missing (3): pig-skl-6260u pig-glk-j5005 pig-icl-1065g7
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5718 -> IGTPW_4719
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_8678: 7cafa8aeca728d8abd1bc9d31d2fca60757a00c4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_4719: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/index.html
IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4719/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-06-30 20:12 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-30 14:50 [igt-dev] [PATCH i-g-t v11 0/4] dd api_intel_bb test Zbigniew Kempczyński
2020-06-30 14:50 ` [igt-dev] [PATCH i-g-t v11 1/4] lib/intel_batchbuffer: Extend intel_bb Zbigniew Kempczyński
2020-06-30 14:50 ` [igt-dev] [PATCH i-g-t v11 2/4] lib/intel_bufops: Add new functions and intel_buf fields Zbigniew Kempczyński
2020-06-30 14:50 ` [igt-dev] [PATCH i-g-t v11 3/4] tests/api_intel_bb: Add intel_bb API test Zbigniew Kempczyński
2020-06-30 14:50 ` [igt-dev] [PATCH i-g-t v11 4/4] intel-ci/fast-feedback: add api_intel_bb tests Zbigniew Kempczyński
2020-06-30 15:27 ` [igt-dev] ✓ Fi.CI.BAT: success for dd api_intel_bb test Patchwork
2020-06-30 20:12 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
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