* [igt-dev] [PATCH i-g-t v16 0/4] Add api_intel_bb test
@ 2020-07-03 11:30 Zbigniew Kempczyński
2020-07-03 11:30 ` [igt-dev] [PATCH i-g-t v16 1/4] lib/intel_batchbuffer: Extend intel_bb Zbigniew Kempczyński
` (6 more replies)
0 siblings, 7 replies; 11+ messages in thread
From: Zbigniew Kempczyński @ 2020-07-03 11:30 UTC (permalink / raw)
To: igt-dev
Slowly as London bus move toward say goodbye to libdrm in the
rendercopy tests.
Seriously - add some new functions in intel_buf/intel_bb and
verify most of them work properly and doesn't affect gem_gpgpu_fill,
gem_media_fill and i915_pm_sseu which were previously migrated.
,,,
v13: add fences as primary synchronisation, add none/x/y
blitting tests to ensure none->?->none blit give same
result
v14: skip gens2/3
v15: fixing blitting Y surfaces, skipping testing Y blit on gens < 6
v16: distinguish reloc/no-reloc offset handling
Zbigniew Kempczyński (4):
lib/intel_batchbuffer: Extend intel_bb
lib/intel_bufops: Add new functions and intel_buf fields
tests/api_intel_bb: Add intel_bb API test
intel-ci/fast-feedback: add api_intel_bb tests
lib/intel_batchbuffer.c | 516 +++++++++++++++++--
lib/intel_batchbuffer.h | 80 ++-
lib/intel_bufops.c | 136 ++++-
lib/intel_bufops.h | 25 +-
tests/i915/api_intel_bb.c | 709 ++++++++++++++++++++++++++
tests/intel-ci/fast-feedback.testlist | 11 +
tests/meson.build | 1 +
7 files changed, 1413 insertions(+), 65 deletions(-)
create mode 100644 tests/i915/api_intel_bb.c
--
2.26.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 11+ messages in thread
* [igt-dev] [PATCH i-g-t v16 1/4] lib/intel_batchbuffer: Extend intel_bb
2020-07-03 11:30 [igt-dev] [PATCH i-g-t v16 0/4] Add api_intel_bb test Zbigniew Kempczyński
@ 2020-07-03 11:30 ` Zbigniew Kempczyński
2020-07-03 11:31 ` [igt-dev] [PATCH i-g-t v16 2/4] lib/intel_bufops: Add new functions and intel_buf fields Zbigniew Kempczyński
` (5 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Zbigniew Kempczyński @ 2020-07-03 11:30 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
As we're going toward removing libdrm from rendercopy tests some
additional code in intel_bb is required. So add new functions
and fix memory issues in the reset path.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_batchbuffer.c | 516 ++++++++++++++++++++++++++++++++++++----
lib/intel_batchbuffer.h | 80 ++++++-
2 files changed, 541 insertions(+), 55 deletions(-)
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 2a882627..9fc75dbe 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -26,6 +26,7 @@
**************************************************************************/
#include <inttypes.h>
+#include <poll.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -42,6 +43,7 @@
#include "rendercopy.h"
#include "media_fill.h"
#include "ioctl_wrappers.h"
+#include "sw_sync.h"
#include "i915/gem_mman.h"
#include "media_spin.h"
#include "gpgpu_fill.h"
@@ -1045,8 +1047,6 @@ void igt_blitter_fast_copy(struct intel_batchbuffer *batch,
intel_batchbuffer_flush(batch);
}
-#undef CHECK_RANGE
-
/**
* igt_get_render_copyfunc:
* @devid: pci device id
@@ -1202,6 +1202,21 @@ static void __reallocate_objects(struct intel_bb *ibb)
}
}
+static inline uint64_t __intel_bb_propose_offset(struct intel_bb *ibb)
+{
+ uint64_t offset;
+
+ if (ibb->enforce_relocs)
+ return 0;
+
+ /* randomize the address, we try to avoid relocations */
+ offset = hars_petruska_f54_1_random64(&ibb->prng);
+ offset &= (ibb->gtt_size - 1);
+ offset &= ~(4096 - 1);
+
+ return offset;
+}
+
/**
* intel_bb_create:
* @i915: drm fd
@@ -1211,22 +1226,26 @@ static void __reallocate_objects(struct intel_bb *ibb)
*
* Pointer the intel_bb, asserts on failure.
*/
-struct intel_bb *intel_bb_create(int i915, uint32_t size)
+static struct intel_bb *
+__intel_bb_create(int i915, uint32_t size, bool do_relocs)
{
struct intel_bb *ibb = calloc(1, sizeof(*ibb));
uint64_t gtt_size;
+ uint64_t bb_address;
igt_assert(ibb);
ibb->i915 = i915;
ibb->devid = intel_get_drm_devid(i915);
ibb->gen = intel_gen(ibb->devid);
+ ibb->enforce_relocs = do_relocs;
ibb->handle = gem_create(i915, size);
ibb->size = size;
ibb->batch = calloc(1, size);
igt_assert(ibb->batch);
ibb->ptr = ibb->batch;
ibb->prng = (uint32_t) to_user_pointer(ibb);
+ ibb->fence = -1;
gtt_size = gem_aperture_size(i915);
if (!gem_uses_full_ppgtt(i915))
@@ -1236,11 +1255,45 @@ struct intel_bb *intel_bb_create(int i915, uint32_t size)
ibb->gtt_size = gtt_size;
__reallocate_objects(ibb);
- intel_bb_add_object(ibb, ibb->handle, 0, false);
+ bb_address = __intel_bb_propose_offset(ibb);
+ intel_bb_add_object(ibb, ibb->handle, bb_address, false);
+
+ ibb->refcount = 1;
return ibb;
}
+/**
+ * intel_bb_create:
+ * @i915: drm fd
+ * @size: size of the batchbuffer
+ *
+ * Returns:
+ *
+ * Pointer the intel_bb, asserts on failure.
+ */
+struct intel_bb *intel_bb_create(int i915, uint32_t size)
+{
+ return __intel_bb_create(i915, size, false);
+}
+
+/**
+ * intel_bb_create_with_relocs:
+ * @i915: drm fd
+ * @size: size of the batchbuffer
+ *
+ * Disable passing or randomizing addresses. This will lead to relocations
+ * when objects are not previously pinned.
+ *
+ * Returns:
+ *
+ * Pointer the intel_bb, asserts on failure.
+ */
+struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size)
+{
+ return __intel_bb_create(i915, size, true);
+}
+
/*
* tdestroy() calls free function for each node, but we spread tree
* on objects array, so do nothing.
@@ -1250,24 +1303,32 @@ static void __do_nothing(void *node)
(void) node;
}
-static void __intel_bb_destroy_objects(struct intel_bb *ibb)
+static void __intel_bb_destroy_relocations(struct intel_bb *ibb)
{
uint32_t i;
/* Free relocations */
- for (i = 0; i < ibb->num_objects; i++)
+ for (i = 0; i < ibb->num_objects; i++) {
free(from_user_pointer(ibb->objects[i].relocs_ptr));
+ ibb->objects[i].relocs_ptr = to_user_pointer(NULL);
+ ibb->objects[i].relocation_count = 0;
+ }
- free(ibb->objects);
- tdestroy(ibb->root, __do_nothing);
+ ibb->relocs = NULL;
+ ibb->num_relocs = 0;
+ ibb->allocated_relocs = 0;
+}
+static void __intel_bb_destroy_objects(struct intel_bb *ibb)
+{
+ free(ibb->objects);
ibb->objects = NULL;
+
+ tdestroy(ibb->root, __do_nothing);
ibb->root = NULL;
+
ibb->num_objects = 0;
- ibb->num_relocs = 0;
ibb->allocated_objects = 0;
- ibb->allocated_relocs = 0;
- ibb->ptr = ibb->batch;
}
/**
@@ -1280,9 +1341,16 @@ void intel_bb_destroy(struct intel_bb *ibb)
{
igt_assert(ibb);
+ ibb->refcount--;
+ igt_assert_f(ibb->refcount == 0, "Trying to destroy referenced bb!");
+
+ __intel_bb_destroy_relocations(ibb);
__intel_bb_destroy_objects(ibb);
gem_close(ibb->i915, ibb->handle);
+ if (ibb->fence >= 0)
+ close(ibb->fence);
+
free(ibb);
}
@@ -1291,10 +1359,21 @@ void intel_bb_destroy(struct intel_bb *ibb)
* @ibb: pointer to intel_bb
* @purge_objects_cache: if true destroy internal execobj and relocs + cache
*
- * Recreate batch bo.
+ * Recreate batch bo when there's no additional reference.
*/
void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
{
+ uint64_t bb_address;
+
+ if (purge_objects_cache && ibb->refcount > 1)
+ igt_warn("Cannot purge objects cache on bb, refcount > 1!");
+
+ /* Someone keeps reference, just exit */
+ if (ibb->refcount > 1)
+ return;
+
+ __intel_bb_destroy_relocations(ibb);
+
if (purge_objects_cache) {
__intel_bb_destroy_objects(ibb);
__reallocate_objects(ibb);
@@ -1303,8 +1382,75 @@ void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
gem_close(ibb->i915, ibb->handle);
ibb->handle = gem_create(ibb->i915, ibb->size);
- intel_bb_add_object(ibb, ibb->handle, 0, false);
+ bb_address = __intel_bb_propose_offset(ibb);
+ intel_bb_add_object(ibb, ibb->handle, bb_address, false);
ibb->ptr = ibb->batch;
+ memset(ibb->batch, 0, ibb->size);
+}
+
+/*
+ * intel_bb_sync:
+ * @ibb: pointer to intel_bb
+ *
+ * Waits for bb completion. Returns 0 on success, otherwise errno.
+ */
+int intel_bb_sync(struct intel_bb *ibb)
+{
+ int ret;
+
+ if (ibb->fence < 0)
+ return 0;
+
+ ret = sync_fence_wait(ibb->fence, -1);
+ if (ret == 0) {
+ close(ibb->fence);
+ ibb->fence = -1;
+ }
+
+ return ret;
+}
+
+/*
+ * intel_bb_print:
+ * @ibb: pointer to intel_bb
+ *
+ * Prints batch to stdout.
+ */
+void intel_bb_print(struct intel_bb *ibb)
+{
+ igt_info("drm fd: %d, gen: %d, devid: %u, debug: %d\n",
+ ibb->i915, ibb->gen, ibb->devid, ibb->debug);
+ igt_info("handle: %u, size: %u, batch: %p, ptr: %p\n",
+ ibb->handle, ibb->size, ibb->batch, ibb->ptr);
+ igt_info("prng: %u, gtt_size: %" PRIu64 ", supports 48bit: %d\n",
+ ibb->prng, ibb->gtt_size, ibb->supports_48b_address);
+ igt_info("ctx: %u\n", ibb->ctx);
+ igt_info("root: %p\n", ibb->root);
+ igt_info("objects: %p, num_objects: %u, allocated obj: %u\n",
+ ibb->objects, ibb->num_objects, ibb->allocated_objects);
+ igt_info("relocs: %p, num_relocs: %u, allocated_relocs: %u\n----\n",
+ ibb->relocs, ibb->num_relocs, ibb->allocated_relocs);
+}
+
+/*
+ * intel_bb_dump:
+ * @ibb: pointer to intel_bb
+ * @filename: name to which write bb
+ *
+ * Dump batch bo to file.
+ */
+void intel_bb_dump(struct intel_bb *ibb, const char *filename)
+{
+ FILE *out;
+ void *ptr;
+
+ ptr = gem_mmap__device_coherent(ibb->i915, ibb->handle, 0, ibb->size,
+ PROT_READ);
+ out = fopen(filename, "wb");
+ igt_assert(out);
+ fwrite(ptr, ibb->size, 1, out);
+ fclose(out);
+ munmap(ptr, ibb->size);
}
/**
@@ -1331,8 +1477,7 @@ static int __compare_objects(const void *p1, const void *p2)
* intel_bb_add_object:
* @ibb: pointer to intel_bb
* @handle: which handle to add to objects array
- * @offset: presumed offset of the object when I915_EXEC_NO_RELOC flag is
- * used in execbuf call
+ * @offset: presumed offset of the object when no relocation is enforced
* @write: does a handle is a render target
*
* Function adds or updates execobj slot in bb objects array and
@@ -1352,6 +1497,7 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle,
i = ibb->num_objects;
object = &ibb->objects[i];
object->handle = handle;
+ object->offset = offset;
found = tsearch((void *) object, &ibb->root, __compare_objects);
@@ -1360,18 +1506,8 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle,
else
object = *found;
- /* Assign address once */
- if (object->offset == 0) {
- if (offset) {
- object->offset = offset;
- } else {
- /* randomize the address, we try to avoid relocations */
- offset = hars_petruska_f54_1_random64(&ibb->prng);
- offset &= (ibb->gtt_size - 1);
- offset &= ~(4096 - 1);
- object->offset = offset;
- }
- }
+ if (object->offset == INTEL_BUF_INVALID_ADDRESS)
+ object->offset = __intel_bb_propose_offset(ibb);
if (write)
object->flags |= EXEC_OBJECT_WRITE;
@@ -1382,6 +1518,23 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle,
return object;
}
+static bool intel_bb_object_set_fence(struct intel_bb *ibb, uint32_t handle)
+{
+ struct drm_i915_gem_exec_object2 object = { .handle = handle };
+ struct drm_i915_gem_exec_object2 **found;
+
+ found = tfind((void *) &object, &ibb->root, __compare_objects);
+ if (!found) {
+ igt_warn("Trying to set fence on not found handle: %u\n",
+ handle);
+ return false;
+ }
+
+ (*found)->flags |= EXEC_OBJECT_NEEDS_FENCE;
+
+ return true;
+}
+
/*
* intel_bb_add_reloc:
* @ibb: pointer to intel_bb
@@ -1390,8 +1543,10 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle,
* @write_domain: gem domain bit for the relocation
* @delta: delta value to add to @buffer's gpu address
* @offset: offset within bb to be patched
- * @presumed_offset: address of the object in address space, important for
- * I915_EXEC_NO_RELOC flag
+ * @presumed_offset: address of the object in address space. If -1 is passed
+ * then final offset of the object will be randomized (for no-reloc bb) or
+ * 0 (for reloc bb, in that case reloc.presumed_offset will be -1). In
+ * case address is known it should passed in @presumed_offset (for no-reloc).
*
* Function allocates additional relocation slot in reloc array for a handle.
* It also implicitly adds handle in the objects array if object doesn't
@@ -1426,14 +1581,18 @@ static uint64_t intel_bb_add_reloc(struct intel_bb *ibb,
relocs[i].write_domain = write_domain;
relocs[i].delta = delta;
relocs[i].offset = offset;
- relocs[i].presumed_offset = object->offset;
+ if (ibb->enforce_relocs)
+ relocs[i].presumed_offset = -1;
+ else
+ relocs[i].presumed_offset = object->offset;
igt_debug("add reloc: handle: %u, r/w: 0x%x/0x%x, "
"delta: 0x%" PRIx64 ", "
"offset: 0x%" PRIx64 ", "
- "poffset: 0x%" PRIx64 "\n",
+ "poffset: %p\n",
handle, read_domains, write_domain,
- delta, offset, presumed_offset);
+ delta, offset,
+ from_user_pointer(relocs[i].presumed_offset));
return object->offset;
}
@@ -1445,8 +1604,10 @@ static uint64_t intel_bb_add_reloc(struct intel_bb *ibb,
* @read_domains: gem domain bits for the relocation
* @write_domain: gem domain bit for the relocation
* @delta: delta value to add to @buffer's gpu address
- * @presumed_offset: address of the object in address space, important for
- * I915_EXEC_NO_RELOC flag
+ * @presumed_offset: address of the object in address space. If -1 is passed
+ * then final offset of the object will be randomized (for no-reloc bb) or
+ * 0 (for reloc bb, in that case reloc.presumed_offset will be -1). In
+ * case address is known it should passed in @presumed_offset (for no-reloc).
* @write: does a handle is a render target
*
* Function prepares relocation (execobj if required + reloc) and emits
@@ -1479,6 +1640,23 @@ uint64_t intel_bb_emit_reloc(struct intel_bb *ibb,
return address;
}
+uint64_t intel_bb_emit_reloc_fenced(struct intel_bb *ibb,
+ uint32_t handle,
+ uint32_t read_domains,
+ uint32_t write_domain,
+ uint64_t delta,
+ uint64_t presumed_offset)
+{
+ uint64_t address;
+
+ address = intel_bb_emit_reloc(ibb, handle, read_domains, write_domain,
+ delta, presumed_offset);
+
+ intel_bb_object_set_fence(ibb, handle);
+
+ return address;
+}
+
/**
* intel_bb_offset_reloc:
* @ibb: pointer to intel_bb
@@ -1486,8 +1664,10 @@ uint64_t intel_bb_emit_reloc(struct intel_bb *ibb,
* @read_domains: gem domain bits for the relocation
* @write_domain: gem domain bit for the relocation
* @offset: offset within bb to be patched
- * @presumed_offset: address of the object in address space, important for
- * I915_EXEC_NO_RELOC flag
+ * @presumed_offset: address of the object in address space. If -1 is passed
+ * then final offset of the object will be randomized (for no-reloc bb) or
+ * 0 (for reloc bb, in that case reloc.presumed_offset will be -1). In
+ * case address is known it should passed in @presumed_offset (for no-reloc).
*
* Function prepares relocation (execobj if required + reloc). It it used
* for editing batchbuffer via modifying structures. It means when we're
@@ -1509,11 +1689,27 @@ uint64_t intel_bb_offset_reloc(struct intel_bb *ibb,
0, offset, presumed_offset);
}
-static void intel_bb_dump_execbuf(struct drm_i915_gem_execbuffer2 *execbuf)
+uint64_t intel_bb_offset_reloc_with_delta(struct intel_bb *ibb,
+ uint32_t handle,
+ uint32_t read_domains,
+ uint32_t write_domain,
+ uint32_t delta,
+ uint32_t offset,
+ uint64_t presumed_offset)
+{
+ igt_assert(ibb);
+
+ return intel_bb_add_reloc(ibb, handle, read_domains, write_domain,
+ delta, offset, presumed_offset);
+}
+
+static void intel_bb_dump_execbuf(struct intel_bb *ibb,
+ struct drm_i915_gem_execbuffer2 *execbuf)
{
struct drm_i915_gem_exec_object2 *objects;
struct drm_i915_gem_relocation_entry *relocs, *reloc;
int i, j;
+ uint64_t address;
igt_info("execbuf batch len: %u, start offset: 0x%x, "
"DR1: 0x%x, DR4: 0x%x, "
@@ -1529,26 +1725,33 @@ static void intel_bb_dump_execbuf(struct drm_i915_gem_execbuffer2 *execbuf)
objects = &((struct drm_i915_gem_exec_object2 *)
from_user_pointer(execbuf->buffers_ptr))[i];
relocs = from_user_pointer(objects->relocs_ptr);
+ address = objects->offset;
+ if (address != INTEL_BUF_INVALID_ADDRESS)
+ address = address & (ibb->gtt_size - 1);
igt_info(" [%d] handle: %u, reloc_count: %d, reloc_ptr: %p, "
- "align: 0x%llx, offset: 0x%llx, flags: 0x%llx, "
+ "align: 0x%llx, offset: 0x%" PRIx64 ", flags: 0x%llx, "
"rsvd1: 0x%llx, rsvd2: 0x%llx\n",
i, objects->handle, objects->relocation_count,
relocs,
objects->alignment,
- objects->offset, objects->flags,
+ address,
+ objects->flags,
objects->rsvd1, objects->rsvd2);
if (objects->relocation_count) {
igt_info("\texecbuf relocs:\n");
for (j = 0; j < objects->relocation_count; j++) {
reloc = &relocs[j];
+ address = reloc->presumed_offset;
+ if (address != INTEL_BUF_INVALID_ADDRESS)
+ address = address & (ibb->gtt_size - 1);
igt_info("\t [%d] target handle: %u, "
"offset: 0x%llx, delta: 0x%x, "
- "presumed_offset: 0x%llx, "
+ "presumed_offset: 0x%" PRIx64 ", "
"read_domains: 0x%x, "
"write_domain: 0x%x\n",
j, reloc->target_handle,
reloc->offset, reloc->delta,
- reloc->presumed_offset,
+ address,
reloc->read_domains,
reloc->write_domain);
}
@@ -1593,7 +1796,7 @@ int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
uint32_t ctx, uint64_t flags, bool sync)
{
struct drm_i915_gem_execbuffer2 execbuf;
- int ret;
+ int ret, fence, new_fence;
ibb->objects[0].relocs_ptr = to_user_pointer(ibb->relocs);
ibb->objects[0].relocation_count = ibb->num_relocs;
@@ -1606,17 +1809,34 @@ int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
execbuf.buffer_count = ibb->num_objects;
execbuf.batch_len = end_offset;
execbuf.rsvd1 = ibb->ctx = ctx;
- execbuf.flags = flags | I915_EXEC_BATCH_FIRST;
-
- ret = __gem_execbuf(ibb->i915, &execbuf);
- if (ret)
+ execbuf.flags = flags | I915_EXEC_BATCH_FIRST | I915_EXEC_FENCE_OUT;
+ if (ibb->enforce_relocs)
+ execbuf.flags &= ~I915_EXEC_NO_RELOC;
+ execbuf.rsvd2 = 0;
+
+ ret = __gem_execbuf_wr(ibb->i915, &execbuf);
+ if (ret) {
+ intel_bb_dump_execbuf(ibb, &execbuf);
return ret;
+ }
+
+ /* Save/merge fences */
+ fence = execbuf.rsvd2 >> 32;
+
+ if (ibb->fence < 0) {
+ ibb->fence = fence;
+ } else {
+ new_fence = sync_fence_merge(ibb->fence, fence);
+ close(ibb->fence);
+ close(fence);
+ ibb->fence = new_fence;
+ }
if (sync || ibb->debug)
- gem_sync(ibb->i915, ibb->handle);
+ igt_assert(intel_bb_sync(ibb) == 0);
if (ibb->debug) {
- intel_bb_dump_execbuf(&execbuf);
+ intel_bb_dump_execbuf(ibb, &execbuf);
if (intel_bb_debug_tree) {
igt_info("\nTree:\n");
twalk(ibb->root, print_node);
@@ -1672,14 +1892,20 @@ uint64_t intel_bb_get_object_offset(struct intel_bb *ibb, uint32_t handle)
{
struct drm_i915_gem_exec_object2 object = { .handle = handle };
struct drm_i915_gem_exec_object2 **found;
+ uint64_t address;
igt_assert(ibb);
found = tfind((void *) &object, &ibb->root, __compare_objects);
if (!found)
- return 0;
+ return INTEL_BUF_INVALID_ADDRESS;
+
+ address = (*found)->offset;
- return (*found)->offset;
+ if (address == INTEL_BUF_INVALID_ADDRESS)
+ return address;
+
+ return address & (ibb->gtt_size - 1);
}
/**
@@ -1706,8 +1932,196 @@ bool intel_bb_object_offset_to_buf(struct intel_bb *ibb, struct intel_buf *buf)
return false;
}
- buf->addr.offset = (*found)->offset;
+ buf->addr.offset = (*found)->offset & (ibb->gtt_size - 1);
buf->addr.ctx = ibb->ctx;
return true;
}
+
+/*
+ * intel_bb_emit_bbe:
+ * @ibb: batchbuffer
+ *
+ * Outputs MI_BATCH_BUFFER_END and ensures batch is properly aligned.
+ */
+uint32_t intel_bb_emit_bbe(struct intel_bb *ibb)
+{
+ /* Mark the end of the buffer. */
+ intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+ intel_bb_ptr_align(ibb, 8);
+
+ return intel_bb_offset(ibb);
+}
+
+/*
+ * intel_bb_flush_with_context_ring:
+ * @ibb: batchbuffer
+ * @ctx: context id
+ * @ring: ring
+ *
+ * Submits the batch for execution on the @ring engine with the supplied
+ * hardware context @ctx.
+ */
+static void intel_bb_flush_with_context_ring(struct intel_bb *ibb,
+ uint32_t ctx, uint32_t ring)
+{
+ intel_bb_exec_with_context(ibb, intel_bb_offset(ibb), ctx,
+ ring | I915_EXEC_NO_RELOC,
+ false);
+ intel_bb_reset(ibb, false);
+}
+
+void intel_bb_flush_render(struct intel_bb *ibb)
+{
+ uint32_t ring = I915_EXEC_RENDER;
+
+ intel_bb_flush_with_context_ring(ibb, ibb->ctx, ring);
+}
+
+void intel_bb_flush_blit(struct intel_bb *ibb)
+{
+ uint32_t ring = I915_EXEC_DEFAULT;
+
+ if (HAS_BLT_RING(ibb->devid))
+ ring = I915_EXEC_BLT;
+
+ intel_bb_flush_with_context_ring(ibb, ibb->ctx, ring);
+}
+
+uint32_t intel_bb_copy_data(struct intel_bb *ibb,
+ const void *data, unsigned int bytes,
+ uint32_t align)
+{
+ uint32_t *subdata, offset;
+
+ igt_assert((bytes & 3) == 0);
+
+ intel_bb_ptr_align(ibb, align);
+ offset = intel_bb_offset(ibb);
+ igt_assert(offset + bytes < ibb->size);
+
+ subdata = intel_bb_ptr(ibb);
+ memcpy(subdata, data, bytes);
+ intel_bb_ptr_add(ibb, bytes);
+
+ return offset;
+}
+
+void intel_bb_blit_start(struct intel_bb *ibb, uint32_t flags)
+{
+ intel_bb_out(ibb, XY_SRC_COPY_BLT_CMD |
+ XY_SRC_COPY_BLT_WRITE_ALPHA |
+ XY_SRC_COPY_BLT_WRITE_RGB |
+ (flags) |
+ (6 + 2*(ibb->gen >= 8)));
+}
+
+void intel_bb_emit_blt_copy(struct intel_bb *ibb,
+ struct intel_buf *src,
+ int src_x1, int src_y1, int src_pitch,
+ struct intel_buf *dst,
+ int dst_x1, int dst_y1, int dst_pitch,
+ int width, int height, int bpp)
+{
+ const int gen = ibb->gen;
+ uint32_t cmd_bits = 0;
+ uint32_t br13_bits;
+ uint32_t mask;
+
+ igt_assert(bpp*(src_x1 + width) <= 8*src_pitch);
+ igt_assert(bpp*(dst_x1 + width) <= 8*dst_pitch);
+ igt_assert(src_pitch * (src_y1 + height) <= src->size);
+ igt_assert(dst_pitch * (dst_y1 + height) <= dst->size);
+
+ if (gen >= 4 && src->tiling != I915_TILING_NONE) {
+ src_pitch /= 4;
+ cmd_bits |= XY_SRC_COPY_BLT_SRC_TILED;
+ }
+
+ if (gen >= 4 && dst->tiling != I915_TILING_NONE) {
+ dst_pitch /= 4;
+ cmd_bits |= XY_SRC_COPY_BLT_DST_TILED;
+ }
+
+ CHECK_RANGE(src_x1); CHECK_RANGE(src_y1);
+ CHECK_RANGE(dst_x1); CHECK_RANGE(dst_y1);
+ CHECK_RANGE(width); CHECK_RANGE(height);
+ CHECK_RANGE(src_x1 + width); CHECK_RANGE(src_y1 + height);
+ CHECK_RANGE(dst_x1 + width); CHECK_RANGE(dst_y1 + height);
+ CHECK_RANGE(src_pitch); CHECK_RANGE(dst_pitch);
+
+ br13_bits = 0;
+ switch (bpp) {
+ case 8:
+ break;
+ case 16: /* supporting only RGB565, not ARGB1555 */
+ br13_bits |= 1 << 24;
+ break;
+ case 32:
+ br13_bits |= 3 << 24;
+ cmd_bits |= XY_SRC_COPY_BLT_WRITE_ALPHA |
+ XY_SRC_COPY_BLT_WRITE_RGB;
+ break;
+ default:
+ igt_fail(IGT_EXIT_FAILURE);
+ }
+
+ if ((src->tiling | dst->tiling) >= I915_TILING_Y) {
+ intel_bb_out(ibb, MI_LOAD_REGISTER_IMM);
+ intel_bb_out(ibb, BCS_SWCTRL);
+
+ mask = (BCS_SRC_Y | BCS_DST_Y) << 16;
+ if (src->tiling == I915_TILING_Y)
+ mask |= BCS_SRC_Y;
+ if (dst->tiling == I915_TILING_Y)
+ mask |= BCS_DST_Y;
+ intel_bb_out(ibb, mask);
+ }
+
+ intel_bb_blit_start(ibb, cmd_bits);
+ intel_bb_out(ibb, (br13_bits) |
+ (0xcc << 16) | /* copy ROP */
+ dst_pitch);
+ intel_bb_out(ibb, (dst_y1 << 16) | dst_x1); /* dst x1,y1 */
+ intel_bb_out(ibb, ((dst_y1 + height) << 16) | (dst_x1 + width)); /* dst x2,y2 */
+ intel_bb_emit_reloc_fenced(ibb, dst->handle,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ 0, dst->addr.offset);
+ intel_bb_out(ibb, (src_y1 << 16) | src_x1); /* src x1,y1 */
+ intel_bb_out(ibb, src_pitch);
+ intel_bb_emit_reloc_fenced(ibb, src->handle,
+ I915_GEM_DOMAIN_RENDER, 0,
+ 0, src->addr.offset);
+
+ if (gen >= 6 && src->handle == dst->handle) {
+ intel_bb_out(ibb, XY_SETUP_CLIP_BLT_CMD);
+ intel_bb_out(ibb, 0);
+ intel_bb_out(ibb, 0);
+ }
+
+ if ((src->tiling | dst->tiling) >= I915_TILING_Y) {
+ igt_assert(ibb->gen >= 6);
+ intel_bb_out(ibb, MI_FLUSH_DW | 2);
+ intel_bb_out(ibb, 0);
+ intel_bb_out(ibb, 0);
+ intel_bb_out(ibb, 0);
+
+ intel_bb_out(ibb, MI_LOAD_REGISTER_IMM);
+ intel_bb_out(ibb, BCS_SWCTRL);
+ intel_bb_out(ibb, (BCS_SRC_Y | BCS_DST_Y) << 16);
+ }
+}
+
+void intel_bb_blt_copy(struct intel_bb *ibb,
+ struct intel_buf *src,
+ int src_x1, int src_y1, int src_pitch,
+ struct intel_buf *dst,
+ int dst_x1, int dst_y1, int dst_pitch,
+ int width, int height, int bpp)
+{
+ intel_bb_emit_blt_copy(ibb, src, src_x1, src_y1, src_pitch,
+ dst, dst_x1, dst_y1, dst_pitch,
+ width, height, bpp);
+ intel_bb_emit_bbe(ibb);
+ intel_bb_flush_blit(ibb);
+}
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 0649fc22..02168b9d 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -433,11 +433,13 @@ struct intel_bb {
int i915;
int gen;
bool debug;
+ bool enforce_relocs;
uint32_t devid;
uint32_t handle;
uint32_t size;
uint32_t *batch;
uint32_t *ptr;
+ int fence;
uint32_t prng;
uint64_t gtt_size;
@@ -454,12 +456,34 @@ struct intel_bb {
struct drm_i915_gem_relocation_entry *relocs;
uint32_t num_relocs;
uint32_t allocated_relocs;
+
+ /*
+ * BO recreate in reset path only when refcount == 0
+ * Currently we don't need to use atomics because intel_bb
+ * is not thread-safe.
+ */
+ int32_t refcount;
};
struct intel_bb *intel_bb_create(int i915, uint32_t size);
-
+struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size);
void intel_bb_destroy(struct intel_bb *ibb);
+
+static inline void intel_bb_ref(struct intel_bb *ibb)
+{
+ ibb->refcount++;
+}
+
+static inline void intel_bb_unref(struct intel_bb *ibb)
+{
+ igt_assert_f(ibb->refcount > 0, "intel_bb refcount is 0!");
+ ibb->refcount--;
+}
+
void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache);
+int intel_bb_sync(struct intel_bb *ibb);
+void intel_bb_print(struct intel_bb *ibb);
+void intel_bb_dump(struct intel_bb *ibb, const char *filename);
void intel_bb_set_debug(struct intel_bb *ibb, bool debug);
static inline uint32_t intel_bb_offset(struct intel_bb *ibb)
@@ -471,7 +495,7 @@ static inline void intel_bb_ptr_set(struct intel_bb *ibb, uint32_t offset)
{
ibb->ptr = (void *) ((uint8_t *) ibb->batch + offset);
- igt_assert(intel_bb_offset(ibb) < ibb->size);
+ igt_assert(intel_bb_offset(ibb) <= ibb->size);
}
static inline void intel_bb_ptr_add(struct intel_bb *ibb, uint32_t offset)
@@ -479,10 +503,22 @@ static inline void intel_bb_ptr_add(struct intel_bb *ibb, uint32_t offset)
intel_bb_ptr_set(ibb, intel_bb_offset(ibb) + offset);
}
-static inline void intel_bb_ptr_align(struct intel_bb *ibb,
+static inline uint32_t intel_bb_ptr_add_return_prev_offset(struct intel_bb *ibb,
+ uint32_t offset)
+{
+ uint32_t previous_offset = intel_bb_offset(ibb);
+
+ intel_bb_ptr_set(ibb, previous_offset + offset);
+
+ return previous_offset;
+}
+
+static inline void *intel_bb_ptr_align(struct intel_bb *ibb,
uint32_t alignment)
{
intel_bb_ptr_set(ibb, ALIGN(intel_bb_offset(ibb), alignment));
+
+ return (void *) ibb->ptr;
}
static inline void *intel_bb_ptr(struct intel_bb *ibb)
@@ -495,7 +531,7 @@ static inline void intel_bb_out(struct intel_bb *ibb, uint32_t dword)
*ibb->ptr = dword;
ibb->ptr++;
- igt_assert(intel_bb_offset(ibb) < ibb->size);
+ igt_assert(intel_bb_offset(ibb) <= ibb->size);
}
@@ -510,6 +546,13 @@ uint64_t intel_bb_emit_reloc(struct intel_bb *ibb,
uint64_t delta,
uint64_t presumed_offset);
+uint64_t intel_bb_emit_reloc_fenced(struct intel_bb *ibb,
+ uint32_t handle,
+ uint32_t read_domains,
+ uint32_t write_domain,
+ uint64_t delta,
+ uint64_t presumed_offset);
+
uint64_t intel_bb_offset_reloc(struct intel_bb *ibb,
uint32_t handle,
uint32_t read_domains,
@@ -517,6 +560,14 @@ uint64_t intel_bb_offset_reloc(struct intel_bb *ibb,
uint32_t offset,
uint64_t presumed_offset);
+uint64_t intel_bb_offset_reloc_with_delta(struct intel_bb *ibb,
+ uint32_t handle,
+ uint32_t read_domains,
+ uint32_t write_domain,
+ uint32_t delta,
+ uint32_t offset,
+ uint64_t presumed_offset);
+
int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
uint32_t ctx, uint64_t flags, bool sync);
@@ -529,4 +580,25 @@ void intel_bb_exec_with_context(struct intel_bb *ibb, uint32_t end_offset,
uint64_t intel_bb_get_object_offset(struct intel_bb *ibb, uint32_t handle);
bool intel_bb_object_offset_to_buf(struct intel_bb *ibb, struct intel_buf *buf);
+uint32_t intel_bb_emit_bbe(struct intel_bb *ibb);
+void intel_bb_flush_render(struct intel_bb *ibb);
+void intel_bb_flush_blit(struct intel_bb *ibb);
+
+uint32_t intel_bb_copy_data(struct intel_bb *ibb,
+ const void *data, unsigned int bytes,
+ uint32_t align);
+
+void intel_bb_blit_start(struct intel_bb *ibb, uint32_t flags);
+void intel_bb_emit_blt_copy(struct intel_bb *ibb,
+ struct intel_buf *src,
+ int src_x1, int src_y1, int src_pitch,
+ struct intel_buf *dst,
+ int dst_x1, int dst_y1, int dst_pitch,
+ int width, int height, int bpp);
+void intel_bb_blt_copy(struct intel_bb *ibb,
+ struct intel_buf *src,
+ int src_x1, int src_y1, int src_pitch,
+ struct intel_buf *dst,
+ int dst_x1, int dst_y1, int dst_pitch,
+ int width, int height, int bpp);
#endif
--
2.26.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [igt-dev] [PATCH i-g-t v16 2/4] lib/intel_bufops: Add new functions and intel_buf fields
2020-07-03 11:30 [igt-dev] [PATCH i-g-t v16 0/4] Add api_intel_bb test Zbigniew Kempczyński
2020-07-03 11:30 ` [igt-dev] [PATCH i-g-t v16 1/4] lib/intel_batchbuffer: Extend intel_bb Zbigniew Kempczyński
@ 2020-07-03 11:31 ` Zbigniew Kempczyński
2020-07-03 11:31 ` [igt-dev] [PATCH i-g-t v16 3/4] tests/api_intel_bb: Add intel_bb API test Zbigniew Kempczyński
` (4 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Zbigniew Kempczyński @ 2020-07-03 11:31 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
This is minor step toward removing libdrm from rendercopy. Lets
add new functions and structure fields to verify we don't introduce
regressions in already migrated code.
Some utility functions - write buf/aux (ccs) to png were added.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_bufops.c | 136 ++++++++++++++++++++++++++++++++++++++++++---
lib/intel_bufops.h | 25 ++++++++-
2 files changed, 151 insertions(+), 10 deletions(-)
diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
index 0337b638..094b3597 100644
--- a/lib/intel_bufops.c
+++ b/lib/intel_bufops.c
@@ -23,6 +23,7 @@
*/
#include <sys/ioctl.h>
+#include <cairo.h>
#include "igt.h"
#include "igt_x86.h"
#include "intel_bufops.h"
@@ -174,10 +175,14 @@ static bool __get_tiling(int fd, uint32_t handle, uint32_t *tiling,
}
static int __set_tiling(int fd, uint32_t handle, uint32_t tiling,
- uint32_t stride)
+ uint32_t stride,
+ uint32_t *ret_tiling, uint32_t *ret_swizzle)
{
+ struct drm_i915_gem_set_tiling st;
+
+ memset(&st, 0, sizeof(st));
do {
- struct drm_i915_gem_set_tiling st;
+
int err;
st.handle = handle;
@@ -188,13 +193,22 @@ static int __set_tiling(int fd, uint32_t handle, uint32_t tiling,
if (ioctl(fd, DRM_IOCTL_I915_GEM_SET_TILING, &st))
err = -errno;
errno = 0;
- if (err != -EINTR)
+ if (err != -EINTR) {
+ if (ret_tiling)
+ *ret_tiling = st.tiling_mode;
+
+ if (ret_swizzle)
+ *ret_swizzle = st.swizzle_mode;
+
return err;
+ }
} while (1);
}
static void set_hw_tiled(struct buf_ops *bops, struct intel_buf *buf)
{
+ uint32_t ret_tiling, ret_swizzle;
+
if (buf->tiling != I915_TILING_X && buf->tiling != I915_TILING_Y)
return;
@@ -202,8 +216,12 @@ static void set_hw_tiled(struct buf_ops *bops, struct intel_buf *buf)
return;
igt_assert_eq(__set_tiling(bops->fd,
- buf->handle, buf->tiling, buf->stride),
+ buf->handle, buf->tiling, buf->stride,
+ &ret_tiling, &ret_swizzle),
0);
+
+ igt_assert(ret_tiling == buf->tiling);
+ buf->swizzle_mode = ret_swizzle;
}
static unsigned long swizzle_bit(unsigned int bit, unsigned long offset)
@@ -690,6 +708,7 @@ static void __intel_buf_init(struct buf_ops *bops,
memset(buf, 0, sizeof(*buf));
buf->bops = bops;
+ buf->addr.offset = INTEL_BUF_INVALID_ADDRESS;
if (compression) {
int aux_width, aux_height;
@@ -697,7 +716,6 @@ static void __intel_buf_init(struct buf_ops *bops,
igt_require(bops->intel_gen >= 9);
igt_assert(req_tiling == I915_TILING_Y ||
req_tiling == I915_TILING_Yf);
-
/*
* On GEN12+ we align the main surface to 4 * 4 main surface
* tiles, which is 64kB. These 16 tiles are mapped by 4 AUX
@@ -724,7 +742,6 @@ static void __intel_buf_init(struct buf_ops *bops,
buf->aux.stride = aux_width;
size = buf->aux.offset + aux_width * aux_height;
-
} else {
if (buf->tiling) {
devid = intel_get_drm_devid(bops->fd);
@@ -826,6 +843,98 @@ void intel_buf_init_using_handle(struct buf_ops *bops,
req_tiling, compression);
}
+struct intel_buf *intel_buf_create(struct buf_ops *bops,
+ int width, int height,
+ int bpp, int alignment,
+ uint32_t req_tiling, uint32_t compression)
+{
+ struct intel_buf *buf;
+
+ igt_assert(bops);
+
+ buf = calloc(1, sizeof(*buf));
+ igt_assert(buf);
+
+ intel_buf_init(bops, buf, width, height, bpp, alignment,
+ req_tiling, compression);
+
+ return buf;
+}
+
+void intel_buf_destroy(struct intel_buf *buf)
+{
+ igt_assert(buf);
+
+ intel_buf_close(buf->bops, buf);
+ free(buf);
+}
+
+void intel_buf_print(const struct intel_buf *buf)
+{
+ igt_info("[name: %s]\n", buf->name);
+ igt_info("[%u]: w: %u, h: %u, stride: %u, size: %u, bo-size: %u, "
+ "bpp: %u, tiling: %u, compress: %u\n",
+ buf->handle, intel_buf_width(buf), intel_buf_height(buf),
+ buf->stride, buf->size,
+ intel_buf_bo_size(buf), buf->bpp,
+ buf->tiling, buf->compression);
+ igt_info(" aux <offset: %u, stride: %u, w: %u, h: %u> cc <offset: %u>\n",
+ buf->aux.offset,
+ intel_buf_aux_width(buf->bops->intel_gen, buf),
+ intel_buf_aux_height(buf->bops->intel_gen, buf),
+ buf->aux.stride, buf->cc.offset);
+ igt_info(" addr <offset: %p, ctx: %u>\n",
+ from_user_pointer(buf->addr.offset), buf->addr.ctx);
+}
+
+const char *intel_buf_set_name(struct intel_buf *buf, const char *name)
+{
+ return strncpy(buf->name, name, INTEL_BUF_NAME_MAXSIZE);
+}
+
+static void __intel_buf_write_to_png(struct buf_ops *bops,
+ struct intel_buf *buf,
+ const char *filename,
+ bool write_aux)
+{
+ cairo_surface_t *surface;
+ cairo_status_t ret;
+ void *linear;
+ int format, width, height, stride, offset;
+ int gen = bops->intel_gen;
+
+ igt_assert_eq(posix_memalign(&linear, 16, intel_buf_bo_size(buf)), 0);
+
+ format = write_aux ? CAIRO_FORMAT_A8 : CAIRO_FORMAT_RGB24;
+ width = write_aux ? intel_buf_aux_width(gen, buf) : intel_buf_width(buf);
+ height = write_aux ? intel_buf_aux_height(gen, buf) : intel_buf_height(buf);
+ stride = write_aux ? buf->aux.stride : buf->stride;
+ offset = write_aux ? buf->aux.offset : 0;
+
+ intel_buf_to_linear(bops, buf, linear);
+
+ surface = cairo_image_surface_create_for_data((uint8_t *) linear + offset,
+ format, width, height,
+ stride);
+ ret = cairo_surface_write_to_png(surface, filename);
+ igt_assert(ret == CAIRO_STATUS_SUCCESS);
+ cairo_surface_destroy(surface);
+
+ free(linear);
+}
+
+void intel_buf_write_to_png(struct intel_buf *buf, const char *filename)
+{
+ __intel_buf_write_to_png(buf->bops, buf, filename, false);
+}
+
+void intel_buf_write_aux_to_png(struct intel_buf *buf, const char *filename)
+{
+ igt_assert(buf->compression);
+
+ __intel_buf_write_to_png(buf->bops, buf, filename, true);
+}
+
#define DEFAULT_BUFOPS(__gen_start, __gen_end) \
.gen_start = __gen_start, \
.gen_end = __gen_end, \
@@ -876,7 +985,7 @@ static bool probe_hw_tiling(struct buf_ops *bops, uint32_t tiling)
handle = gem_create(bops->fd, size);
/* Single shot, if no fences are available we fail immediately */
- ret = __set_tiling(bops->fd, handle, tiling, stride);
+ ret = __set_tiling(bops->fd, handle, tiling, stride, NULL, NULL);
if (ret)
goto end;
@@ -956,6 +1065,15 @@ static void idempotency_selftest(struct buf_ops *bops, uint32_t tiling)
buf_ops_set_software_tiling(bops, tiling, false);
}
+int intel_buf_bo_size(const struct intel_buf *buf)
+{
+ int offset = CCS_OFFSET(buf) ?: buf->size;
+ int ccs_size = buf->compression ?
+ CCS_SIZE(buf->bops->intel_gen, buf) : 0;
+
+ return offset + ccs_size;
+}
+
/**
* buf_ops_create
* @fd: device filedescriptor
@@ -1061,12 +1179,12 @@ void buf_ops_destroy(struct buf_ops *bops)
}
/**
- * buf_ops_getfd
+ * buf_ops_get_fd
* @bops: pointer to buf_ops
*
* Returns: drm fd
*/
-int buf_ops_getfd(struct buf_ops *bops)
+int buf_ops_get_fd(struct buf_ops *bops)
{
igt_assert(bops);
diff --git a/lib/intel_bufops.h b/lib/intel_bufops.h
index 95217cfe..d82f49a4 100644
--- a/lib/intel_bufops.h
+++ b/lib/intel_bufops.h
@@ -6,6 +6,8 @@
struct buf_ops;
+#define INTEL_BUF_INVALID_ADDRESS -1
+#define INTEL_BUF_NAME_MAXSIZE 32
struct intel_buf {
struct buf_ops *bops;
uint32_t handle;
@@ -14,14 +16,21 @@ struct intel_buf {
uint32_t bpp;
uint32_t size;
uint32_t compression;
+ uint32_t swizzle_mode;
struct {
uint32_t offset;
uint32_t stride;
} aux;
+ struct {
+ uint32_t offset;
+ } cc;
struct {
uint64_t offset;
uint32_t ctx;
} addr;
+
+ /* For debugging purposes */
+ char name[INTEL_BUF_NAME_MAXSIZE + 1];
};
static inline unsigned int intel_buf_width(const struct intel_buf *buf)
@@ -62,9 +71,11 @@ intel_buf_aux_height(int gen, const struct intel_buf *buf)
return DIV_ROUND_UP(intel_buf_height(buf), 512) * 32;
}
+int intel_buf_bo_size(const struct intel_buf *buf);
+
struct buf_ops *buf_ops_create(int fd);
void buf_ops_destroy(struct buf_ops *bops);
-int buf_ops_getfd(struct buf_ops *bops);
+int buf_ops_get_fd(struct buf_ops *bops);
bool buf_ops_set_software_tiling(struct buf_ops *bops,
uint32_t tiling,
@@ -90,4 +101,16 @@ void intel_buf_init_using_handle(struct buf_ops *bops,
int width, int height, int bpp, int alignment,
uint32_t req_tiling, uint32_t compression);
+struct intel_buf *intel_buf_create(struct buf_ops *bops,
+ int width, int height,
+ int bpp, int alignment,
+ uint32_t req_tiling, uint32_t compression);
+void intel_buf_destroy(struct intel_buf *buf);
+
+void intel_buf_print(const struct intel_buf *buf);
+const char *intel_buf_set_name(struct intel_buf *buf, const char *name);
+
+void intel_buf_write_to_png(struct intel_buf *buf, const char *filename);
+void intel_buf_write_aux_to_png(struct intel_buf *buf, const char *filename);
+
#endif
--
2.26.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [igt-dev] [PATCH i-g-t v16 3/4] tests/api_intel_bb: Add intel_bb API test
2020-07-03 11:30 [igt-dev] [PATCH i-g-t v16 0/4] Add api_intel_bb test Zbigniew Kempczyński
2020-07-03 11:30 ` [igt-dev] [PATCH i-g-t v16 1/4] lib/intel_batchbuffer: Extend intel_bb Zbigniew Kempczyński
2020-07-03 11:31 ` [igt-dev] [PATCH i-g-t v16 2/4] lib/intel_bufops: Add new functions and intel_buf fields Zbigniew Kempczyński
@ 2020-07-03 11:31 ` Zbigniew Kempczyński
2020-07-03 11:31 ` [igt-dev] [PATCH i-g-t v16 4/4] intel-ci/fast-feedback: add api_intel_bb tests Zbigniew Kempczyński
` (3 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Zbigniew Kempczyński @ 2020-07-03 11:31 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
IGT code contains some mechanisms which are quite large and cover
different gens so they deserve own api_* checks.
Starting with api_intel_bb verify intel_bb functions work as expected.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/i915/api_intel_bb.c | 709 ++++++++++++++++++++++++++++++++++++++
tests/meson.build | 1 +
2 files changed, 710 insertions(+)
create mode 100644 tests/i915/api_intel_bb.c
diff --git a/tests/i915/api_intel_bb.c b/tests/i915/api_intel_bb.c
new file mode 100644
index 00000000..d16b558c
--- /dev/null
+++ b/tests/i915/api_intel_bb.c
@@ -0,0 +1,709 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include <unistd.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <cairo.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/ioctl.h>
+#include "intel_bufops.h"
+
+#define PAGE_SIZE 4096
+
+#define WIDTH 64
+#define HEIGHT 64
+#define COLOR_00 0x00
+#define COLOR_33 0x33
+#define COLOR_77 0x77
+#define COLOR_CC 0xcc
+
+IGT_TEST_DESCRIPTION("intel_bb API check.");
+
+enum reloc_objects {
+ RELOC,
+ NORELOC,
+};
+
+enum obj_cache_ops {
+ PURGE_CACHE,
+ KEEP_CACHE,
+};
+
+static bool debug_bb = false;
+static bool write_png = false;
+static bool buf_info = false;
+
+static void *alloc_aligned(uint64_t size)
+{
+ void *p;
+
+ igt_assert_eq(posix_memalign(&p, 16, size), 0);
+
+ return p;
+}
+
+static void fill_buf(struct intel_buf *buf, uint8_t color)
+{
+ uint8_t *ptr;
+ int i915 = buf_ops_get_fd(buf->bops);
+ int i;
+
+ ptr = gem_mmap__device_coherent(i915, buf->handle, 0, buf->size,
+ PROT_WRITE);
+
+ for (i = 0; i < buf->size; i++)
+ ptr[i] = color;
+
+ munmap(ptr, buf->size);
+}
+
+static void check_buf(struct intel_buf *buf, uint8_t color)
+{
+ uint8_t *ptr;
+ int i915 = buf_ops_get_fd(buf->bops);
+ int i;
+
+ ptr = gem_mmap__device_coherent(i915, buf->handle, 0, buf->size,
+ PROT_READ);
+
+ for (i = 0; i < buf->size; i++)
+ igt_assert(ptr[i] == color);
+
+ munmap(ptr, buf->size);
+}
+
+
+static struct intel_buf *
+create_buf(struct buf_ops *bops, int width, int height, uint8_t color)
+{
+ struct intel_buf *buf;
+
+ buf = calloc(1, sizeof(*buf));
+ igt_assert(buf);
+
+ intel_buf_init(bops, buf, width/4, height, 32, 0, I915_TILING_NONE, 0);
+ fill_buf(buf, color);
+
+ return buf;
+}
+
+static void print_buf(struct intel_buf *buf, const char *name)
+{
+ uint8_t *ptr;
+ int i915 = buf_ops_get_fd(buf->bops);
+
+ ptr = gem_mmap__device_coherent(i915, buf->handle, 0, buf->size,
+ PROT_READ);
+ igt_debug("[%s] Buf handle: %d, size: %d, v: 0x%02x, presumed_addr: %p\n",
+ name, buf->handle, buf->size, ptr[0],
+ from_user_pointer(buf->addr.offset));
+ munmap(ptr, buf->size);
+}
+
+static void simple_bb(struct buf_ops *bops, bool use_context)
+{
+ int i915 = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+ uint32_t ctx;
+
+ if (use_context) {
+ gem_require_contexts(i915);
+ ctx = gem_context_create(i915);
+ }
+
+ ibb = intel_bb_create(i915, PAGE_SIZE);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+ intel_bb_ptr_align(ibb, 8);
+
+ intel_bb_exec(ibb, intel_bb_offset(ibb),
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+
+ /* Check we're safe with reset and no double-free will occur */
+ intel_bb_reset(ibb, true);
+ intel_bb_reset(ibb, false);
+ intel_bb_reset(ibb, true);
+
+ intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+ intel_bb_ptr_align(ibb, 8);
+
+ if (use_context)
+ intel_bb_exec_with_context(ibb, intel_bb_offset(ibb), ctx,
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC,
+ true);
+
+ intel_bb_destroy(ibb);
+ if (use_context)
+ gem_context_destroy(i915, ctx);
+}
+
+#define MI_FLUSH_DW (0x26<<23)
+#define BCS_SWCTRL 0x22200
+#define BCS_SRC_Y (1 << 0)
+#define BCS_DST_Y (1 << 1)
+static void __emit_blit(struct intel_bb *ibb,
+ struct intel_buf *src, struct intel_buf *dst)
+{
+ uint32_t mask;
+ bool has_64b_reloc;
+
+ has_64b_reloc = ibb->gen >= 8;
+
+ if ((src->tiling | dst->tiling) >= I915_TILING_Y) {
+ intel_bb_out(ibb, MI_LOAD_REGISTER_IMM);
+ intel_bb_out(ibb, BCS_SWCTRL);
+
+ mask = (BCS_SRC_Y | BCS_DST_Y) << 16;
+ if (src->tiling == I915_TILING_Y)
+ mask |= BCS_SRC_Y;
+ if (dst->tiling == I915_TILING_Y)
+ mask |= BCS_DST_Y;
+ intel_bb_out(ibb, mask);
+ }
+
+ intel_bb_out(ibb,
+ XY_SRC_COPY_BLT_CMD |
+ XY_SRC_COPY_BLT_WRITE_ALPHA |
+ XY_SRC_COPY_BLT_WRITE_RGB |
+ (6 + 2 * has_64b_reloc));
+ intel_bb_out(ibb, 3 << 24 | 0xcc << 16 | dst->stride);
+ intel_bb_out(ibb, 0);
+ intel_bb_out(ibb, intel_buf_height(dst) << 16 | intel_buf_width(dst));
+ intel_bb_emit_reloc_fenced(ibb, dst->handle,
+ I915_GEM_DOMAIN_RENDER,
+ I915_GEM_DOMAIN_RENDER,
+ 0, dst->addr.offset);
+ intel_bb_out(ibb, 0);
+ intel_bb_out(ibb, src->stride);
+ intel_bb_emit_reloc_fenced(ibb, src->handle,
+ I915_GEM_DOMAIN_RENDER, 0,
+ 0, src->addr.offset);
+
+ if ((src->tiling | dst->tiling) >= I915_TILING_Y) {
+ igt_assert(ibb->gen >= 6);
+ intel_bb_out(ibb, MI_FLUSH_DW | 2);
+ intel_bb_out(ibb, 0);
+ intel_bb_out(ibb, 0);
+ intel_bb_out(ibb, 0);
+
+ intel_bb_out(ibb, MI_LOAD_REGISTER_IMM);
+ intel_bb_out(ibb, BCS_SWCTRL);
+ intel_bb_out(ibb, (BCS_SRC_Y | BCS_DST_Y) << 16);
+ }
+}
+
+static void blit(struct buf_ops *bops,
+ enum reloc_objects reloc_obj,
+ enum obj_cache_ops cache_op)
+{
+ int i915 = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+ struct intel_buf *src, *dst;
+ uint64_t poff_bb, poff_src, poff_dst;
+ uint64_t poff2_bb, poff2_src, poff2_dst;
+ uint64_t flags = 0;
+ bool purge_cache = cache_op == PURGE_CACHE ? true : false;
+ bool do_relocs = reloc_obj == RELOC ? true : false;
+
+ src = create_buf(bops, WIDTH, HEIGHT, COLOR_CC);
+ dst = create_buf(bops, WIDTH, HEIGHT, COLOR_00);
+
+ if (buf_info) {
+ print_buf(src, "src");
+ print_buf(dst, "dst");
+ }
+
+ if (do_relocs) {
+ ibb = intel_bb_create_with_relocs(i915, PAGE_SIZE);
+ } else {
+ ibb = intel_bb_create(i915, PAGE_SIZE);
+ flags |= I915_EXEC_NO_RELOC;
+ }
+
+ if (ibb->gen >= 6)
+ flags |= I915_EXEC_BLT;
+
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ __emit_blit(ibb, src, dst);
+
+ /* We expect initial addresses are zeroed for relocs */
+ poff_bb = intel_bb_get_object_offset(ibb, ibb->handle);
+ poff_src = intel_bb_get_object_offset(ibb, src->handle);
+ poff_dst = intel_bb_get_object_offset(ibb, dst->handle);
+ igt_debug("bb presumed offset: 0x%lx\n", poff_bb);
+ igt_debug("src presumed offset: 0x%lx\n", poff_src);
+ igt_debug("dst presumed offset: 0x%lx\n", poff_dst);
+ if (reloc_obj == RELOC) {
+ igt_assert(poff_bb == 0);
+ igt_assert(poff_src == 0);
+ igt_assert(poff_dst == 0);
+ }
+
+ intel_bb_emit_bbe(ibb);
+ igt_debug("exec flags: %" PRIX64 "\n", flags);
+ intel_bb_exec(ibb, intel_bb_offset(ibb), flags, true);
+ check_buf(dst, COLOR_CC);
+
+ poff_bb = intel_bb_get_object_offset(ibb, ibb->handle);
+ poff_src = intel_bb_get_object_offset(ibb, src->handle);
+ poff_dst = intel_bb_get_object_offset(ibb, dst->handle);
+ intel_bb_reset(ibb, purge_cache);
+
+ fill_buf(src, COLOR_77);
+ fill_buf(dst, COLOR_00);
+
+ __emit_blit(ibb, src, dst);
+
+ poff2_bb = intel_bb_get_object_offset(ibb, ibb->handle);
+ poff2_src = intel_bb_get_object_offset(ibb, src->handle);
+ poff2_dst = intel_bb_get_object_offset(ibb, dst->handle);
+
+ igt_debug("purge: %d, relocs: %d\n", purge_cache, do_relocs);
+ igt_debug("bb presumed offset: 0x%lx\n", poff_bb);
+ igt_debug("src presumed offset: 0x%lx\n", poff_src);
+ igt_debug("dst presumed offset: 0x%lx\n", poff_dst);
+ igt_debug("bb2 presumed offset: 0x%lx\n", poff2_bb);
+ igt_debug("src2 presumed offset: 0x%lx\n", poff2_src);
+ igt_debug("dst2 presumed offset: 0x%lx\n", poff2_dst);
+ if (purge_cache) {
+ if (do_relocs) {
+ igt_assert(poff2_bb == 0);
+ igt_assert(poff2_src == 0);
+ igt_assert(poff2_dst == 0);
+ } else {
+ igt_assert(poff_bb != poff2_bb);
+ igt_assert(poff_src != poff2_src);
+ igt_assert(poff_dst != poff2_dst);
+ }
+ } else {
+ igt_assert(poff_bb == poff2_bb);
+ igt_assert(poff_src == poff2_src);
+ igt_assert(poff_dst == poff2_dst);
+ }
+
+ intel_bb_emit_bbe(ibb);
+ intel_bb_exec(ibb, intel_bb_offset(ibb), flags, true);
+ check_buf(dst, COLOR_77);
+
+ poff2_src = intel_bb_get_object_offset(ibb, src->handle);
+ poff2_dst = intel_bb_get_object_offset(ibb, dst->handle);
+ igt_assert(poff_src == poff2_src);
+ igt_assert(poff_dst == poff2_dst);
+
+ intel_buf_close(bops, src);
+ intel_buf_close(bops, dst);
+ intel_bb_destroy(ibb);
+}
+
+static void scratch_buf_init(struct buf_ops *bops,
+ struct intel_buf *buf,
+ int width, int height,
+ uint32_t req_tiling,
+ enum i915_compression compression)
+{
+ int bpp = 32;
+
+ intel_buf_init(bops, buf, width, height, bpp, 0,
+ req_tiling, compression);
+
+ igt_assert(intel_buf_width(buf) == width);
+ igt_assert(intel_buf_height(buf) == height);
+}
+
+static void scratch_buf_draw_pattern(struct buf_ops *bops,
+ struct intel_buf *buf,
+ int x, int y, int w, int h,
+ int cx, int cy, int cw, int ch,
+ bool use_alternate_colors)
+{
+ cairo_surface_t *surface;
+ cairo_pattern_t *pat;
+ cairo_t *cr;
+ void *linear;
+
+ linear = alloc_aligned(buf->size);
+
+ surface = cairo_image_surface_create_for_data(linear,
+ CAIRO_FORMAT_RGB24,
+ intel_buf_width(buf),
+ intel_buf_height(buf),
+ buf->stride);
+
+ cr = cairo_create(surface);
+
+ cairo_rectangle(cr, cx, cy, cw, ch);
+ cairo_clip(cr);
+
+ pat = cairo_pattern_create_mesh();
+ cairo_mesh_pattern_begin_patch(pat);
+ cairo_mesh_pattern_move_to(pat, x, y);
+ cairo_mesh_pattern_line_to(pat, x+w, y);
+ cairo_mesh_pattern_line_to(pat, x+w, y+h);
+ cairo_mesh_pattern_line_to(pat, x, y+h);
+ if (use_alternate_colors) {
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 0, 0.0, 1.0, 1.0);
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 1, 1.0, 0.0, 1.0);
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 2, 1.0, 1.0, 0.0);
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 3, 0.0, 0.0, 0.0);
+ } else {
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 0, 1.0, 0.0, 0.0);
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 1, 0.0, 1.0, 0.0);
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 2, 0.0, 0.0, 1.0);
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 3, 1.0, 1.0, 1.0);
+ }
+ cairo_mesh_pattern_end_patch(pat);
+
+ cairo_rectangle(cr, x, y, w, h);
+ cairo_set_source(cr, pat);
+ cairo_fill(cr);
+ cairo_pattern_destroy(pat);
+
+ cairo_destroy(cr);
+
+ cairo_surface_destroy(surface);
+
+ linear_to_intel_buf(bops, buf, linear);
+
+ free(linear);
+}
+
+#define GROUP_SIZE 4096
+static int compare_detail(const uint32_t *ptr1, uint32_t *ptr2,
+ uint32_t size)
+{
+ int i, ok = 0, fail = 0;
+ int groups = size / GROUP_SIZE;
+ int *hist = calloc(GROUP_SIZE, groups);
+
+ igt_debug("size: %d, group_size: %d, groups: %d\n",
+ size, GROUP_SIZE, groups);
+
+ for (i = 0; i < size / sizeof(uint32_t); i++) {
+ if (ptr1[i] == ptr2[i]) {
+ ok++;
+ } else {
+ fail++;
+ hist[i * sizeof(uint32_t) / GROUP_SIZE]++;
+ }
+ }
+
+ for (i = 0; i < groups; i++) {
+ if (hist[i]) {
+ igt_debug("[group %4x]: %d\n", i, hist[i]);
+ }
+ }
+ free(hist);
+
+ igt_debug("ok: %d, fail: %d\n", ok, fail);
+
+ return fail;
+}
+
+static int compare_bufs(struct intel_buf *buf1, struct intel_buf *buf2,
+ bool detail_compare)
+{
+ void *ptr1, *ptr2;
+ int fd1, fd2, ret;
+
+ igt_assert(buf1->size == buf2->size);
+
+ fd1 = buf_ops_get_fd(buf1->bops);
+ fd2 = buf_ops_get_fd(buf2->bops);
+
+ ptr1 = gem_mmap__device_coherent(fd1, buf1->handle, 0, buf1->size,
+ PROT_READ);
+ ptr2 = gem_mmap__device_coherent(fd2, buf2->handle, 0, buf2->size,
+ PROT_READ);
+ ret = memcmp(ptr1, ptr2, buf1->size);
+ if (detail_compare)
+ ret = compare_detail(ptr1, ptr2, buf1->size);
+
+ munmap(ptr1, buf1->size);
+ munmap(ptr2, buf2->size);
+
+ return ret;
+}
+
+static int __do_intel_bb_blit(struct buf_ops *bops, uint32_t tiling)
+{
+ struct intel_bb *ibb;
+ const int width = 1024;
+ const int height = 1024;
+ struct intel_buf src, dst, final;
+ char name[128];
+ int i915 = buf_ops_get_fd(bops), fails;
+
+ ibb = intel_bb_create(i915, PAGE_SIZE);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ scratch_buf_init(bops, &src, width, height, I915_TILING_NONE,
+ I915_COMPRESSION_NONE);
+ scratch_buf_init(bops, &dst, width, height, tiling,
+ I915_COMPRESSION_NONE);
+ scratch_buf_init(bops, &final, width, height, I915_TILING_NONE,
+ I915_COMPRESSION_NONE);
+
+ if (buf_info) {
+ intel_buf_print(&src);
+ intel_buf_print(&dst);
+ }
+
+ scratch_buf_draw_pattern(bops, &src,
+ 0, 0, width, height,
+ 0, 0, width, height, 0);
+
+ intel_bb_blt_copy(ibb,
+ &src, 0, 0, src.stride,
+ &dst, 0, 0, dst.stride,
+ intel_buf_width(&dst),
+ intel_buf_height(&dst),
+ dst.bpp);
+
+ intel_bb_blt_copy(ibb,
+ &dst, 0, 0, dst.stride,
+ &final, 0, 0, final.stride,
+ intel_buf_width(&dst),
+ intel_buf_height(&dst),
+ dst.bpp);
+
+ igt_assert(intel_bb_sync(ibb) == 0);
+ intel_bb_destroy(ibb);
+
+ if (write_png) {
+ snprintf(name, sizeof(name) - 1,
+ "bb_blit_dst_tiling_%d.png", tiling);
+ intel_buf_write_to_png(&src, "bb_blit_src_tiling_none.png");
+ intel_buf_write_to_png(&dst, name);
+ intel_buf_write_to_png(&final, "bb_blit_final_tiling_none.png");
+ }
+
+ /* We'll fail on src <-> final compare so just warn */
+ if (tiling == I915_TILING_NONE) {
+ if (compare_bufs(&src, &dst, false) > 0)
+ igt_warn("none->none blit failed!");
+ } else {
+ if (compare_bufs(&src, &dst, false) == 0)
+ igt_warn("none->tiled blit failed!");
+ }
+
+ fails = compare_bufs(&src, &final, true);
+
+ intel_buf_close(bops, &src);
+ intel_buf_close(bops, &dst);
+ intel_buf_close(bops, &final);
+
+ return fails;
+}
+
+static void do_intel_bb_blit(struct buf_ops *bops, int loops, uint32_t tiling)
+{
+ int i, fails = 0, i915 = buf_ops_get_fd(bops);
+
+ gem_require_blitter(i915);
+
+ /* We'll fix it for gen2/3 later. */
+ igt_require(intel_gen(intel_get_drm_devid(i915)) > 3);
+
+ for (i = 0; i < loops; i++) {
+ fails += __do_intel_bb_blit(bops, tiling);
+ }
+ igt_assert_f(fails == 0, "intel-bb-blit (tiling: %d) fails: %d\n",
+ tiling, fails);
+}
+
+static void offset_control(struct buf_ops *bops)
+{
+ int i915 = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+ struct intel_buf *src, *dst1, *dst2, *dst3;
+ uint64_t poff_src, poff_dst1, poff_dst2;
+
+ ibb = intel_bb_create(i915, PAGE_SIZE);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ src = create_buf(bops, WIDTH, HEIGHT, COLOR_CC);
+ dst1 = create_buf(bops, WIDTH, HEIGHT, COLOR_00);
+ dst2 = create_buf(bops, WIDTH, HEIGHT, COLOR_77);
+
+ intel_bb_add_object(ibb, src->handle, src->addr.offset, false);
+ intel_bb_add_object(ibb, dst1->handle, dst1->addr.offset, true);
+ intel_bb_add_object(ibb, dst2->handle, dst2->addr.offset, true);
+
+ intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+ intel_bb_ptr_align(ibb, 8);
+
+ intel_bb_exec(ibb, intel_bb_offset(ibb),
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, false);
+
+ if (buf_info) {
+ print_buf(src, "src ");
+ print_buf(dst1, "dst1");
+ print_buf(dst2, "dst2");
+ }
+
+ igt_assert(intel_bb_object_offset_to_buf(ibb, src) == true);
+ igt_assert(intel_bb_object_offset_to_buf(ibb, dst1) == true);
+ igt_assert(intel_bb_object_offset_to_buf(ibb, dst2) == true);
+ poff_src = src->addr.offset;
+ poff_dst1 = dst1->addr.offset;
+ poff_dst2 = dst2->addr.offset;
+ intel_bb_reset(ibb, true);
+
+ dst3 = create_buf(bops, WIDTH, HEIGHT, COLOR_33);
+ intel_bb_add_object(ibb, dst3->handle, dst3->addr.offset, true);
+ intel_bb_add_object(ibb, src->handle, src->addr.offset, false);
+ intel_bb_add_object(ibb, dst1->handle, dst1->addr.offset, true);
+ intel_bb_add_object(ibb, dst2->handle, dst2->addr.offset, true);
+
+ intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+ intel_bb_ptr_align(ibb, 8);
+
+ intel_bb_exec(ibb, intel_bb_offset(ibb),
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, false);
+ intel_bb_sync(ibb);
+
+ igt_assert(intel_bb_object_offset_to_buf(ibb, src) == true);
+ igt_assert(intel_bb_object_offset_to_buf(ibb, dst1) == true);
+ igt_assert(intel_bb_object_offset_to_buf(ibb, dst2) == true);
+ igt_assert(intel_bb_object_offset_to_buf(ibb, dst3) == true);
+ igt_assert(poff_src == src->addr.offset);
+ igt_assert(poff_dst1 == dst1->addr.offset);
+ igt_assert(poff_dst2 == dst2->addr.offset);
+
+ if (buf_info) {
+ print_buf(src, "src ");
+ print_buf(dst1, "dst1");
+ print_buf(dst2, "dst2");
+ }
+
+ intel_bb_destroy(ibb);
+}
+
+static void full_batch(struct buf_ops *bops)
+{
+ int i915 = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+ int i;
+
+ ibb = intel_bb_create(i915, PAGE_SIZE);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ for (i = 0; i < PAGE_SIZE / sizeof(uint32_t) - 1; i++)
+ intel_bb_out(ibb, 0);
+ intel_bb_emit_bbe(ibb);
+
+ igt_assert(intel_bb_offset(ibb) == PAGE_SIZE);
+ intel_bb_exec(ibb, intel_bb_offset(ibb),
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, false);
+
+ intel_bb_destroy(ibb);
+}
+
+static int opt_handler(int opt, int opt_index, void *data)
+{
+ switch (opt) {
+ case 'd':
+ debug_bb = true;
+ break;
+ case 'p':
+ write_png = true;
+ break;
+ case 'i':
+ buf_info = true;
+ break;
+ default:
+ return IGT_OPT_HANDLER_ERROR;
+ }
+
+ return IGT_OPT_HANDLER_SUCCESS;
+}
+
+const char *help_str =
+ " -d\tDebug bb\n"
+ " -p\tWrite surfaces to png\n"
+ " -i\tPrint buffer info\n"
+ ;
+
+igt_main_args("dpi", NULL, help_str, opt_handler, NULL)
+{
+ int i915;
+ struct buf_ops *bops;
+
+ igt_fixture {
+ i915 = drm_open_driver(DRIVER_INTEL);
+ bops = buf_ops_create(i915);
+ }
+
+ igt_subtest("simple-bb")
+ simple_bb(bops, false);
+
+ igt_subtest("simple-bb-ctx")
+ simple_bb(bops, true);
+
+ igt_subtest("blit-noreloc-keep-cache")
+ blit(bops, NORELOC, KEEP_CACHE);
+
+ igt_subtest("blit-reloc-purge-cache")
+ blit(bops, RELOC, PURGE_CACHE);
+
+ igt_subtest("blit-noreloc-purge-cache")
+ blit(bops, NORELOC, PURGE_CACHE);
+
+ igt_subtest("blit-reloc-keep-cache")
+ blit(bops, RELOC, KEEP_CACHE);
+
+ igt_subtest("intel-bb-blit-none")
+ do_intel_bb_blit(bops, 10, I915_TILING_NONE);
+
+ igt_subtest("intel-bb-blit-x")
+ do_intel_bb_blit(bops, 10, I915_TILING_X);
+
+ igt_subtest("intel-bb-blit-y") {
+ igt_require(intel_gen(intel_get_drm_devid(i915)) >= 6);
+ do_intel_bb_blit(bops, 10, I915_TILING_Y);
+ }
+
+ igt_subtest("offset-control")
+ offset_control(bops);
+
+ igt_subtest("full-batch")
+ full_batch(bops);
+
+ igt_fixture {
+ buf_ops_destroy(bops);
+ close(i915);
+ }
+}
diff --git a/tests/meson.build b/tests/meson.build
index 28091794..06a47e37 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -103,6 +103,7 @@ test_progs = [
]
i915_progs = [
+ 'api_intel_bb',
'gen3_mixed_blits',
'gen3_render_linear_blits',
'gen3_render_mixed_blits',
--
2.26.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [igt-dev] [PATCH i-g-t v16 4/4] intel-ci/fast-feedback: add api_intel_bb tests
2020-07-03 11:30 [igt-dev] [PATCH i-g-t v16 0/4] Add api_intel_bb test Zbigniew Kempczyński
` (2 preceding siblings ...)
2020-07-03 11:31 ` [igt-dev] [PATCH i-g-t v16 3/4] tests/api_intel_bb: Add intel_bb API test Zbigniew Kempczyński
@ 2020-07-03 11:31 ` Zbigniew Kempczyński
2020-07-03 18:19 ` Chris Wilson
2020-07-03 12:46 ` [igt-dev] ✓ Fi.CI.BAT: success for Add api_intel_bb test Patchwork
` (2 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: Zbigniew Kempczyński @ 2020-07-03 11:31 UTC (permalink / raw)
To: igt-dev; +Cc: Petri Latvala, Chris Wilson
intel_bb has to replace libdrm intel_batchbuffer. We need to know
any changes in its infrastructure doesn't lead to regression.
Add api_intel_bb to BAT to be verified on the very beginning.
Test execution time is very short so it shouldn't be noticable
on CI.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Petri Latvala <petri.latvala@intel.com>
---
tests/intel-ci/fast-feedback.testlist | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-feedback.testlist
index 04f6affc..f08d582d 100644
--- a/tests/intel-ci/fast-feedback.testlist
+++ b/tests/intel-ci/fast-feedback.testlist
@@ -1,5 +1,16 @@
# Keep alphabetically sorted by default
+igt@api_intel_bb@simple-bb
+igt@api_intel_bb@simple-bb-ctx
+igt@api_intel_bb@blit-noreloc-keep-cache
+igt@api_intel_bb@blit-reloc-purge-cache
+igt@api_intel_bb@blit-noreloc-purge-cache
+igt@api_intel_bb@blit-reloc-keep-cache
+igt@api_intel_bb@intel-bb-blit-none
+igt@api_intel_bb@intel-bb-blit-x
+igt@api_intel_bb@intel-bb-blit-y
+igt@api_intel_bb@offset-control
+igt@api_intel_bb@full-batch
igt@core_auth@basic-auth
igt@debugfs_test@read_all_entries
igt@fbdev@mmap
--
2.26.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Add api_intel_bb test
2020-07-03 11:30 [igt-dev] [PATCH i-g-t v16 0/4] Add api_intel_bb test Zbigniew Kempczyński
` (3 preceding siblings ...)
2020-07-03 11:31 ` [igt-dev] [PATCH i-g-t v16 4/4] intel-ci/fast-feedback: add api_intel_bb tests Zbigniew Kempczyński
@ 2020-07-03 12:46 ` Patchwork
2020-07-03 14:55 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2020-07-13 11:35 ` [igt-dev] [PATCH i-g-t v16 0/4] " Lionel Landwerlin
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2020-07-03 12:46 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
== Series Details ==
Series: Add api_intel_bb test
URL : https://patchwork.freedesktop.org/series/79089/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8706 -> IGTPW_4734
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/index.html
New tests
---------
New tests have been introduced between CI_DRM_8706 and IGTPW_4734:
### New IGT tests (11) ###
* igt@api_intel_bb@blit-noreloc-keep-cache:
- Statuses : 38 pass(s)
- Exec time: [0.00, 0.03] s
* igt@api_intel_bb@blit-noreloc-purge-cache:
- Statuses : 38 pass(s)
- Exec time: [0.00, 0.03] s
* igt@api_intel_bb@blit-reloc-keep-cache:
- Statuses : 38 pass(s)
- Exec time: [0.00, 0.03] s
* igt@api_intel_bb@blit-reloc-purge-cache:
- Statuses : 38 pass(s)
- Exec time: [0.00, 0.04] s
* igt@api_intel_bb@full-batch:
- Statuses : 38 pass(s)
- Exec time: [0.0, 0.01] s
* igt@api_intel_bb@intel-bb-blit-none:
- Statuses : 35 pass(s) 3 skip(s)
- Exec time: [0.0, 16.35] s
* igt@api_intel_bb@intel-bb-blit-x:
- Statuses : 35 pass(s) 3 skip(s)
- Exec time: [0.0, 15.28] s
* igt@api_intel_bb@intel-bb-blit-y:
- Statuses : 32 pass(s) 6 skip(s)
- Exec time: [0.0, 15.34] s
* igt@api_intel_bb@offset-control:
- Statuses : 38 pass(s)
- Exec time: [0.00, 0.02] s
* igt@api_intel_bb@simple-bb:
- Statuses : 1 dmesg-warn(s) 37 pass(s)
- Exec time: [0.00, 0.03] s
* igt@api_intel_bb@simple-bb-ctx:
- Statuses : 35 pass(s) 3 skip(s)
- Exec time: [0.0, 0.03] s
Known issues
------------
Here are the changes found in IGTPW_4734 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_flink_basic@double-flink:
- fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/fi-tgl-y/igt@gem_flink_basic@double-flink.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/fi-tgl-y/igt@gem_flink_basic@double-flink.html
* igt@i915_pm_rpm@module-reload:
- fi-glk-dsi: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/fi-glk-dsi/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/fi-glk-dsi/igt@i915_pm_rpm@module-reload.html
* igt@kms_busy@basic@modeset:
- fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/fi-tgl-y/igt@kms_busy@basic@modeset.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/fi-tgl-y/igt@kms_busy@basic@modeset.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
#### Possible fixes ####
* igt@gem_exec_store@basic:
- fi-tgl-y: [DMESG-WARN][9] ([i915#402]) -> [PASS][10] +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/fi-tgl-y/igt@gem_exec_store@basic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/fi-tgl-y/igt@gem_exec_store@basic.html
* igt@gem_exec_suspend@basic-s0:
- fi-tgl-u2: [FAIL][11] ([i915#1888]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html
* igt@i915_module_load@reload:
- fi-bsw-kefka: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/fi-bsw-kefka/igt@i915_module_load@reload.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/fi-bsw-kefka/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@module-reload:
- fi-byt-n2820: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/fi-byt-n2820/igt@i915_pm_rpm@module-reload.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/fi-byt-n2820/igt@i915_pm_rpm@module-reload.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
#### Warnings ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [SKIP][19] ([fdo#109271]) -> [DMESG-FAIL][20] ([i915#62])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
* igt@kms_flip@basic-flip-vs-wf_vblank@a-dp1:
- fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +3 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-wf_vblank@a-dp1.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-wf_vblank@a-dp1.html
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (45 -> 38)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5721 -> IGTPW_4734
CI-20190529: 20190529
CI_DRM_8706: 7839b66a1c775fce16da3297056ccee2e81bc4c0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_4734: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/index.html
IGT_5721: df9004c501b203c1b418781ad2c94dfe36892ef5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@api_intel_bb@blit-noreloc-keep-cache
+igt@api_intel_bb@blit-noreloc-purge-cache
+igt@api_intel_bb@blit-reloc-keep-cache
+igt@api_intel_bb@blit-reloc-purge-cache
+igt@api_intel_bb@full-batch
+igt@api_intel_bb@intel-bb-blit-none
+igt@api_intel_bb@intel-bb-blit-x
+igt@api_intel_bb@intel-bb-blit-y
+igt@api_intel_bb@offset-control
+igt@api_intel_bb@simple-bb
+igt@api_intel_bb@simple-bb-ctx
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 11+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for Add api_intel_bb test
2020-07-03 11:30 [igt-dev] [PATCH i-g-t v16 0/4] Add api_intel_bb test Zbigniew Kempczyński
` (4 preceding siblings ...)
2020-07-03 12:46 ` [igt-dev] ✓ Fi.CI.BAT: success for Add api_intel_bb test Patchwork
@ 2020-07-03 14:55 ` Patchwork
2020-07-13 11:35 ` [igt-dev] [PATCH i-g-t v16 0/4] " Lionel Landwerlin
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2020-07-03 14:55 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
== Series Details ==
Series: Add api_intel_bb test
URL : https://patchwork.freedesktop.org/series/79089/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8706_full -> IGTPW_4734_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/index.html
New tests
---------
New tests have been introduced between CI_DRM_8706_full and IGTPW_4734_full:
### New IGT tests (11) ###
* igt@api_intel_bb@blit-noreloc-keep-cache:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@api_intel_bb@blit-noreloc-purge-cache:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@api_intel_bb@blit-reloc-keep-cache:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@api_intel_bb@blit-reloc-purge-cache:
- Statuses : 1 pass(s)
- Exec time: [0.01] s
* igt@api_intel_bb@full-batch:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@api_intel_bb@intel-bb-blit-none:
- Statuses : 7 pass(s)
- Exec time: [2.70, 5.01] s
* igt@api_intel_bb@intel-bb-blit-x:
- Statuses : 7 pass(s)
- Exec time: [2.55, 4.72] s
* igt@api_intel_bb@intel-bb-blit-y:
- Statuses : 7 pass(s)
- Exec time: [2.63, 4.62] s
* igt@api_intel_bb@offset-control:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@api_intel_bb@simple-bb:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@api_intel_bb@simple-bb-ctx:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
Known issues
------------
Here are the changes found in IGTPW_4734_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_whisper@basic-contexts-all:
- shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-glk1/igt@gem_exec_whisper@basic-contexts-all.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-glk2/igt@gem_exec_whisper@basic-contexts-all.html
* igt@gem_exec_whisper@basic-fds-priority-all:
- shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#93] / [i915#95]) +34 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-kbl7/igt@gem_exec_whisper@basic-fds-priority-all.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-kbl4/igt@gem_exec_whisper@basic-fds-priority-all.html
* igt@kms_color@pipe-b-legacy-gamma:
- shard-kbl: [PASS][5] -> [FAIL][6] ([i915#71])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-kbl6/igt@kms_color@pipe-b-legacy-gamma.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-kbl4/igt@kms_color@pipe-b-legacy-gamma.html
* igt@kms_color@pipe-invalid-ctm-matrix-sizes:
- shard-hsw: [PASS][7] -> [TIMEOUT][8] ([i915#1958] / [i915#2119]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-hsw5/igt@kms_color@pipe-invalid-ctm-matrix-sizes.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-hsw6/igt@kms_color@pipe-invalid-ctm-matrix-sizes.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen:
- shard-kbl: [PASS][9] -> [DMESG-FAIL][10] ([i915#54] / [i915#95]) +4 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-128x128-onscreen:
- shard-kbl: [PASS][11] -> [FAIL][12] ([i915#54])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-kbl1/igt@kms_cursor_crc@pipe-b-cursor-128x128-onscreen.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-kbl7/igt@kms_cursor_crc@pipe-b-cursor-128x128-onscreen.html
- shard-apl: [PASS][13] -> [FAIL][14] ([i915#54])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-apl6/igt@kms_cursor_crc@pipe-b-cursor-128x128-onscreen.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-apl1/igt@kms_cursor_crc@pipe-b-cursor-128x128-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding:
- shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#165] / [i915#93] / [i915#95])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding.html
* igt@kms_cursor_legacy@pipe-c-torture-bo:
- shard-tglb: [PASS][17] -> [DMESG-WARN][18] ([i915#128])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-tglb5/igt@kms_cursor_legacy@pipe-c-torture-bo.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-tglb7/igt@kms_cursor_legacy@pipe-c-torture-bo.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt:
- shard-tglb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-tglb7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-tglb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- shard-kbl: [PASS][23] -> [DMESG-FAIL][24] ([i915#95]) +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-kbl6/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-kbl6/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
* igt@kms_plane_cursor@pipe-a-overlay-size-64:
- shard-apl: [PASS][25] -> [DMESG-FAIL][26] ([i915#1635] / [i915#95]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-apl6/igt@kms_plane_cursor@pipe-a-overlay-size-64.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-apl4/igt@kms_plane_cursor@pipe-a-overlay-size-64.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-iclb8/igt@kms_psr@psr2_cursor_render.html
* igt@kms_setmode@basic:
- shard-hsw: [PASS][29] -> [FAIL][30] ([i915#31])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-hsw6/igt@kms_setmode@basic.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-hsw2/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-query-forked-hang:
- shard-tglb: [PASS][31] -> [DMESG-WARN][32] ([i915#402]) +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-tglb5/igt@kms_vblank@pipe-a-query-forked-hang.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-tglb5/igt@kms_vblank@pipe-a-query-forked-hang.html
* igt@perf@blocking-parameterized:
- shard-iclb: [PASS][33] -> [FAIL][34] ([i915#1542])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-iclb3/igt@perf@blocking-parameterized.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-iclb2/igt@perf@blocking-parameterized.html
* igt@perf_pmu@other-read-0:
- shard-apl: [PASS][35] -> [DMESG-WARN][36] ([i915#1635] / [i915#95]) +34 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-apl7/igt@perf_pmu@other-read-0.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-apl6/igt@perf_pmu@other-read-0.html
* igt@testdisplay:
- shard-kbl: [PASS][37] -> [DMESG-WARN][38] ([i915#62] / [i915#78] / [i915#92])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-kbl3/igt@testdisplay.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-kbl2/igt@testdisplay.html
#### Possible fixes ####
* igt@gem_exec_whisper@basic-forked-all:
- shard-glk: [DMESG-WARN][39] ([i915#118] / [i915#95]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-glk6/igt@gem_exec_whisper@basic-forked-all.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-glk4/igt@gem_exec_whisper@basic-forked-all.html
* igt@gem_userptr_blits@invalid-mmap-offset-unsync@uc:
- shard-iclb: [INCOMPLETE][41] -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-iclb8/igt@gem_userptr_blits@invalid-mmap-offset-unsync@uc.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-iclb3/igt@gem_userptr_blits@invalid-mmap-offset-unsync@uc.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +3 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-kbl7/igt@gem_workarounds@suspend-resume-fd.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-kbl6/igt@gem_workarounds@suspend-resume-fd.html
* igt@i915_module_load@reload:
- shard-iclb: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-iclb4/igt@i915_module_load@reload.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-iclb7/igt@i915_module_load@reload.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-180:
- shard-glk: [DMESG-FAIL][47] ([i915#118] / [i915#95]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-glk8/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-glk9/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
* igt@kms_cursor_crc@pipe-a-cursor-256x256-random:
- shard-kbl: [DMESG-FAIL][49] ([i915#54] / [i915#95]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-256x256-random.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-256x256-random.html
* igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding:
- shard-hsw: [TIMEOUT][51] ([i915#1958] / [i915#2119]) -> [PASS][52] +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-hsw2/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-hsw1/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html
* igt@kms_cursor_legacy@pipe-c-forked-bo:
- shard-apl: [DMESG-WARN][53] ([i915#1635] / [i915#95]) -> [PASS][54] +28 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-apl8/igt@kms_cursor_legacy@pipe-c-forked-bo.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-apl8/igt@kms_cursor_legacy@pipe-c-forked-bo.html
* igt@kms_fbcon_fbt@fbc:
- shard-iclb: [FAIL][55] -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-iclb2/igt@kms_fbcon_fbt@fbc.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-iclb6/igt@kms_fbcon_fbt@fbc.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [FAIL][57] ([i915#1525]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html
- shard-kbl: [FAIL][59] ([i915#64]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-kbl2/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip_tiling@flip-changes-tiling-y:
- shard-apl: [DMESG-FAIL][61] ([i915#1635] / [i915#95]) -> [PASS][62] +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-apl8/igt@kms_flip_tiling@flip-changes-tiling-y.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-apl6/igt@kms_flip_tiling@flip-changes-tiling-y.html
* igt@kms_frontbuffer_tracking@basic:
- shard-snb: [TIMEOUT][63] ([i915#1958] / [i915#2119]) -> [PASS][64] +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-snb1/igt@kms_frontbuffer_tracking@basic.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-snb6/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_frontbuffer_tracking@fbc-farfromfence:
- shard-kbl: [DMESG-WARN][65] ([i915#93] / [i915#95]) -> [PASS][66] +35 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-farfromfence.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-farfromfence.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc:
- shard-tglb: [DMESG-WARN][67] ([i915#1982]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-tglb7/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-tglb1/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc.html
* igt@kms_hdmi_inject@inject-audio:
- shard-tglb: [SKIP][69] ([i915#433]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-tglb7/igt@kms_hdmi_inject@inject-audio.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-tglb5/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [DMESG-FAIL][71] ([i915#95]) -> [PASS][72] +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant:
- shard-kbl: [DMESG-FAIL][73] ([fdo#108145] / [i915#95]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-kbl7/igt@kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-kbl3/igt@kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html
- shard-apl: [DMESG-FAIL][75] ([fdo#108145] / [i915#1635] / [i915#95]) -> [PASS][76] +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html
* igt@kms_vblank@pipe-a-query-idle-hang:
- shard-hsw: [INCOMPLETE][77] -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-hsw1/igt@kms_vblank@pipe-a-query-idle-hang.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-hsw7/igt@kms_vblank@pipe-a-query-idle-hang.html
* igt@kms_vblank@pipe-c-accuracy-idle:
- shard-glk: [FAIL][79] ([i915#43]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-glk9/igt@kms_vblank@pipe-c-accuracy-idle.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-glk9/igt@kms_vblank@pipe-c-accuracy-idle.html
#### Warnings ####
* igt@gem_exec_reloc@basic-concurrent16:
- shard-snb: [TIMEOUT][81] ([i915#1958] / [i915#2119]) -> [FAIL][82] ([i915#1930])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-snb1/igt@gem_exec_reloc@basic-concurrent16.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-snb5/igt@gem_exec_reloc@basic-concurrent16.html
- shard-kbl: [INCOMPLETE][83] ([i915#1958] / [i915#95]) -> [INCOMPLETE][84] ([i915#1958])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-kbl2/igt@gem_exec_reloc@basic-concurrent16.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-kbl2/igt@gem_exec_reloc@basic-concurrent16.html
* igt@i915_pm_dc@dc6-dpms:
- shard-kbl: [DMESG-FAIL][85] ([i915#95]) -> [FAIL][86] ([i915#454])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-kbl7/igt@i915_pm_dc@dc6-dpms.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-kbl4/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_color_chamelium@pipe-a-ctm-0-5:
- shard-apl: [SKIP][87] ([fdo#109271] / [fdo#111827]) -> [SKIP][88] ([fdo#109271] / [fdo#111827] / [i915#1635]) +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-apl2/igt@kms_color_chamelium@pipe-a-ctm-0-5.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-apl4/igt@kms_color_chamelium@pipe-a-ctm-0-5.html
* igt@kms_color_chamelium@pipe-d-ctm-0-5:
- shard-apl: [SKIP][89] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][90] ([fdo#109271] / [fdo#111827]) +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-apl4/igt@kms_color_chamelium@pipe-d-ctm-0-5.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-apl6/igt@kms_color_chamelium@pipe-d-ctm-0-5.html
* igt@kms_content_protection@srm:
- shard-apl: [DMESG-FAIL][91] ([fdo#110321] / [i915#1635] / [i915#95]) -> [FAIL][92] ([fdo#110321])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-apl4/igt@kms_content_protection@srm.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-apl6/igt@kms_content_protection@srm.html
* igt@kms_flip@2x-flip-vs-rmfb:
- shard-snb: [TIMEOUT][93] ([i915#1958] / [i915#2119]) -> [SKIP][94] ([fdo#109271]) +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-snb1/igt@kms_flip@2x-flip-vs-rmfb.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-snb4/igt@kms_flip@2x-flip-vs-rmfb.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-cpu:
- shard-hsw: [SKIP][95] ([fdo#109271]) -> [TIMEOUT][96] ([i915#1958] / [i915#2119]) +1 similar issue
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-hsw7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-cpu.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-hsw6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-cpu.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: [FAIL][97] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][98] ([fdo#108145] / [i915#1635] / [i915#95])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-apl7/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-apl7/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
- shard-kbl: [FAIL][99] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][100] ([fdo#108145] / [i915#95])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-kbl4/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-kbl4/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_vblank@pipe-d-wait-forked:
- shard-apl: [SKIP][101] ([fdo#109271]) -> [SKIP][102] ([fdo#109271] / [i915#1635]) +12 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-apl3/igt@kms_vblank@pipe-d-wait-forked.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-apl7/igt@kms_vblank@pipe-d-wait-forked.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-apl: [SKIP][103] ([fdo#109271] / [i915#1635]) -> [SKIP][104] ([fdo#109271]) +14 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-apl1/igt@kms_vblank@pipe-d-wait-idle.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-apl6/igt@kms_vblank@pipe-d-wait-idle.html
* igt@runner@aborted:
- shard-iclb: ([FAIL][105], [FAIL][106]) ([i915#2102] / [i915#2110]) -> [FAIL][107] ([i915#2110])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-iclb1/igt@runner@aborted.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-iclb8/igt@runner@aborted.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-iclb2/igt@runner@aborted.html
- shard-apl: ([FAIL][108], [FAIL][109]) ([i915#1610] / [i915#1635] / [i915#2110]) -> [FAIL][110] ([i915#1635] / [i915#2110])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-apl3/igt@runner@aborted.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8706/shard-apl1/igt@runner@aborted.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/shard-apl7/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128
[i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930
[i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2102]: https://gitlab.freedesktop.org/drm/intel/issues/2102
[i915#2110]: https://gitlab.freedesktop.org/drm/intel/issues/2110
[i915#2119]: https://gitlab.freedesktop.org/drm/intel/issues/2119
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#43]: https://gitlab.freedesktop.org/drm/intel/issues/43
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#64]: https://gitlab.freedesktop.org/drm/intel/issues/64
[i915#71]: https://gitlab.freedesktop.org/drm/intel/issues/71
[i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (10 -> 8)
------------------------------
Missing (2): pig-skl-6260u pig-glk-j5005
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5721 -> IGTPW_4734
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_8706: 7839b66a1c775fce16da3297056ccee2e81bc4c0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_4734: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/index.html
IGT_5721: df9004c501b203c1b418781ad2c94dfe36892ef5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4734/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v16 4/4] intel-ci/fast-feedback: add api_intel_bb tests
2020-07-03 11:31 ` [igt-dev] [PATCH i-g-t v16 4/4] intel-ci/fast-feedback: add api_intel_bb tests Zbigniew Kempczyński
@ 2020-07-03 18:19 ` Chris Wilson
2020-07-03 19:45 ` Zbigniew Kempczyński
0 siblings, 1 reply; 11+ messages in thread
From: Chris Wilson @ 2020-07-03 18:19 UTC (permalink / raw)
To: zbigniew.kempczynski, igt-dev; +Cc: Petri Latvala
Quoting Zbigniew Kempczyński (2020-07-03 12:31:02)
> intel_bb has to replace libdrm intel_batchbuffer. We need to know
> any changes in its infrastructure doesn't lead to regression.
> Add api_intel_bb to BAT to be verified on the very beginning.
> Test execution time is very short so it shouldn't be noticable
> on CI.
Ok, up to here, all done. But BAT for an igt selftest? The criteria for
BAT is "catch the most amount of bugs in the least amount of time", for
which we like to have tests that exercise a lot of the driver very
quickly. I don't think this adds anything? [I would be very happy to be
proved wrong with some path coverage / kcov]. So I don't see much reason
to have it in BAT, and just leave it to shards/idle.
-Chris
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v16 4/4] intel-ci/fast-feedback: add api_intel_bb tests
2020-07-03 18:19 ` Chris Wilson
@ 2020-07-03 19:45 ` Zbigniew Kempczyński
0 siblings, 0 replies; 11+ messages in thread
From: Zbigniew Kempczyński @ 2020-07-03 19:45 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev, Petri Latvala
On Fri, Jul 03, 2020 at 07:19:02PM +0100, Chris Wilson wrote:
> Quoting Zbigniew Kempczyński (2020-07-03 12:31:02)
> > intel_bb has to replace libdrm intel_batchbuffer. We need to know
> > any changes in its infrastructure doesn't lead to regression.
> > Add api_intel_bb to BAT to be verified on the very beginning.
> > Test execution time is very short so it shouldn't be noticable
> > on CI.
>
> Ok, up to here, all done. But BAT for an igt selftest? The criteria for
> BAT is "catch the most amount of bugs in the least amount of time", for
> which we like to have tests that exercise a lot of the driver very
> quickly. I don't think this adds anything? [I would be very happy to be
> proved wrong with some path coverage / kcov]. So I don't see much reason
> to have it in BAT, and just leave it to shards/idle.
> -Chris
Ok, I won't complain :) Especially the criteria you've explained
doesn't match to api_intel_bb. In cases I'll need to update it I will
just use HAX and leave final commit to the shards run.
--
Zbigniew
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v16 0/4] Add api_intel_bb test
2020-07-03 11:30 [igt-dev] [PATCH i-g-t v16 0/4] Add api_intel_bb test Zbigniew Kempczyński
` (5 preceding siblings ...)
2020-07-03 14:55 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
@ 2020-07-13 11:35 ` Lionel Landwerlin
2020-07-13 18:40 ` Zbigniew Kempczyński
6 siblings, 1 reply; 11+ messages in thread
From: Lionel Landwerlin @ 2020-07-13 11:35 UTC (permalink / raw)
To: Zbigniew Kempczyński, igt-dev
Looking forward to this landing as I need to move test/i915/perf.c over
to it to cover the submission uAPI a bit more.
Thanks for doing the hard work!
-Lionel
On 03/07/2020 14:30, Zbigniew Kempczyński wrote:
> Slowly as London bus move toward say goodbye to libdrm in the
> rendercopy tests.
>
> Seriously - add some new functions in intel_buf/intel_bb and
> verify most of them work properly and doesn't affect gem_gpgpu_fill,
> gem_media_fill and i915_pm_sseu which were previously migrated.
>
> ,,,
> v13: add fences as primary synchronisation, add none/x/y
> blitting tests to ensure none->?->none blit give same
> result
> v14: skip gens2/3
> v15: fixing blitting Y surfaces, skipping testing Y blit on gens < 6
> v16: distinguish reloc/no-reloc offset handling
>
> Zbigniew Kempczyński (4):
> lib/intel_batchbuffer: Extend intel_bb
> lib/intel_bufops: Add new functions and intel_buf fields
> tests/api_intel_bb: Add intel_bb API test
> intel-ci/fast-feedback: add api_intel_bb tests
>
> lib/intel_batchbuffer.c | 516 +++++++++++++++++--
> lib/intel_batchbuffer.h | 80 ++-
> lib/intel_bufops.c | 136 ++++-
> lib/intel_bufops.h | 25 +-
> tests/i915/api_intel_bb.c | 709 ++++++++++++++++++++++++++
> tests/intel-ci/fast-feedback.testlist | 11 +
> tests/meson.build | 1 +
> 7 files changed, 1413 insertions(+), 65 deletions(-)
> create mode 100644 tests/i915/api_intel_bb.c
>
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v16 0/4] Add api_intel_bb test
2020-07-13 11:35 ` [igt-dev] [PATCH i-g-t v16 0/4] " Lionel Landwerlin
@ 2020-07-13 18:40 ` Zbigniew Kempczyński
0 siblings, 0 replies; 11+ messages in thread
From: Zbigniew Kempczyński @ 2020-07-13 18:40 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: igt-dev
On Mon, Jul 13, 2020 at 02:35:13PM +0300, Lionel Landwerlin wrote:
> Looking forward to this landing as I need to move test/i915/perf.c over to
> it to cover the submission uAPI a bit more.
>
> Thanks for doing the hard work!
I'm working on libdrm removal in rendercopy, so I need to change
your perf.c code too. It seems it must be done in parallel, so you
can expect I'll do that in the series. A lot of things depend on
that so when I'll be ready with first try a lot of things can be
still broken, so I also consider introducing rendercopy with
_v2 suffix to migrate all rendercopy related code to new interface
one by one. But I'll decide that in next week depending on work
progress. I'll add you to cc list then.
--
Zbigniew
>
> -Lionel
>
> On 03/07/2020 14:30, Zbigniew Kempczyński wrote:
> > Slowly as London bus move toward say goodbye to libdrm in the
> > rendercopy tests.
> >
> > Seriously - add some new functions in intel_buf/intel_bb and
> > verify most of them work properly and doesn't affect gem_gpgpu_fill,
> > gem_media_fill and i915_pm_sseu which were previously migrated.
> >
> > ,,,
> > v13: add fences as primary synchronisation, add none/x/y
> > blitting tests to ensure none->?->none blit give same
> > result
> > v14: skip gens2/3
> > v15: fixing blitting Y surfaces, skipping testing Y blit on gens < 6
> > v16: distinguish reloc/no-reloc offset handling
> >
> > Zbigniew Kempczyński (4):
> > lib/intel_batchbuffer: Extend intel_bb
> > lib/intel_bufops: Add new functions and intel_buf fields
> > tests/api_intel_bb: Add intel_bb API test
> > intel-ci/fast-feedback: add api_intel_bb tests
> >
> > lib/intel_batchbuffer.c | 516 +++++++++++++++++--
> > lib/intel_batchbuffer.h | 80 ++-
> > lib/intel_bufops.c | 136 ++++-
> > lib/intel_bufops.h | 25 +-
> > tests/i915/api_intel_bb.c | 709 ++++++++++++++++++++++++++
> > tests/intel-ci/fast-feedback.testlist | 11 +
> > tests/meson.build | 1 +
> > 7 files changed, 1413 insertions(+), 65 deletions(-)
> > create mode 100644 tests/i915/api_intel_bb.c
> >
>
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-07-13 18:40 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-03 11:30 [igt-dev] [PATCH i-g-t v16 0/4] Add api_intel_bb test Zbigniew Kempczyński
2020-07-03 11:30 ` [igt-dev] [PATCH i-g-t v16 1/4] lib/intel_batchbuffer: Extend intel_bb Zbigniew Kempczyński
2020-07-03 11:31 ` [igt-dev] [PATCH i-g-t v16 2/4] lib/intel_bufops: Add new functions and intel_buf fields Zbigniew Kempczyński
2020-07-03 11:31 ` [igt-dev] [PATCH i-g-t v16 3/4] tests/api_intel_bb: Add intel_bb API test Zbigniew Kempczyński
2020-07-03 11:31 ` [igt-dev] [PATCH i-g-t v16 4/4] intel-ci/fast-feedback: add api_intel_bb tests Zbigniew Kempczyński
2020-07-03 18:19 ` Chris Wilson
2020-07-03 19:45 ` Zbigniew Kempczyński
2020-07-03 12:46 ` [igt-dev] ✓ Fi.CI.BAT: success for Add api_intel_bb test Patchwork
2020-07-03 14:55 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2020-07-13 11:35 ` [igt-dev] [PATCH i-g-t v16 0/4] " Lionel Landwerlin
2020-07-13 18:40 ` Zbigniew Kempczyński
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