Re: [PATCH 3/3] arm64: Add KRYO4XX silver CPU cores to erratum list 1530923 and 1024718

Re: [PATCH 3/3] arm64: Add KRYO4XX silver CPU cores to erratum list 1530923 and 1024718

[Sai Prakash Ranjan]

Hi Will,

On 2020-07-03 19:25, Will Deacon wrote:
> On Tue, Jun 30, 2020 at 11:30:55PM +0530, Sai Prakash Ranjan wrote:
>> KRYO4XX silver/LITTLE CPU cores with revision r1p0 are affected by
>> erratum 1530923 and 1024718, so add them to the respective list.
>> The variant and revision bits are implementation defined and are
>> different from the their Cortex CPU counterparts on which they are
>> based on, i.e., r1p0 is equivalent to rdpe.
> 
> So just to confirm, revisions prior to rdpe are unaffected, or do those
> parts simply not exist?
> 

There is one revision prior to this r0p1(r7pc) which has a different 
part
number and are used in v1 of SoCs which are limited to only internal 
test
platforms in the early stages of bringup and not used in actual devices 
out
there, so I did not add it to the list but they are affected. Plus we 
would
need to add another MIDR_QCOM_KRYO_4XX_SILVER_V1 if we are supporting 
them
which I thought was not worth it when devices with those CPUs are not 
available.

Thanks,
Sai

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH 3/3] arm64: Add KRYO4XX silver CPU cores to erratum list 1530923 and 1024718

[Will Deacon]

On Fri, Jul 03, 2020 at 08:04:04PM +0530, Sai Prakash Ranjan wrote:
> On 2020-07-03 19:25, Will Deacon wrote:
> > On Tue, Jun 30, 2020 at 11:30:55PM +0530, Sai Prakash Ranjan wrote:
> > > KRYO4XX silver/LITTLE CPU cores with revision r1p0 are affected by
> > > erratum 1530923 and 1024718, so add them to the respective list.
> > > The variant and revision bits are implementation defined and are
> > > different from the their Cortex CPU counterparts on which they are
> > > based on, i.e., r1p0 is equivalent to rdpe.
> > 
> > So just to confirm, revisions prior to rdpe are unaffected, or do those
> > parts simply not exist?
> > 
> 
> There is one revision prior to this r0p1(r7pc) which has a different part
> number and are used in v1 of SoCs which are limited to only internal test
> platforms in the early stages of bringup and not used in actual devices out
> there, so I did not add it to the list but they are affected. Plus we would
> need to add another MIDR_QCOM_KRYO_4XX_SILVER_V1 if we are supporting them
> which I thought was not worth it when devices with those CPUs are not
> available.

Thanks, just wanted to make sure. Sounds like we can safely assume those
parts don't exist.

Will

Re: [PATCH 3/3] arm64: Add KRYO4XX silver CPU cores to erratum list 1530923 and 1024718

[Will Deacon]

On Fri, Jul 03, 2020 at 08:04:04PM +0530, Sai Prakash Ranjan wrote:
> On 2020-07-03 19:25, Will Deacon wrote:
> > On Tue, Jun 30, 2020 at 11:30:55PM +0530, Sai Prakash Ranjan wrote:
> > > KRYO4XX silver/LITTLE CPU cores with revision r1p0 are affected by
> > > erratum 1530923 and 1024718, so add them to the respective list.
> > > The variant and revision bits are implementation defined and are
> > > different from the their Cortex CPU counterparts on which they are
> > > based on, i.e., r1p0 is equivalent to rdpe.
> > 
> > So just to confirm, revisions prior to rdpe are unaffected, or do those
> > parts simply not exist?
> > 
> 
> There is one revision prior to this r0p1(r7pc) which has a different part
> number and are used in v1 of SoCs which are limited to only internal test
> platforms in the early stages of bringup and not used in actual devices out
> there, so I did not add it to the list but they are affected. Plus we would
> need to add another MIDR_QCOM_KRYO_4XX_SILVER_V1 if we are supporting them
> which I thought was not worth it when devices with those CPUs are not
> available.

Thanks, just wanted to make sure. Sounds like we can safely assume those
parts don't exist.

Will

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Re: [PATCH 3/3] arm64: Add KRYO4XX silver CPU cores to erratum list 1530923 and 1024718

[Will Deacon]

On Tue, Jun 30, 2020 at 11:30:55PM +0530, Sai Prakash Ranjan wrote:
> KRYO4XX silver/LITTLE CPU cores with revision r1p0 are affected by
> erratum 1530923 and 1024718, so add them to the respective list.
> The variant and revision bits are implementation defined and are
> different from the their Cortex CPU counterparts on which they are
> based on, i.e., r1p0 is equivalent to rdpe.

So just to confirm, revisions prior to rdpe are unaffected, or do those
parts simply not exist?

Cheers,

Will

Re: [PATCH 3/3] arm64: Add KRYO4XX silver CPU cores to erratum list 1530923 and 1024718

[Will Deacon]

On Tue, Jun 30, 2020 at 11:30:55PM +0530, Sai Prakash Ranjan wrote:
> KRYO4XX silver/LITTLE CPU cores with revision r1p0 are affected by
> erratum 1530923 and 1024718, so add them to the respective list.
> The variant and revision bits are implementation defined and are
> different from the their Cortex CPU counterparts on which they are
> based on, i.e., r1p0 is equivalent to rdpe.

So just to confirm, revisions prior to rdpe are unaffected, or do those
parts simply not exist?

Cheers,

Will

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 3/3] arm64: Add KRYO4XX silver CPU cores to erratum list 1530923 and 1024718

[Sai Prakash Ranjan]

KRYO4XX silver/LITTLE CPU cores with revision r1p0 are affected by
erratum 1530923 and 1024718, so add them to the respective list.
The variant and revision bits are implementation defined and are
different from the their Cortex CPU counterparts on which they are
based on, i.e., r1p0 is equivalent to rdpe.

Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
 Documentation/arm64/silicon-errata.rst | 4 ++++
 arch/arm64/kernel/cpu_errata.c         | 2 ++
 arch/arm64/kernel/cpufeature.c         | 2 ++
 3 files changed, 8 insertions(+)

diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
index f3c0c4393e7e..3f7c3a7e8a2b 100644
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -151,6 +151,10 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | Qualcomm Tech. | Kryo4xx Gold    | N/A             | ARM64_ERRATUM_1418040       |
 +----------------+-----------------+-----------------+-----------------------------+
+| Qualcomm Tech. | Kryo4xx Silver  | N/A             | ARM64_ERRATUM_1530923       |
++----------------+-----------------+-----------------+-----------------------------+
+| Qualcomm Tech. | Kryo4xx Silver  | N/A             | ARM64_ERRATUM_1024718       |
++----------------+-----------------+-----------------+-----------------------------+
 +----------------+-----------------+-----------------+-----------------------------+
 | Fujitsu        | A64FX           | E#010001        | FUJITSU_ERRATUM_010001      |
 +----------------+-----------------+-----------------+-----------------------------+
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 044f1d7aebdf..8e302dc093d0 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -769,6 +769,8 @@ static const struct midr_range erratum_speculative_at_list[] = {
 #ifdef CONFIG_ARM64_ERRATUM_1530923
 	/* Cortex A55 r0p0 to r2p0 */
 	MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),
+	/* Kryo4xx Silver (rdpe => r1p0) */
+	MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
 #endif
 	{},
 };
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 9f63053a63a9..9fae0efc80c1 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1408,6 +1408,8 @@ static bool cpu_has_broken_dbm(void)
 	static const struct midr_range cpus[] = {
 #ifdef CONFIG_ARM64_ERRATUM_1024718
 		MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),  // A55 r0p0 -r1p0
+		/* Kryo4xx Silver (rdpe => r1p0) */
+		MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
 #endif
 		{},
 	};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH 3/3] arm64: Add KRYO4XX silver CPU cores to erratum list 1530923 and 1024718

[Sai Prakash Ranjan]

KRYO4XX silver/LITTLE CPU cores with revision r1p0 are affected by
erratum 1530923 and 1024718, so add them to the respective list.
The variant and revision bits are implementation defined and are
different from the their Cortex CPU counterparts on which they are
based on, i.e., r1p0 is equivalent to rdpe.

Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
 Documentation/arm64/silicon-errata.rst | 4 ++++
 arch/arm64/kernel/cpu_errata.c         | 2 ++
 arch/arm64/kernel/cpufeature.c         | 2 ++
 3 files changed, 8 insertions(+)

diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
index f3c0c4393e7e..3f7c3a7e8a2b 100644
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -151,6 +151,10 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | Qualcomm Tech. | Kryo4xx Gold    | N/A             | ARM64_ERRATUM_1418040       |
 +----------------+-----------------+-----------------+-----------------------------+
+| Qualcomm Tech. | Kryo4xx Silver  | N/A             | ARM64_ERRATUM_1530923       |
++----------------+-----------------+-----------------+-----------------------------+
+| Qualcomm Tech. | Kryo4xx Silver  | N/A             | ARM64_ERRATUM_1024718       |
++----------------+-----------------+-----------------+-----------------------------+
 +----------------+-----------------+-----------------+-----------------------------+
 | Fujitsu        | A64FX           | E#010001        | FUJITSU_ERRATUM_010001      |
 +----------------+-----------------+-----------------+-----------------------------+
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 044f1d7aebdf..8e302dc093d0 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -769,6 +769,8 @@ static const struct midr_range erratum_speculative_at_list[] = {
 #ifdef CONFIG_ARM64_ERRATUM_1530923
 	/* Cortex A55 r0p0 to r2p0 */
 	MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),
+	/* Kryo4xx Silver (rdpe => r1p0) */
+	MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
 #endif
 	{},
 };
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 9f63053a63a9..9fae0efc80c1 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1408,6 +1408,8 @@ static bool cpu_has_broken_dbm(void)
 	static const struct midr_range cpus[] = {
 #ifdef CONFIG_ARM64_ERRATUM_1024718
 		MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),  // A55 r0p0 -r1p0
+		/* Kryo4xx Silver (rdpe => r1p0) */
+		MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
 #endif
 		{},
 	};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


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