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* [PATCH 0/8] DC Patches July 03, 2020
@ 2020-07-04  1:14 Rodrigo Siqueira
  2020-07-04  1:14 ` [PATCH 1/8] drm/amd/display: Add diags scaling log by default Rodrigo Siqueira
                   ` (8 more replies)
  0 siblings, 9 replies; 11+ messages in thread
From: Rodrigo Siqueira @ 2020-07-04  1:14 UTC (permalink / raw)
  To: amd-gfx
  Cc: eryk.brol, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
	aurabindo.pillai, Bhawanpreet.Lakha

This DC patchset brings improvements in multiple areas. In summary, we
have:
* SMU logger messages
* DMCU improvements
* Bug fixes

Anthony Koo (2):
  drm/amd/display: [FW Promotion] Release 0.0.23
  drm/amd/display: 3.2.93

Dmytro Laktyushkin (1):
  drm/amd/display: Add diags scaling log by default

Igor Kravchenko (1):
  drm/amd/display: Register init

Jaehyun Chung (1):
  drm/amd/display: Send VSIF on unsupported modes on DAL

Joshua Aberback (1):
  drm/amd/display: Request PHYCLK adjustment on PHY enable/disable

Roman Li (1):
  drm/amd/display: Remove VSC infoframe dep on DMCU

Wesley Chalmers (1):
  drm/amd/display: Add logger for SMU msg

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 30 ++++-----
 .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c  | 35 +++++++---
 .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 27 ++++++--
 .../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c  | 32 ++++++---
 .../dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c  | 65 ++++++++++++++++++-
 .../drm/amd/display/dc/core/dc_link_hwss.c    | 11 +++-
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 39 +++++++----
 drivers/gpu/drm/amd/display/dc/dc.h           |  2 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 58 ++++++++++-------
 .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h   |  3 +
 .../amd/display/dc/inc/hw/clk_mgr_internal.h  |  2 +
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 18 ++---
 .../drm/amd/display/include/logger_types.h    |  4 +-
 .../amd/display/modules/freesync/freesync.c   |  2 +-
 14 files changed, 232 insertions(+), 96 deletions(-)

-- 
2.27.0

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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 11+ messages in thread
* [PATCH 1/8] drm/amd/display: Add diags scaling log by default
  2020-07-04  1:14 [PATCH 0/8] DC Patches July 03, 2020 Rodrigo Siqueira
@ 2020-07-04  1:14 ` Rodrigo Siqueira
  2020-07-04  1:14 ` [PATCH 2/8] drm/amd/display: Register init Rodrigo Siqueira
                   ` (7 subsequent siblings)
  8 siblings, 0 replies; 11+ messages in thread
From: Rodrigo Siqueira @ 2020-07-04  1:14 UTC (permalink / raw)
  To: amd-gfx
  Cc: Dmytro Laktyushkin, eryk.brol, Sunpeng.Li, Harry.Wentland,
	qingqing.zhuo, aurabindo.pillai, Eric Bernstein,
	Bhawanpreet.Lakha

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Print scaling parameters as they are calculated in diags.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 39 ++++++++++++-------
 .../drm/amd/display/include/logger_types.h    |  2 +-
 2 files changed, 27 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 1000dc6daf72..7b5f90ebb133 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1162,19 +1162,32 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
 		/* May need to re-check lb size after this in some obscure scenario */
 		calculate_inits_and_adj_vp(pipe_ctx);
 
-	DC_LOG_SCALER(
-				"%s: Viewport:\nheight:%d width:%d x:%d "
-				"y:%d\n dst_rect:\nheight:%d width:%d x:%d "
-				"y:%d\n",
-				__func__,
-				pipe_ctx->plane_res.scl_data.viewport.height,
-				pipe_ctx->plane_res.scl_data.viewport.width,
-				pipe_ctx->plane_res.scl_data.viewport.x,
-				pipe_ctx->plane_res.scl_data.viewport.y,
-				plane_state->dst_rect.height,
-				plane_state->dst_rect.width,
-				plane_state->dst_rect.x,
-				plane_state->dst_rect.y);
+	DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d  Recout: height:%d width:%d x:%d y:%d  HACTIVE:%d VACTIVE:%d\n"
+			"src_rect: height:%d width:%d x:%d y:%d  dst_rect: height:%d width:%d x:%d y:%d  clip_rect: height:%d width:%d x:%d y:%d\n",
+			__func__,
+			pipe_ctx->pipe_idx,
+			pipe_ctx->plane_res.scl_data.viewport.height,
+			pipe_ctx->plane_res.scl_data.viewport.width,
+			pipe_ctx->plane_res.scl_data.viewport.x,
+			pipe_ctx->plane_res.scl_data.viewport.y,
+			pipe_ctx->plane_res.scl_data.recout.height,
+			pipe_ctx->plane_res.scl_data.recout.width,
+			pipe_ctx->plane_res.scl_data.recout.x,
+			pipe_ctx->plane_res.scl_data.recout.y,
+			pipe_ctx->plane_res.scl_data.h_active,
+			pipe_ctx->plane_res.scl_data.v_active,
+			plane_state->src_rect.height,
+			plane_state->src_rect.width,
+			plane_state->src_rect.x,
+			plane_state->src_rect.y,
+			plane_state->dst_rect.height,
+			plane_state->dst_rect.width,
+			plane_state->dst_rect.x,
+			plane_state->dst_rect.y,
+			plane_state->clip_rect.height,
+			plane_state->clip_rect.width,
+			plane_state->clip_rect.x,
+			plane_state->clip_rect.y);
 
 	if (store_h_border_left)
 		restore_border_left_from_dst(pipe_ctx, store_h_border_left);
diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h b/drivers/gpu/drm/amd/display/include/logger_types.h
index d66f9d8eefb4..5dea27fc5198 100644
--- a/drivers/gpu/drm/amd/display/include/logger_types.h
+++ b/drivers/gpu/drm/amd/display/include/logger_types.h
@@ -147,11 +147,11 @@ enum dc_log_type {
 		(1ULL << LOG_I2C_AUX) | \
 		(1ULL << LOG_IF_TRACE) | \
 		(1ULL << LOG_HDMI_FRL) | \
+		(1ULL << LOG_SCALER) | \
 		(1ULL << LOG_DTN) /* | \
 		(1ULL << LOG_DEBUG) | \
 		(1ULL << LOG_BIOS) | \
 		(1ULL << LOG_SURFACE) | \
-		(1ULL << LOG_SCALER) | \
 		(1ULL << LOG_DML) | \
 		(1ULL << LOG_HW_LINK_TRAINING) | \
 		(1ULL << LOG_HW_AUDIO)| \
-- 
2.27.0

_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [PATCH 2/8] drm/amd/display: Register init
  2020-07-04  1:14 [PATCH 0/8] DC Patches July 03, 2020 Rodrigo Siqueira
  2020-07-04  1:14 ` [PATCH 1/8] drm/amd/display: Add diags scaling log by default Rodrigo Siqueira
@ 2020-07-04  1:14 ` Rodrigo Siqueira
  2020-07-04  1:14 ` [PATCH 3/8] drm/amd/display: Send VSIF on unsupported modes on DAL Rodrigo Siqueira
                   ` (6 subsequent siblings)
  8 siblings, 0 replies; 11+ messages in thread
From: Rodrigo Siqueira @ 2020-07-04  1:14 UTC (permalink / raw)
  To: amd-gfx
  Cc: eryk.brol, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
	Igor Kravchenko, aurabindo.pillai, Tony Cheng, Bhawanpreet.Lakha

From: Igor Kravchenko <Igor.Kravchenko@amd.com>

[Why]
Driver re-initialize registers already set in FW

[How]
Transfer init to FW

Signed-off-by: Igor Kravchenko <Igor.Kravchenko@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 58 +++++++++++--------
 1 file changed, 35 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index cb45f05a0319..6711ff908bcf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1255,6 +1255,7 @@ void dcn10_init_hw(struct dc *dc)
 	struct dc_bios *dcb = dc->ctx->dc_bios;
 	struct resource_pool *res_pool = dc->res_pool;
 	uint32_t backlight = MAX_BACKLIGHT_LEVEL;
+	bool   is_optimized_init_done = false;
 
 	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
 		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
@@ -1288,7 +1289,9 @@ void dcn10_init_hw(struct dc *dc)
 	if (!dcb->funcs->is_accelerated_mode(dcb))
 		hws->funcs.disable_vga(dc->hwseq);
 
-	if (!dc_dmub_srv_optimized_init_done(dc->ctx->dmub_srv))
+	is_optimized_init_done = dc_dmub_srv_optimized_init_done(dc->ctx->dmub_srv);
+
+	if (!is_optimized_init_done)
 		hws->funcs.bios_golden_init(dc);
 
 	if (dc->ctx->dc_bios->fw_info_valid) {
@@ -1323,7 +1326,8 @@ void dcn10_init_hw(struct dc *dc)
 		 */
 		struct dc_link *link = dc->links[i];
 
-		link->link_enc->funcs->hw_init(link->link_enc);
+		if (!is_optimized_init_done)
+			link->link_enc->funcs->hw_init(link->link_enc);
 
 		/* Check for enabled DIG to identify enabled display */
 		if (link->link_enc->funcs->is_dig_enabled &&
@@ -1332,9 +1336,11 @@ void dcn10_init_hw(struct dc *dc)
 	}
 
 	/* Power gate DSCs */
-	for (i = 0; i < res_pool->res_cap->num_dsc; i++)
-		if (hws->funcs.dsc_pg_control != NULL)
-			hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
+	if (!is_optimized_init_done) {
+		for (i = 0; i < res_pool->res_cap->num_dsc; i++)
+			if (hws->funcs.dsc_pg_control != NULL)
+				hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
+	}
 
 	/* we want to turn off all dp displays before doing detection */
 	if (dc->config.power_down_display_on_boot) {
@@ -1379,10 +1385,12 @@ void dcn10_init_hw(struct dc *dc)
 	 * everything down.
 	 */
 	if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
-		hws->funcs.init_pipes(dc, dc->current_state);
-		if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
-			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
-					!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
+		if (!is_optimized_init_done) {
+			hws->funcs.init_pipes(dc, dc->current_state);
+			if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
+				dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
+						!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
+		}
 	}
 
 	/* In headless boot cases, DIG may be turned
@@ -1417,30 +1425,34 @@ void dcn10_init_hw(struct dc *dc)
 		}
 	}
 
-	for (i = 0; i < res_pool->audio_count; i++) {
-		struct audio *audio = res_pool->audios[i];
+	if (!is_optimized_init_done) {
 
-		audio->funcs->hw_init(audio);
-	}
+		for (i = 0; i < res_pool->audio_count; i++) {
+			struct audio *audio = res_pool->audios[i];
 
-	for (i = 0; i < dc->link_count; i++) {
-		struct dc_link *link = dc->links[i];
+			audio->funcs->hw_init(audio);
+		}
 
-		if (link->panel_cntl)
-			backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
-	}
+		for (i = 0; i < dc->link_count; i++) {
+			struct dc_link *link = dc->links[i];
 
-	if (abm != NULL)
-		abm->funcs->abm_init(abm, backlight);
+			if (link->panel_cntl)
+				backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
+		}
 
-	if (dmcu != NULL && !dmcu->auto_load_dmcu)
-		dmcu->funcs->dmcu_init(dmcu);
+		if (abm != NULL)
+			abm->funcs->abm_init(abm, backlight);
+
+		if (dmcu != NULL && !dmcu->auto_load_dmcu)
+			dmcu->funcs->dmcu_init(dmcu);
+	}
 
 	if (abm != NULL && dmcu != NULL)
 		abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
 
 	/* power AFMT HDMI memory TODO: may move to dis/en output save power*/
-	REG_WRITE(DIO_MEM_PWR_CTRL, 0);
+	if (!is_optimized_init_done)
+		REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 
 	if (!dc->debug.disable_clock_gate) {
 		/* enable all DCN clock gating */
-- 
2.27.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [PATCH 3/8] drm/amd/display: Send VSIF on unsupported modes on DAL
  2020-07-04  1:14 [PATCH 0/8] DC Patches July 03, 2020 Rodrigo Siqueira
  2020-07-04  1:14 ` [PATCH 1/8] drm/amd/display: Add diags scaling log by default Rodrigo Siqueira
  2020-07-04  1:14 ` [PATCH 2/8] drm/amd/display: Register init Rodrigo Siqueira
@ 2020-07-04  1:14 ` Rodrigo Siqueira
  2020-07-04  1:14 ` [PATCH 4/8] drm/amd/display: Remove VSC infoframe dep on DMCU Rodrigo Siqueira
                   ` (5 subsequent siblings)
  8 siblings, 0 replies; 11+ messages in thread
From: Rodrigo Siqueira @ 2020-07-04  1:14 UTC (permalink / raw)
  To: amd-gfx
  Cc: eryk.brol, Jaehyun Chung, Sunpeng.Li, Harry.Wentland,
	qingqing.zhuo, aurabindo.pillai, Bhawanpreet.Lakha, Anthony Koo

From: Jaehyun Chung <jaehyun.chung@amd.com>

[Why]
Current DAL behaviour is to not send VSIF if mode does not support VRR
(ie. FS range is < 10Hz). However, we should still set FS Native Color
Active bit in some unsupported mode cases.

[How]
Remove check for if VRR is supported before building infopacket.

Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 5ddfd6476ff9..d3a5ba9ee782 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -790,7 +790,7 @@ void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
 	 * Check if Freesync is supported. Return if false. If true,
 	 * set the corresponding bit in the info packet
 	 */
-	if (!vrr->supported || (!vrr->send_info_frame))
+	if (!vrr->send_info_frame)
 		return;
 
 	switch (packet_type) {
-- 
2.27.0

_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [PATCH 4/8] drm/amd/display: Remove VSC infoframe dep on DMCU
  2020-07-04  1:14 [PATCH 0/8] DC Patches July 03, 2020 Rodrigo Siqueira
                   ` (2 preceding siblings ...)
  2020-07-04  1:14 ` [PATCH 3/8] drm/amd/display: Send VSIF on unsupported modes on DAL Rodrigo Siqueira
@ 2020-07-04  1:14 ` Rodrigo Siqueira
  2020-07-04  1:14 ` [PATCH 5/8] drm/amd/display: [FW Promotion] Release 0.0.23 Rodrigo Siqueira
                   ` (4 subsequent siblings)
  8 siblings, 0 replies; 11+ messages in thread
From: Rodrigo Siqueira @ 2020-07-04  1:14 UTC (permalink / raw)
  To: amd-gfx
  Cc: eryk.brol, Sunpeng.Li, Harry.Wentland, qingqing.zhuo, Roman Li,
	aurabindo.pillai, Bhawanpreet.Lakha

From: Roman Li <roman.li@amd.com>

[Why]
VSC infoframe is needed for PSR. Previously only DMCU controller
supported PSR. Now DMUB also implements PSR.

[How]
Remove VSC infoframe dependency on DMCU.

Signed-off-by: Roman Li <roman.li@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 30 ++++++++-----------
 1 file changed, 13 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 132a2bde6a14..b4e120e95438 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4629,24 +4629,20 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
 
 	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
 		mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket, false, false);
-	if (stream->link->psr_settings.psr_feature_enabled)	{
-		struct dc  *core_dc = stream->link->ctx->dc;
-
-		if (dc_is_dmcu_initialized(core_dc)) {
-			//
-			// should decide stream support vsc sdp colorimetry capability
-			// before building vsc info packet
-			//
-			stream->use_vsc_sdp_for_colorimetry = false;
-			if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
-				stream->use_vsc_sdp_for_colorimetry =
-					aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
-			} else {
-				if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
-					stream->use_vsc_sdp_for_colorimetry = true;
-			}
-			mod_build_vsc_infopacket(stream, &stream->vsc_infopacket);
+	if (stream->link->psr_settings.psr_feature_enabled) {
+		//
+		// should decide stream support vsc sdp colorimetry capability
+		// before building vsc info packet
+		//
+		stream->use_vsc_sdp_for_colorimetry = false;
+		if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
+			stream->use_vsc_sdp_for_colorimetry =
+				aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
+		} else {
+			if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
+				stream->use_vsc_sdp_for_colorimetry = true;
 		}
+		mod_build_vsc_infopacket(stream, &stream->vsc_infopacket);
 	}
 finish:
 	dc_sink_release(sink);
-- 
2.27.0

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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [PATCH 5/8] drm/amd/display: [FW Promotion] Release 0.0.23
  2020-07-04  1:14 [PATCH 0/8] DC Patches July 03, 2020 Rodrigo Siqueira
                   ` (3 preceding siblings ...)
  2020-07-04  1:14 ` [PATCH 4/8] drm/amd/display: Remove VSC infoframe dep on DMCU Rodrigo Siqueira
@ 2020-07-04  1:14 ` Rodrigo Siqueira
  2020-07-04  1:14 ` [PATCH 6/8] drm/amd/display: 3.2.93 Rodrigo Siqueira
                   ` (3 subsequent siblings)
  8 siblings, 0 replies; 11+ messages in thread
From: Rodrigo Siqueira @ 2020-07-04  1:14 UTC (permalink / raw)
  To: amd-gfx
  Cc: eryk.brol, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
	aurabindo.pillai, Bhawanpreet.Lakha, Anthony Koo

From: Anthony Koo <Anthony.Koo@amd.com>

[Header Changes]
- Drop unused firmware SCRATCH bits from interface

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h    | 18 ++++++------------
 1 file changed, 6 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index d6c7a20c23b2..ce96143c402a 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -36,10 +36,10 @@
 
 /* Firmware versioning. */
 #ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x5b1691c92
-#define DMUB_FW_VERSION_MAJOR 1
+#define DMUB_FW_VERSION_GIT_HASH 0x5ad38d883
+#define DMUB_FW_VERSION_MAJOR 0
 #define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 22
+#define DMUB_FW_VERSION_REVISION 23
 #define DMUB_FW_VERSION_UCODE ((DMUB_FW_VERSION_MAJOR << 24) | (DMUB_FW_VERSION_MINOR << 16) | DMUB_FW_VERSION_REVISION)
 #endif
 
@@ -123,12 +123,15 @@ union dmub_psr_debug_flags {
  * @fw_region_size: size of the firmware state region
  * @trace_buffer_size: size of the tracebuffer region
  * @fw_version: the firmware version information
+ * @dal_fw: 1 if the firmware is DAL
  */
 struct dmub_fw_meta_info {
 	uint32_t magic_value;
 	uint32_t fw_region_size;
 	uint32_t trace_buffer_size;
 	uint32_t fw_version;
+	uint8_t dal_fw;
+	uint8_t reserved[3];
 };
 
 /* Ensure that the structure remains 64 bytes. */
@@ -151,15 +154,6 @@ union dmub_fw_meta {
  * SCRATCH15: FW Boot Options register
  */
 
-/**
- * DMCUB firmware status bits for SCRATCH2.
- */
-enum dmub_fw_status_bit {
-	DMUB_FW_STATUS_BIT_DAL_FIRMWARE = (1 << 0),
-	DMUB_FW_STATUS_BIT_COMMAND_TABLE_READY = (1 << 1),
-};
-
-
 /* Register bit definition for SCRATCH0 */
 union dmub_fw_boot_status {
 	struct {
-- 
2.27.0

_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [PATCH 6/8] drm/amd/display: 3.2.93
  2020-07-04  1:14 [PATCH 0/8] DC Patches July 03, 2020 Rodrigo Siqueira
                   ` (4 preceding siblings ...)
  2020-07-04  1:14 ` [PATCH 5/8] drm/amd/display: [FW Promotion] Release 0.0.23 Rodrigo Siqueira
@ 2020-07-04  1:14 ` Rodrigo Siqueira
  2020-07-04  1:14 ` [PATCH 7/8] drm/amd/display: Request PHYCLK adjustment on PHY enable/disable Rodrigo Siqueira
                   ` (2 subsequent siblings)
  8 siblings, 0 replies; 11+ messages in thread
From: Rodrigo Siqueira @ 2020-07-04  1:14 UTC (permalink / raw)
  To: amd-gfx
  Cc: eryk.brol, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
	aurabindo.pillai, Bhawanpreet.Lakha, Anthony Koo

From: Anthony Koo <Anthony.Koo@amd.com>

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 90cc3abe26f2..389edcf3f6ce 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -42,7 +42,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.92"
+#define DC_VER "3.2.93"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.27.0

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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [PATCH 7/8] drm/amd/display: Request PHYCLK adjustment on PHY enable/disable
  2020-07-04  1:14 [PATCH 0/8] DC Patches July 03, 2020 Rodrigo Siqueira
                   ` (5 preceding siblings ...)
  2020-07-04  1:14 ` [PATCH 6/8] drm/amd/display: 3.2.93 Rodrigo Siqueira
@ 2020-07-04  1:14 ` Rodrigo Siqueira
  2020-07-04  1:14 ` [PATCH 8/8] drm/amd/display: Add logger for SMU msg Rodrigo Siqueira
  2020-07-06 16:36 ` [PATCH 0/8] DC Patches July 03, 2020 Michel Dänzer
  8 siblings, 0 replies; 11+ messages in thread
From: Rodrigo Siqueira @ 2020-07-04  1:14 UTC (permalink / raw)
  To: amd-gfx
  Cc: Joshua Aberback, eryk.brol, Sunpeng.Li, Harry.Wentland,
	qingqing.zhuo, aurabindo.pillai, Jun Lei, Bhawanpreet.Lakha

From: Joshua Aberback <joshua.aberback@amd.com>

[Why]
Currently we don't explicitly send a request for a minimum PHYCLK, and
we hope that the dependencies other clocks have will raise PHYCLK when
needed.

[How]
- new clk_mgr function to keep track of PHYCLK requirements
- request maximum requirement across all links
- remove PHYCLK from clock state comparator, as it doesn't come from DML

Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c  | 35 ++++++++++++++-----
 .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 27 ++++++++++----
 .../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c  | 32 ++++++++++++-----
 .../drm/amd/display/dc/core/dc_link_hwss.c    | 11 ++++--
 .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h   |  3 ++
 .../amd/display/dc/inc/hw/clk_mgr_internal.h  |  2 ++
 6 files changed, 85 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index c63ec960e116..f2114bc910bf 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -184,13 +184,6 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
 			pp_smu->set_display_count(&pp_smu->pp_smu, display_count);
 	}
 
-	if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
-		clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
-		if (pp_smu && pp_smu->set_voltage_by_freq)
-			pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);
-	}
-
-
 	if (dc->debug.force_min_dcfclk_mhz > 0)
 		new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
 				new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
@@ -417,8 +410,6 @@ static bool dcn2_are_clock_states_equal(struct dc_clocks *a,
 		return false;
 	else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
 		return false;
-	else if (a->phyclk_khz != b->phyclk_khz)
-		return false;
 	else if (a->dramclk_khz != b->dramclk_khz)
 		return false;
 	else if (a->p_state_change_support != b->p_state_change_support)
@@ -427,6 +418,31 @@ static bool dcn2_are_clock_states_equal(struct dc_clocks *a,
 	return true;
 }
 
+/* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
+static void dcn2_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	unsigned int i, max_phyclk_req = 0;
+	struct pp_smu_funcs_nv *pp_smu = NULL;
+
+	if (!clk_mgr->pp_smu || !clk_mgr->pp_smu->nv_funcs.set_voltage_by_freq)
+		return;
+
+	pp_smu = &clk_mgr->pp_smu->nv_funcs;
+
+	clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
+
+	for (i = 0; i < MAX_PIPES * 2; i++) {
+		if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)
+			max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];
+	}
+
+	if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) {
+		clk_mgr_base->clks.phyclk_khz = max_phyclk_req;
+		pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);
+	}
+}
+
 static struct clk_mgr_funcs dcn2_funcs = {
 	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
 	.update_clocks = dcn2_update_clocks,
@@ -434,6 +450,7 @@ static struct clk_mgr_funcs dcn2_funcs = {
 	.enable_pme_wa = dcn2_enable_pme_wa,
 	.get_clock = dcn2_get_clock,
 	.are_clock_states_equal = dcn2_are_clock_states_equal,
+	.notify_link_rate_change = dcn2_notify_link_rate_change,
 };
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 39788a7bd003..9b4807f52381 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -136,11 +136,6 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
 		}
 	}
 
-	if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
-		clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
-		rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz);
-	}
-
 	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
 		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
 		rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
@@ -496,13 +491,33 @@ static bool rn_are_clock_states_equal(struct dc_clocks *a,
 }
 
 
+/* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
+static void rn_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	unsigned int i, max_phyclk_req = 0;
+
+	clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
+
+	for (i = 0; i < MAX_PIPES * 2; i++) {
+		if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)
+			max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];
+	}
+
+	if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) {
+		clk_mgr_base->clks.phyclk_khz = max_phyclk_req;
+		rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz);
+	}
+}
+
 static struct clk_mgr_funcs dcn21_funcs = {
 	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
 	.update_clocks = rn_update_clocks,
 	.init_clocks = rn_init_clocks,
 	.enable_pme_wa = rn_enable_pme_wa,
 	.are_clock_states_equal = rn_are_clock_states_equal,
-	.notify_wm_ranges = rn_notify_wm_ranges
+	.notify_wm_ranges = rn_notify_wm_ranges,
+	.notify_link_rate_change = rn_notify_link_rate_change,
 };
 
 static struct clk_bw_params rn_bw_params = {
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
index 872ee08b315f..d94fdc52be37 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
@@ -260,11 +260,6 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base,
 	if (enter_display_off == safe_to_lower)
 		dcn30_smu_set_num_of_displays(clk_mgr, display_count);
 
-	if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
-		clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
-		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);
-	}
-
 	if (dc->debug.force_min_dcfclk_mhz > 0)
 		new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
 				new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
@@ -431,8 +426,6 @@ static bool dcn3_are_clock_states_equal(struct dc_clocks *a,
 		return false;
 	else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
 		return false;
-	else if (a->phyclk_khz != b->phyclk_khz)
-		return false;
 	else if (a->dramclk_khz != b->dramclk_khz)
 		return false;
 	else if (a->p_state_change_support != b->p_state_change_support)
@@ -451,6 +444,28 @@ static void dcn3_enable_pme_wa(struct clk_mgr *clk_mgr_base)
 	dcn30_smu_set_pme_workaround(clk_mgr);
 }
 
+/* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
+static void dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	unsigned int i, max_phyclk_req = clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz * 1000;
+
+	if (!clk_mgr->smu_present)
+		return;
+
+	clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
+
+	for (i = 0; i < MAX_PIPES * 2; i++) {
+		if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)
+			max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];
+	}
+
+	if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) {
+		clk_mgr_base->clks.phyclk_khz = max_phyclk_req;
+		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);
+	}
+}
+
 static struct clk_mgr_funcs dcn3_funcs = {
 		.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
 		.update_clocks = dcn3_update_clocks,
@@ -460,7 +475,8 @@ static struct clk_mgr_funcs dcn3_funcs = {
 		.set_hard_max_memclk = dcn3_set_hard_max_memclk,
 		.get_memclk_states_from_smu = dcn3_get_memclk_states_from_smu,
 		.are_clock_states_equal = dcn3_are_clock_states_equal,
-		.enable_pme_wa = dcn3_enable_pme_wa
+		.enable_pme_wa = dcn3_enable_pme_wa,
+		.notify_link_rate_change = dcn30_notify_link_rate_change,
 };
 
 static void dcn3_init_clocks_fpga(struct clk_mgr *clk_mgr)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index d0a23b72e604..dd88eb348dfa 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -14,6 +14,7 @@
 #include "dpcd_defs.h"
 #include "dsc.h"
 #include "resource.h"
+#include "clk_mgr.h"
 
 static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
 {
@@ -123,6 +124,11 @@ void dp_enable_link_phy(
 		}
 	}
 
+	link->cur_link_settings = *link_settings;
+
+	if (dc->clk_mgr->funcs->notify_link_rate_change)
+		dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);
+
 	if (dmcu != NULL && dmcu->funcs->lock_phy)
 		dmcu->funcs->lock_phy(dmcu);
 
@@ -141,8 +147,6 @@ void dp_enable_link_phy(
 	if (dmcu != NULL && dmcu->funcs->unlock_phy)
 		dmcu->funcs->unlock_phy(dmcu);
 
-	link->cur_link_settings = *link_settings;
-
 	dp_receiver_power_ctrl(link, true);
 }
 
@@ -234,6 +238,9 @@ void dp_disable_link_phy(struct dc_link *link, enum signal_type signal)
 	/* Clear current link setting.*/
 	memset(&link->cur_link_settings, 0,
 			sizeof(link->cur_link_settings));
+
+	if (dc->clk_mgr->funcs->notify_link_rate_change)
+		dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);
 }
 
 void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index 505357597603..5994d2a33c40 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -241,6 +241,9 @@ struct clk_mgr_funcs {
 	bool (*are_clock_states_equal) (struct dc_clocks *a,
 			struct dc_clocks *b);
 	void (*notify_wm_ranges)(struct clk_mgr *clk_mgr);
+
+	/* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
+	void (*notify_link_rate_change)(struct clk_mgr *clk_mgr, struct dc_link *link);
 #ifdef CONFIG_DRM_AMD_DC_DCN3_0
 	/*
 	 * Send message to PMFW to set hard min memclk frequency
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index 82212ae2755a..b3b8b46d293e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -270,6 +270,8 @@ struct clk_mgr_internal {
 
 	enum dm_pp_clocks_state max_clks_state;
 	enum dm_pp_clocks_state cur_min_clks_state;
+
+	unsigned int cur_phyclk_req_table[MAX_PIPES * 2];
 #ifdef CONFIG_DRM_AMD_DC_DCN3_0
 
 	bool smu_present;
-- 
2.27.0

_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [PATCH 8/8] drm/amd/display: Add logger for SMU msg
  2020-07-04  1:14 [PATCH 0/8] DC Patches July 03, 2020 Rodrigo Siqueira
                   ` (6 preceding siblings ...)
  2020-07-04  1:14 ` [PATCH 7/8] drm/amd/display: Request PHYCLK adjustment on PHY enable/disable Rodrigo Siqueira
@ 2020-07-04  1:14 ` Rodrigo Siqueira
  2020-07-06 16:36 ` [PATCH 0/8] DC Patches July 03, 2020 Michel Dänzer
  8 siblings, 0 replies; 11+ messages in thread
From: Rodrigo Siqueira @ 2020-07-04  1:14 UTC (permalink / raw)
  To: amd-gfx
  Cc: Joshua Aberback, Wesley Chalmers, eryk.brol, Sunpeng.Li,
	Harry.Wentland, qingqing.zhuo, aurabindo.pillai,
	Bhawanpreet.Lakha

From: Wesley Chalmers <Wesley.Chalmers@amd.com>

[WHY]
We want to be able to see SMU messages sent and their responses

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 .../dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c  | 65 ++++++++++++++++++-
 .../drm/amd/display/include/logger_types.h    |  2 +
 2 files changed, 64 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
index 986c53a3b6a8..7ee3ec5a8af8 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
@@ -37,6 +37,13 @@
 #define REG(reg_name) \
 	mm ## reg_name
 
+#include "logger_types.h"
+#undef DC_LOGGER
+#define DC_LOGGER \
+	CTX->logger
+#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
+
+
 /*
  * Function to be used instead of REG_WAIT macro because the wait ends when
  * the register is NOT EQUAL to zero, and because the translation in msg_if.h
@@ -94,6 +101,8 @@ bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input)
 {
 	uint32_t response = 0;
 
+	smu_print("SMU Test message: %d\n", input);
+
 	if (dcn30_smu_send_msg_with_param(clk_mgr,
 			DALSMC_MSG_TestMessage, input, &response))
 		if (response == input + 1)
@@ -104,9 +113,15 @@ bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input)
 
 bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version)
 {
+	smu_print("SMU Get SMU version\n");
+
 	if (dcn30_smu_send_msg_with_param(clk_mgr,
-			DALSMC_MSG_GetSmuVersion, 0, version))
+			DALSMC_MSG_GetSmuVersion, 0, version)) {
+
+		smu_print("SMU version: %d\n", *version);
+
 		return true;
+	}
 
 	return false;
 }
@@ -116,10 +131,16 @@ bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr)
 {
 	uint32_t response = 0;
 
+	smu_print("SMU Check driver if version\n");
+
 	if (dcn30_smu_send_msg_with_param(clk_mgr,
-			DALSMC_MSG_GetDriverIfVersion, 0, &response))
+			DALSMC_MSG_GetDriverIfVersion, 0, &response)) {
+
+		smu_print("SMU driver if version: %d\n", response);
+
 		if (response == SMU11_DRIVER_IF_VERSION)
 			return true;
+	}
 
 	return false;
 }
@@ -129,34 +150,48 @@ bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr)
 {
 	uint32_t response = 0;
 
+	smu_print("SMU Check msg header version\n");
+
 	if (dcn30_smu_send_msg_with_param(clk_mgr,
-			DALSMC_MSG_GetMsgHeaderVersion, 0, &response))
+			DALSMC_MSG_GetMsgHeaderVersion, 0, &response)) {
+
+		smu_print("SMU msg header version: %d\n", response);
+
 		if (response == DALSMC_VERSION)
 			return true;
+	}
 
 	return false;
 }
 
 void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)
 {
+	smu_print("SMU Set DRAM addr high: %d\n", addr_high);
+
 	dcn30_smu_send_msg_with_param(clk_mgr,
 			DALSMC_MSG_SetDalDramAddrHigh, addr_high, NULL);
 }
 
 void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)
 {
+	smu_print("SMU Set DRAM addr low: %d\n", addr_low);
+
 	dcn30_smu_send_msg_with_param(clk_mgr,
 			DALSMC_MSG_SetDalDramAddrLow, addr_low, NULL);
 }
 
 void dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)
 {
+	smu_print("SMU Transfer WM table SMU 2 DRAM\n");
+
 	dcn30_smu_send_msg_with_param(clk_mgr,
 			DALSMC_MSG_TransferTableSmu2Dram, TABLE_WATERMARKS, NULL);
 }
 
 void dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
 {
+	smu_print("SMU Transfer WM table DRAM 2 SMU\n");
+
 	dcn30_smu_send_msg_with_param(clk_mgr,
 			DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS, NULL);
 }
@@ -169,9 +204,13 @@ unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, PP
 	/* bits 23:16 for clock type, lower 16 bits for frequency in MHz */
 	uint32_t param = (clk << 16) | freq_mhz;
 
+	smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz);
+
 	dcn30_smu_send_msg_with_param(clk_mgr,
 			DALSMC_MSG_SetHardMinByFreq, param, &response);
 
+	smu_print("SMU Frequency set = %d MHz\n", response);
+
 	return response;
 }
 
@@ -183,9 +222,13 @@ unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, PP
 	/* bits 23:16 for clock type, lower 16 bits for frequency in MHz */
 	uint32_t param = (clk << 16) | freq_mhz;
 
+	smu_print("SMU Set hard max by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz);
+
 	dcn30_smu_send_msg_with_param(clk_mgr,
 			DALSMC_MSG_SetHardMaxByFreq, param, &response);
 
+	smu_print("SMU Frequency set = %d MHz\n", response);
+
 	return response;
 }
 
@@ -210,9 +253,13 @@ unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, P
 	/* bits 23:16 for clock type, lower 8 bits for DPM level */
 	uint32_t param = (clk << 16) | dpm_level;
 
+	smu_print("SMU Get dpm freq by index: clk = %d, dpm_level = %d\n", clk, dpm_level);
+
 	dcn30_smu_send_msg_with_param(clk_mgr,
 			DALSMC_MSG_GetDpmFreqByIndex, param, &response);
 
+	smu_print("SMU dpm freq: %d MHz\n", response);
+
 	return response;
 }
 
@@ -224,32 +271,44 @@ unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr
 	/* bits 23:16 for clock type */
 	uint32_t param = clk << 16;
 
+	smu_print("SMU Get DC mode max DPM freq: clk = %d\n", clk);
+
 	dcn30_smu_send_msg_with_param(clk_mgr,
 			DALSMC_MSG_GetDcModeMaxDpmFreq, param, &response);
 
+	smu_print("SMU DC mode max DMP freq: %d MHz\n", response);
+
 	return response;
 }
 
 void dcn30_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz)
 {
+	smu_print("SMU Set min deep sleep dcef clk: freq_mhz = %d MHz\n", freq_mhz);
+
 	dcn30_smu_send_msg_with_param(clk_mgr,
 			DALSMC_MSG_SetMinDeepSleepDcefclk, freq_mhz, NULL);
 }
 
 void dcn30_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays)
 {
+	smu_print("SMU Set num of displays: num_displays = %d\n", num_displays);
+
 	dcn30_smu_send_msg_with_param(clk_mgr,
 			DALSMC_MSG_NumOfDisplays, num_displays, NULL);
 }
 
 void dcn30_smu_set_external_client_df_cstate_allow(struct clk_mgr_internal *clk_mgr, bool enable)
 {
+	smu_print("SMU Set external client df cstate allow: enable = %d\n", enable);
+
 	dcn30_smu_send_msg_with_param(clk_mgr,
 			DALSMC_MSG_SetExternalClientDfCstateAllow, enable ? 1 : 0, NULL);
 }
 
 void dcn30_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr)
 {
+	smu_print("SMU Set PME workaround\n");
+
 	dcn30_smu_send_msg_with_param(clk_mgr,
 	DALSMC_MSG_BacoAudioD3PME, 0, NULL);
 }
diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h b/drivers/gpu/drm/amd/display/include/logger_types.h
index 5dea27fc5198..21bbee17c527 100644
--- a/drivers/gpu/drm/amd/display/include/logger_types.h
+++ b/drivers/gpu/drm/amd/display/include/logger_types.h
@@ -67,6 +67,7 @@
 #define DC_LOG_ALL_GAMMA(...) pr_debug("[GAMMA]:"__VA_ARGS__)
 #define DC_LOG_ALL_TF_CHANNELS(...) pr_debug("[GAMMA]:"__VA_ARGS__)
 #define DC_LOG_DSC(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_SMU(...) pr_debug("[SMU_MSG]:"__VA_ARGS__)
 #define DC_LOG_DWB(...) DRM_DEBUG_KMS(__VA_ARGS__)
 
 struct dal_logger;
@@ -113,6 +114,7 @@ enum dc_log_type {
 	LOG_DISPLAYSTATS,
 	LOG_HDMI_RETIMER_REDRIVER,
 	LOG_DSC,
+	LOG_SMU_MSG,
 	LOG_DWB,
 	LOG_GAMMA_DEBUG,
 	LOG_MAX_HW_POINTS,
-- 
2.27.0

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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 11+ messages in thread
* Re: [PATCH 0/8] DC Patches July 03, 2020
  2020-07-04  1:14 [PATCH 0/8] DC Patches July 03, 2020 Rodrigo Siqueira
                   ` (7 preceding siblings ...)
  2020-07-04  1:14 ` [PATCH 8/8] drm/amd/display: Add logger for SMU msg Rodrigo Siqueira
@ 2020-07-06 16:36 ` Michel Dänzer
  2020-07-10 20:24   ` Rodrigo Siqueira
  8 siblings, 1 reply; 11+ messages in thread
From: Michel Dänzer @ 2020-07-06 16:36 UTC (permalink / raw)
  To: Rodrigo Siqueira
  Cc: eryk.brol, Sunpeng.Li, Bhawanpreet.Lakha, qingqing.zhuo, amd-gfx,
	aurabindo.pillai, Harry.Wentland

On 2020-07-04 3:14 a.m., Rodrigo Siqueira wrote:
> This DC patchset brings improvements in multiple areas. In summary, we
> have:
> * SMU logger messages
> * DMCU improvements
> * Bug fixes

Are you guys keeping track of upstream bug reports like e.g.
https://gitlab.freedesktop.org/drm/amd/-/issues/1108 ? (I also reported
that on the amd-gfx list early in the 4.7 cycle)


-- 
Earthling Michel Dänzer               |               https://redhat.com
Libre software enthusiast             |             Mesa and X developer
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [PATCH 0/8] DC Patches July 03, 2020
  2020-07-06 16:36 ` [PATCH 0/8] DC Patches July 03, 2020 Michel Dänzer
@ 2020-07-10 20:24   ` Rodrigo Siqueira
  0 siblings, 0 replies; 11+ messages in thread
From: Rodrigo Siqueira @ 2020-07-10 20:24 UTC (permalink / raw)
  To: Michel Dänzer
  Cc: eryk.brol, Sunpeng.Li, Harry.Wentland, qingqing.zhuo, amd-gfx,
	aurabindo.pillai, Bhawanpreet.Lakha


[-- Attachment #1.1: Type: text/plain, Size: 1948 bytes --]

Hi Michel,

We try to follow tickets reported in FDO and try to make a triage of it
(using the DC label). However, we need to find a better process to keep
track of FDO bugs and try to map some of the fixes in our weekly
promotion.

Best Regards
Rodrigo Siqueira

On 07/06, Michel Dänzer wrote:
> On 2020-07-04 3:14 a.m., Rodrigo Siqueira wrote:
> > This DC patchset brings improvements in multiple areas. In summary, we
> > have:
> > * SMU logger messages
> > * DMCU improvements
> > * Bug fixes
> 
> Are you guys keeping track of upstream bug reports like e.g.
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Famd%2F-%2Fissues%2F1108&amp;data=02%7C01%7CRodrigo.Siqueira%40amd.com%7C247ae3741e1640db86b708d821cacc44%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637296502193019525&amp;sdata=TQrrKligwedm0lVWldziBLr4LQVyt2gFEAvz0WAH6oc%3D&amp;reserved=0 ? (I also reported
> that on the amd-gfx list early in the 4.7 cycle)
> 
> 
> -- 
> Earthling Michel Dänzer               |               https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fredhat.com%2F&amp;data=02%7C01%7CRodrigo.Siqueira%40amd.com%7C247ae3741e1640db86b708d821cacc44%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637296502193019525&amp;sdata=l%2BztOfG%2BVHJ2Niv5TqiYmFbjjZvMI%2F2%2F0D5CAagPR1E%3D&amp;reserved=0
> Libre software enthusiast             |             Mesa and X developer
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7CRodrigo.Siqueira%40amd.com%7C247ae3741e1640db86b708d821cacc44%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637296502193019525&amp;sdata=UmKL%2Bbe3dKiOT1LW1p4y42mdC%2FiHp1Dz2L8x%2FOSHvaQ%3D&amp;reserved=0

-- 
Rodrigo Siqueira
https://siqueira.tech

[-- Attachment #1.2: signature.asc --]
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[-- Attachment #2: Type: text/plain, Size: 154 bytes --]

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^ permalink raw reply	[flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-07-10 20:24 UTC | newest]

Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-04  1:14 [PATCH 0/8] DC Patches July 03, 2020 Rodrigo Siqueira
2020-07-04  1:14 ` [PATCH 1/8] drm/amd/display: Add diags scaling log by default Rodrigo Siqueira
2020-07-04  1:14 ` [PATCH 2/8] drm/amd/display: Register init Rodrigo Siqueira
2020-07-04  1:14 ` [PATCH 3/8] drm/amd/display: Send VSIF on unsupported modes on DAL Rodrigo Siqueira
2020-07-04  1:14 ` [PATCH 4/8] drm/amd/display: Remove VSC infoframe dep on DMCU Rodrigo Siqueira
2020-07-04  1:14 ` [PATCH 5/8] drm/amd/display: [FW Promotion] Release 0.0.23 Rodrigo Siqueira
2020-07-04  1:14 ` [PATCH 6/8] drm/amd/display: 3.2.93 Rodrigo Siqueira
2020-07-04  1:14 ` [PATCH 7/8] drm/amd/display: Request PHYCLK adjustment on PHY enable/disable Rodrigo Siqueira
2020-07-04  1:14 ` [PATCH 8/8] drm/amd/display: Add logger for SMU msg Rodrigo Siqueira
2020-07-06 16:36 ` [PATCH 0/8] DC Patches July 03, 2020 Michel Dänzer
2020-07-10 20:24   ` Rodrigo Siqueira

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