* [Intel-gfx] [PATCH v4 1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder
@ 2020-07-08 20:55 José Roberto de Souza
2020-07-08 20:55 ` [Intel-gfx] [PATCH v4 2/5] drm/i915/display: Remove port and phy from voltage swing functions José Roberto de Souza
` (10 more replies)
0 siblings, 11 replies; 17+ messages in thread
From: José Roberto de Souza @ 2020-07-08 20:55 UTC (permalink / raw)
To: intel-gfx
intel_encoder will be needed inside of vswing functions in a future
patch, so here doing this change in all vswing functions since HSW.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 164 +++++++++++++----------
1 file changed, 95 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 5773ebefffc7..e80319aa7cf0 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -707,8 +707,10 @@ static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] =
};
static const struct ddi_buf_trans *
-bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
+bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
if (dev_priv->vbt.edp.low_vswing) {
*n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
return bdw_ddi_translations_edp;
@@ -719,8 +721,10 @@ bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
}
static const struct ddi_buf_trans *
-skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
+skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
if (IS_SKL_ULX(dev_priv)) {
*n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
return skl_y_ddi_translations_dp;
@@ -734,8 +738,10 @@ skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
}
static const struct ddi_buf_trans *
-kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
+kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
if (IS_KBL_ULX(dev_priv) ||
IS_CFL_ULX(dev_priv) ||
IS_CML_ULX(dev_priv)) {
@@ -753,8 +759,10 @@ kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
}
static const struct ddi_buf_trans *
-skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
+skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
if (dev_priv->vbt.edp.low_vswing) {
if (IS_SKL_ULX(dev_priv) ||
IS_KBL_ULX(dev_priv) ||
@@ -777,9 +785,9 @@ skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
if (IS_KABYLAKE(dev_priv) ||
IS_COFFEELAKE(dev_priv) ||
IS_COMETLAKE(dev_priv))
- return kbl_get_buf_trans_dp(dev_priv, n_entries);
+ return kbl_get_buf_trans_dp(encoder, n_entries);
else
- return skl_get_buf_trans_dp(dev_priv, n_entries);
+ return skl_get_buf_trans_dp(encoder, n_entries);
}
static const struct ddi_buf_trans *
@@ -807,19 +815,21 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries)
}
static const struct ddi_buf_trans *
-intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
+intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder,
enum port port, int *n_entries)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
if (IS_KABYLAKE(dev_priv) ||
IS_COFFEELAKE(dev_priv) ||
IS_COMETLAKE(dev_priv)) {
const struct ddi_buf_trans *ddi_translations =
- kbl_get_buf_trans_dp(dev_priv, n_entries);
+ kbl_get_buf_trans_dp(encoder, n_entries);
*n_entries = skl_buf_trans_num_entries(port, *n_entries);
return ddi_translations;
} else if (IS_SKYLAKE(dev_priv)) {
const struct ddi_buf_trans *ddi_translations =
- skl_get_buf_trans_dp(dev_priv, n_entries);
+ skl_get_buf_trans_dp(encoder, n_entries);
*n_entries = skl_buf_trans_num_entries(port, *n_entries);
return ddi_translations;
} else if (IS_BROADWELL(dev_priv)) {
@@ -835,16 +845,18 @@ intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
}
static const struct ddi_buf_trans *
-intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
+intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder,
enum port port, int *n_entries)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
if (IS_GEN9_BC(dev_priv)) {
const struct ddi_buf_trans *ddi_translations =
- skl_get_buf_trans_edp(dev_priv, n_entries);
+ skl_get_buf_trans_edp(encoder, n_entries);
*n_entries = skl_buf_trans_num_entries(port, *n_entries);
return ddi_translations;
} else if (IS_BROADWELL(dev_priv)) {
- return bdw_get_buf_trans_edp(dev_priv, n_entries);
+ return bdw_get_buf_trans_edp(encoder, n_entries);
} else if (IS_HASWELL(dev_priv)) {
*n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
return hsw_ddi_translations_dp;
@@ -871,9 +883,11 @@ intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
}
static const struct ddi_buf_trans *
-intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
+intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder,
int *n_entries)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
if (IS_GEN9_BC(dev_priv)) {
return skl_get_buf_trans_hdmi(dev_priv, n_entries);
} else if (IS_BROADWELL(dev_priv)) {
@@ -889,33 +903,36 @@ intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
}
static const struct bxt_ddi_buf_trans *
-bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
+bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
{
*n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
return bxt_ddi_translations_dp;
}
static const struct bxt_ddi_buf_trans *
-bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
+bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
if (dev_priv->vbt.edp.low_vswing) {
*n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
return bxt_ddi_translations_edp;
}
- return bxt_get_buf_trans_dp(dev_priv, n_entries);
+ return bxt_get_buf_trans_dp(encoder, n_entries);
}
static const struct bxt_ddi_buf_trans *
-bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
+bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries)
{
*n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
return bxt_ddi_translations_hdmi;
}
static const struct cnl_ddi_buf_trans *
-cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
+cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
if (voltage == VOLTAGE_INFO_0_85V) {
@@ -935,8 +952,9 @@ cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
}
static const struct cnl_ddi_buf_trans *
-cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
+cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
if (voltage == VOLTAGE_INFO_0_85V) {
@@ -956,8 +974,9 @@ cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
}
static const struct cnl_ddi_buf_trans *
-cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
+cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
if (dev_priv->vbt.edp.low_vswing) {
@@ -976,14 +995,16 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
}
return NULL;
} else {
- return cnl_get_buf_trans_dp(dev_priv, n_entries);
+ return cnl_get_buf_trans_dp(encoder, n_entries);
}
}
static const struct cnl_ddi_buf_trans *
-icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
+icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
int *n_entries)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
if (type == INTEL_OUTPUT_HDMI) {
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
return icl_combo_phy_ddi_translations_hdmi;
@@ -1000,7 +1021,7 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
}
static const struct icl_mg_phy_ddi_buf_trans *
-icl_get_mg_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
+icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
int *n_entries)
{
if (type == INTEL_OUTPUT_HDMI) {
@@ -1016,7 +1037,7 @@ icl_get_mg_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
}
static const struct cnl_ddi_buf_trans *
-ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
+ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
int *n_entries)
{
if (type != INTEL_OUTPUT_HDMI && type != INTEL_OUTPUT_EDP) {
@@ -1024,15 +1045,15 @@ ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
return ehl_combo_phy_ddi_translations_dp;
}
- return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries);
+ return icl_get_combo_buf_trans(encoder, type, rate, n_entries);
}
static const struct cnl_ddi_buf_trans *
-tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
+tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
int *n_entries)
{
if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) {
- return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries);
+ return icl_get_combo_buf_trans(encoder, type, rate, n_entries);
} else if (rate > 270000) {
*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
return tgl_combo_phy_ddi_translations_dp_hbr2;
@@ -1043,7 +1064,7 @@ tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
}
static const struct tgl_dkl_phy_ddi_buf_trans *
-tgl_get_dkl_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
+tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int type, int rate,
int *n_entries)
{
if (type == INTEL_OUTPUT_HDMI) {
@@ -1066,34 +1087,34 @@ static int intel_ddi_hdmi_level(struct intel_encoder *encoder)
if (INTEL_GEN(dev_priv) >= 12) {
if (intel_phy_is_combo(dev_priv, phy))
- tgl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
+ tgl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
0, &n_entries);
else
- tgl_get_dkl_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0,
+ tgl_get_dkl_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
&n_entries);
default_entry = n_entries - 1;
} else if (INTEL_GEN(dev_priv) == 11) {
if (intel_phy_is_combo(dev_priv, phy))
- icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
+ icl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
0, &n_entries);
else
- icl_get_mg_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0,
+ icl_get_mg_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
&n_entries);
default_entry = n_entries - 1;
} else if (IS_CANNONLAKE(dev_priv)) {
- cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
+ cnl_get_buf_trans_hdmi(encoder, &n_entries);
default_entry = n_entries - 1;
} else if (IS_GEN9_LP(dev_priv)) {
- bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
+ bxt_get_buf_trans_hdmi(encoder, &n_entries);
default_entry = n_entries - 1;
} else if (IS_GEN9_BC(dev_priv)) {
- intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
+ intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
default_entry = 8;
} else if (IS_BROADWELL(dev_priv)) {
- intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
+ intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
default_entry = 7;
} else if (IS_HASWELL(dev_priv)) {
- intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
+ intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
default_entry = 6;
} else {
drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n");
@@ -1131,10 +1152,10 @@ static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
&n_entries);
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
- ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
+ ddi_translations = intel_ddi_get_buf_trans_edp(encoder, port,
&n_entries);
else
- ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
+ ddi_translations = intel_ddi_get_buf_trans_dp(encoder, port,
&n_entries);
/* If we're boosting the current, set bit 31 of trans1 */
@@ -1163,7 +1184,7 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
enum port port = encoder->port;
const struct ddi_buf_trans *ddi_translations;
- ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
+ ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
return;
@@ -2098,11 +2119,15 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder,
int n_entries;
if (type == INTEL_OUTPUT_HDMI)
- ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
+ ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
else if (type == INTEL_OUTPUT_EDP)
- ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
+ ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
+ port,
+ &n_entries);
else
- ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
+ ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
+ port,
+ &n_entries);
if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
return;
@@ -2133,11 +2158,11 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
int n_entries;
if (type == INTEL_OUTPUT_HDMI)
- ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
+ ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries);
else if (type == INTEL_OUTPUT_EDP)
- ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
+ ddi_translations = bxt_get_buf_trans_edp(encoder, &n_entries);
else
- ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
+ ddi_translations = bxt_get_buf_trans_dp(encoder, &n_entries);
if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
return;
@@ -2161,36 +2186,36 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
if (INTEL_GEN(dev_priv) >= 12) {
if (intel_phy_is_combo(dev_priv, phy))
- tgl_get_combo_buf_trans(dev_priv, encoder->type,
+ tgl_get_combo_buf_trans(encoder, encoder->type,
intel_dp->link_rate, &n_entries);
else
- tgl_get_dkl_buf_trans(dev_priv, encoder->type,
+ tgl_get_dkl_buf_trans(encoder, encoder->type,
intel_dp->link_rate, &n_entries);
} else if (INTEL_GEN(dev_priv) == 11) {
if (IS_ELKHARTLAKE(dev_priv))
- ehl_get_combo_buf_trans(dev_priv, encoder->type,
+ ehl_get_combo_buf_trans(encoder, encoder->type,
intel_dp->link_rate, &n_entries);
else if (intel_phy_is_combo(dev_priv, phy))
- icl_get_combo_buf_trans(dev_priv, encoder->type,
+ icl_get_combo_buf_trans(encoder, encoder->type,
intel_dp->link_rate, &n_entries);
else
- icl_get_mg_buf_trans(dev_priv, encoder->type,
+ icl_get_mg_buf_trans(encoder, encoder->type,
intel_dp->link_rate, &n_entries);
} else if (IS_CANNONLAKE(dev_priv)) {
if (encoder->type == INTEL_OUTPUT_EDP)
- cnl_get_buf_trans_edp(dev_priv, &n_entries);
+ cnl_get_buf_trans_edp(encoder, &n_entries);
else
- cnl_get_buf_trans_dp(dev_priv, &n_entries);
+ cnl_get_buf_trans_dp(encoder, &n_entries);
} else if (IS_GEN9_LP(dev_priv)) {
if (encoder->type == INTEL_OUTPUT_EDP)
- bxt_get_buf_trans_edp(dev_priv, &n_entries);
+ bxt_get_buf_trans_edp(encoder, &n_entries);
else
- bxt_get_buf_trans_dp(dev_priv, &n_entries);
+ bxt_get_buf_trans_dp(encoder, &n_entries);
} else {
if (encoder->type == INTEL_OUTPUT_EDP)
- intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
+ intel_ddi_get_buf_trans_edp(encoder, port, &n_entries);
else
- intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
+ intel_ddi_get_buf_trans_dp(encoder, port, &n_entries);
}
if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
@@ -2223,11 +2248,11 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
u32 val;
if (type == INTEL_OUTPUT_HDMI)
- ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
+ ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries);
else if (type == INTEL_OUTPUT_EDP)
- ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
+ ddi_translations = cnl_get_buf_trans_edp(encoder, &n_entries);
else
- ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
+ ddi_translations = cnl_get_buf_trans_dp(encoder, &n_entries);
if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
return;
@@ -2344,22 +2369,23 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
}
-static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
- u32 level, enum phy phy, int type,
- int rate)
+static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
+ u32 level, enum phy phy, int type,
+ int rate)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
const struct cnl_ddi_buf_trans *ddi_translations = NULL;
u32 n_entries, val;
int ln;
if (INTEL_GEN(dev_priv) >= 12)
- ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate,
+ ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate,
&n_entries);
else if (IS_ELKHARTLAKE(dev_priv))
- ddi_translations = ehl_get_combo_buf_trans(dev_priv, type, rate,
+ ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate,
&n_entries);
else
- ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
+ ddi_translations = icl_get_combo_buf_trans(encoder, type, rate,
&n_entries);
if (!ddi_translations)
return;
@@ -2471,7 +2497,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
/* 5. Program swing and de-emphasis */
- icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
+ icl_ddi_combo_vswing_program(encoder, level, phy, type, rate);
/* 6. Set training enable to trigger update */
val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
@@ -2495,7 +2521,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
rate = intel_dp->link_rate;
}
- ddi_translations = icl_get_mg_buf_trans(dev_priv, type, rate,
+ ddi_translations = icl_get_mg_buf_trans(encoder, type, rate,
&n_entries);
/* The table does not have values for level 3 and level 9. */
if (level >= n_entries || level == 3 || level == 9) {
@@ -2640,7 +2666,7 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
rate = intel_dp->link_rate;
}
- ddi_translations = tgl_get_dkl_buf_trans(dev_priv, encoder->type, rate,
+ ddi_translations = tgl_get_dkl_buf_trans(encoder, encoder->type, rate,
&n_entries);
if (level >= n_entries)
--
2.27.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH v4 2/5] drm/i915/display: Remove port and phy from voltage swing functions
2020-07-08 20:55 [Intel-gfx] [PATCH v4 1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder José Roberto de Souza
@ 2020-07-08 20:55 ` José Roberto de Souza
2020-07-09 14:12 ` Ville Syrjälä
2020-07-08 20:55 ` [Intel-gfx] [PATCH v4 3/5] drm/i915/bios: Parse HOBL parameter José Roberto de Souza
` (9 subsequent siblings)
10 siblings, 1 reply; 17+ messages in thread
From: José Roberto de Souza @ 2020-07-08 20:55 UTC (permalink / raw)
To: intel-gfx
This information can be get directly from intel_encoder so no need
of those parameters.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 33 ++++++++++--------------
1 file changed, 14 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index e80319aa7cf0..2c484b55bcdf 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -815,8 +815,7 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries)
}
static const struct ddi_buf_trans *
-intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder,
- enum port port, int *n_entries)
+intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -825,12 +824,12 @@ intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder,
IS_COMETLAKE(dev_priv)) {
const struct ddi_buf_trans *ddi_translations =
kbl_get_buf_trans_dp(encoder, n_entries);
- *n_entries = skl_buf_trans_num_entries(port, *n_entries);
+ *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
return ddi_translations;
} else if (IS_SKYLAKE(dev_priv)) {
const struct ddi_buf_trans *ddi_translations =
skl_get_buf_trans_dp(encoder, n_entries);
- *n_entries = skl_buf_trans_num_entries(port, *n_entries);
+ *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
return ddi_translations;
} else if (IS_BROADWELL(dev_priv)) {
*n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
@@ -845,15 +844,14 @@ intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder,
}
static const struct ddi_buf_trans *
-intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder,
- enum port port, int *n_entries)
+intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
if (IS_GEN9_BC(dev_priv)) {
const struct ddi_buf_trans *ddi_translations =
skl_get_buf_trans_edp(encoder, n_entries);
- *n_entries = skl_buf_trans_num_entries(port, *n_entries);
+ *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
return ddi_translations;
} else if (IS_BROADWELL(dev_priv)) {
return bdw_get_buf_trans_edp(encoder, n_entries);
@@ -1152,10 +1150,10 @@ static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
&n_entries);
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
- ddi_translations = intel_ddi_get_buf_trans_edp(encoder, port,
+ ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
&n_entries);
else
- ddi_translations = intel_ddi_get_buf_trans_dp(encoder, port,
+ ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
&n_entries);
/* If we're boosting the current, set bit 31 of trans1 */
@@ -2106,7 +2104,6 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder,
{
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum port port = encoder->port;
u8 iboost;
if (type == INTEL_OUTPUT_HDMI)
@@ -2122,11 +2119,9 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder,
ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
else if (type == INTEL_OUTPUT_EDP)
ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
- port,
&n_entries);
else
ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
- port,
&n_entries);
if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
@@ -2143,9 +2138,9 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder,
return;
}
- _skl_ddi_set_iboost(dev_priv, port, iboost);
+ _skl_ddi_set_iboost(dev_priv, encoder->port, iboost);
- if (port == PORT_A && dig_port->max_lanes == 4)
+ if (encoder->port == PORT_A && dig_port->max_lanes == 4)
_skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
}
@@ -2213,9 +2208,9 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
bxt_get_buf_trans_dp(encoder, &n_entries);
} else {
if (encoder->type == INTEL_OUTPUT_EDP)
- intel_ddi_get_buf_trans_edp(encoder, port, &n_entries);
+ intel_ddi_get_buf_trans_edp(encoder, &n_entries);
else
- intel_ddi_get_buf_trans_dp(encoder, port, &n_entries);
+ intel_ddi_get_buf_trans_dp(encoder, &n_entries);
}
if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
@@ -2370,10 +2365,10 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
}
static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
- u32 level, enum phy phy, int type,
- int rate)
+ u32 level, int type, int rate)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
const struct cnl_ddi_buf_trans *ddi_translations = NULL;
u32 n_entries, val;
int ln;
@@ -2497,7 +2492,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
/* 5. Program swing and de-emphasis */
- icl_ddi_combo_vswing_program(encoder, level, phy, type, rate);
+ icl_ddi_combo_vswing_program(encoder, level, type, rate);
/* 6. Set training enable to trigger update */
val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
--
2.27.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH v4 3/5] drm/i915/bios: Parse HOBL parameter
2020-07-08 20:55 [Intel-gfx] [PATCH v4 1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder José Roberto de Souza
2020-07-08 20:55 ` [Intel-gfx] [PATCH v4 2/5] drm/i915/display: Remove port and phy from voltage swing functions José Roberto de Souza
@ 2020-07-08 20:55 ` José Roberto de Souza
2020-07-08 20:55 ` [Intel-gfx] [PATCH v4 4/5] drm/i915/display: Implement HOBL José Roberto de Souza
` (8 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: José Roberto de Souza @ 2020-07-08 20:55 UTC (permalink / raw)
To: intel-gfx
HOBL means hours of battery life, it is a power-saving feature
were supported motherboards can use a special voltage swing table
that uses less power.
So here parsing the VBT to check if this feature is supported.
BSpec: 20150
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 3 +++
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
3 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 6593e2c38043..c53c85d38fa5 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -722,6 +722,9 @@ parse_power_conservation_features(struct drm_i915_private *dev_priv,
*/
if (!(power->drrs & BIT(panel_type)))
dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
+
+ if (bdb->version >= 232)
+ dev_priv->vbt.edp.hobl = power->hobl & BIT(panel_type);
}
static void
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index aef7fe932d1a..6faabd4f6d49 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -820,6 +820,7 @@ struct bdb_lfp_power {
u16 adb;
u16 lace_enabled_status;
struct agressiveness_profile_entry aggressivenes[16];
+ u16 hobl; /* 232+ */
} __packed;
/*
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2c2e88d49f3e..5b100c2df8df 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -692,6 +692,7 @@ struct intel_vbt_data {
bool initialized;
int bpp;
struct edp_power_seq pps;
+ bool hobl;
} edp;
struct {
--
2.27.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH v4 4/5] drm/i915/display: Implement HOBL
2020-07-08 20:55 [Intel-gfx] [PATCH v4 1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder José Roberto de Souza
2020-07-08 20:55 ` [Intel-gfx] [PATCH v4 2/5] drm/i915/display: Remove port and phy from voltage swing functions José Roberto de Souza
2020-07-08 20:55 ` [Intel-gfx] [PATCH v4 3/5] drm/i915/bios: Parse HOBL parameter José Roberto de Souza
@ 2020-07-08 20:55 ` José Roberto de Souza
2020-07-09 14:24 ` Ville Syrjälä
2020-07-08 20:55 ` [Intel-gfx] [PATCH v4 5/5] DO_NOT_MERGE_IT: drm/i915/display: Enable HOBL by default José Roberto de Souza
` (7 subsequent siblings)
10 siblings, 1 reply; 17+ messages in thread
From: José Roberto de Souza @ 2020-07-08 20:55 UTC (permalink / raw)
To: intel-gfx
Hours Of Battery Life is a new GEN12+ power-saving feature that allows
supported motherboards to use a special voltage swing table for eDP
panels that uses less power.
So here if supported by HW, OEM will set it in VBT and i915 will try
to train link with HOBL vswing table if link training fails it fall
back to the original table.
intel_ddi_dp_preemph_max() was optimized to only check the HOBL flag
instead of do something like is done in intel_ddi_dp_voltage_max()
because it is only called after the first entry of the voltage swing
table was loaded so the HOBL flag is valid at that point.
v3:
- removed a few parameters of icl_ddi_combo_vswing_program() that
can be taken from encoder(TODO)
v4:
- using the HOBL vswing table until training fails completely (Ville)
BSpec: 49291
BSpec: 49399
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 37 ++++++++++++++++---
.../drm/i915/display/intel_display_types.h | 2 +
.../drm/i915/display/intel_dp_link_training.c | 5 +++
drivers/gpu/drm/i915/i915_reg.h | 2 +
4 files changed, 41 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 2c484b55bcdf..bf86c588f726 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -706,6 +706,15 @@ static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] =
{ 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
};
+static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = {
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }
+};
+
+static bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table)
+{
+ return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
+}
+
static const struct ddi_buf_trans *
bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
{
@@ -1050,6 +1059,16 @@ static const struct cnl_ddi_buf_trans *
tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
int *n_entries)
{
+ if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.hobl) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ if (!intel_dp->hobl_disabled && rate <= 540000) {
+ /* Same table applies to TGL, RKL and DG1 */
+ *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
+ return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
+ }
+ }
+
if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) {
return icl_get_combo_buf_trans(encoder, type, rate, n_entries);
} else if (rate > 270000) {
@@ -2223,13 +2242,12 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
DP_TRAIN_VOLTAGE_SWING_MASK;
}
-/*
- * We assume that the full set of pre-emphasis values can be
- * used on all DDI platforms. Should that change we need to
- * rethink this code.
- */
static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
{
+ /* HOBL voltage swing table only have one entry */
+ if (intel_dp->hobl_active)
+ return DP_TRAIN_PRE_EMPH_LEVEL_0;
+
return DP_TRAIN_PRE_EMPH_LEVEL_3;
}
@@ -2392,6 +2410,15 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
level = n_entries - 1;
}
+ if (INTEL_GEN(dev_priv) >= 12 && type == INTEL_OUTPUT_EDP) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
+ intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations);
+ intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,
+ intel_dp->hobl_active ? val : 0);
+ }
+
/* Set PORT_TX_DW5 */
val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e8f809161c75..fd4f0e4d0be7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1375,6 +1375,8 @@ struct intel_dp {
/* Display stream compression testing */
bool force_dsc_en;
+
+ u8 hobl_disabled : 1, hobl_active : 1, hobl_not_used : 6;
};
enum lspcon_vendor {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 2493142a70e9..925822fd386d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -401,6 +401,11 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
intel_connector->base.base.id,
intel_connector->base.name,
intel_dp->link_rate, intel_dp->lane_count);
+ if (intel_dp->hobl_active) {
+ drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
+ "Link Training failed with HOBL active, not enabling it for now on");
+ intel_dp->hobl_disabled = true;
+ }
if (!intel_dp_get_link_train_fallback_values(intel_dp,
intel_dp->link_rate,
intel_dp->lane_count))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 86a23ced051b..ea16931c0fa4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1898,6 +1898,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define PWR_DOWN_LN_3_1_0 (0xb << 4)
#define PWR_DOWN_LN_MASK (0xf << 4)
#define PWR_DOWN_LN_SHIFT 4
+#define EDP4K2K_MODE_OVRD_EN (1 << 3)
+#define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2)
#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
#define ICL_LANE_ENABLE_AUX (1 << 0)
--
2.27.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH v4 5/5] DO_NOT_MERGE_IT: drm/i915/display: Enable HOBL by default
2020-07-08 20:55 [Intel-gfx] [PATCH v4 1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder José Roberto de Souza
` (2 preceding siblings ...)
2020-07-08 20:55 ` [Intel-gfx] [PATCH v4 4/5] drm/i915/display: Implement HOBL José Roberto de Souza
@ 2020-07-08 20:55 ` José Roberto de Souza
2020-07-08 22:04 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder Patchwork
` (6 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: José Roberto de Souza @ 2020-07-08 20:55 UTC (permalink / raw)
To: intel-gfx
Enabling by default to have some testing in CI but the desired behavior
is only enable it when HW/VBT says it is supported.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index bf86c588f726..1f82c538435a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1059,7 +1059,7 @@ static const struct cnl_ddi_buf_trans *
tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
int *n_entries)
{
- if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.hobl) {
+ if (type == INTEL_OUTPUT_EDP) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
if (!intel_dp->hobl_disabled && rate <= 540000) {
--
2.27.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder
2020-07-08 20:55 [Intel-gfx] [PATCH v4 1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder José Roberto de Souza
` (3 preceding siblings ...)
2020-07-08 20:55 ` [Intel-gfx] [PATCH v4 5/5] DO_NOT_MERGE_IT: drm/i915/display: Enable HOBL by default José Roberto de Souza
@ 2020-07-08 22:04 ` Patchwork
2020-07-08 22:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (5 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2020-07-08 22:04 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder
URL : https://patchwork.freedesktop.org/series/79265/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1223:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1226:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1229:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1232:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2271:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2272:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2273:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion
+drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion
+drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder
2020-07-08 20:55 [Intel-gfx] [PATCH v4 1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder José Roberto de Souza
` (4 preceding siblings ...)
2020-07-08 22:04 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder Patchwork
@ 2020-07-08 22:23 ` Patchwork
2020-07-09 2:53 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (4 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2020-07-08 22:23 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder
URL : https://patchwork.freedesktop.org/series/79265/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8717 -> Patchwork_18115
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/index.html
Known issues
------------
Here are the changes found in Patchwork_18115 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
* igt@gem_flink_basic@flink-lifetime:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/fi-tgl-y/igt@gem_flink_basic@flink-lifetime.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/fi-tgl-y/igt@gem_flink_basic@flink-lifetime.html
* igt@i915_module_load@reload:
- fi-tgl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#402])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/fi-tgl-u2/igt@i915_module_load@reload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/fi-tgl-u2/igt@i915_module_load@reload.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
#### Possible fixes ####
* igt@kms_busy@basic@flip:
- fi-tgl-y: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/fi-tgl-y/igt@kms_busy@basic@flip.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/fi-tgl-y/igt@kms_busy@basic@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- {fi-kbl-7560u}: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1:
- fi-icl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-tgl-u2: [DMESG-WARN][15] ([i915#402]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/fi-tgl-u2/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/fi-tgl-u2/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
* igt@vgem_basic@dmabuf-fence-before:
- fi-tgl-y: [DMESG-WARN][17] ([i915#402]) -> [PASS][18] +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/fi-tgl-y/igt@vgem_basic@dmabuf-fence-before.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/fi-tgl-y/igt@vgem_basic@dmabuf-fence-before.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#1982] / [i915#62] / [i915#92] / [i915#95])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +3 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/fi-kbl-x1275/igt@prime_vgem@basic-fence-flip.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/fi-kbl-x1275/igt@prime_vgem@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (44 -> 37)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_8717 -> Patchwork_18115
CI-20190529: 20190529
CI_DRM_8717: 6e5ac4c72af4e86138f04cc2dd089b069bad873f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5728: 6988eebf78e9ce9746b8c2b7d21cb4174d6623a9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18115: 79e12a5e0e106e784d61a3d6f6d20231dfbce95a @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
79e12a5e0e10 DO_NOT_MERGE_IT: drm/i915/display: Enable HOBL by default
d0987aebbcac drm/i915/display: Implement HOBL
afe4b37a6b77 drm/i915/bios: Parse HOBL parameter
e1c95381ccca drm/i915/display: Remove port and phy from voltage swing functions
1509338debe5 drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder
2020-07-08 20:55 [Intel-gfx] [PATCH v4 1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder José Roberto de Souza
` (5 preceding siblings ...)
2020-07-08 22:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-07-09 2:53 ` Patchwork
2020-07-09 14:10 ` [Intel-gfx] [PATCH v4 1/5] " Ville Syrjälä
` (3 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2020-07-09 2:53 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder
URL : https://patchwork.freedesktop.org/series/79265/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8717_full -> Patchwork_18115_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18115_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18115_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18115_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-tglb5/igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-tglb8/igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing.html
Known issues
------------
Here are the changes found in Patchwork_18115_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@fences-dpms:
- shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-apl2/igt@i915_pm_rpm@fences-dpms.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-apl6/igt@i915_pm_rpm@fences-dpms.html
* igt@kms_big_fb@linear-16bpp-rotate-0:
- shard-kbl: [PASS][5] -> [DMESG-FAIL][6] ([i915#95])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-kbl1/igt@kms_big_fb@linear-16bpp-rotate-0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-kbl4/igt@kms_big_fb@linear-16bpp-rotate-0.html
- shard-apl: [PASS][7] -> [DMESG-FAIL][8] ([i915#1635] / [i915#95])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-apl7/igt@kms_big_fb@linear-16bpp-rotate-0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-apl4/igt@kms_big_fb@linear-16bpp-rotate-0.html
* igt@kms_big_fb@linear-64bpp-rotate-0:
- shard-glk: [PASS][9] -> [DMESG-FAIL][10] ([i915#118] / [i915#95])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-glk3/igt@kms_big_fb@linear-64bpp-rotate-0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-glk8/igt@kms_big_fb@linear-64bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-b-cursor-128x128-rapid-movement:
- shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#93] / [i915#95]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-kbl6/igt@kms_cursor_crc@pipe-b-cursor-128x128-rapid-movement.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-kbl7/igt@kms_cursor_crc@pipe-b-cursor-128x128-rapid-movement.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [PASS][13] -> [FAIL][14] ([IGT#5])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic:
- shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#1635] / [i915#95]) +13 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-apl3/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-apl7/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_cursor_legacy@pipe-a-forked-move:
- shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#118] / [i915#95]) +2 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-glk3/igt@kms_cursor_legacy@pipe-a-forked-move.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-glk8/igt@kms_cursor_legacy@pipe-a-forked-move.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +6 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-skl9/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +5 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu:
- shard-tglb: [PASS][23] -> [DMESG-WARN][24] ([i915#1982])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-tglb8/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-tglb8/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html
* igt@kms_plane_scaling@pipe-c-scaler-with-clipping-clamping:
- shard-iclb: [PASS][25] -> [DMESG-WARN][26] ([i915#1982])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-iclb4/igt@kms_plane_scaling@pipe-c-scaler-with-clipping-clamping.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-iclb3/igt@kms_plane_scaling@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109642] / [fdo#111068])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-iclb2/igt@kms_psr2_su@page_flip.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-iclb5/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-iclb2/igt@kms_psr@psr2_suspend.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-iclb5/igt@kms_psr@psr2_suspend.html
* igt@perf@polling-parameterized:
- shard-iclb: [PASS][31] -> [FAIL][32] ([i915#1542])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-iclb6/igt@perf@polling-parameterized.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-iclb7/igt@perf@polling-parameterized.html
* igt@perf_pmu@module-unload:
- shard-tglb: [PASS][33] -> [DMESG-WARN][34] ([i915#402])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-tglb2/igt@perf_pmu@module-unload.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-tglb3/igt@perf_pmu@module-unload.html
* igt@perf_pmu@semaphore-busy@rcs0:
- shard-kbl: [PASS][35] -> [FAIL][36] ([i915#1820])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-kbl4/igt@perf_pmu@semaphore-busy@rcs0.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-kbl1/igt@perf_pmu@semaphore-busy@rcs0.html
#### Possible fixes ####
* igt@gem_exec_whisper@basic-normal:
- shard-glk: [DMESG-WARN][37] ([i915#118] / [i915#95]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-glk9/igt@gem_exec_whisper@basic-normal.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-glk8/igt@gem_exec_whisper@basic-normal.html
* igt@gem_mmap_gtt@big-bo:
- shard-skl: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40] +5 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-skl8/igt@gem_mmap_gtt@big-bo.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-skl4/igt@gem_mmap_gtt@big-bo.html
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [DMESG-WARN][41] ([i915#1436] / [i915#716]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-apl6/igt@gen9_exec_parse@allowed-all.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-apl4/igt@gen9_exec_parse@allowed-all.html
* igt@i915_module_load@reload:
- shard-apl: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-apl1/igt@i915_module_load@reload.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-apl4/igt@i915_module_load@reload.html
* igt@i915_selftest@mock@requests:
- shard-skl: [INCOMPLETE][45] ([i915#198] / [i915#2110]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-skl5/igt@i915_selftest@mock@requests.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-skl9/igt@i915_selftest@mock@requests.html
* igt@kms_addfb_basic@unused-pitches:
- shard-apl: [DMESG-WARN][47] ([i915#1635] / [i915#95]) -> [PASS][48] +15 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-apl4/igt@kms_addfb_basic@unused-pitches.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-apl8/igt@kms_addfb_basic@unused-pitches.html
* igt@kms_big_fb@linear-64bpp-rotate-180:
- shard-glk: [DMESG-FAIL][49] ([i915#118] / [i915#95]) -> [PASS][50] +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-glk8/igt@kms_big_fb@linear-64bpp-rotate-180.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-glk9/igt@kms_big_fb@linear-64bpp-rotate-180.html
* igt@kms_color@pipe-b-legacy-gamma:
- shard-skl: [FAIL][51] ([i915#71]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-skl4/igt@kms_color@pipe-b-legacy-gamma.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-skl9/igt@kms_color@pipe-b-legacy-gamma.html
* igt@kms_cursor_crc@pipe-a-cursor-256x256-sliding:
- shard-snb: [TIMEOUT][53] ([i915#1958] / [i915#2119]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-snb6/igt@kms_cursor_crc@pipe-a-cursor-256x256-sliding.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-snb4/igt@kms_cursor_crc@pipe-a-cursor-256x256-sliding.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][55] ([i915#180]) -> [PASS][56] +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-tglb: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-tglb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-tglb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [FAIL][59] ([fdo#108145] / [i915#265]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62] +2 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-iclb4/igt@kms_psr@psr2_primary_page_flip.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_pwrite_crc:
- shard-skl: [FAIL][63] ([i915#150]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-skl2/igt@kms_pwrite_crc.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-skl1/igt@kms_pwrite_crc.html
#### Warnings ####
* igt@gem_exec_reloc@basic-concurrent16:
- shard-snb: [TIMEOUT][65] ([i915#1958] / [i915#2119]) -> [FAIL][66] ([i915#1930])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-snb6/igt@gem_exec_reloc@basic-concurrent16.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-snb4/igt@gem_exec_reloc@basic-concurrent16.html
* igt@gem_vm_create@execbuf:
- shard-snb: [TIMEOUT][67] ([i915#1958] / [i915#2119]) -> [SKIP][68] ([fdo#109271]) +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-snb6/igt@gem_vm_create@execbuf.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-snb4/igt@gem_vm_create@execbuf.html
* igt@kms_chamelium@dp-crc-fast:
- shard-apl: [SKIP][69] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][70] ([fdo#109271] / [fdo#111827])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-apl4/igt@kms_chamelium@dp-crc-fast.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-apl8/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
- shard-apl: [SKIP][71] ([fdo#109271]) -> [SKIP][72] ([fdo#109271] / [i915#1635]) +9 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-apl2/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-apl6/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
* igt@kms_plane_alpha_blend@pipe-d-coverage-vs-premult-vs-constant:
- shard-apl: [SKIP][73] ([fdo#109271] / [i915#1635]) -> [SKIP][74] ([fdo#109271]) +2 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-apl7/igt@kms_plane_alpha_blend@pipe-d-coverage-vs-premult-vs-constant.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-apl2/igt@kms_plane_alpha_blend@pipe-d-coverage-vs-premult-vs-constant.html
* igt@runner@aborted:
- shard-apl: ([FAIL][75], [FAIL][76], [FAIL][77]) ([fdo#109271] / [i915#1610] / [i915#1635] / [i915#2110] / [i915#716]) -> [FAIL][78] ([i915#1635] / [i915#2110])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-apl6/igt@runner@aborted.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-apl2/igt@runner@aborted.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8717/shard-apl6/igt@runner@aborted.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/shard-apl6/igt@runner@aborted.html
[IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#150]: https://gitlab.freedesktop.org/drm/intel/issues/150
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820
[i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930
[i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2110]: https://gitlab.freedesktop.org/drm/intel/issues/2110
[i915#2119]: https://gitlab.freedesktop.org/drm/intel/issues/2119
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#71]: https://gitlab.freedesktop.org/drm/intel/issues/71
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_8717 -> Patchwork_18115
CI-20190529: 20190529
CI_DRM_8717: 6e5ac4c72af4e86138f04cc2dd089b069bad873f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5728: 6988eebf78e9ce9746b8c2b7d21cb4174d6623a9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18115: 79e12a5e0e106e784d61a3d6f6d20231dfbce95a @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18115/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v4 1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder
2020-07-08 20:55 [Intel-gfx] [PATCH v4 1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder José Roberto de Souza
` (6 preceding siblings ...)
2020-07-09 2:53 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-07-09 14:10 ` Ville Syrjälä
2020-07-09 16:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder (rev2) Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjälä @ 2020-07-09 14:10 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Wed, Jul 08, 2020 at 01:55:08PM -0700, José Roberto de Souza wrote:
> intel_encoder will be needed inside of vswing functions in a future
> patch, so here doing this change in all vswing functions since HSW.
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 164 +++++++++++++----------
> 1 file changed, 95 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 5773ebefffc7..e80319aa7cf0 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -707,8 +707,10 @@ static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] =
> };
>
> static const struct ddi_buf_trans *
> -bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
> +bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> if (dev_priv->vbt.edp.low_vswing) {
> *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
> return bdw_ddi_translations_edp;
> @@ -719,8 +721,10 @@ bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
> }
>
> static const struct ddi_buf_trans *
> -skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
> +skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> if (IS_SKL_ULX(dev_priv)) {
> *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
> return skl_y_ddi_translations_dp;
> @@ -734,8 +738,10 @@ skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
> }
>
> static const struct ddi_buf_trans *
> -kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
> +kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> if (IS_KBL_ULX(dev_priv) ||
> IS_CFL_ULX(dev_priv) ||
> IS_CML_ULX(dev_priv)) {
> @@ -753,8 +759,10 @@ kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
> }
>
> static const struct ddi_buf_trans *
> -skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
> +skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> if (dev_priv->vbt.edp.low_vswing) {
> if (IS_SKL_ULX(dev_priv) ||
> IS_KBL_ULX(dev_priv) ||
> @@ -777,9 +785,9 @@ skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
> if (IS_KABYLAKE(dev_priv) ||
> IS_COFFEELAKE(dev_priv) ||
> IS_COMETLAKE(dev_priv))
> - return kbl_get_buf_trans_dp(dev_priv, n_entries);
> + return kbl_get_buf_trans_dp(encoder, n_entries);
> else
> - return skl_get_buf_trans_dp(dev_priv, n_entries);
> + return skl_get_buf_trans_dp(encoder, n_entries);
> }
>
> static const struct ddi_buf_trans *
> @@ -807,19 +815,21 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries)
> }
>
> static const struct ddi_buf_trans *
> -intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
> +intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder,
> enum port port, int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> if (IS_KABYLAKE(dev_priv) ||
> IS_COFFEELAKE(dev_priv) ||
> IS_COMETLAKE(dev_priv)) {
> const struct ddi_buf_trans *ddi_translations =
> - kbl_get_buf_trans_dp(dev_priv, n_entries);
> + kbl_get_buf_trans_dp(encoder, n_entries);
> *n_entries = skl_buf_trans_num_entries(port, *n_entries);
> return ddi_translations;
> } else if (IS_SKYLAKE(dev_priv)) {
> const struct ddi_buf_trans *ddi_translations =
> - skl_get_buf_trans_dp(dev_priv, n_entries);
> + skl_get_buf_trans_dp(encoder, n_entries);
> *n_entries = skl_buf_trans_num_entries(port, *n_entries);
> return ddi_translations;
> } else if (IS_BROADWELL(dev_priv)) {
> @@ -835,16 +845,18 @@ intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
> }
>
> static const struct ddi_buf_trans *
> -intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
> +intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder,
> enum port port, int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> if (IS_GEN9_BC(dev_priv)) {
> const struct ddi_buf_trans *ddi_translations =
> - skl_get_buf_trans_edp(dev_priv, n_entries);
> + skl_get_buf_trans_edp(encoder, n_entries);
> *n_entries = skl_buf_trans_num_entries(port, *n_entries);
> return ddi_translations;
> } else if (IS_BROADWELL(dev_priv)) {
> - return bdw_get_buf_trans_edp(dev_priv, n_entries);
> + return bdw_get_buf_trans_edp(encoder, n_entries);
> } else if (IS_HASWELL(dev_priv)) {
> *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
> return hsw_ddi_translations_dp;
> @@ -871,9 +883,11 @@ intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
> }
>
> static const struct ddi_buf_trans *
> -intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
> +intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder,
> int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> if (IS_GEN9_BC(dev_priv)) {
> return skl_get_buf_trans_hdmi(dev_priv, n_entries);
> } else if (IS_BROADWELL(dev_priv)) {
> @@ -889,33 +903,36 @@ intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
> }
>
> static const struct bxt_ddi_buf_trans *
> -bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
> +bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
> {
> *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
> return bxt_ddi_translations_dp;
> }
>
> static const struct bxt_ddi_buf_trans *
> -bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
> +bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> if (dev_priv->vbt.edp.low_vswing) {
> *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
> return bxt_ddi_translations_edp;
> }
>
> - return bxt_get_buf_trans_dp(dev_priv, n_entries);
> + return bxt_get_buf_trans_dp(encoder, n_entries);
> }
>
> static const struct bxt_ddi_buf_trans *
> -bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
> +bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries)
> {
> *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
> return bxt_ddi_translations_hdmi;
> }
>
> static const struct cnl_ddi_buf_trans *
> -cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
> +cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
>
> if (voltage == VOLTAGE_INFO_0_85V) {
> @@ -935,8 +952,9 @@ cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
> }
>
> static const struct cnl_ddi_buf_trans *
> -cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
> +cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
>
> if (voltage == VOLTAGE_INFO_0_85V) {
> @@ -956,8 +974,9 @@ cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
> }
>
> static const struct cnl_ddi_buf_trans *
> -cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
> +cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
>
> if (dev_priv->vbt.edp.low_vswing) {
> @@ -976,14 +995,16 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
> }
> return NULL;
> } else {
> - return cnl_get_buf_trans_dp(dev_priv, n_entries);
> + return cnl_get_buf_trans_dp(encoder, n_entries);
> }
> }
>
> static const struct cnl_ddi_buf_trans *
> -icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> +icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> if (type == INTEL_OUTPUT_HDMI) {
> *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> return icl_combo_phy_ddi_translations_hdmi;
> @@ -1000,7 +1021,7 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> }
>
> static const struct icl_mg_phy_ddi_buf_trans *
> -icl_get_mg_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> +icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
> int *n_entries)
> {
> if (type == INTEL_OUTPUT_HDMI) {
> @@ -1016,7 +1037,7 @@ icl_get_mg_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> }
>
> static const struct cnl_ddi_buf_trans *
> -ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> +ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> int *n_entries)
> {
> if (type != INTEL_OUTPUT_HDMI && type != INTEL_OUTPUT_EDP) {
> @@ -1024,15 +1045,15 @@ ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> return ehl_combo_phy_ddi_translations_dp;
> }
>
> - return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries);
> + return icl_get_combo_buf_trans(encoder, type, rate, n_entries);
> }
>
> static const struct cnl_ddi_buf_trans *
> -tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> +tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> int *n_entries)
> {
> if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) {
> - return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries);
> + return icl_get_combo_buf_trans(encoder, type, rate, n_entries);
> } else if (rate > 270000) {
> *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
> return tgl_combo_phy_ddi_translations_dp_hbr2;
> @@ -1043,7 +1064,7 @@ tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> }
>
> static const struct tgl_dkl_phy_ddi_buf_trans *
> -tgl_get_dkl_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> +tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int type, int rate,
> int *n_entries)
> {
> if (type == INTEL_OUTPUT_HDMI) {
> @@ -1066,34 +1087,34 @@ static int intel_ddi_hdmi_level(struct intel_encoder *encoder)
>
> if (INTEL_GEN(dev_priv) >= 12) {
> if (intel_phy_is_combo(dev_priv, phy))
> - tgl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
> + tgl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
> 0, &n_entries);
> else
> - tgl_get_dkl_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0,
> + tgl_get_dkl_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
> &n_entries);
> default_entry = n_entries - 1;
> } else if (INTEL_GEN(dev_priv) == 11) {
> if (intel_phy_is_combo(dev_priv, phy))
> - icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
> + icl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
> 0, &n_entries);
> else
> - icl_get_mg_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0,
> + icl_get_mg_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
> &n_entries);
> default_entry = n_entries - 1;
> } else if (IS_CANNONLAKE(dev_priv)) {
> - cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
> + cnl_get_buf_trans_hdmi(encoder, &n_entries);
> default_entry = n_entries - 1;
> } else if (IS_GEN9_LP(dev_priv)) {
> - bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
> + bxt_get_buf_trans_hdmi(encoder, &n_entries);
> default_entry = n_entries - 1;
> } else if (IS_GEN9_BC(dev_priv)) {
> - intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
> + intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
> default_entry = 8;
> } else if (IS_BROADWELL(dev_priv)) {
> - intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
> + intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
> default_entry = 7;
> } else if (IS_HASWELL(dev_priv)) {
> - intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
> + intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
> default_entry = 6;
> } else {
> drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n");
> @@ -1131,10 +1152,10 @@ static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
> ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
> &n_entries);
> else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> - ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
> + ddi_translations = intel_ddi_get_buf_trans_edp(encoder, port,
> &n_entries);
> else
> - ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
> + ddi_translations = intel_ddi_get_buf_trans_dp(encoder, port,
> &n_entries);
>
> /* If we're boosting the current, set bit 31 of trans1 */
> @@ -1163,7 +1184,7 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
> enum port port = encoder->port;
> const struct ddi_buf_trans *ddi_translations;
>
> - ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
> + ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
>
> if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
> return;
> @@ -2098,11 +2119,15 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder,
> int n_entries;
>
> if (type == INTEL_OUTPUT_HDMI)
> - ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
> + ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
> else if (type == INTEL_OUTPUT_EDP)
> - ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
> + ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
> + port,
> + &n_entries);
> else
> - ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
> + ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
> + port,
> + &n_entries);
>
> if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
> return;
> @@ -2133,11 +2158,11 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
> int n_entries;
>
> if (type == INTEL_OUTPUT_HDMI)
> - ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
> + ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries);
> else if (type == INTEL_OUTPUT_EDP)
> - ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
> + ddi_translations = bxt_get_buf_trans_edp(encoder, &n_entries);
> else
> - ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
> + ddi_translations = bxt_get_buf_trans_dp(encoder, &n_entries);
>
> if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
> return;
> @@ -2161,36 +2186,36 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
>
> if (INTEL_GEN(dev_priv) >= 12) {
> if (intel_phy_is_combo(dev_priv, phy))
> - tgl_get_combo_buf_trans(dev_priv, encoder->type,
> + tgl_get_combo_buf_trans(encoder, encoder->type,
> intel_dp->link_rate, &n_entries);
> else
> - tgl_get_dkl_buf_trans(dev_priv, encoder->type,
> + tgl_get_dkl_buf_trans(encoder, encoder->type,
> intel_dp->link_rate, &n_entries);
> } else if (INTEL_GEN(dev_priv) == 11) {
> if (IS_ELKHARTLAKE(dev_priv))
> - ehl_get_combo_buf_trans(dev_priv, encoder->type,
> + ehl_get_combo_buf_trans(encoder, encoder->type,
> intel_dp->link_rate, &n_entries);
> else if (intel_phy_is_combo(dev_priv, phy))
> - icl_get_combo_buf_trans(dev_priv, encoder->type,
> + icl_get_combo_buf_trans(encoder, encoder->type,
> intel_dp->link_rate, &n_entries);
> else
> - icl_get_mg_buf_trans(dev_priv, encoder->type,
> + icl_get_mg_buf_trans(encoder, encoder->type,
> intel_dp->link_rate, &n_entries);
> } else if (IS_CANNONLAKE(dev_priv)) {
> if (encoder->type == INTEL_OUTPUT_EDP)
> - cnl_get_buf_trans_edp(dev_priv, &n_entries);
> + cnl_get_buf_trans_edp(encoder, &n_entries);
> else
> - cnl_get_buf_trans_dp(dev_priv, &n_entries);
> + cnl_get_buf_trans_dp(encoder, &n_entries);
> } else if (IS_GEN9_LP(dev_priv)) {
> if (encoder->type == INTEL_OUTPUT_EDP)
> - bxt_get_buf_trans_edp(dev_priv, &n_entries);
> + bxt_get_buf_trans_edp(encoder, &n_entries);
> else
> - bxt_get_buf_trans_dp(dev_priv, &n_entries);
> + bxt_get_buf_trans_dp(encoder, &n_entries);
> } else {
> if (encoder->type == INTEL_OUTPUT_EDP)
> - intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
> + intel_ddi_get_buf_trans_edp(encoder, port, &n_entries);
> else
> - intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
> + intel_ddi_get_buf_trans_dp(encoder, port, &n_entries);
> }
>
> if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
> @@ -2223,11 +2248,11 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
> u32 val;
>
> if (type == INTEL_OUTPUT_HDMI)
> - ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
> + ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries);
> else if (type == INTEL_OUTPUT_EDP)
> - ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
> + ddi_translations = cnl_get_buf_trans_edp(encoder, &n_entries);
> else
> - ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
> + ddi_translations = cnl_get_buf_trans_dp(encoder, &n_entries);
>
> if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
> return;
> @@ -2344,22 +2369,23 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
> intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
> }
>
> -static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> - u32 level, enum phy phy, int type,
> - int rate)
> +static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
> + u32 level, enum phy phy, int type,
> + int rate)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> const struct cnl_ddi_buf_trans *ddi_translations = NULL;
> u32 n_entries, val;
> int ln;
>
> if (INTEL_GEN(dev_priv) >= 12)
> - ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate,
> + ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate,
> &n_entries);
> else if (IS_ELKHARTLAKE(dev_priv))
> - ddi_translations = ehl_get_combo_buf_trans(dev_priv, type, rate,
> + ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate,
> &n_entries);
> else
> - ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
> + ddi_translations = icl_get_combo_buf_trans(encoder, type, rate,
> &n_entries);
> if (!ddi_translations)
> return;
> @@ -2471,7 +2497,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
>
> /* 5. Program swing and de-emphasis */
> - icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
> + icl_ddi_combo_vswing_program(encoder, level, phy, type, rate);
>
> /* 6. Set training enable to trigger update */
> val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> @@ -2495,7 +2521,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> rate = intel_dp->link_rate;
> }
>
> - ddi_translations = icl_get_mg_buf_trans(dev_priv, type, rate,
> + ddi_translations = icl_get_mg_buf_trans(encoder, type, rate,
> &n_entries);
> /* The table does not have values for level 3 and level 9. */
> if (level >= n_entries || level == 3 || level == 9) {
> @@ -2640,7 +2666,7 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
> rate = intel_dp->link_rate;
> }
>
> - ddi_translations = tgl_get_dkl_buf_trans(dev_priv, encoder->type, rate,
> + ddi_translations = tgl_get_dkl_buf_trans(encoder, encoder->type, rate,
> &n_entries);
>
> if (level >= n_entries)
> --
> 2.27.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v4 2/5] drm/i915/display: Remove port and phy from voltage swing functions
2020-07-08 20:55 ` [Intel-gfx] [PATCH v4 2/5] drm/i915/display: Remove port and phy from voltage swing functions José Roberto de Souza
@ 2020-07-09 14:12 ` Ville Syrjälä
0 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjälä @ 2020-07-09 14:12 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Wed, Jul 08, 2020 at 01:55:09PM -0700, José Roberto de Souza wrote:
> This information can be get directly from intel_encoder so no need
> of those parameters.
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 33 ++++++++++--------------
> 1 file changed, 14 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index e80319aa7cf0..2c484b55bcdf 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -815,8 +815,7 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries)
> }
>
> static const struct ddi_buf_trans *
> -intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder,
> - enum port port, int *n_entries)
> +intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> @@ -825,12 +824,12 @@ intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder,
> IS_COMETLAKE(dev_priv)) {
> const struct ddi_buf_trans *ddi_translations =
> kbl_get_buf_trans_dp(encoder, n_entries);
> - *n_entries = skl_buf_trans_num_entries(port, *n_entries);
> + *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
> return ddi_translations;
> } else if (IS_SKYLAKE(dev_priv)) {
> const struct ddi_buf_trans *ddi_translations =
> skl_get_buf_trans_dp(encoder, n_entries);
> - *n_entries = skl_buf_trans_num_entries(port, *n_entries);
> + *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
> return ddi_translations;
> } else if (IS_BROADWELL(dev_priv)) {
> *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
> @@ -845,15 +844,14 @@ intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder,
> }
>
> static const struct ddi_buf_trans *
> -intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder,
> - enum port port, int *n_entries)
> +intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> if (IS_GEN9_BC(dev_priv)) {
> const struct ddi_buf_trans *ddi_translations =
> skl_get_buf_trans_edp(encoder, n_entries);
> - *n_entries = skl_buf_trans_num_entries(port, *n_entries);
> + *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
> return ddi_translations;
> } else if (IS_BROADWELL(dev_priv)) {
> return bdw_get_buf_trans_edp(encoder, n_entries);
> @@ -1152,10 +1150,10 @@ static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
> ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
> &n_entries);
> else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> - ddi_translations = intel_ddi_get_buf_trans_edp(encoder, port,
> + ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
> &n_entries);
> else
> - ddi_translations = intel_ddi_get_buf_trans_dp(encoder, port,
> + ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
> &n_entries);
>
> /* If we're boosting the current, set bit 31 of trans1 */
> @@ -2106,7 +2104,6 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder,
> {
> struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum port port = encoder->port;
> u8 iboost;
>
> if (type == INTEL_OUTPUT_HDMI)
> @@ -2122,11 +2119,9 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder,
> ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
> else if (type == INTEL_OUTPUT_EDP)
> ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
> - port,
> &n_entries);
> else
> ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
> - port,
> &n_entries);
>
> if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
> @@ -2143,9 +2138,9 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder,
> return;
> }
>
> - _skl_ddi_set_iboost(dev_priv, port, iboost);
> + _skl_ddi_set_iboost(dev_priv, encoder->port, iboost);
>
> - if (port == PORT_A && dig_port->max_lanes == 4)
> + if (encoder->port == PORT_A && dig_port->max_lanes == 4)
> _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
> }
>
> @@ -2213,9 +2208,9 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
> bxt_get_buf_trans_dp(encoder, &n_entries);
> } else {
> if (encoder->type == INTEL_OUTPUT_EDP)
> - intel_ddi_get_buf_trans_edp(encoder, port, &n_entries);
> + intel_ddi_get_buf_trans_edp(encoder, &n_entries);
> else
> - intel_ddi_get_buf_trans_dp(encoder, port, &n_entries);
> + intel_ddi_get_buf_trans_dp(encoder, &n_entries);
> }
>
> if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
> @@ -2370,10 +2365,10 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
> }
>
> static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
> - u32 level, enum phy phy, int type,
> - int rate)
> + u32 level, int type, int rate)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> const struct cnl_ddi_buf_trans *ddi_translations = NULL;
> u32 n_entries, val;
> int ln;
> @@ -2497,7 +2492,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
>
> /* 5. Program swing and de-emphasis */
> - icl_ddi_combo_vswing_program(encoder, level, phy, type, rate);
> + icl_ddi_combo_vswing_program(encoder, level, type, rate);
>
> /* 6. Set training enable to trigger update */
> val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> --
> 2.27.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v4 4/5] drm/i915/display: Implement HOBL
2020-07-08 20:55 ` [Intel-gfx] [PATCH v4 4/5] drm/i915/display: Implement HOBL José Roberto de Souza
@ 2020-07-09 14:24 ` Ville Syrjälä
2020-07-09 19:40 ` Souza, Jose
0 siblings, 1 reply; 17+ messages in thread
From: Ville Syrjälä @ 2020-07-09 14:24 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Wed, Jul 08, 2020 at 01:55:11PM -0700, José Roberto de Souza wrote:
> Hours Of Battery Life is a new GEN12+ power-saving feature that allows
> supported motherboards to use a special voltage swing table for eDP
> panels that uses less power.
>
> So here if supported by HW, OEM will set it in VBT and i915 will try
> to train link with HOBL vswing table if link training fails it fall
> back to the original table.
>
> intel_ddi_dp_preemph_max() was optimized to only check the HOBL flag
> instead of do something like is done in intel_ddi_dp_voltage_max()
> because it is only called after the first entry of the voltage swing
> table was loaded so the HOBL flag is valid at that point.
>
> v3:
> - removed a few parameters of icl_ddi_combo_vswing_program() that
> can be taken from encoder(TODO)
>
> v4:
> - using the HOBL vswing table until training fails completely (Ville)
>
> BSpec: 49291
> BSpec: 49399
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 37 ++++++++++++++++---
> .../drm/i915/display/intel_display_types.h | 2 +
> .../drm/i915/display/intel_dp_link_training.c | 5 +++
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> 4 files changed, 41 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 2c484b55bcdf..bf86c588f726 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -706,6 +706,15 @@ static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] =
> { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> };
>
> +static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = {
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }
> +};
> +
> +static bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table)
> +{
> + return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
> +}
> +
> static const struct ddi_buf_trans *
> bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
> {
> @@ -1050,6 +1059,16 @@ static const struct cnl_ddi_buf_trans *
> tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> int *n_entries)
> {
> + if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.hobl) {
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + if (!intel_dp->hobl_disabled && rate <= 540000) {
> + /* Same table applies to TGL, RKL and DG1 */
> + *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
> + return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
> + }
> + }
> +
> if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) {
> return icl_get_combo_buf_trans(encoder, type, rate, n_entries);
> } else if (rate > 270000) {
> @@ -2223,13 +2242,12 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
> DP_TRAIN_VOLTAGE_SWING_MASK;
> }
>
> -/*
> - * We assume that the full set of pre-emphasis values can be
> - * used on all DDI platforms. Should that change we need to
> - * rethink this code.
> - */
> static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
> {
> + /* HOBL voltage swing table only have one entry */
> + if (intel_dp->hobl_active)
> + return DP_TRAIN_PRE_EMPH_LEVEL_0;
That's illegal. We need to claim support for at least all
vswing/pre-emphasis levels 0-2. 3 is optional. Though there is
some confusion around this in the eDP spec where it kinda seems suggest
that even some of the level 2 things are optional. But it's so unclear
I would defer to just trusting what the DP spec says.
/me goes to write the patch with the WARNs...
> +
> return DP_TRAIN_PRE_EMPH_LEVEL_3;
> }
>
> @@ -2392,6 +2410,15 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
> level = n_entries - 1;
> }
>
> + if (INTEL_GEN(dev_priv) >= 12 && type == INTEL_OUTPUT_EDP) {
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
> + intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations);
> + intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,
> + intel_dp->hobl_active ? val : 0);
> + }
I'd still suggest writing that unconditionally.
> +
> /* Set PORT_TX_DW5 */
> val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e8f809161c75..fd4f0e4d0be7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1375,6 +1375,8 @@ struct intel_dp {
>
> /* Display stream compression testing */
> bool force_dsc_en;
> +
> + u8 hobl_disabled : 1, hobl_active : 1, hobl_not_used : 6;
Why did we go from a simple boolean to this complicated thing?
> };
>
> enum lspcon_vendor {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 2493142a70e9..925822fd386d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -401,6 +401,11 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> intel_connector->base.base.id,
> intel_connector->base.name,
> intel_dp->link_rate, intel_dp->lane_count);
> + if (intel_dp->hobl_active) {
> + drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
> + "Link Training failed with HOBL active, not enabling it for now on");
> + intel_dp->hobl_disabled = true;
I don't think we should do the link rate/lanes reduction in
this case. Ie. we should just mark hobl as no good and retry
the link training with the same link param limits.
> + }
> if (!intel_dp_get_link_train_fallback_values(intel_dp,
> intel_dp->link_rate,
> intel_dp->lane_count))
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 86a23ced051b..ea16931c0fa4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1898,6 +1898,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define PWR_DOWN_LN_3_1_0 (0xb << 4)
> #define PWR_DOWN_LN_MASK (0xf << 4)
> #define PWR_DOWN_LN_SHIFT 4
> +#define EDP4K2K_MODE_OVRD_EN (1 << 3)
> +#define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2)
>
> #define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
> #define ICL_LANE_ENABLE_AUX (1 << 0)
> --
> 2.27.0
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder (rev2)
2020-07-08 20:55 [Intel-gfx] [PATCH v4 1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder José Roberto de Souza
` (7 preceding siblings ...)
2020-07-09 14:10 ` [Intel-gfx] [PATCH v4 1/5] " Ville Syrjälä
@ 2020-07-09 16:34 ` Patchwork
2020-07-09 16:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-09 18:59 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
10 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2020-07-09 16:34 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder (rev2)
URL : https://patchwork.freedesktop.org/series/79265/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1223:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1226:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1229:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1232:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2271:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2272:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2273:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion
+drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion
+drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder (rev2)
2020-07-08 20:55 [Intel-gfx] [PATCH v4 1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder José Roberto de Souza
` (8 preceding siblings ...)
2020-07-09 16:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder (rev2) Patchwork
@ 2020-07-09 16:53 ` Patchwork
2020-07-09 18:59 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
10 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2020-07-09 16:53 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder (rev2)
URL : https://patchwork.freedesktop.org/series/79265/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8719 -> Patchwork_18124
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/index.html
Known issues
------------
Here are the changes found in Patchwork_18124 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_store@basic:
- fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/fi-tgl-y/igt@gem_exec_store@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/fi-tgl-y/igt@gem_exec_store@basic.html
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2: [PASS][3] -> [FAIL][4] ([i915#1888])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [PASS][7] -> [DMESG-WARN][8] ([i915#62] / [i915#92] / [i915#95])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/fi-kbl-x1275/igt@kms_busy@basic@flip.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/fi-kbl-x1275/igt@kms_busy@basic@flip.html
#### Possible fixes ####
* igt@i915_module_load@reload:
- fi-bxt-dsi: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/fi-bxt-dsi/igt@i915_module_load@reload.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/fi-bxt-dsi/igt@i915_module_load@reload.html
* igt@i915_pm_backlight@basic-brightness:
- fi-whl-u: [DMESG-WARN][11] ([i915#95]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/fi-whl-u/igt@i915_pm_backlight@basic-brightness.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/fi-whl-u/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_rpm@module-reload:
- fi-bsw-n3050: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/fi-bsw-n3050/igt@i915_pm_rpm@module-reload.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/fi-bsw-n3050/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@gem_contexts:
- fi-tgl-u2: [INCOMPLETE][15] ([i915#1932] / [i915#2045]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/fi-tgl-u2/igt@i915_selftest@live@gem_contexts.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/fi-tgl-u2/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@gt_pm:
- fi-apl-guc: [DMESG-FAIL][17] ([i915#1751]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/fi-apl-guc/igt@i915_selftest@live@gt_pm.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/fi-apl-guc/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- fi-bsw-n3050: [INCOMPLETE][19] ([i915#1506]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/fi-bsw-n3050/igt@i915_selftest@live@hangcheck.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/fi-bsw-n3050/igt@i915_selftest@live@hangcheck.html
* igt@kms_addfb_basic@addfb25-bad-modifier:
- fi-tgl-y: [DMESG-WARN][21] ([i915#402]) -> [PASS][22] +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/fi-tgl-y/igt@kms_addfb_basic@addfb25-bad-modifier.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/fi-tgl-y/igt@kms_addfb_basic@addfb25-bad-modifier.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- {fi-kbl-7560u}: [DMESG-WARN][23] ([i915#1982]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][25] ([i915#1982]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
#### Warnings ####
* igt@i915_module_load@reload:
- fi-icl-u2: [DMESG-WARN][27] ([i915#289]) -> [DMESG-WARN][28] ([i915#1982] / [i915#289])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/fi-icl-u2/igt@i915_module_load@reload.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/fi-icl-u2/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [SKIP][29] ([fdo#109271]) -> [DMESG-FAIL][30] ([i915#62])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
* igt@kms_flip@basic-flip-vs-modeset@a-dp1:
- fi-kbl-x1275: [DMESG-WARN][31] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][32] ([i915#62] / [i915#92])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset@a-dp1.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset@a-dp1.html
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-x1275: [DMESG-WARN][33] ([i915#62] / [i915#92]) -> [DMESG-WARN][34] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/fi-kbl-x1275/igt@prime_vgem@basic-fence-flip.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/fi-kbl-x1275/igt@prime_vgem@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1506]: https://gitlab.freedesktop.org/drm/intel/issues/1506
[i915#1751]: https://gitlab.freedesktop.org/drm/intel/issues/1751
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1932]: https://gitlab.freedesktop.org/drm/intel/issues/1932
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2045]: https://gitlab.freedesktop.org/drm/intel/issues/2045
[i915#289]: https://gitlab.freedesktop.org/drm/intel/issues/289
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (43 -> 37)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper
Build changes
-------------
* Linux: CI_DRM_8719 -> Patchwork_18124
CI-20190529: 20190529
CI_DRM_8719: 6ca80d83ae657da395ab20034f0f66209b456127 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5729: a048d54f58dd70b07dbeb4541b273ec230ddb586 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18124: fc1806ac58ba125b3ae1694ecf14b24a6dc5ffa0 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
fc1806ac58ba DO_NOT_MERGE_IT: drm/i915/display: Enable HOBL by default
bf56c0fa3559 drm/i915/display: Implement HOBL
b77c0a387a4f drm/i915/bios: Parse HOBL parameter
9a55c71fcfe3 drm/i915/display: Remove port and phy from voltage swing functions
7823dc29cae5 drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder (rev2)
2020-07-08 20:55 [Intel-gfx] [PATCH v4 1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder José Roberto de Souza
` (9 preceding siblings ...)
2020-07-09 16:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-07-09 18:59 ` Patchwork
2020-07-09 19:35 ` Souza, Jose
10 siblings, 1 reply; 17+ messages in thread
From: Patchwork @ 2020-07-09 18:59 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder (rev2)
URL : https://patchwork.freedesktop.org/series/79265/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8719_full -> Patchwork_18124_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_18124_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@engines-mixed-process@vecs0:
- shard-skl: [PASS][1] -> [FAIL][2] ([i915#1528])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl6/igt@gem_ctx_persistence@engines-mixed-process@vecs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl8/igt@gem_ctx_persistence@engines-mixed-process@vecs0.html
* igt@gem_eio@kms:
- shard-snb: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-snb1/igt@gem_eio@kms.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-snb6/igt@gem_eio@kms.html
* igt@gem_exec_balancer@bonded-early:
- shard-kbl: [PASS][5] -> [FAIL][6] ([i915#2079])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-kbl4/igt@gem_exec_balancer@bonded-early.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-kbl6/igt@gem_exec_balancer@bonded-early.html
* igt@gem_exec_params@invalid-fence-in:
- shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#93] / [i915#95]) +4 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-kbl7/igt@gem_exec_params@invalid-fence-in.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-kbl2/igt@gem_exec_params@invalid-fence-in.html
* igt@gem_exec_reloc@basic-concurrent0:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#1930])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-glk3/igt@gem_exec_reloc@basic-concurrent0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-glk5/igt@gem_exec_reloc@basic-concurrent0.html
* igt@i915_pm_backlight@fade_with_suspend:
- shard-skl: [PASS][11] -> [INCOMPLETE][12] ([i915#69])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl5/igt@i915_pm_backlight@fade_with_suspend.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl1/igt@i915_pm_backlight@fade_with_suspend.html
* igt@i915_selftest@mock@requests:
- shard-apl: [PASS][13] -> [INCOMPLETE][14] ([i915#1635] / [i915#2110])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl3/igt@i915_selftest@mock@requests.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl2/igt@i915_selftest@mock@requests.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-0:
- shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl3/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl2/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-0:
- shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +8 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl1/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl2/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-0:
- shard-glk: [PASS][19] -> [DMESG-FAIL][20] ([i915#118] / [i915#95])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-glk6/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-glk8/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding:
- shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#1635] / [i915#95]) +15 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl4/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +4 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
- shard-glk: [PASS][25] -> [FAIL][26] ([i915#54])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-glk3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-glk8/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
- shard-tglb: [PASS][27] -> [DMESG-WARN][28] ([i915#402])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb5/igt@kms_cursor_legacy@cursora-vs-flipa-toggle.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb2/igt@kms_cursor_legacy@cursora-vs-flipa-toggle.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1:
- shard-tglb: [PASS][29] -> [FAIL][30] ([i915#2122])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb2/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb3/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
* igt@kms_flip@plain-flip-fb-recreate@b-edp1:
- shard-skl: [PASS][31] -> [FAIL][32] ([i915#2122])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl4/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl10/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
* igt@kms_frontbuffer_tracking@basic:
- shard-glk: [PASS][33] -> [DMESG-WARN][34] ([i915#1982])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-glk8/igt@kms_frontbuffer_tracking@basic.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-glk4/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt:
- shard-tglb: [PASS][35] -> [DMESG-WARN][36] ([i915#1982])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_psr@no_drrs:
- shard-iclb: [PASS][37] -> [FAIL][38] ([i915#173])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-iclb2/igt@kms_psr@no_drrs.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-iclb1/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][39] -> [SKIP][40] ([fdo#109441]) +3 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@perf_pmu@semaphore-busy@rcs0:
- shard-kbl: [PASS][41] -> [FAIL][42] ([i915#1820])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-kbl7/igt@perf_pmu@semaphore-busy@rcs0.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-kbl2/igt@perf_pmu@semaphore-busy@rcs0.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +4 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-kbl3/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-hsw: [TIMEOUT][45] ([i915#1958] / [i915#1976] / [i915#2119]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-hsw2/igt@gem_eio@in-flight-contexts-10ms.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-hsw7/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_eio@reset-stress:
- shard-hsw: [INCOMPLETE][47] ([CI#80]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-hsw2/igt@gem_eio@reset-stress.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-hsw7/igt@gem_eio@reset-stress.html
* igt@gem_exec_whisper@basic-normal:
- shard-glk: [DMESG-WARN][49] ([i915#118] / [i915#95]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-glk9/igt@gem_exec_whisper@basic-normal.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-glk7/igt@gem_exec_whisper@basic-normal.html
* igt@i915_module_load@reload:
- shard-tglb: [DMESG-WARN][51] ([i915#402]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb2/igt@i915_module_load@reload.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb3/igt@i915_module_load@reload.html
* igt@i915_selftest@mock@requests:
- shard-skl: [INCOMPLETE][53] ([i915#198] / [i915#2110]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl8/igt@i915_selftest@mock@requests.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl1/igt@i915_selftest@mock@requests.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-0:
- shard-glk: [DMESG-FAIL][55] ([i915#118] / [i915#95]) -> [PASS][56] +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-glk8/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-glk4/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
* igt@kms_color@pipe-b-ctm-negative:
- shard-skl: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] +6 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl2/igt@kms_color@pipe-b-ctm-negative.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl6/igt@kms_color@pipe-b-ctm-negative.html
* igt@kms_cursor_edge_walk@pipe-b-128x128-left-edge:
- shard-glk: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-glk7/igt@kms_cursor_edge_walk@pipe-b-128x128-left-edge.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-glk9/igt@kms_cursor_edge_walk@pipe-b-128x128-left-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic:
- shard-tglb: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb2/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb3/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html
* igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled:
- shard-apl: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl1/igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl6/igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled.html
* igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible@ab-vga1-hdmi-a1:
- shard-hsw: [DMESG-WARN][65] ([i915#1982]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-hsw6/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible@ab-vga1-hdmi-a1.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-hsw6/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible@ab-vga1-hdmi-a1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
- shard-apl: [DMESG-WARN][67] ([i915#1635] / [i915#95]) -> [PASS][68] +13 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt:
- shard-tglb: [SKIP][69] ([i915#668]) -> [PASS][70] +2 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][71] ([i915#1188]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl10/igt@kms_hdr@bpc-switch.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl5/igt@kms_hdr@bpc-switch.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][73] ([fdo#108145] / [i915#265]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][75] ([fdo#109441]) -> [PASS][76] +2 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-iclb5/igt@kms_psr@psr2_cursor_render.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][77] ([i915#658]) -> [SKIP][78] ([i915#588])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-iclb1/igt@i915_pm_dc@dc3co-vpb-simulation.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_color_chamelium@pipe-b-ctm-0-5:
- shard-apl: [SKIP][79] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][80] ([fdo#109271] / [fdo#111827])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl7/igt@kms_color_chamelium@pipe-b-ctm-0-5.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl2/igt@kms_color_chamelium@pipe-b-ctm-0-5.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
- shard-apl: [SKIP][81] ([fdo#109271] / [i915#1635]) -> [SKIP][82] ([fdo#109271]) +3 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl8/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend@a-edp1:
- shard-tglb: [DMESG-WARN][83] ([i915#1602] / [i915#1887]) -> [INCOMPLETE][84] ([i915#1602] / [i915#1887] / [i915#456])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb8/igt@kms_flip@flip-vs-suspend@a-edp1.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb5/igt@kms_flip@flip-vs-suspend@a-edp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite:
- shard-apl: [SKIP][85] ([fdo#109271]) -> [SKIP][86] ([fdo#109271] / [i915#1635])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-apl: [DMESG-FAIL][87] ([fdo#108145] / [i915#1982]) -> [FAIL][88] ([fdo#108145] / [i915#265])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl4/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl1/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@runner@aborted:
- shard-apl: ([FAIL][89], [FAIL][90]) ([i915#1610] / [i915#1635] / [i915#2110]) -> [FAIL][91] ([i915#1635] / [i915#2110])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl2/igt@runner@aborted.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl4/igt@runner@aborted.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl2/igt@runner@aborted.html
- shard-tglb: ([FAIL][92], [FAIL][93]) ([i915#2110] / [i915#2150]) -> ([FAIL][94], [FAIL][95]) ([i915#1764] / [i915#2110] / [i915#2150])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb8/igt@runner@aborted.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb2/igt@runner@aborted.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb5/igt@runner@aborted.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb3/igt@runner@aborted.html
[CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173
[i915#1764]: https://gitlab.freedesktop.org/drm/intel/issues/1764
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820
[i915#1887]: https://gitlab.freedesktop.org/drm/intel/issues/1887
[i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930
[i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
[i915#1976]: https://gitlab.freedesktop.org/drm/intel/issues/1976
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2079]: https://gitlab.freedesktop.org/drm/intel/issues/2079
[i915#2110]: https://gitlab.freedesktop.org/drm/intel/issues/2110
[i915#2119]: https://gitlab.freedesktop.org/drm/intel/issues/2119
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2150]: https://gitlab.freedesktop.org/drm/intel/issues/2150
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_8719 -> Patchwork_18124
CI-20190529: 20190529
CI_DRM_8719: 6ca80d83ae657da395ab20034f0f66209b456127 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5729: a048d54f58dd70b07dbeb4541b273ec230ddb586 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18124: fc1806ac58ba125b3ae1694ecf14b24a6dc5ffa0 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder (rev2)
2020-07-09 18:59 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2020-07-09 19:35 ` Souza, Jose
0 siblings, 0 replies; 17+ messages in thread
From: Souza, Jose @ 2020-07-09 19:35 UTC (permalink / raw)
To: intel-gfx
On Thu, 2020-07-09 at 18:59 +0000, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder (rev2)
> URL : https://patchwork.freedesktop.org/series/79265/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_8719_full -> Patchwork_18124_full
> ====================================================
>
> Summary
> -------
>
> **SUCCESS**
>
> No regressions found.
Pushed the 3 first patches to dinq, thanks for the reviews.
>
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_18124_full that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_ctx_persistence@engines-mixed-process@vecs0:
> - shard-skl: [PASS][1] -> [FAIL][2] ([i915#1528])
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl6/igt@gem_ctx_persistence@engines-mixed-process@vecs0.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl8/igt@gem_ctx_persistence@engines-mixed-process@vecs0.html
>
> * igt@gem_eio@kms:
> - shard-snb: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-snb1/igt@gem_eio@kms.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-snb6/igt@gem_eio@kms.html
>
> * igt@gem_exec_balancer@bonded-early:
> - shard-kbl: [PASS][5] -> [FAIL][6] ([i915#2079])
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-kbl4/igt@gem_exec_balancer@bonded-early.html
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-kbl6/igt@gem_exec_balancer@bonded-early.html
>
> * igt@gem_exec_params@invalid-fence-in:
> - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#93] / [i915#95]) +4 similar issues
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-kbl7/igt@gem_exec_params@invalid-fence-in.html
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-kbl2/igt@gem_exec_params@invalid-fence-in.html
>
> * igt@gem_exec_reloc@basic-concurrent0:
> - shard-glk: [PASS][9] -> [FAIL][10] ([i915#1930])
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-glk3/igt@gem_exec_reloc@basic-concurrent0.html
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-glk5/igt@gem_exec_reloc@basic-concurrent0.html
>
> * igt@i915_pm_backlight@fade_with_suspend:
> - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([i915#69])
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl5/igt@i915_pm_backlight@fade_with_suspend.html
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl1/igt@i915_pm_backlight@fade_with_suspend.html
>
> * igt@i915_selftest@mock@requests:
> - shard-apl: [PASS][13] -> [INCOMPLETE][14] ([i915#1635] / [i915#2110])
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl3/igt@i915_selftest@mock@requests.html
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl2/igt@i915_selftest@mock@requests.html
>
> * igt@kms_big_fb@x-tiled-64bpp-rotate-0:
> - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982])
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl3/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl2/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
>
> * igt@kms_big_fb@y-tiled-16bpp-rotate-0:
> - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +8 similar issues
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl1/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl2/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
>
> * igt@kms_big_fb@y-tiled-64bpp-rotate-0:
> - shard-glk: [PASS][19] -> [DMESG-FAIL][20] ([i915#118] / [i915#95])
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-glk6/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-glk8/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html
>
> * igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding:
> - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#1635] / [i915#95]) +15 similar issues
> [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
> [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl4/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
>
> * igt@kms_cursor_crc@pipe-a-cursor-suspend:
> - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +4 similar issues
> [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
> [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
> - shard-glk: [PASS][25] -> [FAIL][26] ([i915#54])
> [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-glk3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
> [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-glk8/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
>
> * igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
> - shard-tglb: [PASS][27] -> [DMESG-WARN][28] ([i915#402])
> [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb5/igt@kms_cursor_legacy@cursora-vs-flipa-toggle.html
> [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb2/igt@kms_cursor_legacy@cursora-vs-flipa-toggle.html
>
> * igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1:
> - shard-tglb: [PASS][29] -> [FAIL][30] ([i915#2122])
> [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb2/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
> [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb3/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
>
> * igt@kms_flip@plain-flip-fb-recreate@b-edp1:
> - shard-skl: [PASS][31] -> [FAIL][32] ([i915#2122])
> [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl4/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
> [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl10/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
>
> * igt@kms_frontbuffer_tracking@basic:
> - shard-glk: [PASS][33] -> [DMESG-WARN][34] ([i915#1982])
> [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-glk8/igt@kms_frontbuffer_tracking@basic.html
> [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-glk4/igt@kms_frontbuffer_tracking@basic.html
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt:
> - shard-tglb: [PASS][35] -> [DMESG-WARN][36] ([i915#1982])
> [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html
> [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html
>
> * igt@kms_psr@no_drrs:
> - shard-iclb: [PASS][37] -> [FAIL][38] ([i915#173])
> [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-iclb2/igt@kms_psr@no_drrs.html
> [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-iclb1/igt@kms_psr@no_drrs.html
>
> * igt@kms_psr@psr2_cursor_mmap_cpu:
> - shard-iclb: [PASS][39] -> [SKIP][40] ([fdo#109441]) +3 similar issues
> [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
> [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html
>
> * igt@perf_pmu@semaphore-busy@rcs0:
> - shard-kbl: [PASS][41] -> [FAIL][42] ([i915#1820])
> [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-kbl7/igt@perf_pmu@semaphore-busy@rcs0.html
> [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-kbl2/igt@perf_pmu@semaphore-busy@rcs0.html
>
>
> #### Possible fixes ####
>
> * igt@gem_ctx_isolation@preservation-s3@bcs0:
> - shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +4 similar issues
> [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@bcs0.html
> [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-kbl3/igt@gem_ctx_isolation@preservation-s3@bcs0.html
>
> * igt@gem_eio@in-flight-contexts-10ms:
> - shard-hsw: [TIMEOUT][45] ([i915#1958] / [i915#1976] / [i915#2119]) -> [PASS][46]
> [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-hsw2/igt@gem_eio@in-flight-contexts-10ms.html
> [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-hsw7/igt@gem_eio@in-flight-contexts-10ms.html
>
> * igt@gem_eio@reset-stress:
> - shard-hsw: [INCOMPLETE][47] ([CI#80]) -> [PASS][48]
> [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-hsw2/igt@gem_eio@reset-stress.html
> [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-hsw7/igt@gem_eio@reset-stress.html
>
> * igt@gem_exec_whisper@basic-normal:
> - shard-glk: [DMESG-WARN][49] ([i915#118] / [i915#95]) -> [PASS][50]
> [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-glk9/igt@gem_exec_whisper@basic-normal.html
> [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-glk7/igt@gem_exec_whisper@basic-normal.html
>
> * igt@i915_module_load@reload:
> - shard-tglb: [DMESG-WARN][51] ([i915#402]) -> [PASS][52]
> [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb2/igt@i915_module_load@reload.html
> [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb3/igt@i915_module_load@reload.html
>
> * igt@i915_selftest@mock@requests:
> - shard-skl: [INCOMPLETE][53] ([i915#198] / [i915#2110]) -> [PASS][54]
> [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl8/igt@i915_selftest@mock@requests.html
> [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl1/igt@i915_selftest@mock@requests.html
>
> * igt@kms_big_fb@x-tiled-64bpp-rotate-0:
> - shard-glk: [DMESG-FAIL][55] ([i915#118] / [i915#95]) -> [PASS][56] +1 similar issue
> [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-glk8/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
> [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-glk4/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
>
> * igt@kms_color@pipe-b-ctm-negative:
> - shard-skl: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] +6 similar issues
> [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl2/igt@kms_color@pipe-b-ctm-negative.html
> [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl6/igt@kms_color@pipe-b-ctm-negative.html
>
> * igt@kms_cursor_edge_walk@pipe-b-128x128-left-edge:
> - shard-glk: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] +1 similar issue
> [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-glk7/igt@kms_cursor_edge_walk@pipe-b-128x128-left-edge.html
> [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-glk9/igt@kms_cursor_edge_walk@pipe-b-128x128-left-edge.html
>
> * igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic:
> - shard-tglb: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +1 similar issue
> [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb2/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html
> [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb3/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html
>
> * igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled:
> - shard-apl: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64]
> [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl1/igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled.html
> [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl6/igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled.html
>
> * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible@ab-vga1-hdmi-a1:
> - shard-hsw: [DMESG-WARN][65] ([i915#1982]) -> [PASS][66]
> [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-hsw6/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible@ab-vga1-hdmi-a1.html
> [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-hsw6/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible@ab-vga1-hdmi-a1.html
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
> - shard-apl: [DMESG-WARN][67] ([i915#1635] / [i915#95]) -> [PASS][68] +13 similar issues
> [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
> [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt:
> - shard-tglb: [SKIP][69] ([i915#668]) -> [PASS][70] +2 similar issues
> [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
> [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
>
> * igt@kms_hdr@bpc-switch:
> - shard-skl: [FAIL][71] ([i915#1188]) -> [PASS][72]
> [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl10/igt@kms_hdr@bpc-switch.html
> [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl5/igt@kms_hdr@bpc-switch.html
>
> * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
> - shard-skl: [FAIL][73] ([fdo#108145] / [i915#265]) -> [PASS][74]
> [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
> [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>
> * igt@kms_psr@psr2_cursor_render:
> - shard-iclb: [SKIP][75] ([fdo#109441]) -> [PASS][76] +2 similar issues
> [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-iclb5/igt@kms_psr@psr2_cursor_render.html
> [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
>
>
> #### Warnings ####
>
> * igt@i915_pm_dc@dc3co-vpb-simulation:
> - shard-iclb: [SKIP][77] ([i915#658]) -> [SKIP][78] ([i915#588])
> [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-iclb1/igt@i915_pm_dc@dc3co-vpb-simulation.html
> [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
>
> * igt@kms_color_chamelium@pipe-b-ctm-0-5:
> - shard-apl: [SKIP][79] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][80] ([fdo#109271] / [fdo#111827])
> [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl7/igt@kms_color_chamelium@pipe-b-ctm-0-5.html
> [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl2/igt@kms_color_chamelium@pipe-b-ctm-0-5.html
>
> * igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
> - shard-apl: [SKIP][81] ([fdo#109271] / [i915#1635]) -> [SKIP][82] ([fdo#109271]) +3 similar issues
> [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
> [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl8/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
>
> * igt@kms_flip@flip-vs-suspend@a-edp1:
> - shard-tglb: [DMESG-WARN][83] ([i915#1602] / [i915#1887]) -> [INCOMPLETE][84] ([i915#1602] / [i915#1887] / [i915#456])
> [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb8/igt@kms_flip@flip-vs-suspend@a-edp1.html
> [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb5/igt@kms_flip@flip-vs-suspend@a-edp1.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite:
> - shard-apl: [SKIP][85] ([fdo#109271]) -> [SKIP][86] ([fdo#109271] / [i915#1635])
> [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite.html
> [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite.html
>
> * igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
> - shard-apl: [DMESG-FAIL][87] ([fdo#108145] / [i915#1982]) -> [FAIL][88] ([fdo#108145] / [i915#265])
> [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl4/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
> [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl1/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
>
> * igt@runner@aborted:
> - shard-apl: ([FAIL][89], [FAIL][90]) ([i915#1610] / [i915#1635] / [i915#2110]) -> [FAIL][91] ([i915#1635] / [i915#2110])
> [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl2/igt@runner@aborted.html
> [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl4/igt@runner@aborted.html
> [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl2/igt@runner@aborted.html
> - shard-tglb: ([FAIL][92], [FAIL][93]) ([i915#2110] / [i915#2150]) -> ([FAIL][94], [FAIL][95]) ([i915#1764] / [i915#2110] / [i915#2150])
> [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb8/igt@runner@aborted.html
> [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb2/igt@runner@aborted.html
> [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb5/igt@runner@aborted.html
> [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb3/igt@runner@aborted.html
>
>
> [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80
> [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
> [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
> [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
> [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
> [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
> [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528
> [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
> [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
> [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
> [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173
> [i915#1764]: https://gitlab.freedesktop.org/drm/intel/issues/1764
> [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
> [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820
> [i915#1887]: https://gitlab.freedesktop.org/drm/intel/issues/1887
> [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930
> [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
> [i915#1976]: https://gitlab.freedesktop.org/drm/intel/issues/1976
> [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
> [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
> [i915#2079]: https://gitlab.freedesktop.org/drm/intel/issues/2079
> [i915#2110]: https://gitlab.freedesktop.org/drm/intel/issues/2110
> [i915#2119]: https://gitlab.freedesktop.org/drm/intel/issues/2119
> [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
> [i915#2150]: https://gitlab.freedesktop.org/drm/intel/issues/2150
> [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
> [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
> [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
> [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
> [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
> [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
> [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
> [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
> [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
> [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
>
>
> Participating hosts (10 -> 10)
> ------------------------------
>
> No changes in participating hosts
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_8719 -> Patchwork_18124
>
> CI-20190529: 20190529
> CI_DRM_8719: 6ca80d83ae657da395ab20034f0f66209b456127 @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_5729: a048d54f58dd70b07dbeb4541b273ec230ddb586 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_18124: fc1806ac58ba125b3ae1694ecf14b24a6dc5ffa0 @ git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v4 4/5] drm/i915/display: Implement HOBL
2020-07-09 14:24 ` Ville Syrjälä
@ 2020-07-09 19:40 ` Souza, Jose
2020-07-10 11:56 ` Ville Syrjälä
0 siblings, 1 reply; 17+ messages in thread
From: Souza, Jose @ 2020-07-09 19:40 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Thu, 2020-07-09 at 17:24 +0300, Ville Syrjälä wrote:
> On Wed, Jul 08, 2020 at 01:55:11PM -0700, José Roberto de Souza wrote:
> > Hours Of Battery Life is a new GEN12+ power-saving feature that allows
> > supported motherboards to use a special voltage swing table for eDP
> > panels that uses less power.
> >
> > So here if supported by HW, OEM will set it in VBT and i915 will try
> > to train link with HOBL vswing table if link training fails it fall
> > back to the original table.
> >
> > intel_ddi_dp_preemph_max() was optimized to only check the HOBL flag
> > instead of do something like is done in intel_ddi_dp_voltage_max()
> > because it is only called after the first entry of the voltage swing
> > table was loaded so the HOBL flag is valid at that point.
> >
> > v3:
> > - removed a few parameters of icl_ddi_combo_vswing_program() that
> > can be taken from encoder(TODO)
> >
> > v4:
> > - using the HOBL vswing table until training fails completely (Ville)
> >
> > BSpec: 49291
> > BSpec: 49399
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Animesh Manna <animesh.manna@intel.com>
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 37 ++++++++++++++++---
> > .../drm/i915/display/intel_display_types.h | 2 +
> > .../drm/i915/display/intel_dp_link_training.c | 5 +++
> > drivers/gpu/drm/i915/i915_reg.h | 2 +
> > 4 files changed, 41 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 2c484b55bcdf..bf86c588f726 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -706,6 +706,15 @@ static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] =
> > { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> > };
> >
> > +static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = {
> > + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }
> > +};
> > +
> > +static bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table)
> > +{
> > + return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
> > +}
> > +
> > static const struct ddi_buf_trans *
> > bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
> > {
> > @@ -1050,6 +1059,16 @@ static const struct cnl_ddi_buf_trans *
> > tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> > int *n_entries)
> > {
> > + if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.hobl) {
> > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +
> > + if (!intel_dp->hobl_disabled && rate <= 540000) {
> > + /* Same table applies to TGL, RKL and DG1 */
> > + *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
> > + return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
> > + }
> > + }
> > +
> > if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) {
> > return icl_get_combo_buf_trans(encoder, type, rate, n_entries);
> > } else if (rate > 270000) {
> > @@ -2223,13 +2242,12 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
> > DP_TRAIN_VOLTAGE_SWING_MASK;
> > }
> >
> > -/*
> > - * We assume that the full set of pre-emphasis values can be
> > - * used on all DDI platforms. Should that change we need to
> > - * rethink this code.
> > - */
> > static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
> > {
> > + /* HOBL voltage swing table only have one entry */
> > + if (intel_dp->hobl_active)
> > + return DP_TRAIN_PRE_EMPH_LEVEL_0;
>
> That's illegal. We need to claim support for at least all
> vswing/pre-emphasis levels 0-2. 3 is optional. Though there is
> some confusion around this in the eDP spec where it kinda seems suggest
> that even some of the level 2 things are optional. But it's so unclear
> I would defer to just trusting what the DP spec says.
Okay so in this case I should add more entries to tgl_combo_phy_ddi_translations_edp_hbr2_hobl with the same values to match the minimum required by
DP spec?
>
> /me goes to write the patch with the WARNs...
Will take a look.
>
>
> > +
> > return DP_TRAIN_PRE_EMPH_LEVEL_3;
> > }
> >
> > @@ -2392,6 +2410,15 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
> > level = n_entries - 1;
> > }
> >
> > + if (INTEL_GEN(dev_priv) >= 12 && type == INTEL_OUTPUT_EDP) {
> > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +
> > + val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
> > + intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations);
> > + intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,
> > + intel_dp->hobl_active ? val : 0);
> > + }
>
> I'd still suggest writing that unconditionally.
Okay
>
> > +
> > /* Set PORT_TX_DW5 */
> > val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> > val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index e8f809161c75..fd4f0e4d0be7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1375,6 +1375,8 @@ struct intel_dp {
> >
> > /* Display stream compression testing */
> > bool force_dsc_en;
> > +
> > + u8 hobl_disabled : 1, hobl_active : 1, hobl_not_used : 6;
>
> Why did we go from a simple boolean to this complicated thing?
Will try to remove one.
>
> > };
> >
> > enum lspcon_vendor {
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > index 2493142a70e9..925822fd386d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > @@ -401,6 +401,11 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> > intel_connector->base.base.id,
> > intel_connector->base.name,
> > intel_dp->link_rate, intel_dp->lane_count);
> > + if (intel_dp->hobl_active) {
> > + drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
> > + "Link Training failed with HOBL active, not enabling it for now on");
> > + intel_dp->hobl_disabled = true;
>
> I don't think we should do the link rate/lanes reduction in
> this case. Ie. we should just mark hobl as no good and retry
> the link training with the same link param limits.
Okay
>
> > + }
> > if (!intel_dp_get_link_train_fallback_values(intel_dp,
> > intel_dp->link_rate,
> > intel_dp->lane_count))
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 86a23ced051b..ea16931c0fa4 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1898,6 +1898,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> > #define PWR_DOWN_LN_3_1_0 (0xb << 4)
> > #define PWR_DOWN_LN_MASK (0xf << 4)
> > #define PWR_DOWN_LN_SHIFT 4
> > +#define EDP4K2K_MODE_OVRD_EN (1 << 3)
> > +#define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2)
> >
> > #define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
> > #define ICL_LANE_ENABLE_AUX (1 << 0)
> > --
> > 2.27.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v4 4/5] drm/i915/display: Implement HOBL
2020-07-09 19:40 ` Souza, Jose
@ 2020-07-10 11:56 ` Ville Syrjälä
0 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjälä @ 2020-07-10 11:56 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
On Thu, Jul 09, 2020 at 07:40:35PM +0000, Souza, Jose wrote:
> On Thu, 2020-07-09 at 17:24 +0300, Ville Syrjälä wrote:
> > On Wed, Jul 08, 2020 at 01:55:11PM -0700, José Roberto de Souza wrote:
> > > Hours Of Battery Life is a new GEN12+ power-saving feature that allows
> > > supported motherboards to use a special voltage swing table for eDP
> > > panels that uses less power.
> > >
> > > So here if supported by HW, OEM will set it in VBT and i915 will try
> > > to train link with HOBL vswing table if link training fails it fall
> > > back to the original table.
> > >
> > > intel_ddi_dp_preemph_max() was optimized to only check the HOBL flag
> > > instead of do something like is done in intel_ddi_dp_voltage_max()
> > > because it is only called after the first entry of the voltage swing
> > > table was loaded so the HOBL flag is valid at that point.
> > >
> > > v3:
> > > - removed a few parameters of icl_ddi_combo_vswing_program() that
> > > can be taken from encoder(TODO)
> > >
> > > v4:
> > > - using the HOBL vswing table until training fails completely (Ville)
> > >
> > > BSpec: 49291
> > > BSpec: 49399
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Cc: Animesh Manna <animesh.manna@intel.com>
> > > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 37 ++++++++++++++++---
> > > .../drm/i915/display/intel_display_types.h | 2 +
> > > .../drm/i915/display/intel_dp_link_training.c | 5 +++
> > > drivers/gpu/drm/i915/i915_reg.h | 2 +
> > > 4 files changed, 41 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index 2c484b55bcdf..bf86c588f726 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -706,6 +706,15 @@ static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] =
> > > { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> > > };
> > >
> > > +static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = {
> > > + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }
> > > +};
> > > +
> > > +static bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table)
> > > +{
> > > + return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
> > > +}
> > > +
> > > static const struct ddi_buf_trans *
> > > bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
> > > {
> > > @@ -1050,6 +1059,16 @@ static const struct cnl_ddi_buf_trans *
> > > tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> > > int *n_entries)
> > > {
> > > + if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.hobl) {
> > > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > > +
> > > + if (!intel_dp->hobl_disabled && rate <= 540000) {
> > > + /* Same table applies to TGL, RKL and DG1 */
> > > + *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
> > > + return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
> > > + }
> > > + }
> > > +
> > > if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) {
> > > return icl_get_combo_buf_trans(encoder, type, rate, n_entries);
> > > } else if (rate > 270000) {
> > > @@ -2223,13 +2242,12 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
> > > DP_TRAIN_VOLTAGE_SWING_MASK;
> > > }
> > >
> > > -/*
> > > - * We assume that the full set of pre-emphasis values can be
> > > - * used on all DDI platforms. Should that change we need to
> > > - * rethink this code.
> > > - */
> > > static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
> > > {
> > > + /* HOBL voltage swing table only have one entry */
> > > + if (intel_dp->hobl_active)
> > > + return DP_TRAIN_PRE_EMPH_LEVEL_0;
> >
> > That's illegal. We need to claim support for at least all
> > vswing/pre-emphasis levels 0-2. 3 is optional. Though there is
> > some confusion around this in the eDP spec where it kinda seems suggest
> > that even some of the level 2 things are optional. But it's so unclear
> > I would defer to just trusting what the DP spec says.
>
> Okay so in this case I should add more entries to tgl_combo_phy_ddi_translations_edp_hbr2_hobl with the same values to match the minimum required by
> DP spec?
Yeah, I guess that's the easiest way to do it without redesigning the
whole .{voltage,preemph}_max() stuff.
>
> >
> > /me goes to write the patch with the WARNs...
>
> Will take a look.
>
> >
> >
> > > +
> > > return DP_TRAIN_PRE_EMPH_LEVEL_3;
> > > }
> > >
> > > @@ -2392,6 +2410,15 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
> > > level = n_entries - 1;
> > > }
> > >
> > > + if (INTEL_GEN(dev_priv) >= 12 && type == INTEL_OUTPUT_EDP) {
> > > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > > +
> > > + val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
> > > + intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations);
> > > + intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,
> > > + intel_dp->hobl_active ? val : 0);
> > > + }
> >
> > I'd still suggest writing that unconditionally.
>
> Okay
>
> >
> > > +
> > > /* Set PORT_TX_DW5 */
> > > val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> > > val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index e8f809161c75..fd4f0e4d0be7 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -1375,6 +1375,8 @@ struct intel_dp {
> > >
> > > /* Display stream compression testing */
> > > bool force_dsc_en;
> > > +
> > > + u8 hobl_disabled : 1, hobl_active : 1, hobl_not_used : 6;
> >
> > Why did we go from a simple boolean to this complicated thing?
>
> Will try to remove one.
>
> >
> > > };
> > >
> > > enum lspcon_vendor {
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > index 2493142a70e9..925822fd386d 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > @@ -401,6 +401,11 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> > > intel_connector->base.base.id,
> > > intel_connector->base.name,
> > > intel_dp->link_rate, intel_dp->lane_count);
> > > + if (intel_dp->hobl_active) {
> > > + drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
> > > + "Link Training failed with HOBL active, not enabling it for now on");
> > > + intel_dp->hobl_disabled = true;
> >
> > I don't think we should do the link rate/lanes reduction in
> > this case. Ie. we should just mark hobl as no good and retry
> > the link training with the same link param limits.
>
> Okay
>
> >
> > > + }
> > > if (!intel_dp_get_link_train_fallback_values(intel_dp,
> > > intel_dp->link_rate,
> > > intel_dp->lane_count))
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 86a23ced051b..ea16931c0fa4 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -1898,6 +1898,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> > > #define PWR_DOWN_LN_3_1_0 (0xb << 4)
> > > #define PWR_DOWN_LN_MASK (0xf << 4)
> > > #define PWR_DOWN_LN_SHIFT 4
> > > +#define EDP4K2K_MODE_OVRD_EN (1 << 3)
> > > +#define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2)
> > >
> > > #define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
> > > #define ICL_LANE_ENABLE_AUX (1 << 0)
> > > --
> > > 2.27.0
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2020-07-10 11:56 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-08 20:55 [Intel-gfx] [PATCH v4 1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder José Roberto de Souza
2020-07-08 20:55 ` [Intel-gfx] [PATCH v4 2/5] drm/i915/display: Remove port and phy from voltage swing functions José Roberto de Souza
2020-07-09 14:12 ` Ville Syrjälä
2020-07-08 20:55 ` [Intel-gfx] [PATCH v4 3/5] drm/i915/bios: Parse HOBL parameter José Roberto de Souza
2020-07-08 20:55 ` [Intel-gfx] [PATCH v4 4/5] drm/i915/display: Implement HOBL José Roberto de Souza
2020-07-09 14:24 ` Ville Syrjälä
2020-07-09 19:40 ` Souza, Jose
2020-07-10 11:56 ` Ville Syrjälä
2020-07-08 20:55 ` [Intel-gfx] [PATCH v4 5/5] DO_NOT_MERGE_IT: drm/i915/display: Enable HOBL by default José Roberto de Souza
2020-07-08 22:04 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder Patchwork
2020-07-08 22:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-09 2:53 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-07-09 14:10 ` [Intel-gfx] [PATCH v4 1/5] " Ville Syrjälä
2020-07-09 16:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder (rev2) Patchwork
2020-07-09 16:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-09 18:59 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-07-09 19:35 ` Souza, Jose
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.