[linux-next:master 3504/6488] arch/riscv/include/asm/irqflags.h:22:9: sparse: sparse: context imbalance in 'pci_wait_cfg' - unexpected unlock

[linux-next:master 3504/6488] arch/riscv/include/asm/irqflags.h:22:9: sparse: sparse: context imbalance in 'pci_wait_cfg' - unexpected unlock

[kernel test robot]

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tree:   https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head:   8903263671cb22bc33545eb7cbd68c875bb87e95
commit: f3691b7ba5c39508aaac341050e72304bb1a115d [3504/6488] PCI: Fix pci_cfg_wait queue locking problem
config: riscv-randconfig-s031-20200708 (attached as .config)
compiler: riscv64-linux-gcc (GCC) 9.3.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # apt-get install sparse
        # sparse version: v0.6.2-37-gc9676a3b-dirty
        git checkout f3691b7ba5c39508aaac341050e72304bb1a115d
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=riscv 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>


sparse warnings: (new ones prefixed by >>)

>> arch/riscv/include/asm/irqflags.h:22:9: sparse: sparse: context imbalance in 'pci_wait_cfg' - unexpected unlock

vim +/pci_wait_cfg +22 arch/riscv/include/asm/irqflags.h

6d60b6ee0c9777 Palmer Dabbelt    2017-07-10  18  
6d60b6ee0c9777 Palmer Dabbelt    2017-07-10  19  /* unconditionally enable interrupts */
6d60b6ee0c9777 Palmer Dabbelt    2017-07-10  20  static inline void arch_local_irq_enable(void)
6d60b6ee0c9777 Palmer Dabbelt    2017-07-10  21  {
a4c3733d32a72f Christoph Hellwig 2019-10-28 @22  	csr_set(CSR_STATUS, SR_IE);
6d60b6ee0c9777 Palmer Dabbelt    2017-07-10  23  }
6d60b6ee0c9777 Palmer Dabbelt    2017-07-10  24  

:::::: The code at line 22 was first introduced by commit
:::::: a4c3733d32a72f11dee86d0731d7565aa6ebe22d riscv: abstract out CSR names for supervisor vs machine mode

:::::: TO: Christoph Hellwig <hch@lst.de>
:::::: CC: Paul Walmsley <paul.walmsley@sifive.com>

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

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