* [PATCH linux dev-5.7 v2 0/2] clk: Aspeed: Fix eMMC clock speeds
@ 2020-07-09 19:41 Eddie James
2020-07-09 19:41 ` [PATCH linux dev-5.7 v2 1/2] clk: AST2600: Add mux for EMMC clock Eddie James
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Eddie James @ 2020-07-09 19:41 UTC (permalink / raw)
To: openbmc; +Cc: joel, andrew, Eddie James
There were two problems affecting clock speeds to the eMMC chip. Firstly, the
AST2600 clock was not muxed correctly to be derived from the MPLL. Secondly,
the SDHCI clock control divider was not calculated correctly. This series
addresses these problems.
Eddie James (2):
clk: AST2600: Add mux for EMMC clock
mmc: sdhci-of-aspeed: Fix clock divider calculation
drivers/clk/clk-ast2600.c | 49 +++++++++++++++++++++++++-----
drivers/mmc/host/sdhci-of-aspeed.c | 2 +-
2 files changed, 42 insertions(+), 9 deletions(-)
--
2.24.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH linux dev-5.7 v2 1/2] clk: AST2600: Add mux for EMMC clock
2020-07-09 19:41 [PATCH linux dev-5.7 v2 0/2] clk: Aspeed: Fix eMMC clock speeds Eddie James
@ 2020-07-09 19:41 ` Eddie James
2020-07-09 19:41 ` [PATCH linux dev-5.7 v2 2/2] mmc: sdhci-of-aspeed: Fix clock divider calculation Eddie James
2020-07-10 13:13 ` [PATCH linux dev-5.7 v2 0/2] clk: Aspeed: Fix eMMC clock speeds Patrick Williams
2 siblings, 0 replies; 6+ messages in thread
From: Eddie James @ 2020-07-09 19:41 UTC (permalink / raw)
To: openbmc; +Cc: joel, andrew, Eddie James
The EMMC clock can be derived from either the HPLL or the MPLL. Register
a clock mux so that the rate is calculated correctly based upon the
parent.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
---
drivers/clk/clk-ast2600.c | 49 ++++++++++++++++++++++++++++++++-------
1 file changed, 41 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
index 35f53956c762..bbacaccad554 100644
--- a/drivers/clk/clk-ast2600.c
+++ b/drivers/clk/clk-ast2600.c
@@ -131,6 +131,18 @@ static const struct clk_div_table ast2600_eclk_div_table[] = {
{ 0 }
};
+static const struct clk_div_table ast2600_emmc_extclk_div_table[] = {
+ { 0x0, 2 },
+ { 0x1, 4 },
+ { 0x2, 6 },
+ { 0x3, 8 },
+ { 0x4, 10 },
+ { 0x5, 12 },
+ { 0x6, 14 },
+ { 0x7, 16 },
+ { 0 }
+};
+
static const struct clk_div_table ast2600_mac_div_table[] = {
{ 0x0, 4 },
{ 0x1, 4 },
@@ -390,6 +402,11 @@ static struct clk_hw *aspeed_g6_clk_hw_register_gate(struct device *dev,
return hw;
}
+static const char *const emmc_extclk_parent_names[] = {
+ "emmc_extclk_hpll_in",
+ "mpll",
+};
+
static const char * const vclk_parent_names[] = {
"dpll",
"d1pll",
@@ -459,16 +476,32 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
return PTR_ERR(hw);
aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw;
- /* EMMC ext clock divider */
- hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "hpll", 0,
- scu_g6_base + ASPEED_G6_CLK_SELECTION1, 15, 0,
- &aspeed_g6_clk_lock);
+ /* EMMC ext clock */
+ hw = clk_hw_register_fixed_factor(dev, "emmc_extclk_hpll_in", "hpll",
+ 0, 1, 2);
if (IS_ERR(hw))
return PTR_ERR(hw);
- hw = clk_hw_register_divider_table(dev, "emmc_extclk", "emmc_extclk_gate", 0,
- scu_g6_base + ASPEED_G6_CLK_SELECTION1, 12, 3, 0,
- ast2600_div_table,
- &aspeed_g6_clk_lock);
+
+ hw = clk_hw_register_mux(dev, "emmc_extclk_mux",
+ emmc_extclk_parent_names,
+ ARRAY_SIZE(emmc_extclk_parent_names), 0,
+ scu_g6_base + ASPEED_G6_CLK_SELECTION1, 11, 1,
+ 0, &aspeed_g6_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "emmc_extclk_mux",
+ 0, scu_g6_base + ASPEED_G6_CLK_SELECTION1,
+ 15, 0, &aspeed_g6_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ hw = clk_hw_register_divider_table(dev, "emmc_extclk",
+ "emmc_extclk_gate", 0,
+ scu_g6_base +
+ ASPEED_G6_CLK_SELECTION1, 12,
+ 3, 0, ast2600_emmc_extclk_div_table,
+ &aspeed_g6_clk_lock);
if (IS_ERR(hw))
return PTR_ERR(hw);
aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw;
--
2.24.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH linux dev-5.7 v2 2/2] mmc: sdhci-of-aspeed: Fix clock divider calculation
2020-07-09 19:41 [PATCH linux dev-5.7 v2 0/2] clk: Aspeed: Fix eMMC clock speeds Eddie James
2020-07-09 19:41 ` [PATCH linux dev-5.7 v2 1/2] clk: AST2600: Add mux for EMMC clock Eddie James
@ 2020-07-09 19:41 ` Eddie James
2020-07-10 1:14 ` Andrew Jeffery
2020-07-10 13:13 ` [PATCH linux dev-5.7 v2 0/2] clk: Aspeed: Fix eMMC clock speeds Patrick Williams
2 siblings, 1 reply; 6+ messages in thread
From: Eddie James @ 2020-07-09 19:41 UTC (permalink / raw)
To: openbmc; +Cc: joel, andrew, Eddie James
When calculating the clock divider, start dividing at 2 instead of 1.
The divider is divided by two at the end of the calculation, so starting
at 1 may result in a divider of 0, which shouldn't happen.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
---
drivers/mmc/host/sdhci-of-aspeed.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c
index 56912e30c47e..a1bcc0f4ba9e 100644
--- a/drivers/mmc/host/sdhci-of-aspeed.c
+++ b/drivers/mmc/host/sdhci-of-aspeed.c
@@ -68,7 +68,7 @@ static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
if (WARN_ON(clock > host->max_clk))
clock = host->max_clk;
- for (div = 1; div < 256; div *= 2) {
+ for (div = 2; div < 256; div *= 2) {
if ((parent / div) <= clock)
break;
}
--
2.24.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH linux dev-5.7 v2 2/2] mmc: sdhci-of-aspeed: Fix clock divider calculation
2020-07-09 19:41 ` [PATCH linux dev-5.7 v2 2/2] mmc: sdhci-of-aspeed: Fix clock divider calculation Eddie James
@ 2020-07-10 1:14 ` Andrew Jeffery
0 siblings, 0 replies; 6+ messages in thread
From: Andrew Jeffery @ 2020-07-10 1:14 UTC (permalink / raw)
To: Eddie James, openbmc
On Fri, 10 Jul 2020, at 05:11, Eddie James wrote:
> When calculating the clock divider, start dividing at 2 instead of 1.
> The divider is divided by two at the end of the calculation, so starting
> at 1 may result in a divider of 0, which shouldn't happen.
>
> Signed-off-by: Eddie James <eajames@linux.ibm.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH linux dev-5.7 v2 0/2] clk: Aspeed: Fix eMMC clock speeds
2020-07-09 19:41 [PATCH linux dev-5.7 v2 0/2] clk: Aspeed: Fix eMMC clock speeds Eddie James
2020-07-09 19:41 ` [PATCH linux dev-5.7 v2 1/2] clk: AST2600: Add mux for EMMC clock Eddie James
2020-07-09 19:41 ` [PATCH linux dev-5.7 v2 2/2] mmc: sdhci-of-aspeed: Fix clock divider calculation Eddie James
@ 2020-07-10 13:13 ` Patrick Williams
2020-07-10 13:33 ` Andrew Jeffery
2 siblings, 1 reply; 6+ messages in thread
From: Patrick Williams @ 2020-07-10 13:13 UTC (permalink / raw)
To: Eddie James; +Cc: openbmc, andrew
[-- Attachment #1: Type: text/plain, Size: 794 bytes --]
Hi Eddie,
On Thu, Jul 09, 2020 at 02:41:11PM -0500, Eddie James wrote:
> There were two problems affecting clock speeds to the eMMC chip. Firstly, the
> AST2600 clock was not muxed correctly to be derived from the MPLL. Secondly,
> the SDHCI clock control divider was not calculated correctly. This series
> addresses these problems.
Do either of these affect the AST2500? It looks like maybe the sdhci
one would affect both?
>
> Eddie James (2):
> clk: AST2600: Add mux for EMMC clock
> mmc: sdhci-of-aspeed: Fix clock divider calculation
>
> drivers/clk/clk-ast2600.c | 49 +++++++++++++++++++++++++-----
> drivers/mmc/host/sdhci-of-aspeed.c | 2 +-
> 2 files changed, 42 insertions(+), 9 deletions(-)
>
> --
> 2.24.0
>
--
Patrick Williams
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH linux dev-5.7 v2 0/2] clk: Aspeed: Fix eMMC clock speeds
2020-07-10 13:13 ` [PATCH linux dev-5.7 v2 0/2] clk: Aspeed: Fix eMMC clock speeds Patrick Williams
@ 2020-07-10 13:33 ` Andrew Jeffery
0 siblings, 0 replies; 6+ messages in thread
From: Andrew Jeffery @ 2020-07-10 13:33 UTC (permalink / raw)
To: Patrick Williams, Eddie James; +Cc: openbmc
On Fri, 10 Jul 2020, at 22:43, Patrick Williams wrote:
> Hi Eddie,
>
> On Thu, Jul 09, 2020 at 02:41:11PM -0500, Eddie James wrote:
> > There were two problems affecting clock speeds to the eMMC chip. Firstly, the
> > AST2600 clock was not muxed correctly to be derived from the MPLL. Secondly,
> > the SDHCI clock control divider was not calculated correctly. This series
> > addresses these problems.
>
> Do either of these affect the AST2500? It looks like maybe the sdhci
> one would affect both?
Yes, the SDHCI patch is a fix for the 2400, 2500 and 2600.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-07-10 13:33 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-09 19:41 [PATCH linux dev-5.7 v2 0/2] clk: Aspeed: Fix eMMC clock speeds Eddie James
2020-07-09 19:41 ` [PATCH linux dev-5.7 v2 1/2] clk: AST2600: Add mux for EMMC clock Eddie James
2020-07-09 19:41 ` [PATCH linux dev-5.7 v2 2/2] mmc: sdhci-of-aspeed: Fix clock divider calculation Eddie James
2020-07-10 1:14 ` Andrew Jeffery
2020-07-10 13:13 ` [PATCH linux dev-5.7 v2 0/2] clk: Aspeed: Fix eMMC clock speeds Patrick Williams
2020-07-10 13:33 ` Andrew Jeffery
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