* [RFC 00/65] target/riscv: support vector extension v0.9
@ 2020-07-10 10:48 frank.chang
2020-07-10 10:48 ` frank.chang
` (65 more replies)
0 siblings, 66 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Frank Chang
From: Frank Chang <frank.chang@sifive.com>
This patchset implements the vector extension v0.9 for RISC-V on QEMU.
This patchset is sent as RFC because RVV v0.9 is still in draft state.
However, as RVV v1.0 should be ratified soon and there shouldn't be
critical changes between RVV v1.0 and RVV v0.9. We would like to have
the community to review RVV v0.9 implementations. Once RVV v1.0 is
ratified, we will then upgrade to RVV v1.0.
You can change the cpu argument: vext_spec to v0.9 (i.e. vext_spec=v0.9)
to run with RVV v0.9 instructions.
Chih-Min Chao (2):
fpu: fix float16 nan check
fpu: add api to handle alternative sNaN propagation
Frank Chang (58):
target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
target/riscv: fix return value of do_opivx_widen()
target/riscv: fix vill bit index in vtype register
target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
target/riscv: rvv-0.9: remove MLEN calculations
target/riscv: rvv-0.9: add fractional LMUL, VTA and VMA
target/riscv: rvv-0.9: update check functions
target/riscv: rvv-0.9: configure instructions
target/riscv: rvv-0.9: stride load and store instructions
target/riscv: rvv-0.9: index load and store instructions
target/riscv: rvv-0.9: fix address index overflow bug of indexed
load/store insns
target/riscv: rvv-0.9: fault-only-first unit stride load
target/riscv: rvv-0.9: amo operations
target/riscv: rvv-0.9: load/store whole register instructions
target/riscv: rvv-0.9: update vext_max_elems() for load/store insns
target/riscv: rvv-0.9: take fractional LMUL into vector max elements
calculation
target/riscv: rvv-0.9: floating-point square-root instruction
target/riscv: rvv-0.9: floating-point classify instructions
target/riscv: rvv-0.9: mask population count instruction
target/riscv: rvv-0.9: find-first-set mask bit instruction
target/riscv: rvv-0.9: set-X-first mask bit instructions
target/riscv: rvv-0.9: iota instruction
target/riscv: rvv-0.9: element index instruction
target/riscv: rvv-0.9: integer scalar move instructions
target/riscv: rvv-0.9: floating-point scalar move instructions
target/riscv: rvv-0.9: whole register move instructions
target/riscv: rvv-0.9: integer extension instructions
target/riscv: rvv-0.9: single-width averaging add and subtract
instructions
target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow
target/riscv: rvv-0.9: narrowing integer right shift instructions
target/riscv: rvv-0.9: widening integer multiply-add instructions
target/riscv: rvv-0.9: quad-widening integer multiply-add instructions
target/riscv: rvv-0.9: integer merge and move instructions
target/riscv: rvv-0.9: single-width saturating add and subtract
instructions
target/riscv: rvv-0.9: integer comparison instructions
target/riscv: rvv-0.9: floating-point compare instructions
target/riscv: rvv-0.9: single-width integer reduction instructions
target/riscv: rvv-0.9: widening integer reduction instructions
target/riscv: rvv-0.9: mask-register logical instructions
target/riscv: rvv-0.9: register gather instructions
target/riscv: rvv-0.9: slide instructions
target/riscv: rvv-0.9: floating-point slide instructions
target/riscv: rvv-0.9: narrowing fixed-point clip instructions
target/riscv: rvv-0.9: floating-point move instructions
target/riscv: rvv-0.9: floating-point/integer type-convert
instructions
target/riscv: rvv-0.9: single-width floating-point reduction
target/riscv: rvv-0.9: widening floating-point reduction instructions
target/riscv: rvv-0.9: single-width scaling shift instructions
target/riscv: rvv-0.9: remove widening saturating scaled multiply-add
target/riscv: rvv-0.9: remove vmford.vv and vmford.vf
target/riscv: rvv-0.9: remove integer extract instruction
target/riscv: rvv-0.9: floating-point min/max instructions
target/riscv: rvv-0.9: widening floating-point/integer type-convert
target/riscv: rvv-0.9: narrowing floating-point/integer type-convert
softfloat: add fp16 and uint8/int8 interconvert functions
target/riscv: use softfloat lib float16 comparison functions
target/riscv: bump to RVV 0.9
Kito Cheng (1):
fpu: implement full set compare for fp16
LIU Zhiwei (4):
target/riscv: rvv-0.9: add vcsr register
target/riscv: rvv-0.9: add vector context status
target/riscv: rvv-0.9: update mstatus_vs by tb_flags
target/riscv: rvv-0.9: add vlenb register
fpu/softfloat-specialize.inc.c | 4 +-
fpu/softfloat.c | 342 +++-
include/fpu/softfloat.h | 22 +
target/riscv/cpu.c | 9 +-
target/riscv/cpu.h | 68 +-
target/riscv/cpu_bits.h | 9 +
target/riscv/cpu_helper.c | 13 +
target/riscv/csr.c | 53 +-
target/riscv/helper.h | 507 +++--
target/riscv/insn32-64.decode | 18 +-
target/riscv/insn32.decode | 282 +--
target/riscv/insn_trans/trans_rvv.inc.c | 2468 ++++++++++++++---------
target/riscv/internals.h | 18 +-
target/riscv/translate.c | 43 +-
target/riscv/vector_helper.c | 2349 +++++++++++----------
15 files changed, 3833 insertions(+), 2372 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 211+ messages in thread
* [RFC 01/65] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
gvec should provide vecop_list to avoid:
"tcg_tcg_assert_listed_vecop: code should not be reached bug" assertion.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index dc333e6a91..433cdacbe1 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -958,22 +958,27 @@ static void gen_rsub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
static void tcg_gen_gvec_rsubs(unsigned vece, uint32_t dofs, uint32_t aofs,
TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
{
+ static const TCGOpcode vecop_list[] = { INDEX_op_sub_vec, 0 };
static const GVecGen2s rsub_op[4] = {
{ .fni8 = gen_vec_rsub8_i64,
.fniv = gen_rsub_vec,
.fno = gen_helper_vec_rsubs8,
+ .opt_opc = vecop_list,
.vece = MO_8 },
{ .fni8 = gen_vec_rsub16_i64,
.fniv = gen_rsub_vec,
.fno = gen_helper_vec_rsubs16,
+ .opt_opc = vecop_list,
.vece = MO_16 },
{ .fni4 = gen_rsub_i32,
.fniv = gen_rsub_vec,
.fno = gen_helper_vec_rsubs32,
+ .opt_opc = vecop_list,
.vece = MO_32 },
{ .fni8 = gen_rsub_i64,
.fniv = gen_rsub_vec,
.fno = gen_helper_vec_rsubs64,
+ .opt_opc = vecop_list,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
.vece = MO_64 },
};
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 01/65] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
gvec should provide vecop_list to avoid:
"tcg_tcg_assert_listed_vecop: code should not be reached bug" assertion.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index dc333e6a91..433cdacbe1 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -958,22 +958,27 @@ static void gen_rsub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
static void tcg_gen_gvec_rsubs(unsigned vece, uint32_t dofs, uint32_t aofs,
TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
{
+ static const TCGOpcode vecop_list[] = { INDEX_op_sub_vec, 0 };
static const GVecGen2s rsub_op[4] = {
{ .fni8 = gen_vec_rsub8_i64,
.fniv = gen_rsub_vec,
.fno = gen_helper_vec_rsubs8,
+ .opt_opc = vecop_list,
.vece = MO_8 },
{ .fni8 = gen_vec_rsub16_i64,
.fniv = gen_rsub_vec,
.fno = gen_helper_vec_rsubs16,
+ .opt_opc = vecop_list,
.vece = MO_16 },
{ .fni4 = gen_rsub_i32,
.fniv = gen_rsub_vec,
.fno = gen_helper_vec_rsubs32,
+ .opt_opc = vecop_list,
.vece = MO_32 },
{ .fni8 = gen_rsub_i64,
.fniv = gen_rsub_vec,
.fno = gen_helper_vec_rsubs64,
+ .opt_opc = vecop_list,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
.vece = MO_64 },
};
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 02/65] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 433cdacbe1..7cd08f0868 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -937,7 +937,7 @@ static void gen_vec_rsub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
static void gen_vec_rsub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
- tcg_gen_vec_sub8_i64(d, b, a);
+ tcg_gen_vec_sub16_i64(d, b, a);
}
static void gen_rsub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 02/65] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 433cdacbe1..7cd08f0868 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -937,7 +937,7 @@ static void gen_vec_rsub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
static void gen_vec_rsub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
- tcg_gen_vec_sub8_i64(d, b, a);
+ tcg_gen_vec_sub16_i64(d, b, a);
}
static void gen_rsub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 03/65] target/riscv: fix return value of do_opivx_widen()
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
do_opivx_widen() should return false if check function returns false.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 7cd08f0868..c0b7375927 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1151,7 +1151,7 @@ static bool do_opivx_widen(DisasContext *s, arg_rmrr *a,
if (opivx_widen_check(s, a)) {
return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
}
- return true;
+ return false;
}
#define GEN_OPIVX_WIDEN_TRANS(NAME) \
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 03/65] target/riscv: fix return value of do_opivx_widen()
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
do_opivx_widen() should return false if check function returns false.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 7cd08f0868..c0b7375927 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1151,7 +1151,7 @@ static bool do_opivx_widen(DisasContext *s, arg_rmrr *a,
if (opivx_widen_check(s, a)) {
return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
}
- return true;
+ return false;
}
#define GEN_OPIVX_WIDEN_TRANS(NAME) \
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 04/65] target/riscv: fix vill bit index in vtype register
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
vill bit is at vtype[XLEN-1].
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index eef20ca6e5..a804a5d0ba 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -98,7 +98,7 @@ FIELD(VTYPE, VLMUL, 0, 2)
FIELD(VTYPE, VSEW, 2, 3)
FIELD(VTYPE, VEDIV, 5, 2)
FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
-FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 2, 1)
+FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
target_ulong gpr[32];
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 04/65] target/riscv: fix vill bit index in vtype register
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
vill bit is at vtype[XLEN-1].
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index eef20ca6e5..a804a5d0ba 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -98,7 +98,7 @@ FIELD(VTYPE, VLMUL, 0, 2)
FIELD(VTYPE, VSEW, 2, 3)
FIELD(VTYPE, VEDIV, 5, 2)
FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
-FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 2, 1)
+FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
target_ulong gpr[32];
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
vsll.vi, vsrl.vi, vsra.vi cannot use shli gvec as it requires the
shift immediate value to be within the range: [0.. SEW bits].
Otherwise, it will hit the assertion:
tcg_debug_assert(shift >= 0 && shift < (8 << vece));
However, RVV spec does not have such constraint, therefore we have to
use helper functions instead.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index c0b7375927..70d31a5525 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1427,9 +1427,9 @@ GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls)
GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs)
GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars)
-GEN_OPIVI_GVEC_TRANS(vsll_vi, 1, vsll_vx, shli)
-GEN_OPIVI_GVEC_TRANS(vsrl_vi, 1, vsrl_vx, shri)
-GEN_OPIVI_GVEC_TRANS(vsra_vi, 1, vsra_vx, sari)
+GEN_OPIVI_TRANS(vsll_vi, 1, vsll_vx, opivx_check)
+GEN_OPIVI_TRANS(vsrl_vi, 1, vsrl_vx, opivx_check)
+GEN_OPIVI_TRANS(vsra_vi, 1, vsra_vx, opivx_check)
/* Vector Narrowing Integer Right Shift Instructions */
static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
vsll.vi, vsrl.vi, vsra.vi cannot use shli gvec as it requires the
shift immediate value to be within the range: [0.. SEW bits].
Otherwise, it will hit the assertion:
tcg_debug_assert(shift >= 0 && shift < (8 << vece));
However, RVV spec does not have such constraint, therefore we have to
use helper functions instead.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index c0b7375927..70d31a5525 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1427,9 +1427,9 @@ GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls)
GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs)
GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars)
-GEN_OPIVI_GVEC_TRANS(vsll_vi, 1, vsll_vx, shli)
-GEN_OPIVI_GVEC_TRANS(vsrl_vi, 1, vsrl_vx, shri)
-GEN_OPIVI_GVEC_TRANS(vsra_vi, 1, vsra_vx, sari)
+GEN_OPIVI_TRANS(vsll_vi, 1, vsll_vx, opivx_check)
+GEN_OPIVI_TRANS(vsrl_vi, 1, vsrl_vx, opivx_check)
+GEN_OPIVI_TRANS(vsra_vi, 1, vsra_vx, opivx_check)
/* Vector Narrowing Integer Right Shift Instructions */
static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 06/65] target/riscv: rvv-0.9: add vcsr register
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu_bits.h | 7 +++++++
target/riscv/csr.c | 21 +++++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8117e8b5a7..202440e5eb 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -60,9 +60,16 @@
#define CSR_VSTART 0x008
#define CSR_VXSAT 0x009
#define CSR_VXRM 0x00a
+#define CSR_VCSR 0x00f
#define CSR_VL 0xc20
#define CSR_VTYPE 0xc21
+/* VCSR fields */
+#define VCSR_VXSAT_SHIFT 0
+#define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT)
+#define VCSR_VXRM_SHIFT 1
+#define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT)
+
/* User Timers and Counters */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ac01c835e1..34ce509e64 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -238,6 +238,26 @@ static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
+static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT);
+ return 0;
+}
+
+static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
+{
+#if !defined(CONFIG_USER_ONLY)
+ if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+ return -1;
+ }
+ env->mstatus |= MSTATUS_VS;
+#endif
+
+ env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
+ env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT;
+ return 0;
+}
+
/* User Timers and Counters */
static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
{
@@ -1255,6 +1275,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_VSTART] = { vs, read_vstart, write_vstart },
[CSR_VXSAT] = { vs, read_vxsat, write_vxsat },
[CSR_VXRM] = { vs, read_vxrm, write_vxrm },
+ [CSR_VCSR] = { vs, read_vcsr, write_vcsr },
[CSR_VL] = { vs, read_vl },
[CSR_VTYPE] = { vs, read_vtype },
/* User Timers and Counters */
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 06/65] target/riscv: rvv-0.9: add vcsr register
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: LIU Zhiwei, Frank Chang, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu_bits.h | 7 +++++++
target/riscv/csr.c | 21 +++++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8117e8b5a7..202440e5eb 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -60,9 +60,16 @@
#define CSR_VSTART 0x008
#define CSR_VXSAT 0x009
#define CSR_VXRM 0x00a
+#define CSR_VCSR 0x00f
#define CSR_VL 0xc20
#define CSR_VTYPE 0xc21
+/* VCSR fields */
+#define VCSR_VXSAT_SHIFT 0
+#define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT)
+#define VCSR_VXRM_SHIFT 1
+#define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT)
+
/* User Timers and Counters */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ac01c835e1..34ce509e64 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -238,6 +238,26 @@ static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
+static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT);
+ return 0;
+}
+
+static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
+{
+#if !defined(CONFIG_USER_ONLY)
+ if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+ return -1;
+ }
+ env->mstatus |= MSTATUS_VS;
+#endif
+
+ env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
+ env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT;
+ return 0;
+}
+
/* User Timers and Counters */
static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
{
@@ -1255,6 +1275,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_VSTART] = { vs, read_vstart, write_vstart },
[CSR_VXSAT] = { vs, read_vxsat, write_vxsat },
[CSR_VXRM] = { vs, read_vxrm, write_vxrm },
+ [CSR_VCSR] = { vs, read_vcsr, write_vcsr },
[CSR_VL] = { vs, read_vl },
[CSR_VTYPE] = { vs, read_vtype },
/* User Timers and Counters */
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 07/65] target/riscv: rvv-0.9: add vector context status
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 4 ++
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 13 ++++++
target/riscv/csr.c | 25 ++++++++++-
target/riscv/insn_trans/trans_rvv.inc.c | 57 +++++++++++++++++++++----
target/riscv/translate.c | 32 ++++++++++++++
6 files changed, 123 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a804a5d0ba..0cf3fe9456 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -317,6 +317,7 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
bool riscv_cpu_fp_enabled(CPURISCVState *env);
+bool riscv_cpu_vector_enabled(CPURISCVState *env);
bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
@@ -415,6 +416,9 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
if (riscv_cpu_fp_enabled(env)) {
flags |= env->mstatus & MSTATUS_FS;
}
+ if (riscv_cpu_vector_enabled(env)) {
+ flags |= env->mstatus & MSTATUS_VS;
+ }
#endif
*pflags = flags;
}
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 202440e5eb..79ae0accbc 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -376,6 +376,7 @@
#define MSTATUS_SPP 0x00000100
#define MSTATUS_MPP 0x00001800
#define MSTATUS_FS 0x00006000
+#define MSTATUS_VS 0x00000600
#define MSTATUS_XS 0x00018000
#define MSTATUS_MPRV 0x00020000
#define MSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 75d2ae3434..8e119fd8b5 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -108,6 +108,19 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
return false;
}
+/* Return true is vector support is currently enabled */
+bool riscv_cpu_vector_enabled(CPURISCVState *env)
+{
+ if (env->mstatus & MSTATUS_VS) {
+ if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)) {
+ return false;
+ }
+ return true;
+ }
+
+ return false;
+}
+
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
{
target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 34ce509e64..77d371f385 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -180,6 +180,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
return -1;
}
env->mstatus |= MSTATUS_FS;
+ env->mstatus |= MSTATUS_VS;
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
if (vs(env, csrno) >= 0) {
@@ -210,6 +211,13 @@ static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val)
static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val)
{
+#if !defined(CONFIG_USER_ONLY)
+ if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+ return -1;
+ }
+ env->mstatus |= MSTATUS_VS;
+#endif
+
env->vxrm = val;
return 0;
}
@@ -222,6 +230,13 @@ static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val)
static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val)
{
+#if !defined(CONFIG_USER_ONLY)
+ if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+ return -1;
+ }
+ env->mstatus |= MSTATUS_VS;
+#endif
+
env->vxsat = val;
return 0;
}
@@ -234,6 +249,13 @@ static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val)
static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
{
+#if !defined(CONFIG_USER_ONLY)
+ if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+ return -1;
+ }
+ env->mstatus |= MSTATUS_VS;
+#endif
+
env->vstart = val;
return 0;
}
@@ -420,7 +442,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
- MSTATUS_TW;
+ MSTATUS_TW | MSTATUS_VS;
#if defined(TARGET_RISCV64)
/*
* RV32: MPV and MTL are not in mstatus. The current plan is to
@@ -432,6 +454,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
mstatus = (mstatus & ~mask) | (val & mask);
dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
+ ((mstatus & MSTATUS_VS) == MSTATUS_VS) |
((mstatus & MSTATUS_XS) == MSTATUS_XS);
mstatus = set_field(mstatus, MSTATUS_SD, dirty);
env->mstatus = mstatus;
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 70d31a5525..3ae40ad0c1 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -23,6 +23,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
{
TCGv s1, s2, dst;
+ REQUIRE_RVV;
if (!has_ext(ctx, RVV)) {
return false;
}
@@ -48,6 +49,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
tcg_temp_free(s1);
tcg_temp_free(s2);
tcg_temp_free(dst);
+ mark_vs_dirty(s);
return true;
}
@@ -55,6 +57,7 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
{
TCGv s1, s2, dst;
+ REQUIRE_RVV;
if (!has_ext(ctx, RVV)) {
return false;
}
@@ -78,6 +81,7 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
tcg_temp_free(s1);
tcg_temp_free(s2);
tcg_temp_free(dst);
+ mark_vs_dirty(s);
return true;
}
@@ -235,6 +239,7 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
{ NULL, NULL,
gen_helper_vlwu_v_w, gen_helper_vlwu_v_d } }
};
+ bool ret;
fn = fns[a->vm][seq][s->sew];
if (fn == NULL) {
@@ -245,7 +250,9 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
- return ldst_us_trans(a->rd, a->rs1, data, fn, s);
+ ret = ldst_us_trans(a->rd, a->rs1, data, fn, s);
+ mark_vs_dirty(s);
+ return ret;
}
static bool ld_us_check(DisasContext *s, arg_r2nfvm* a)
@@ -372,6 +379,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
{ NULL, NULL,
gen_helper_vlswu_v_w, gen_helper_vlswu_v_d },
};
+ bool ret;
fn = fns[seq][s->sew];
if (fn == NULL) {
@@ -382,7 +390,9 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
- return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
+ ret = ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
+ mark_vs_dirty(s);
+ return ret;
}
static bool ld_stride_check(DisasContext *s, arg_rnfvm* a)
@@ -500,6 +510,7 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
{ NULL, NULL,
gen_helper_vlxwu_v_w, gen_helper_vlxwu_v_d },
};
+ bool ret;
fn = fns[seq][s->sew];
if (fn == NULL) {
@@ -510,7 +521,9 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
- return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
+ ret = ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
+ mark_vs_dirty(s);
+ return ret;
}
static bool ld_index_check(DisasContext *s, arg_rnfvm* a)
@@ -622,6 +635,7 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
{ NULL, NULL,
gen_helper_vlwuff_v_w, gen_helper_vlwuff_v_d }
};
+ bool ret;
fn = fns[seq][s->sew];
if (fn == NULL) {
@@ -632,7 +646,9 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
- return ldff_trans(a->rd, a->rs1, data, fn, s);
+ ret = ldff_trans(a->rd, a->rs1, data, fn, s);
+ mark_vs_dirty(s);
+ return ret;
}
GEN_VEXT_TRANS(vlbff_v, 0, r2nfvm, ldff_op, ld_us_check)
@@ -719,6 +735,7 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
gen_helper_vamomaxud_v_d
};
#endif
+ bool ret;
if (tb_cflags(s->base.tb) & CF_PARALLEL) {
gen_helper_exit_atomic(cpu_env);
@@ -741,7 +758,9 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, WD, a->wd);
- return amo_trans(a->rd, a->rs1, a->rs2, data, fn, s);
+ ret = amo_trans(a->rd, a->rs1, a->rs2, data, fn, s);
+ mark_vs_dirty(s);
+ return ret;
}
/*
* There are two rules check here.
@@ -823,6 +842,7 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
cpu_env, 0, s->vlen / 8, data, fn);
}
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
@@ -896,6 +916,7 @@ static inline bool
do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
gen_helper_opivx *fn)
{
+ bool ret;
if (!opivx_check(s, a)) {
return false;
}
@@ -911,9 +932,12 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
tcg_temp_free_i64(src1);
tcg_temp_free(tmp);
+ mark_vs_dirty(s);
return true;
}
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
+ ret = opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
+ mark_vs_dirty(s);
+ return ret;
}
/* OPIVX with GVEC IR */
@@ -1035,6 +1059,7 @@ static inline bool
do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn,
gen_helper_opivx *fn, int zx)
{
+ bool ret;
if (!opivx_check(s, a)) {
return false;
}
@@ -1047,10 +1072,12 @@ do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn,
gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
sextract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s));
}
+ ret = true;
} else {
- return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx);
+ ret = opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx);
}
- return true;
+ mark_vs_dirty(s);
+ return ret;
}
/* OPIVI with GVEC IR */
@@ -1111,6 +1138,7 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
vreg_ofs(s, a->rs2),
cpu_env, 0, s->vlen / 8,
data, fn);
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
@@ -1198,6 +1226,7 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
vreg_ofs(s, a->rs1),
vreg_ofs(s, a->rs2),
cpu_env, 0, s->vlen / 8, data, fn);
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
@@ -1276,6 +1305,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -1407,6 +1437,7 @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
tcg_temp_free_i32(src1);
tcg_temp_free(tmp);
+ mark_vs_dirty(s);
return true;
}
return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
@@ -1465,6 +1496,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -1830,6 +1862,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -1942,6 +1975,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -2016,6 +2050,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -2130,6 +2165,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -2270,6 +2306,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -2318,6 +2355,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -2824,6 +2862,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), dest);
tcg_temp_free_i64(dest);
+ mark_vs_dirty(s);
} else {
static gen_helper_opivx * const fns[4] = {
gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
@@ -2850,6 +2889,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
endian_ofs(s, a->rs2, a->rs1),
MAXSZ(s), MAXSZ(s));
}
+ mark_vs_dirty(s);
} else {
static gen_helper_opivx * const fns[4] = {
gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
@@ -2886,6 +2926,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9632e79cf3..a806e33301 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -47,6 +47,7 @@ typedef struct DisasContext {
bool virt_enabled;
uint32_t opcode;
uint32_t mstatus_fs;
+ uint32_t mstatus_vs;
uint32_t misa;
uint32_t mem_idx;
/* Remember the rounding mode encoded in the previous fp instruction,
@@ -416,6 +417,37 @@ static void mark_fs_dirty(DisasContext *ctx)
static inline void mark_fs_dirty(DisasContext *ctx) { }
#endif
+#ifndef CONFIG_USER_ONLY
+/* The states of mstatus_vs are:
+ * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
+ * We will have already diagnosed disabled state,
+ * and need to turn initial/clean into dirty.
+ */
+static void mark_vs_dirty(DisasContext *ctx)
+{
+ TCGv tmp;
+ if (ctx->mstatus_vs == MSTATUS_VS) {
+ return;
+ }
+ /* Remember the state change for the rest of the TB. */
+ ctx->mstatus_vs = MSTATUS_VS;
+
+ tmp = tcg_temp_new();
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS | MSTATUS_SD);
+ tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+
+ if (ctx->virt_enabled) {
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS | MSTATUS_SD);
+ tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+ }
+ tcg_temp_free(tmp);
+}
+#else
+static inline void mark_vs_dirty(DisasContext *ctx) { }
+#endif
+
#if !defined(TARGET_RISCV64)
static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
int rs1, target_long imm)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 07/65] target/riscv: rvv-0.9: add vector context status
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: LIU Zhiwei, Frank Chang, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann, Richard Henderson
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 4 ++
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 13 ++++++
target/riscv/csr.c | 25 ++++++++++-
target/riscv/insn_trans/trans_rvv.inc.c | 57 +++++++++++++++++++++----
target/riscv/translate.c | 32 ++++++++++++++
6 files changed, 123 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a804a5d0ba..0cf3fe9456 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -317,6 +317,7 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
bool riscv_cpu_fp_enabled(CPURISCVState *env);
+bool riscv_cpu_vector_enabled(CPURISCVState *env);
bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
@@ -415,6 +416,9 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
if (riscv_cpu_fp_enabled(env)) {
flags |= env->mstatus & MSTATUS_FS;
}
+ if (riscv_cpu_vector_enabled(env)) {
+ flags |= env->mstatus & MSTATUS_VS;
+ }
#endif
*pflags = flags;
}
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 202440e5eb..79ae0accbc 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -376,6 +376,7 @@
#define MSTATUS_SPP 0x00000100
#define MSTATUS_MPP 0x00001800
#define MSTATUS_FS 0x00006000
+#define MSTATUS_VS 0x00000600
#define MSTATUS_XS 0x00018000
#define MSTATUS_MPRV 0x00020000
#define MSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 75d2ae3434..8e119fd8b5 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -108,6 +108,19 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
return false;
}
+/* Return true is vector support is currently enabled */
+bool riscv_cpu_vector_enabled(CPURISCVState *env)
+{
+ if (env->mstatus & MSTATUS_VS) {
+ if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)) {
+ return false;
+ }
+ return true;
+ }
+
+ return false;
+}
+
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
{
target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 34ce509e64..77d371f385 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -180,6 +180,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
return -1;
}
env->mstatus |= MSTATUS_FS;
+ env->mstatus |= MSTATUS_VS;
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
if (vs(env, csrno) >= 0) {
@@ -210,6 +211,13 @@ static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val)
static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val)
{
+#if !defined(CONFIG_USER_ONLY)
+ if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+ return -1;
+ }
+ env->mstatus |= MSTATUS_VS;
+#endif
+
env->vxrm = val;
return 0;
}
@@ -222,6 +230,13 @@ static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val)
static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val)
{
+#if !defined(CONFIG_USER_ONLY)
+ if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+ return -1;
+ }
+ env->mstatus |= MSTATUS_VS;
+#endif
+
env->vxsat = val;
return 0;
}
@@ -234,6 +249,13 @@ static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val)
static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
{
+#if !defined(CONFIG_USER_ONLY)
+ if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+ return -1;
+ }
+ env->mstatus |= MSTATUS_VS;
+#endif
+
env->vstart = val;
return 0;
}
@@ -420,7 +442,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
- MSTATUS_TW;
+ MSTATUS_TW | MSTATUS_VS;
#if defined(TARGET_RISCV64)
/*
* RV32: MPV and MTL are not in mstatus. The current plan is to
@@ -432,6 +454,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
mstatus = (mstatus & ~mask) | (val & mask);
dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
+ ((mstatus & MSTATUS_VS) == MSTATUS_VS) |
((mstatus & MSTATUS_XS) == MSTATUS_XS);
mstatus = set_field(mstatus, MSTATUS_SD, dirty);
env->mstatus = mstatus;
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 70d31a5525..3ae40ad0c1 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -23,6 +23,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
{
TCGv s1, s2, dst;
+ REQUIRE_RVV;
if (!has_ext(ctx, RVV)) {
return false;
}
@@ -48,6 +49,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
tcg_temp_free(s1);
tcg_temp_free(s2);
tcg_temp_free(dst);
+ mark_vs_dirty(s);
return true;
}
@@ -55,6 +57,7 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
{
TCGv s1, s2, dst;
+ REQUIRE_RVV;
if (!has_ext(ctx, RVV)) {
return false;
}
@@ -78,6 +81,7 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
tcg_temp_free(s1);
tcg_temp_free(s2);
tcg_temp_free(dst);
+ mark_vs_dirty(s);
return true;
}
@@ -235,6 +239,7 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
{ NULL, NULL,
gen_helper_vlwu_v_w, gen_helper_vlwu_v_d } }
};
+ bool ret;
fn = fns[a->vm][seq][s->sew];
if (fn == NULL) {
@@ -245,7 +250,9 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
- return ldst_us_trans(a->rd, a->rs1, data, fn, s);
+ ret = ldst_us_trans(a->rd, a->rs1, data, fn, s);
+ mark_vs_dirty(s);
+ return ret;
}
static bool ld_us_check(DisasContext *s, arg_r2nfvm* a)
@@ -372,6 +379,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
{ NULL, NULL,
gen_helper_vlswu_v_w, gen_helper_vlswu_v_d },
};
+ bool ret;
fn = fns[seq][s->sew];
if (fn == NULL) {
@@ -382,7 +390,9 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
- return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
+ ret = ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
+ mark_vs_dirty(s);
+ return ret;
}
static bool ld_stride_check(DisasContext *s, arg_rnfvm* a)
@@ -500,6 +510,7 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
{ NULL, NULL,
gen_helper_vlxwu_v_w, gen_helper_vlxwu_v_d },
};
+ bool ret;
fn = fns[seq][s->sew];
if (fn == NULL) {
@@ -510,7 +521,9 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
- return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
+ ret = ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
+ mark_vs_dirty(s);
+ return ret;
}
static bool ld_index_check(DisasContext *s, arg_rnfvm* a)
@@ -622,6 +635,7 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
{ NULL, NULL,
gen_helper_vlwuff_v_w, gen_helper_vlwuff_v_d }
};
+ bool ret;
fn = fns[seq][s->sew];
if (fn == NULL) {
@@ -632,7 +646,9 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
- return ldff_trans(a->rd, a->rs1, data, fn, s);
+ ret = ldff_trans(a->rd, a->rs1, data, fn, s);
+ mark_vs_dirty(s);
+ return ret;
}
GEN_VEXT_TRANS(vlbff_v, 0, r2nfvm, ldff_op, ld_us_check)
@@ -719,6 +735,7 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
gen_helper_vamomaxud_v_d
};
#endif
+ bool ret;
if (tb_cflags(s->base.tb) & CF_PARALLEL) {
gen_helper_exit_atomic(cpu_env);
@@ -741,7 +758,9 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, WD, a->wd);
- return amo_trans(a->rd, a->rs1, a->rs2, data, fn, s);
+ ret = amo_trans(a->rd, a->rs1, a->rs2, data, fn, s);
+ mark_vs_dirty(s);
+ return ret;
}
/*
* There are two rules check here.
@@ -823,6 +842,7 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
cpu_env, 0, s->vlen / 8, data, fn);
}
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
@@ -896,6 +916,7 @@ static inline bool
do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
gen_helper_opivx *fn)
{
+ bool ret;
if (!opivx_check(s, a)) {
return false;
}
@@ -911,9 +932,12 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
tcg_temp_free_i64(src1);
tcg_temp_free(tmp);
+ mark_vs_dirty(s);
return true;
}
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
+ ret = opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
+ mark_vs_dirty(s);
+ return ret;
}
/* OPIVX with GVEC IR */
@@ -1035,6 +1059,7 @@ static inline bool
do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn,
gen_helper_opivx *fn, int zx)
{
+ bool ret;
if (!opivx_check(s, a)) {
return false;
}
@@ -1047,10 +1072,12 @@ do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn,
gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
sextract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s));
}
+ ret = true;
} else {
- return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx);
+ ret = opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx);
}
- return true;
+ mark_vs_dirty(s);
+ return ret;
}
/* OPIVI with GVEC IR */
@@ -1111,6 +1138,7 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
vreg_ofs(s, a->rs2),
cpu_env, 0, s->vlen / 8,
data, fn);
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
@@ -1198,6 +1226,7 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
vreg_ofs(s, a->rs1),
vreg_ofs(s, a->rs2),
cpu_env, 0, s->vlen / 8, data, fn);
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
@@ -1276,6 +1305,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -1407,6 +1437,7 @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
tcg_temp_free_i32(src1);
tcg_temp_free(tmp);
+ mark_vs_dirty(s);
return true;
}
return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
@@ -1465,6 +1496,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -1830,6 +1862,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -1942,6 +1975,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -2016,6 +2050,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -2130,6 +2165,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -2270,6 +2306,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -2318,6 +2355,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -2824,6 +2862,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), dest);
tcg_temp_free_i64(dest);
+ mark_vs_dirty(s);
} else {
static gen_helper_opivx * const fns[4] = {
gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
@@ -2850,6 +2889,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
endian_ofs(s, a->rs2, a->rs1),
MAXSZ(s), MAXSZ(s));
}
+ mark_vs_dirty(s);
} else {
static gen_helper_opivx * const fns[4] = {
gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
@@ -2886,6 +2926,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9632e79cf3..a806e33301 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -47,6 +47,7 @@ typedef struct DisasContext {
bool virt_enabled;
uint32_t opcode;
uint32_t mstatus_fs;
+ uint32_t mstatus_vs;
uint32_t misa;
uint32_t mem_idx;
/* Remember the rounding mode encoded in the previous fp instruction,
@@ -416,6 +417,37 @@ static void mark_fs_dirty(DisasContext *ctx)
static inline void mark_fs_dirty(DisasContext *ctx) { }
#endif
+#ifndef CONFIG_USER_ONLY
+/* The states of mstatus_vs are:
+ * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
+ * We will have already diagnosed disabled state,
+ * and need to turn initial/clean into dirty.
+ */
+static void mark_vs_dirty(DisasContext *ctx)
+{
+ TCGv tmp;
+ if (ctx->mstatus_vs == MSTATUS_VS) {
+ return;
+ }
+ /* Remember the state change for the rest of the TB. */
+ ctx->mstatus_vs = MSTATUS_VS;
+
+ tmp = tcg_temp_new();
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS | MSTATUS_SD);
+ tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+
+ if (ctx->virt_enabled) {
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS | MSTATUS_SD);
+ tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+ }
+ tcg_temp_free(tmp);
+}
+#else
+static inline void mark_vs_dirty(DisasContext *ctx) { }
+#endif
+
#if !defined(TARGET_RISCV64)
static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
int rs1, target_long imm)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 08/65] target/riscv: rvv-0.9: update mstatus_vs by tb_flags
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 2 ++
target/riscv/translate.c | 1 +
2 files changed, 3 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0cf3fe9456..c02690ed0d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -361,6 +361,7 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
#define TB_FLAGS_MMU_MASK 3
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
+#define TB_FLAGS_MSTATUS_VS MSTATUS_VS
typedef CPURISCVState CPUArchState;
typedef RISCVCPU ArchCPU;
@@ -411,6 +412,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
#ifdef CONFIG_USER_ONLY
flags |= TB_FLAGS_MSTATUS_FS;
+ flags |= TB_FLAGS_MSTATUS_VS;
#else
flags |= cpu_mmu_index(env, 0);
if (riscv_cpu_fp_enabled(env)) {
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a806e33301..02b4204584 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -796,6 +796,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->pc_succ_insn = ctx->base.pc_first;
ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK;
ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
+ ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS;
ctx->priv_ver = env->priv_ver;
#if !defined(CONFIG_USER_ONLY)
if (riscv_has_ext(env, RVH)) {
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 08/65] target/riscv: rvv-0.9: update mstatus_vs by tb_flags
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: LIU Zhiwei, Frank Chang, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 2 ++
target/riscv/translate.c | 1 +
2 files changed, 3 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0cf3fe9456..c02690ed0d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -361,6 +361,7 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
#define TB_FLAGS_MMU_MASK 3
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
+#define TB_FLAGS_MSTATUS_VS MSTATUS_VS
typedef CPURISCVState CPUArchState;
typedef RISCVCPU ArchCPU;
@@ -411,6 +412,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
#ifdef CONFIG_USER_ONLY
flags |= TB_FLAGS_MSTATUS_FS;
+ flags |= TB_FLAGS_MSTATUS_VS;
#else
flags |= cpu_mmu_index(env, 0);
if (riscv_cpu_fp_enabled(env)) {
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a806e33301..02b4204584 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -796,6 +796,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->pc_succ_insn = ctx->base.pc_first;
ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK;
ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
+ ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS;
ctx->priv_ver = env->priv_ver;
#if !defined(CONFIG_USER_ONLY)
if (riscv_has_ext(env, RVH)) {
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 09/65] target/riscv: rvv-0.9: add vlenb register
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann, LIU Zhiwei,
Alistair Francis, Greentime Hu, Palmer Dabbelt
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 7 +++++++
4 files changed, 10 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 228b9bdb5d..871c2ddfa1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -317,6 +317,7 @@ static void riscv_cpu_reset(DeviceState *dev)
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
env->mcause = 0;
env->pc = env->resetvec;
+ env->vlenb = cpu->cfg.vlen >> 3;
#endif
cs->exception_index = EXCP_NONE;
env->load_res = -1;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c02690ed0d..81c85bf4c2 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -111,6 +111,7 @@ struct CPURISCVState {
target_ulong vl;
target_ulong vstart;
target_ulong vtype;
+ target_ulong vlenb;
target_ulong pc;
target_ulong load_res;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 79ae0accbc..62789e3720 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -63,6 +63,7 @@
#define CSR_VCSR 0x00f
#define CSR_VL 0xc20
#define CSR_VTYPE 0xc21
+#define CSR_VLENB 0xc22
/* VCSR fields */
#define VCSR_VXSAT_SHIFT 0
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 77d371f385..6b05c631f4 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -197,6 +197,12 @@ static int read_vtype(CPURISCVState *env, int csrno, target_ulong *val)
return 0;
}
+static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->vlenb;
+ return 0;
+}
+
static int read_vl(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->vl;
@@ -1301,6 +1307,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_VCSR] = { vs, read_vcsr, write_vcsr },
[CSR_VL] = { vs, read_vl },
[CSR_VTYPE] = { vs, read_vtype },
+ [CSR_VLENB] = { vs, read_vlenb },
/* User Timers and Counters */
[CSR_CYCLE] = { ctr, read_instret },
[CSR_INSTRET] = { ctr, read_instret },
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 09/65] target/riscv: rvv-0.9: add vlenb register
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: LIU Zhiwei, Greentime Hu, Frank Chang, Palmer Dabbelt,
Alistair Francis, Sagar Karandikar, Bastian Koppelmann
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 7 +++++++
4 files changed, 10 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 228b9bdb5d..871c2ddfa1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -317,6 +317,7 @@ static void riscv_cpu_reset(DeviceState *dev)
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
env->mcause = 0;
env->pc = env->resetvec;
+ env->vlenb = cpu->cfg.vlen >> 3;
#endif
cs->exception_index = EXCP_NONE;
env->load_res = -1;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c02690ed0d..81c85bf4c2 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -111,6 +111,7 @@ struct CPURISCVState {
target_ulong vl;
target_ulong vstart;
target_ulong vtype;
+ target_ulong vlenb;
target_ulong pc;
target_ulong load_res;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 79ae0accbc..62789e3720 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -63,6 +63,7 @@
#define CSR_VCSR 0x00f
#define CSR_VL 0xc20
#define CSR_VTYPE 0xc21
+#define CSR_VLENB 0xc22
/* VCSR fields */
#define VCSR_VXSAT_SHIFT 0
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 77d371f385..6b05c631f4 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -197,6 +197,12 @@ static int read_vtype(CPURISCVState *env, int csrno, target_ulong *val)
return 0;
}
+static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->vlenb;
+ return 0;
+}
+
static int read_vl(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->vl;
@@ -1301,6 +1307,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_VCSR] = { vs, read_vcsr, write_vcsr },
[CSR_VL] = { vs, read_vl },
[CSR_VTYPE] = { vs, read_vtype },
+ [CSR_VLENB] = { vs, read_vlenb },
/* User Timers and Counters */
[CSR_CYCLE] = { ctr, read_instret },
[CSR_INSTRET] = { ctr, read_instret },
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 10/65] target/riscv: rvv-0.9: remove MLEN calculations
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
As in RVV 0.9 design, MLEN is hardcoded with value 1 (Section 4.5).
Thus, remove all MLEN related calculations.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 44 +----
target/riscv/internals.h | 9 +-
target/riscv/translate.c | 2 -
target/riscv/vector_helper.c | 252 ++++++++++--------------
4 files changed, 116 insertions(+), 191 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 3ae40ad0c1..e222bd78a2 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -246,7 +246,6 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
return false;
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
@@ -301,7 +300,6 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
return false;
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
@@ -386,7 +384,6 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
return false;
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
@@ -427,15 +424,15 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
gen_helper_vsse_v_w, gen_helper_vsse_v_d }
};
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, NF, a->nf);
- fn = fns[seq][s->sew];
+ fn = fns[seq];
if (fn == NULL) {
return false;
}
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, NF, a->nf);
+
return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
@@ -517,7 +514,6 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
return false;
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
@@ -563,7 +559,6 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
return false;
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
@@ -642,7 +637,6 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
return false;
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
@@ -754,7 +748,6 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
}
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, WD, a->wd);
@@ -835,7 +828,6 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
} else {
uint32_t data = 0;
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
@@ -881,7 +873,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
src1 = tcg_temp_new();
gen_get_gpr(src1, rs1);
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
@@ -1032,7 +1023,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
} else {
src1 = tcg_const_tl(sextract64(imm, 0, 5));
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
@@ -1130,7 +1120,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
@@ -1219,7 +1208,6 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
@@ -1298,7 +1286,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
TCGLabel *over = gen_new_label(); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -1489,7 +1476,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
TCGLabel *over = gen_new_label(); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -1855,7 +1841,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_set_rm(s, 7); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -1927,7 +1912,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_d, \
}; \
gen_set_rm(s, 7); \
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -1968,7 +1952,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_set_rm(s, 7); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -2006,7 +1989,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
gen_set_rm(s, 7); \
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2043,7 +2025,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_set_rm(s, 7); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -2079,7 +2060,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
gen_set_rm(s, 7); \
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2159,7 +2139,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_set_rm(s, 7); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -2300,7 +2279,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_set_rm(s, 7); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -2349,7 +2327,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_set_rm(s, 7); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -2412,7 +2389,6 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
TCGLabel *over = gen_new_label(); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
@@ -2441,7 +2417,6 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
TCGv dst;
TCGv_i32 desc;
uint32_t data = 0;
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -2473,7 +2448,6 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
TCGv dst;
TCGv_i32 desc;
uint32_t data = 0;
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -2509,7 +2483,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
TCGLabel *over = gen_new_label(); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
@@ -2536,7 +2509,6 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
static gen_helper_gvec_3_ptr * const fns[4] = {
@@ -2562,7 +2534,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
static gen_helper_gvec_2_ptr * const fns[4] = {
@@ -2850,7 +2821,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
}
if (a->vm && s->vl_eq_vlmax) {
- int vlmax = s->vlen / s->mlen;
+ int vlmax = s->vlen;
TCGv_i64 dest = tcg_temp_new_i64();
if (a->rs1 == 0) {
@@ -2881,7 +2852,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
}
if (a->vm && s->vl_eq_vlmax) {
- if (a->rs1 >= s->vlen / s->mlen) {
+ if (a->rs1 >= s->vlen) {
tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), 0);
} else {
@@ -2921,7 +2892,6 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 37d33820ad..89fc0753bc 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -22,11 +22,10 @@
#include "hw/registerfields.h"
/* share data between vector helpers and decode code */
-FIELD(VDATA, MLEN, 0, 8)
-FIELD(VDATA, VM, 8, 1)
-FIELD(VDATA, LMUL, 9, 2)
-FIELD(VDATA, NF, 11, 4)
-FIELD(VDATA, WD, 11, 1)
+FIELD(VDATA, VM, 0, 1)
+FIELD(VDATA, LMUL, 1, 3)
+FIELD(VDATA, NF, 4, 4)
+FIELD(VDATA, WD, 4, 1)
/* float point classify helpers */
target_ulong fclass_h(uint64_t frs1);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 02b4204584..7593b41a1f 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -62,7 +62,6 @@ typedef struct DisasContext {
uint8_t lmul;
uint8_t sew;
uint16_t vlen;
- uint16_t mlen;
bool vl_eq_vlmax;
} DisasContext;
@@ -824,7 +823,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
- ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul);
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 39f44d1029..6545f91732 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -81,11 +81,6 @@ static inline uint32_t vext_nf(uint32_t desc)
return FIELD_EX32(simd_data(desc), VDATA, NF);
}
-static inline uint32_t vext_mlen(uint32_t desc)
-{
- return FIELD_EX32(simd_data(desc), VDATA, MLEN);
-}
-
static inline uint32_t vext_vm(uint32_t desc)
{
return FIELD_EX32(simd_data(desc), VDATA, VM);
@@ -98,7 +93,7 @@ static inline uint32_t vext_lmul(uint32_t desc)
static uint32_t vext_wd(uint32_t desc)
{
- return (simd_data(desc) >> 11) & 0x1;
+ return FIELD_EX32(simd_data(desc), VDATA, WD);
}
/*
@@ -188,19 +183,24 @@ static void clearq(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
vext_clear(cur, cnt, tot);
}
-static inline void vext_set_elem_mask(void *v0, int mlen, int index,
+static inline void vext_set_elem_mask(void *v0, int index,
uint8_t value)
{
- int idx = (index * mlen) / 64;
- int pos = (index * mlen) % 64;
+ int idx = index / 64;
+ int pos = index % 64;
uint64_t old = ((uint64_t *)v0)[idx];
- ((uint64_t *)v0)[idx] = deposit64(old, pos, mlen, value);
+ ((uint64_t *)v0)[idx] = deposit64(old, pos, 1, value);
}
-static inline int vext_elem_mask(void *v0, int mlen, int index)
+/*
+ * Earlier designs (pre-0.9) had a varying number of bits
+ * per mask value (MLEN). In the 0.9 design, MLEN=1.
+ * (Section 4.6)
+ */
+static inline int vext_elem_mask(void *v0, int index)
{
- int idx = (index * mlen) / 64;
- int pos = (index * mlen) % 64;
+ int idx = index / 64;
+ int pos = index % 64;
return (((uint64_t *)v0)[idx] >> pos) & 1;
}
@@ -277,12 +277,11 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
- uint32_t mlen = vext_mlen(desc);
uint32_t vlmax = vext_maxsz(desc) / esz;
/* probe every access*/
for (i = 0; i < env->vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
probe_pages(env, base + stride * i, nf * msz, ra, access_type);
@@ -290,7 +289,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
/* do real access */
for (i = 0; i < env->vl; i++) {
k = 0;
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
while (k < nf) {
@@ -506,12 +505,11 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
uint32_t i, k;
uint32_t nf = vext_nf(desc);
uint32_t vm = vext_vm(desc);
- uint32_t mlen = vext_mlen(desc);
uint32_t vlmax = vext_maxsz(desc) / esz;
/* probe every access*/
for (i = 0; i < env->vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
probe_pages(env, get_index_addr(base, i, vs2), nf * msz, ra,
@@ -520,7 +518,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
/* load bytes from guest memory */
for (i = 0; i < env->vl; i++) {
k = 0;
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
while (k < nf) {
@@ -604,7 +602,6 @@ vext_ldff(void *vd, void *v0, target_ulong base,
{
void *host;
uint32_t i, k, vl = 0;
- uint32_t mlen = vext_mlen(desc);
uint32_t nf = vext_nf(desc);
uint32_t vm = vext_vm(desc);
uint32_t vlmax = vext_maxsz(desc) / esz;
@@ -612,7 +609,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
/* probe every access*/
for (i = 0; i < env->vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
addr = base + nf * i * msz;
@@ -653,7 +650,7 @@ ProbeSuccess:
}
for (i = 0; i < env->vl; i++) {
k = 0;
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
while (k < nf) {
@@ -784,18 +781,17 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
target_long addr;
uint32_t wd = vext_wd(desc);
uint32_t vm = vext_vm(desc);
- uint32_t mlen = vext_mlen(desc);
uint32_t vlmax = vext_maxsz(desc) / esz;
for (i = 0; i < env->vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_LOAD);
probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_STORE);
}
for (i = 0; i < env->vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
addr = get_index_addr(base, i, vs2);
@@ -911,13 +907,12 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
opivv2_fn *fn, clear_fn *clearfn)
{
uint32_t vlmax = vext_maxsz(desc) / esz;
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
uint32_t i;
for (i = 0; i < vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
fn(vd, vs1, vs2, i);
@@ -976,13 +971,12 @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
opivx2_fn fn, clear_fn *clearfn)
{
uint32_t vlmax = vext_maxsz(desc) / esz;
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
uint32_t i;
for (i = 0; i < vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
fn(vd, s1, vs2, i);
@@ -1172,7 +1166,6 @@ GEN_VEXT_VX(vwsub_wx_w, 4, 8, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
@@ -1181,7 +1174,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
for (i = 0; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, mlen, i); \
+ uint8_t carry = vext_elem_mask(v0, i); \
\
*((ETYPE *)vd + H(i)) = DO_OP(s2, s1, carry); \
} \
@@ -1202,7 +1195,6 @@ GEN_VEXT_VADC_VVM(vsbc_vvm_d, uint64_t, H8, DO_VSBC, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
@@ -1210,7 +1202,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
\
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, mlen, i); \
+ uint8_t carry = vext_elem_mask(v0, i); \
\
*((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\
} \
@@ -1235,7 +1227,6 @@ GEN_VEXT_VADC_VXM(vsbc_vxm_d, uint64_t, H8, DO_VSBC, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
uint32_t i; \
@@ -1243,12 +1234,12 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
for (i = 0; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, mlen, i); \
+ uint8_t carry = vext_elem_mask(v0, i); \
\
- vext_set_elem_mask(vd, mlen, i, DO_OP(s2, s1, carry));\
+ vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \
} \
for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, mlen, i, 0); \
+ vext_set_elem_mask(vd, i, 0); \
} \
}
@@ -1266,20 +1257,19 @@ GEN_VEXT_VMADC_VVM(vmsbc_vvm_d, uint64_t, H8, DO_MSBC)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, mlen, i); \
+ uint8_t carry = vext_elem_mask(v0, i); \
\
- vext_set_elem_mask(vd, mlen, i, \
+ vext_set_elem_mask(vd, i, \
DO_OP(s2, (ETYPE)(target_long)s1, carry)); \
} \
for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, mlen, i, 0); \
+ vext_set_elem_mask(vd, i, 0); \
} \
}
@@ -1353,7 +1343,6 @@ GEN_VEXT_VX(vxor_vx_d, 8, 8, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(TS1); \
@@ -1361,7 +1350,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
TS1 s1 = *((TS1 *)vs1 + HS1(i)); \
@@ -1391,7 +1380,6 @@ GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(TD); \
@@ -1399,7 +1387,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
@@ -1448,7 +1436,6 @@ GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
@@ -1457,13 +1444,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
for (i = 0; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
- vext_set_elem_mask(vd, mlen, i, DO_OP(s2, s1)); \
+ vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
} \
for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, mlen, i, 0); \
+ vext_set_elem_mask(vd, i, 0); \
} \
}
@@ -1501,7 +1488,6 @@ GEN_VEXT_CMP_VV(vmsle_vv_d, int64_t, H8, DO_MSLE)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
@@ -1509,14 +1495,14 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
\
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
- vext_set_elem_mask(vd, mlen, i, \
+ vext_set_elem_mask(vd, i, \
DO_OP(s2, (ETYPE)(target_long)s1)); \
} \
for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, mlen, i, 0); \
+ vext_set_elem_mask(vd, i, 0); \
} \
}
@@ -2078,14 +2064,13 @@ GEN_VEXT_VMV_VX(vmv_v_x_d, int64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- ETYPE *vt = (!vext_elem_mask(v0, mlen, i) ? vs2 : vs1); \
+ ETYPE *vt = (!vext_elem_mask(v0, i) ? vs2 : vs1); \
*((ETYPE *)vd + H(i)) = *(vt + H(i)); \
} \
CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
@@ -2100,7 +2085,6 @@ GEN_VEXT_VMERGE_VV(vmerge_vvm_d, int64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
@@ -2108,7 +2092,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
\
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- ETYPE d = (!vext_elem_mask(v0, mlen, i) ? s2 : \
+ ETYPE d = (!vext_elem_mask(v0, i) ? s2 : \
(ETYPE)(target_long)s1); \
*((ETYPE *)vd + H(i)) = d; \
} \
@@ -2146,11 +2130,11 @@ do_##NAME(void *vd, void *vs1, void *vs2, int i, \
static inline void
vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2,
CPURISCVState *env,
- uint32_t vl, uint32_t vm, uint32_t mlen, int vxrm,
+ uint32_t vl, uint32_t vm, int vxrm,
opivv2_rm_fn *fn)
{
for (uint32_t i = 0; i < vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
fn(vd, vs1, vs2, i, env, vxrm);
@@ -2164,26 +2148,25 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
opivv2_rm_fn *fn, clear_fn *clearfn)
{
uint32_t vlmax = vext_maxsz(desc) / esz;
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
switch (env->vxrm) {
case 0: /* rnu */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, mlen, 0, fn);
+ env, vl, vm, 0, fn);
break;
case 1: /* rne */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, mlen, 1, fn);
+ env, vl, vm, 1, fn);
break;
case 2: /* rdn */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, mlen, 2, fn);
+ env, vl, vm, 2, fn);
break;
default: /* rod */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, mlen, 3, fn);
+ env, vl, vm, 3, fn);
break;
}
@@ -2266,11 +2249,11 @@ do_##NAME(void *vd, target_long s1, void *vs2, int i, \
static inline void
vext_vx_rm_1(void *vd, void *v0, target_long s1, void *vs2,
CPURISCVState *env,
- uint32_t vl, uint32_t vm, uint32_t mlen, int vxrm,
+ uint32_t vl, uint32_t vm, int vxrm,
opivx2_rm_fn *fn)
{
for (uint32_t i = 0; i < vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
fn(vd, s1, vs2, i, env, vxrm);
@@ -2284,26 +2267,25 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
opivx2_rm_fn *fn, clear_fn *clearfn)
{
uint32_t vlmax = vext_maxsz(desc) / esz;
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
switch (env->vxrm) {
case 0: /* rnu */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, mlen, 0, fn);
+ env, vl, vm, 0, fn);
break;
case 1: /* rne */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, mlen, 1, fn);
+ env, vl, vm, 1, fn);
break;
case 2: /* rdn */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, mlen, 2, fn);
+ env, vl, vm, 2, fn);
break;
default: /* rod */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, mlen, 3, fn);
+ env, vl, vm, 3, fn);
break;
}
@@ -3188,13 +3170,12 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t desc) \
{ \
uint32_t vlmax = vext_maxsz(desc) / ESZ; \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
do_##NAME(vd, vs1, vs2, i, env); \
@@ -3223,13 +3204,12 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \
uint32_t desc) \
{ \
uint32_t vlmax = vext_maxsz(desc) / ESZ; \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
do_##NAME(vd, s1, vs2, i, env); \
@@ -3794,7 +3774,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vlmax = vext_maxsz(desc) / ESZ; \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
@@ -3803,7 +3782,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
return; \
} \
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
do_##NAME(vd, vs2, i, env); \
@@ -3935,7 +3914,6 @@ GEN_VEXT_VF(vfsgnjx_vf_d, 8, 8, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
@@ -3944,14 +3922,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
for (i = 0; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
- vext_set_elem_mask(vd, mlen, i, \
+ vext_set_elem_mask(vd, i, \
DO_OP(s2, s1, &env->fp_status)); \
} \
for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, mlen, i, 0); \
+ vext_set_elem_mask(vd, i, 0); \
} \
}
@@ -3969,7 +3947,6 @@ GEN_VEXT_CMP_VV_ENV(vmfeq_vv_d, uint64_t, H8, float64_eq_quiet)
void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
@@ -3977,14 +3954,14 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
\
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
- vext_set_elem_mask(vd, mlen, i, \
+ vext_set_elem_mask(vd, i, \
DO_OP(s2, (ETYPE)s1, &env->fp_status)); \
} \
for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, mlen, i, 0); \
+ vext_set_elem_mask(vd, i, 0); \
} \
}
@@ -4117,13 +4094,12 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vlmax = vext_maxsz(desc) / ESZ; \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
do_##NAME(vd, vs2, i); \
@@ -4200,7 +4176,6 @@ GEN_VEXT_V(vfclass_v_d, 8, 8, clearq)
void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
@@ -4210,7 +4185,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
*((ETYPE *)vd + H(i)) \
- = (!vm && !vext_elem_mask(v0, mlen, i) ? s2 : s1); \
+ = (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \
} \
CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
}
@@ -4341,7 +4316,6 @@ GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4, clearl)
void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
@@ -4350,7 +4324,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
\
for (i = 0; i < vl; i++) { \
TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
s1 = OP(s1, (TD)s2); \
@@ -4424,7 +4398,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
@@ -4433,7 +4406,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
\
for (i = 0; i < vl; i++) { \
TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
s1 = OP(s1, (TD)s2, &env->fp_status); \
@@ -4462,7 +4435,6 @@ GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum, clearq)
void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
void *vs2, CPURISCVState *env, uint32_t desc)
{
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
uint32_t i;
@@ -4471,7 +4443,7 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
for (i = 0; i < vl; i++) {
uint16_t s2 = *((uint16_t *)vs2 + H2(i));
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
s1 = float32_add(s1, float16_to_float32(s2, true, &env->fp_status),
@@ -4484,7 +4456,6 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
void *vs2, CPURISCVState *env, uint32_t desc)
{
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
uint32_t i;
@@ -4493,7 +4464,7 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
for (i = 0; i < vl; i++) {
uint32_t s2 = *((uint32_t *)vs2 + H4(i));
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
s1 = float64_add(s1, float32_to_float64(s2, &env->fp_status),
@@ -4512,19 +4483,18 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vl = env->vl; \
uint32_t i; \
int a, b; \
\
for (i = 0; i < vl; i++) { \
- a = vext_elem_mask(vs1, mlen, i); \
- b = vext_elem_mask(vs2, mlen, i); \
- vext_set_elem_mask(vd, mlen, i, OP(b, a)); \
+ a = vext_elem_mask(vs1, i); \
+ b = vext_elem_mask(vs2, i); \
+ vext_set_elem_mask(vd, i, OP(b, a)); \
} \
for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, mlen, i, 0); \
+ vext_set_elem_mask(vd, i, 0); \
} \
}
@@ -4548,14 +4518,13 @@ target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, CPURISCVState *env,
uint32_t desc)
{
target_ulong cnt = 0;
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
int i;
for (i = 0; i < vl; i++) {
- if (vm || vext_elem_mask(v0, mlen, i)) {
- if (vext_elem_mask(vs2, mlen, i)) {
+ if (vm || vext_elem_mask(v0, i)) {
+ if (vext_elem_mask(vs2, i)) {
cnt++;
}
}
@@ -4567,14 +4536,13 @@ target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, CPURISCVState *env,
target_ulong HELPER(vmfirst_m)(void *v0, void *vs2, CPURISCVState *env,
uint32_t desc)
{
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
int i;
for (i = 0; i < vl; i++) {
- if (vm || vext_elem_mask(v0, mlen, i)) {
- if (vext_elem_mask(vs2, mlen, i)) {
+ if (vm || vext_elem_mask(v0, i)) {
+ if (vext_elem_mask(vs2, i)) {
return i;
}
}
@@ -4591,39 +4559,38 @@ enum set_mask_type {
static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
uint32_t desc, enum set_mask_type type)
{
- uint32_t mlen = vext_mlen(desc);
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen;
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen;
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
int i;
bool first_mask_bit = false;
for (i = 0; i < vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
/* write a zero to all following active elements */
if (first_mask_bit) {
- vext_set_elem_mask(vd, mlen, i, 0);
+ vext_set_elem_mask(vd, i, 0);
continue;
}
- if (vext_elem_mask(vs2, mlen, i)) {
+ if (vext_elem_mask(vs2, i)) {
first_mask_bit = true;
if (type == BEFORE_FIRST) {
- vext_set_elem_mask(vd, mlen, i, 0);
+ vext_set_elem_mask(vd, i, 0);
} else {
- vext_set_elem_mask(vd, mlen, i, 1);
+ vext_set_elem_mask(vd, i, 1);
}
} else {
if (type == ONLY_FIRST) {
- vext_set_elem_mask(vd, mlen, i, 0);
+ vext_set_elem_mask(vd, i, 0);
} else {
- vext_set_elem_mask(vd, mlen, i, 1);
+ vext_set_elem_mask(vd, i, 1);
}
}
}
for (; i < vlmax; i++) {
- vext_set_elem_mask(vd, mlen, i, 0);
+ vext_set_elem_mask(vd, i, 0);
}
}
@@ -4650,19 +4617,18 @@ void HELPER(vmsof_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t sum = 0; \
int i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
*((ETYPE *)vd + H(i)) = sum; \
- if (vext_elem_mask(vs2, mlen, i)) { \
+ if (vext_elem_mask(vs2, i)) { \
sum++; \
} \
} \
@@ -4678,14 +4644,13 @@ GEN_VEXT_VIOTA_M(viota_m_d, uint64_t, H8, clearq)
#define GEN_VEXT_VID_V(NAME, ETYPE, H, CLEAR_FN) \
void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
int i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
*((ETYPE *)vd + H(i)) = i; \
@@ -4707,14 +4672,13 @@ GEN_VEXT_VID_V(vid_v_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
target_ulong offset = s1, i; \
\
for (i = offset; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \
@@ -4732,15 +4696,14 @@ GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
target_ulong offset = s1, i; \
\
for (i = 0; i < vl; ++i) { \
target_ulong j = i + offset; \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
*((ETYPE *)vd + H(i)) = j >= vlmax ? 0 : *((ETYPE *)vs2 + H(j)); \
@@ -4758,14 +4721,13 @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
if (i == 0) { \
@@ -4787,14 +4749,13 @@ GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
if (i == vl - 1) { \
@@ -4817,14 +4778,13 @@ GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t index, i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
index = *((ETYPE *)vs1 + H(i)); \
@@ -4847,14 +4807,13 @@ GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t index = s1, i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
if (index >= vlmax) { \
@@ -4877,13 +4836,12 @@ GEN_VEXT_VRGATHER_VX(vrgather_vx_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vl = env->vl; \
uint32_t num = 0, i; \
\
for (i = 0; i < vl; i++) { \
- if (!vext_elem_mask(vs1, mlen, i)) { \
+ if (!vext_elem_mask(vs1, i)) { \
continue; \
} \
*((ETYPE *)vd + H(num)) = *((ETYPE *)vs2 + H(i)); \
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 10/65] target/riscv: rvv-0.9: remove MLEN calculations
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
As in RVV 0.9 design, MLEN is hardcoded with value 1 (Section 4.5).
Thus, remove all MLEN related calculations.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 44 +----
target/riscv/internals.h | 9 +-
target/riscv/translate.c | 2 -
target/riscv/vector_helper.c | 252 ++++++++++--------------
4 files changed, 116 insertions(+), 191 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 3ae40ad0c1..e222bd78a2 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -246,7 +246,6 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
return false;
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
@@ -301,7 +300,6 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
return false;
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
@@ -386,7 +384,6 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
return false;
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
@@ -427,15 +424,15 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
gen_helper_vsse_v_w, gen_helper_vsse_v_d }
};
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, NF, a->nf);
- fn = fns[seq][s->sew];
+ fn = fns[seq];
if (fn == NULL) {
return false;
}
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, NF, a->nf);
+
return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
@@ -517,7 +514,6 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
return false;
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
@@ -563,7 +559,6 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
return false;
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
@@ -642,7 +637,6 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
return false;
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
@@ -754,7 +748,6 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
}
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, WD, a->wd);
@@ -835,7 +828,6 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
} else {
uint32_t data = 0;
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
@@ -881,7 +873,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
src1 = tcg_temp_new();
gen_get_gpr(src1, rs1);
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
@@ -1032,7 +1023,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
} else {
src1 = tcg_const_tl(sextract64(imm, 0, 5));
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
@@ -1130,7 +1120,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
@@ -1219,7 +1208,6 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
@@ -1298,7 +1286,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
TCGLabel *over = gen_new_label(); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -1489,7 +1476,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
TCGLabel *over = gen_new_label(); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -1855,7 +1841,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_set_rm(s, 7); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -1927,7 +1912,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_d, \
}; \
gen_set_rm(s, 7); \
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -1968,7 +1952,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_set_rm(s, 7); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -2006,7 +1989,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
gen_set_rm(s, 7); \
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2043,7 +2025,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_set_rm(s, 7); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -2079,7 +2060,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
gen_set_rm(s, 7); \
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2159,7 +2139,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_set_rm(s, 7); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -2300,7 +2279,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_set_rm(s, 7); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -2349,7 +2327,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_set_rm(s, 7); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -2412,7 +2389,6 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
TCGLabel *over = gen_new_label(); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
@@ -2441,7 +2417,6 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
TCGv dst;
TCGv_i32 desc;
uint32_t data = 0;
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -2473,7 +2448,6 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
TCGv dst;
TCGv_i32 desc;
uint32_t data = 0;
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -2509,7 +2483,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
TCGLabel *over = gen_new_label(); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
@@ -2536,7 +2509,6 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
static gen_helper_gvec_3_ptr * const fns[4] = {
@@ -2562,7 +2534,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
static gen_helper_gvec_2_ptr * const fns[4] = {
@@ -2850,7 +2821,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
}
if (a->vm && s->vl_eq_vlmax) {
- int vlmax = s->vlen / s->mlen;
+ int vlmax = s->vlen;
TCGv_i64 dest = tcg_temp_new_i64();
if (a->rs1 == 0) {
@@ -2881,7 +2852,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
}
if (a->vm && s->vl_eq_vlmax) {
- if (a->rs1 >= s->vlen / s->mlen) {
+ if (a->rs1 >= s->vlen) {
tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), 0);
} else {
@@ -2921,7 +2892,6 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 37d33820ad..89fc0753bc 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -22,11 +22,10 @@
#include "hw/registerfields.h"
/* share data between vector helpers and decode code */
-FIELD(VDATA, MLEN, 0, 8)
-FIELD(VDATA, VM, 8, 1)
-FIELD(VDATA, LMUL, 9, 2)
-FIELD(VDATA, NF, 11, 4)
-FIELD(VDATA, WD, 11, 1)
+FIELD(VDATA, VM, 0, 1)
+FIELD(VDATA, LMUL, 1, 3)
+FIELD(VDATA, NF, 4, 4)
+FIELD(VDATA, WD, 4, 1)
/* float point classify helpers */
target_ulong fclass_h(uint64_t frs1);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 02b4204584..7593b41a1f 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -62,7 +62,6 @@ typedef struct DisasContext {
uint8_t lmul;
uint8_t sew;
uint16_t vlen;
- uint16_t mlen;
bool vl_eq_vlmax;
} DisasContext;
@@ -824,7 +823,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
- ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul);
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 39f44d1029..6545f91732 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -81,11 +81,6 @@ static inline uint32_t vext_nf(uint32_t desc)
return FIELD_EX32(simd_data(desc), VDATA, NF);
}
-static inline uint32_t vext_mlen(uint32_t desc)
-{
- return FIELD_EX32(simd_data(desc), VDATA, MLEN);
-}
-
static inline uint32_t vext_vm(uint32_t desc)
{
return FIELD_EX32(simd_data(desc), VDATA, VM);
@@ -98,7 +93,7 @@ static inline uint32_t vext_lmul(uint32_t desc)
static uint32_t vext_wd(uint32_t desc)
{
- return (simd_data(desc) >> 11) & 0x1;
+ return FIELD_EX32(simd_data(desc), VDATA, WD);
}
/*
@@ -188,19 +183,24 @@ static void clearq(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
vext_clear(cur, cnt, tot);
}
-static inline void vext_set_elem_mask(void *v0, int mlen, int index,
+static inline void vext_set_elem_mask(void *v0, int index,
uint8_t value)
{
- int idx = (index * mlen) / 64;
- int pos = (index * mlen) % 64;
+ int idx = index / 64;
+ int pos = index % 64;
uint64_t old = ((uint64_t *)v0)[idx];
- ((uint64_t *)v0)[idx] = deposit64(old, pos, mlen, value);
+ ((uint64_t *)v0)[idx] = deposit64(old, pos, 1, value);
}
-static inline int vext_elem_mask(void *v0, int mlen, int index)
+/*
+ * Earlier designs (pre-0.9) had a varying number of bits
+ * per mask value (MLEN). In the 0.9 design, MLEN=1.
+ * (Section 4.6)
+ */
+static inline int vext_elem_mask(void *v0, int index)
{
- int idx = (index * mlen) / 64;
- int pos = (index * mlen) % 64;
+ int idx = index / 64;
+ int pos = index % 64;
return (((uint64_t *)v0)[idx] >> pos) & 1;
}
@@ -277,12 +277,11 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
- uint32_t mlen = vext_mlen(desc);
uint32_t vlmax = vext_maxsz(desc) / esz;
/* probe every access*/
for (i = 0; i < env->vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
probe_pages(env, base + stride * i, nf * msz, ra, access_type);
@@ -290,7 +289,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
/* do real access */
for (i = 0; i < env->vl; i++) {
k = 0;
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
while (k < nf) {
@@ -506,12 +505,11 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
uint32_t i, k;
uint32_t nf = vext_nf(desc);
uint32_t vm = vext_vm(desc);
- uint32_t mlen = vext_mlen(desc);
uint32_t vlmax = vext_maxsz(desc) / esz;
/* probe every access*/
for (i = 0; i < env->vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
probe_pages(env, get_index_addr(base, i, vs2), nf * msz, ra,
@@ -520,7 +518,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
/* load bytes from guest memory */
for (i = 0; i < env->vl; i++) {
k = 0;
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
while (k < nf) {
@@ -604,7 +602,6 @@ vext_ldff(void *vd, void *v0, target_ulong base,
{
void *host;
uint32_t i, k, vl = 0;
- uint32_t mlen = vext_mlen(desc);
uint32_t nf = vext_nf(desc);
uint32_t vm = vext_vm(desc);
uint32_t vlmax = vext_maxsz(desc) / esz;
@@ -612,7 +609,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
/* probe every access*/
for (i = 0; i < env->vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
addr = base + nf * i * msz;
@@ -653,7 +650,7 @@ ProbeSuccess:
}
for (i = 0; i < env->vl; i++) {
k = 0;
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
while (k < nf) {
@@ -784,18 +781,17 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
target_long addr;
uint32_t wd = vext_wd(desc);
uint32_t vm = vext_vm(desc);
- uint32_t mlen = vext_mlen(desc);
uint32_t vlmax = vext_maxsz(desc) / esz;
for (i = 0; i < env->vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_LOAD);
probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_STORE);
}
for (i = 0; i < env->vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
addr = get_index_addr(base, i, vs2);
@@ -911,13 +907,12 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
opivv2_fn *fn, clear_fn *clearfn)
{
uint32_t vlmax = vext_maxsz(desc) / esz;
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
uint32_t i;
for (i = 0; i < vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
fn(vd, vs1, vs2, i);
@@ -976,13 +971,12 @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
opivx2_fn fn, clear_fn *clearfn)
{
uint32_t vlmax = vext_maxsz(desc) / esz;
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
uint32_t i;
for (i = 0; i < vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
fn(vd, s1, vs2, i);
@@ -1172,7 +1166,6 @@ GEN_VEXT_VX(vwsub_wx_w, 4, 8, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
@@ -1181,7 +1174,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
for (i = 0; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, mlen, i); \
+ uint8_t carry = vext_elem_mask(v0, i); \
\
*((ETYPE *)vd + H(i)) = DO_OP(s2, s1, carry); \
} \
@@ -1202,7 +1195,6 @@ GEN_VEXT_VADC_VVM(vsbc_vvm_d, uint64_t, H8, DO_VSBC, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
@@ -1210,7 +1202,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
\
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, mlen, i); \
+ uint8_t carry = vext_elem_mask(v0, i); \
\
*((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\
} \
@@ -1235,7 +1227,6 @@ GEN_VEXT_VADC_VXM(vsbc_vxm_d, uint64_t, H8, DO_VSBC, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
uint32_t i; \
@@ -1243,12 +1234,12 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
for (i = 0; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, mlen, i); \
+ uint8_t carry = vext_elem_mask(v0, i); \
\
- vext_set_elem_mask(vd, mlen, i, DO_OP(s2, s1, carry));\
+ vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \
} \
for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, mlen, i, 0); \
+ vext_set_elem_mask(vd, i, 0); \
} \
}
@@ -1266,20 +1257,19 @@ GEN_VEXT_VMADC_VVM(vmsbc_vvm_d, uint64_t, H8, DO_MSBC)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, mlen, i); \
+ uint8_t carry = vext_elem_mask(v0, i); \
\
- vext_set_elem_mask(vd, mlen, i, \
+ vext_set_elem_mask(vd, i, \
DO_OP(s2, (ETYPE)(target_long)s1, carry)); \
} \
for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, mlen, i, 0); \
+ vext_set_elem_mask(vd, i, 0); \
} \
}
@@ -1353,7 +1343,6 @@ GEN_VEXT_VX(vxor_vx_d, 8, 8, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(TS1); \
@@ -1361,7 +1350,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
TS1 s1 = *((TS1 *)vs1 + HS1(i)); \
@@ -1391,7 +1380,6 @@ GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(TD); \
@@ -1399,7 +1387,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
@@ -1448,7 +1436,6 @@ GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
@@ -1457,13 +1444,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
for (i = 0; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
- vext_set_elem_mask(vd, mlen, i, DO_OP(s2, s1)); \
+ vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
} \
for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, mlen, i, 0); \
+ vext_set_elem_mask(vd, i, 0); \
} \
}
@@ -1501,7 +1488,6 @@ GEN_VEXT_CMP_VV(vmsle_vv_d, int64_t, H8, DO_MSLE)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
@@ -1509,14 +1495,14 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
\
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
- vext_set_elem_mask(vd, mlen, i, \
+ vext_set_elem_mask(vd, i, \
DO_OP(s2, (ETYPE)(target_long)s1)); \
} \
for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, mlen, i, 0); \
+ vext_set_elem_mask(vd, i, 0); \
} \
}
@@ -2078,14 +2064,13 @@ GEN_VEXT_VMV_VX(vmv_v_x_d, int64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- ETYPE *vt = (!vext_elem_mask(v0, mlen, i) ? vs2 : vs1); \
+ ETYPE *vt = (!vext_elem_mask(v0, i) ? vs2 : vs1); \
*((ETYPE *)vd + H(i)) = *(vt + H(i)); \
} \
CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
@@ -2100,7 +2085,6 @@ GEN_VEXT_VMERGE_VV(vmerge_vvm_d, int64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
@@ -2108,7 +2092,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
\
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- ETYPE d = (!vext_elem_mask(v0, mlen, i) ? s2 : \
+ ETYPE d = (!vext_elem_mask(v0, i) ? s2 : \
(ETYPE)(target_long)s1); \
*((ETYPE *)vd + H(i)) = d; \
} \
@@ -2146,11 +2130,11 @@ do_##NAME(void *vd, void *vs1, void *vs2, int i, \
static inline void
vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2,
CPURISCVState *env,
- uint32_t vl, uint32_t vm, uint32_t mlen, int vxrm,
+ uint32_t vl, uint32_t vm, int vxrm,
opivv2_rm_fn *fn)
{
for (uint32_t i = 0; i < vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
fn(vd, vs1, vs2, i, env, vxrm);
@@ -2164,26 +2148,25 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
opivv2_rm_fn *fn, clear_fn *clearfn)
{
uint32_t vlmax = vext_maxsz(desc) / esz;
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
switch (env->vxrm) {
case 0: /* rnu */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, mlen, 0, fn);
+ env, vl, vm, 0, fn);
break;
case 1: /* rne */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, mlen, 1, fn);
+ env, vl, vm, 1, fn);
break;
case 2: /* rdn */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, mlen, 2, fn);
+ env, vl, vm, 2, fn);
break;
default: /* rod */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, mlen, 3, fn);
+ env, vl, vm, 3, fn);
break;
}
@@ -2266,11 +2249,11 @@ do_##NAME(void *vd, target_long s1, void *vs2, int i, \
static inline void
vext_vx_rm_1(void *vd, void *v0, target_long s1, void *vs2,
CPURISCVState *env,
- uint32_t vl, uint32_t vm, uint32_t mlen, int vxrm,
+ uint32_t vl, uint32_t vm, int vxrm,
opivx2_rm_fn *fn)
{
for (uint32_t i = 0; i < vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
fn(vd, s1, vs2, i, env, vxrm);
@@ -2284,26 +2267,25 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
opivx2_rm_fn *fn, clear_fn *clearfn)
{
uint32_t vlmax = vext_maxsz(desc) / esz;
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
switch (env->vxrm) {
case 0: /* rnu */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, mlen, 0, fn);
+ env, vl, vm, 0, fn);
break;
case 1: /* rne */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, mlen, 1, fn);
+ env, vl, vm, 1, fn);
break;
case 2: /* rdn */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, mlen, 2, fn);
+ env, vl, vm, 2, fn);
break;
default: /* rod */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, mlen, 3, fn);
+ env, vl, vm, 3, fn);
break;
}
@@ -3188,13 +3170,12 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t desc) \
{ \
uint32_t vlmax = vext_maxsz(desc) / ESZ; \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
do_##NAME(vd, vs1, vs2, i, env); \
@@ -3223,13 +3204,12 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \
uint32_t desc) \
{ \
uint32_t vlmax = vext_maxsz(desc) / ESZ; \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
do_##NAME(vd, s1, vs2, i, env); \
@@ -3794,7 +3774,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vlmax = vext_maxsz(desc) / ESZ; \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
@@ -3803,7 +3782,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
return; \
} \
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
do_##NAME(vd, vs2, i, env); \
@@ -3935,7 +3914,6 @@ GEN_VEXT_VF(vfsgnjx_vf_d, 8, 8, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
@@ -3944,14 +3922,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
for (i = 0; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
- vext_set_elem_mask(vd, mlen, i, \
+ vext_set_elem_mask(vd, i, \
DO_OP(s2, s1, &env->fp_status)); \
} \
for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, mlen, i, 0); \
+ vext_set_elem_mask(vd, i, 0); \
} \
}
@@ -3969,7 +3947,6 @@ GEN_VEXT_CMP_VV_ENV(vmfeq_vv_d, uint64_t, H8, float64_eq_quiet)
void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
@@ -3977,14 +3954,14 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
\
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
- vext_set_elem_mask(vd, mlen, i, \
+ vext_set_elem_mask(vd, i, \
DO_OP(s2, (ETYPE)s1, &env->fp_status)); \
} \
for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, mlen, i, 0); \
+ vext_set_elem_mask(vd, i, 0); \
} \
}
@@ -4117,13 +4094,12 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vlmax = vext_maxsz(desc) / ESZ; \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
do_##NAME(vd, vs2, i); \
@@ -4200,7 +4176,6 @@ GEN_VEXT_V(vfclass_v_d, 8, 8, clearq)
void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
@@ -4210,7 +4185,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
*((ETYPE *)vd + H(i)) \
- = (!vm && !vext_elem_mask(v0, mlen, i) ? s2 : s1); \
+ = (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \
} \
CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
}
@@ -4341,7 +4316,6 @@ GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4, clearl)
void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
@@ -4350,7 +4324,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
\
for (i = 0; i < vl; i++) { \
TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
s1 = OP(s1, (TD)s2); \
@@ -4424,7 +4398,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
@@ -4433,7 +4406,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
\
for (i = 0; i < vl; i++) { \
TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
s1 = OP(s1, (TD)s2, &env->fp_status); \
@@ -4462,7 +4435,6 @@ GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum, clearq)
void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
void *vs2, CPURISCVState *env, uint32_t desc)
{
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
uint32_t i;
@@ -4471,7 +4443,7 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
for (i = 0; i < vl; i++) {
uint16_t s2 = *((uint16_t *)vs2 + H2(i));
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
s1 = float32_add(s1, float16_to_float32(s2, true, &env->fp_status),
@@ -4484,7 +4456,6 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
void *vs2, CPURISCVState *env, uint32_t desc)
{
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
uint32_t i;
@@ -4493,7 +4464,7 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
for (i = 0; i < vl; i++) {
uint32_t s2 = *((uint32_t *)vs2 + H4(i));
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
s1 = float64_add(s1, float32_to_float64(s2, &env->fp_status),
@@ -4512,19 +4483,18 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vl = env->vl; \
uint32_t i; \
int a, b; \
\
for (i = 0; i < vl; i++) { \
- a = vext_elem_mask(vs1, mlen, i); \
- b = vext_elem_mask(vs2, mlen, i); \
- vext_set_elem_mask(vd, mlen, i, OP(b, a)); \
+ a = vext_elem_mask(vs1, i); \
+ b = vext_elem_mask(vs2, i); \
+ vext_set_elem_mask(vd, i, OP(b, a)); \
} \
for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, mlen, i, 0); \
+ vext_set_elem_mask(vd, i, 0); \
} \
}
@@ -4548,14 +4518,13 @@ target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, CPURISCVState *env,
uint32_t desc)
{
target_ulong cnt = 0;
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
int i;
for (i = 0; i < vl; i++) {
- if (vm || vext_elem_mask(v0, mlen, i)) {
- if (vext_elem_mask(vs2, mlen, i)) {
+ if (vm || vext_elem_mask(v0, i)) {
+ if (vext_elem_mask(vs2, i)) {
cnt++;
}
}
@@ -4567,14 +4536,13 @@ target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, CPURISCVState *env,
target_ulong HELPER(vmfirst_m)(void *v0, void *vs2, CPURISCVState *env,
uint32_t desc)
{
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
int i;
for (i = 0; i < vl; i++) {
- if (vm || vext_elem_mask(v0, mlen, i)) {
- if (vext_elem_mask(vs2, mlen, i)) {
+ if (vm || vext_elem_mask(v0, i)) {
+ if (vext_elem_mask(vs2, i)) {
return i;
}
}
@@ -4591,39 +4559,38 @@ enum set_mask_type {
static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
uint32_t desc, enum set_mask_type type)
{
- uint32_t mlen = vext_mlen(desc);
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen;
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen;
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
int i;
bool first_mask_bit = false;
for (i = 0; i < vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
/* write a zero to all following active elements */
if (first_mask_bit) {
- vext_set_elem_mask(vd, mlen, i, 0);
+ vext_set_elem_mask(vd, i, 0);
continue;
}
- if (vext_elem_mask(vs2, mlen, i)) {
+ if (vext_elem_mask(vs2, i)) {
first_mask_bit = true;
if (type == BEFORE_FIRST) {
- vext_set_elem_mask(vd, mlen, i, 0);
+ vext_set_elem_mask(vd, i, 0);
} else {
- vext_set_elem_mask(vd, mlen, i, 1);
+ vext_set_elem_mask(vd, i, 1);
}
} else {
if (type == ONLY_FIRST) {
- vext_set_elem_mask(vd, mlen, i, 0);
+ vext_set_elem_mask(vd, i, 0);
} else {
- vext_set_elem_mask(vd, mlen, i, 1);
+ vext_set_elem_mask(vd, i, 1);
}
}
}
for (; i < vlmax; i++) {
- vext_set_elem_mask(vd, mlen, i, 0);
+ vext_set_elem_mask(vd, i, 0);
}
}
@@ -4650,19 +4617,18 @@ void HELPER(vmsof_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t sum = 0; \
int i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
*((ETYPE *)vd + H(i)) = sum; \
- if (vext_elem_mask(vs2, mlen, i)) { \
+ if (vext_elem_mask(vs2, i)) { \
sum++; \
} \
} \
@@ -4678,14 +4644,13 @@ GEN_VEXT_VIOTA_M(viota_m_d, uint64_t, H8, clearq)
#define GEN_VEXT_VID_V(NAME, ETYPE, H, CLEAR_FN) \
void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
int i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
*((ETYPE *)vd + H(i)) = i; \
@@ -4707,14 +4672,13 @@ GEN_VEXT_VID_V(vid_v_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
target_ulong offset = s1, i; \
\
for (i = offset; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \
@@ -4732,15 +4696,14 @@ GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
target_ulong offset = s1, i; \
\
for (i = 0; i < vl; ++i) { \
target_ulong j = i + offset; \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
*((ETYPE *)vd + H(i)) = j >= vlmax ? 0 : *((ETYPE *)vs2 + H(j)); \
@@ -4758,14 +4721,13 @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
if (i == 0) { \
@@ -4787,14 +4749,13 @@ GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
if (i == vl - 1) { \
@@ -4817,14 +4778,13 @@ GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t index, i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
index = *((ETYPE *)vs1 + H(i)); \
@@ -4847,14 +4807,13 @@ GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t index = s1, i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
if (index >= vlmax) { \
@@ -4877,13 +4836,12 @@ GEN_VEXT_VRGATHER_VX(vrgather_vx_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vl = env->vl; \
uint32_t num = 0, i; \
\
for (i = 0; i < vl; i++) { \
- if (!vext_elem_mask(vs1, mlen, i)) { \
+ if (!vext_elem_mask(vs1, i)) { \
continue; \
} \
*((ETYPE *)vd + H(num)) = *((ETYPE *)vs2 + H(i)); \
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 11/65] target/riscv: rvv-0.9: add fractional LMUL, VTA and VMA
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 25 +++-
target/riscv/insn_trans/trans_rvv.inc.c | 79 ++++++++++-
target/riscv/internals.h | 13 +-
target/riscv/translate.c | 8 ++
target/riscv/vector_helper.c | 166 +++++++++++++++++-------
5 files changed, 232 insertions(+), 59 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 81c85bf4c2..61393c9e2e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -96,8 +96,11 @@ typedef struct CPURISCVState CPURISCVState;
FIELD(VTYPE, VLMUL, 0, 2)
FIELD(VTYPE, VSEW, 2, 3)
-FIELD(VTYPE, VEDIV, 5, 2)
-FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
+FIELD(VTYPE, VFLMUL, 5, 1)
+FIELD(VTYPE, VTA, 6, 1)
+FIELD(VTYPE, VMA, 7, 1)
+FIELD(VTYPE, VEDIV, 8, 2)
+FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
@@ -369,9 +372,13 @@ typedef RISCVCPU ArchCPU;
#include "exec/cpu-all.h"
FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)
-FIELD(TB_FLAGS, LMUL, 3, 2)
-FIELD(TB_FLAGS, SEW, 5, 3)
-FIELD(TB_FLAGS, VILL, 8, 1)
+FIELD(TB_FLAGS, LMUL, 3, 3)
+FIELD(TB_FLAGS, SEW, 6, 3)
+/* Skip MSTATUS_VS (0x600) fields */
+FIELD(TB_FLAGS, VTA, 11, 1)
+FIELD(TB_FLAGS, VMA, 12, 1)
+/* Skip MSTATUS_VS (0x6000) fields */
+FIELD(TB_FLAGS, VILL, 15, 1)
/*
* A simplification for VLMAX
@@ -400,12 +407,18 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
if (riscv_has_ext(env, RVV)) {
uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
+
flags = FIELD_DP32(flags, TB_FLAGS, VILL,
FIELD_EX64(env->vtype, VTYPE, VILL));
flags = FIELD_DP32(flags, TB_FLAGS, SEW,
FIELD_EX64(env->vtype, VTYPE, VSEW));
flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
- FIELD_EX64(env->vtype, VTYPE, VLMUL));
+ (FIELD_EX64(env->vtype, VTYPE, VFLMUL) << 2)
+ | FIELD_EX64(env->vtype, VTYPE, VLMUL));
+ flags = FIELD_DP32(flags, TB_FLAGS, VTA,
+ FIELD_EX64(env->vtype, VTYPE, VTA));
+ flags = FIELD_DP32(flags, TB_FLAGS, VMA,
+ FIELD_EX64(env->vtype, VTYPE, VMA));
flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
} else {
flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index e222bd78a2..1cc58c86b2 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -248,6 +248,9 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
data = FIELD_DP32(data, VDATA, NF, a->nf);
ret = ldst_us_trans(a->rd, a->rs1, data, fn, s);
mark_vs_dirty(s);
@@ -302,6 +305,9 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldst_us_trans(a->rd, a->rs1, data, fn, s);
}
@@ -386,6 +392,9 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
data = FIELD_DP32(data, VDATA, NF, a->nf);
ret = ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
mark_vs_dirty(s);
@@ -431,6 +440,9 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
@@ -516,6 +528,9 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
data = FIELD_DP32(data, VDATA, NF, a->nf);
ret = ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
mark_vs_dirty(s);
@@ -561,6 +576,9 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
@@ -639,6 +657,9 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
data = FIELD_DP32(data, VDATA, NF, a->nf);
ret = ldff_trans(a->rd, a->rs1, data, fn, s);
mark_vs_dirty(s);
@@ -750,6 +771,9 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
data = FIELD_DP32(data, VDATA, WD, a->wd);
ret = amo_trans(a->rd, a->rs1, a->rs2, data, fn, s);
mark_vs_dirty(s);
@@ -830,6 +854,8 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
cpu_env, 0, s->vlen / 8, data, fn);
@@ -875,6 +901,8 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
data = FIELD_DP32(data, VDATA, VM, vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
@@ -1025,6 +1053,8 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
}
data = FIELD_DP32(data, VDATA, VM, vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
@@ -1122,6 +1152,8 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1),
vreg_ofs(s, a->rs2),
@@ -1210,6 +1242,8 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1),
vreg_ofs(s, a->rs2),
@@ -1288,6 +1322,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
@@ -1478,6 +1514,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
@@ -1654,7 +1692,9 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
vreg_ofs(s, a->rs1),
MAXSZ(s), MAXSZ(s));
} else {
- uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+ uint32_t data = 0;
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
static gen_helper_gvec_2_ptr * const fns[4] = {
gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
@@ -1691,7 +1731,9 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
TCGv_i32 desc ;
TCGv_i64 s1_i64 = tcg_temp_new_i64();
TCGv_ptr dest = tcg_temp_new_ptr();
- uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+ uint32_t data = 0;
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
static gen_helper_vmv_vx * const fns[4] = {
gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
@@ -1727,7 +1769,10 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
TCGv_i32 desc;
TCGv_i64 s1;
TCGv_ptr dest;
- uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+ uint32_t data = 0;
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
static gen_helper_vmv_vx * const fns[4] = {
gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
@@ -1843,6 +1888,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
@@ -1914,6 +1961,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_set_rm(s, 7); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
fns[s->sew - 1], s); \
} \
@@ -1954,6 +2003,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
@@ -1991,6 +2042,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_set_rm(s, 7); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
fns[s->sew - 1], s); \
} \
@@ -2027,6 +2080,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
@@ -2062,6 +2117,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_set_rm(s, 7); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
fns[s->sew - 1], s); \
} \
@@ -2141,6 +2198,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
@@ -2281,6 +2340,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
@@ -2329,6 +2390,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
@@ -2390,6 +2453,7 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
@@ -2419,6 +2483,7 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
uint32_t data = 0;
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr();
@@ -2450,6 +2515,7 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
uint32_t data = 0;
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr();
@@ -2485,6 +2551,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
cpu_env, 0, s->vlen / 8, data, fn); \
@@ -2511,6 +2578,8 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
static gen_helper_gvec_3_ptr * const fns[4] = {
gen_helper_viota_m_b, gen_helper_viota_m_h,
gen_helper_viota_m_w, gen_helper_viota_m_d,
@@ -2536,6 +2605,8 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
static gen_helper_gvec_2_ptr * const fns[4] = {
gen_helper_vid_v_b, gen_helper_vid_v_h,
gen_helper_vid_v_w, gen_helper_vid_v_d,
@@ -2893,6 +2964,8 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 89fc0753bc..4538e5faf8 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -24,8 +24,11 @@
/* share data between vector helpers and decode code */
FIELD(VDATA, VM, 0, 1)
FIELD(VDATA, LMUL, 1, 3)
-FIELD(VDATA, NF, 4, 4)
-FIELD(VDATA, WD, 4, 1)
+FIELD(VDATA, SEW, 4, 3)
+FIELD(VDATA, VTA, 7, 1)
+FIELD(VDATA, VMA, 8, 1)
+FIELD(VDATA, NF, 9, 4)
+FIELD(VDATA, WD, 9, 1)
/* float point classify helpers */
target_ulong fclass_h(uint64_t frs1);
@@ -37,4 +40,10 @@ target_ulong fclass_d(uint64_t frs1);
#define SEW32 2
#define SEW64 3
+/* table to convert fractional LMUL value */
+static const float flmul_table[8] = {
+ 1, 2, 4, 8, /* LMUL */
+ -1, /* reserved */
+ 0.125, 0.25, 0.5 /* fractional LMUL */
+};
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 7593b41a1f..4599e3574e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -60,6 +60,11 @@ typedef struct DisasContext {
/* vector extension */
bool vill;
uint8_t lmul;
+ float flmul;
+ uint8_t eew;
+ float emul;
+ uint8_t vta;
+ uint8_t vma;
uint8_t sew;
uint16_t vlen;
bool vl_eq_vlmax;
@@ -823,6 +828,9 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
+ ctx->flmul = flmul_table[ctx->lmul];
+ ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA);
+ ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA);
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 6545f91732..db54288c08 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -86,9 +86,15 @@ static inline uint32_t vext_vm(uint32_t desc)
return FIELD_EX32(simd_data(desc), VDATA, VM);
}
-static inline uint32_t vext_lmul(uint32_t desc)
+static inline uint32_t vext_sew(uint32_t desc)
{
- return FIELD_EX32(simd_data(desc), VDATA, LMUL);
+ return 1 << (FIELD_EX32(simd_data(desc), VDATA, SEW) + 3);
+}
+
+static inline float vext_vflmul(uint32_t desc)
+{
+ uint32_t lmul = FIELD_EX32(simd_data(desc), VDATA, LMUL);
+ return flmul_table[lmul];
}
static uint32_t vext_wd(uint32_t desc)
@@ -96,6 +102,16 @@ static uint32_t vext_wd(uint32_t desc)
return FIELD_EX32(simd_data(desc), VDATA, WD);
}
+static inline uint32_t vext_vta(uint32_t desc)
+{
+ return FIELD_EX32(simd_data(desc), VDATA, VTA);
+}
+
+static inline uint32_t vext_vma(uint32_t desc)
+{
+ return FIELD_EX32(simd_data(desc), VDATA, VMA);
+}
+
/*
* Get vector group length in bytes. Its range is [64, 2048].
*
@@ -135,8 +151,13 @@ static void probe_pages(CPURISCVState *env, target_ulong addr,
}
#ifdef HOST_WORDS_BIGENDIAN
-static void vext_clear(void *tail, uint32_t cnt, uint32_t tot)
+static void vext_clear(void *tail, uint32_t vta, uint32_t cnt, uint32_t tot)
{
+ /* tail element undisturbed */
+ if (vta == 0) {
+ return;
+ }
+
/*
* Split the remaining range to two parts.
* The first part is in the last uint64_t unit.
@@ -153,34 +174,43 @@ static void vext_clear(void *tail, uint32_t cnt, uint32_t tot)
}
}
#else
-static void vext_clear(void *tail, uint32_t cnt, uint32_t tot)
+static void vext_clear(void *tail, uint32_t vta, uint32_t cnt, uint32_t tot)
{
+ /* tail element undisturbed */
+ if (vta == 0) {
+ return;
+ }
+
memset(tail, 0, tot - cnt);
}
#endif
-static void clearb(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
+static void clearb(void *vd, uint32_t vta, uint32_t idx,
+ uint32_t cnt, uint32_t tot)
{
int8_t *cur = ((int8_t *)vd + H1(idx));
- vext_clear(cur, cnt, tot);
+ vext_clear(cur, vta, cnt, tot);
}
-static void clearh(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
+static void clearh(void *vd, uint32_t vta, uint32_t idx,
+ uint32_t cnt, uint32_t tot)
{
int16_t *cur = ((int16_t *)vd + H2(idx));
- vext_clear(cur, cnt, tot);
+ vext_clear(cur, vta, cnt, tot);
}
-static void clearl(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
+static void clearl(void *vd, uint32_t vta, uint32_t idx,
+ uint32_t cnt, uint32_t tot)
{
int32_t *cur = ((int32_t *)vd + H4(idx));
- vext_clear(cur, cnt, tot);
+ vext_clear(cur, vta, cnt, tot);
}
-static void clearq(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
+static void clearq(void *vd, uint32_t vta, uint32_t idx,
+ uint32_t cnt, uint32_t tot)
{
int64_t *cur = (int64_t *)vd + idx;
- vext_clear(cur, cnt, tot);
+ vext_clear(cur, vta, cnt, tot);
}
static inline void vext_set_elem_mask(void *v0, int index,
@@ -207,7 +237,8 @@ static inline int vext_elem_mask(void *v0, int index)
/* elements operations for load and store */
typedef void vext_ldst_elem_fn(CPURISCVState *env, target_ulong addr,
uint32_t idx, void *vd, uintptr_t retaddr);
-typedef void clear_fn(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot);
+typedef void clear_fn(void *vd, uint32_t vta, uint32_t idx,
+ uint32_t cnt, uint32_t tot);
#define GEN_VEXT_LD_ELEM(NAME, MTYPE, ETYPE, H, LDSUF) \
static void NAME(CPURISCVState *env, abi_ptr addr, \
@@ -278,6 +309,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
uint32_t i, k;
uint32_t nf = vext_nf(desc);
uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t vta = vext_vta(desc);
/* probe every access*/
for (i = 0; i < env->vl; i++) {
@@ -301,7 +333,8 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
/* clear tail elements */
if (clear_elem) {
for (k = 0; k < nf; k++) {
- clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
+ clear_elem(vd, vta, env->vl + k * vlmax,
+ env->vl * esz, vlmax * esz);
}
}
}
@@ -379,6 +412,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
uint32_t i, k;
uint32_t nf = vext_nf(desc);
uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t vta = vext_vta(desc);
/* probe every access */
probe_pages(env, base, env->vl * nf * msz, ra, access_type);
@@ -394,7 +428,8 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
/* clear tail elements */
if (clear_elem) {
for (k = 0; k < nf; k++) {
- clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
+ clear_elem(vd, vta, env->vl + k * vlmax,
+ env->vl * esz, vlmax * esz);
}
}
}
@@ -506,6 +541,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
uint32_t nf = vext_nf(desc);
uint32_t vm = vext_vm(desc);
uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t vta = vext_vta(desc);
/* probe every access*/
for (i = 0; i < env->vl; i++) {
@@ -530,7 +566,8 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
/* clear tail elements */
if (clear_elem) {
for (k = 0; k < nf; k++) {
- clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
+ clear_elem(vd, vta, env->vl + k * vlmax,
+ env->vl * esz, vlmax * esz);
}
}
}
@@ -605,6 +642,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
uint32_t nf = vext_nf(desc);
uint32_t vm = vext_vm(desc);
uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t vta = vext_vta(desc);
target_ulong addr, offset, remain;
/* probe every access*/
@@ -664,7 +702,8 @@ ProbeSuccess:
return;
}
for (k = 0; k < nf; k++) {
- clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
+ clear_elem(vd, vta, env->vl + k * vlmax,
+ env->vl * esz, vlmax * esz);
}
}
@@ -782,6 +821,7 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
uint32_t wd = vext_wd(desc);
uint32_t vm = vext_vm(desc);
uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t vta = vext_vta(desc);
for (i = 0; i < env->vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
@@ -797,7 +837,7 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
addr = get_index_addr(base, i, vs2);
noatomic_op(vs3, addr, wd, i, env, ra);
}
- clear_elem(vs3, env->vl, env->vl * esz, vlmax * esz);
+ clear_elem(vs3, vta, env->vl, env->vl * esz, vlmax * esz);
}
#define GEN_VEXT_AMO(NAME, MTYPE, ETYPE, INDEX_FN, CLEAR_FN) \
@@ -908,6 +948,7 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
{
uint32_t vlmax = vext_maxsz(desc) / esz;
uint32_t vm = vext_vm(desc);
+ uint32_t vta = vext_vta(desc);
uint32_t vl = env->vl;
uint32_t i;
@@ -917,7 +958,7 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
}
fn(vd, vs1, vs2, i);
}
- clearfn(vd, vl, vl * dsz, vlmax * dsz);
+ clearfn(vd, vta, vl, vl * dsz, vlmax * dsz);
}
/* generate the helpers for OPIVV */
@@ -972,6 +1013,7 @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
{
uint32_t vlmax = vext_maxsz(desc) / esz;
uint32_t vm = vext_vm(desc);
+ uint32_t vta = vext_vta(desc);
uint32_t vl = env->vl;
uint32_t i;
@@ -981,7 +1023,7 @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
}
fn(vd, s1, vs2, i);
}
- clearfn(vd, vl, vl * dsz, vlmax * dsz);
+ clearfn(vd, vta, vl, vl * dsz, vlmax * dsz);
}
/* generate the helpers for OPIVX */
@@ -1169,6 +1211,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -1178,7 +1221,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
\
*((ETYPE *)vd + H(i)) = DO_OP(s2, s1, carry); \
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
+ CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \
}
GEN_VEXT_VADC_VVM(vadc_vvm_b, uint8_t, H1, DO_VADC, clearb)
@@ -1198,6 +1241,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -1206,7 +1250,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
\
*((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
+ CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \
}
GEN_VEXT_VADC_VXM(vadc_vxm_b, uint8_t, H1, DO_VADC, clearb)
@@ -1347,6 +1391,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(TS1); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -1357,7 +1402,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
*((TS1 *)vd + HS1(i)) = OP(s2, s1 & MASK); \
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
+ CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \
}
GEN_VEXT_SHIFT_VV(vsll_vv_b, uint8_t, uint8_t, H1, H1, DO_SLL, 0x7, clearb)
@@ -1384,6 +1429,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(TD); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -1393,7 +1439,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
*((TD *)vd + HD(i)) = OP(s2, s1 & MASK); \
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
+ CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \
}
GEN_VEXT_SHIFT_VX(vsll_vx_b, uint8_t, int8_t, H1, H1, DO_SLL, 0x7, clearb)
@@ -2026,13 +2072,14 @@ void HELPER(NAME)(void *vd, void *vs1, CPURISCVState *env, \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
*((ETYPE *)vd + H(i)) = s1; \
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
+ CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \
}
GEN_VEXT_VMV_VV(vmv_v_v_b, int8_t, H1, clearb)
@@ -2047,12 +2094,13 @@ void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVState *env, \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
*((ETYPE *)vd + H(i)) = (ETYPE)s1; \
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
+ CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \
}
GEN_VEXT_VMV_VX(vmv_v_x_b, int8_t, H1, clearb)
@@ -2067,13 +2115,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
ETYPE *vt = (!vext_elem_mask(v0, i) ? vs2 : vs1); \
*((ETYPE *)vd + H(i)) = *(vt + H(i)); \
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
+ CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \
}
GEN_VEXT_VMERGE_VV(vmerge_vvm_b, int8_t, H1, clearb)
@@ -2088,6 +2137,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -2096,7 +2146,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
(ETYPE)(target_long)s1); \
*((ETYPE *)vd + H(i)) = d; \
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
+ CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \
}
GEN_VEXT_VMERGE_VX(vmerge_vxm_b, int8_t, H1, clearb)
@@ -2149,6 +2199,7 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
{
uint32_t vlmax = vext_maxsz(desc) / esz;
uint32_t vm = vext_vm(desc);
+ uint32_t vta = vext_vta(desc);
uint32_t vl = env->vl;
switch (env->vxrm) {
@@ -2170,7 +2221,7 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
break;
}
- clearfn(vd, vl, vl * dsz, vlmax * dsz);
+ clearfn(vd, vta, vl, vl * dsz, vlmax * dsz);
}
/* generate helpers for fixed point instructions with OPIVV format */
@@ -2268,6 +2319,7 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
{
uint32_t vlmax = vext_maxsz(desc) / esz;
uint32_t vm = vext_vm(desc);
+ uint32_t vta = vext_vta(desc);
uint32_t vl = env->vl;
switch (env->vxrm) {
@@ -2289,7 +2341,7 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
break;
}
- clearfn(vd, vl, vl * dsz, vlmax * dsz);
+ clearfn(vd, vta, vl, vl * dsz, vlmax * dsz);
}
/* generate helpers for fixed point instructions with OPIVX format */
@@ -3171,6 +3223,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
{ \
uint32_t vlmax = vext_maxsz(desc) / ESZ; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
@@ -3180,7 +3233,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
} \
do_##NAME(vd, vs1, vs2, i, env); \
} \
- CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \
+ CLEAR_FN(vd, vta, vl, vl * DSZ, vlmax * DSZ); \
}
RVVCALL(OPFVV2, vfadd_vv_h, OP_UUU_H, H2, H2, H2, float16_add)
@@ -3205,6 +3258,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \
{ \
uint32_t vlmax = vext_maxsz(desc) / ESZ; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
@@ -3214,7 +3268,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \
} \
do_##NAME(vd, s1, vs2, i, env); \
} \
- CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \
+ CLEAR_FN(vd, vta, vl, vl * DSZ, vlmax * DSZ); \
}
RVVCALL(OPFVF2, vfadd_vf_h, OP_UUU_H, H2, H2, float16_add)
@@ -3775,6 +3829,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
{ \
uint32_t vlmax = vext_maxsz(desc) / ESZ; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
@@ -3787,7 +3842,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
} \
do_##NAME(vd, vs2, i, env); \
} \
- CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \
+ CLEAR_FN(vd, vta, vl, vl * DSZ, vlmax * DSZ); \
}
RVVCALL(OPFVV1, vfsqrt_v_h, OP_UU_H, H2, H2, float16_sqrt)
@@ -4095,6 +4150,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
{ \
uint32_t vlmax = vext_maxsz(desc) / ESZ; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
@@ -4104,7 +4160,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
} \
do_##NAME(vd, vs2, i); \
} \
- CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \
+ CLEAR_FN(vd, vta, vl, vl * DSZ, vlmax * DSZ); \
}
target_ulong fclass_h(uint64_t frs1)
@@ -4180,6 +4236,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -4187,7 +4244,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
*((ETYPE *)vd + H(i)) \
= (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
+ CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \
}
GEN_VFMERGE_VF(vfmerge_vfm_h, int16_t, H2, clearh)
@@ -4317,6 +4374,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
uint32_t tot = env_archcpu(env)->cfg.vlen / 8; \
@@ -4330,7 +4388,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
s1 = OP(s1, (TD)s2); \
} \
*((TD *)vd + HD(0)) = s1; \
- CLEAR_FN(vd, 1, sizeof(TD), tot); \
+ CLEAR_FN(vd, vta, 1, sizeof(TD), tot); \
}
/* vd[0] = sum(vs1[0], vs2[*]) */
@@ -4399,6 +4457,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
uint32_t tot = env_archcpu(env)->cfg.vlen / 8; \
@@ -4412,7 +4471,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
s1 = OP(s1, (TD)s2, &env->fp_status); \
} \
*((TD *)vd + HD(0)) = s1; \
- CLEAR_FN(vd, 1, sizeof(TD), tot); \
+ CLEAR_FN(vd, vta, 1, sizeof(TD), tot); \
}
/* Unordered sum */
@@ -4436,6 +4495,7 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
void *vs2, CPURISCVState *env, uint32_t desc)
{
uint32_t vm = vext_vm(desc);
+ uint32_t vta = vext_vta(desc);
uint32_t vl = env->vl;
uint32_t i;
uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
@@ -4450,13 +4510,14 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
&env->fp_status);
}
*((uint32_t *)vd + H4(0)) = s1;
- clearl(vd, 1, sizeof(uint32_t), tot);
+ clearl(vd, vta, 1, sizeof(uint32_t), tot);
}
void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
void *vs2, CPURISCVState *env, uint32_t desc)
{
uint32_t vm = vext_vm(desc);
+ uint32_t vta = vext_vta(desc);
uint32_t vl = env->vl;
uint32_t i;
uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
@@ -4471,7 +4532,7 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
&env->fp_status);
}
*((uint64_t *)vd) = s1;
- clearq(vd, 1, sizeof(uint64_t), tot);
+ clearq(vd, vta, 1, sizeof(uint64_t), tot);
}
/*
@@ -4619,6 +4680,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \
{ \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t sum = 0; \
int i; \
@@ -4632,7 +4694,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \
sum++; \
} \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+ CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1, clearb)
@@ -4646,6 +4708,7 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
int i; \
\
@@ -4655,7 +4718,7 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \
} \
*((ETYPE *)vd + H(i)) = i; \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+ CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
GEN_VEXT_VID_V(vid_v_b, uint8_t, H1, clearb)
@@ -4674,6 +4737,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
{ \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
target_ulong offset = s1, i; \
\
@@ -4683,7 +4747,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
} \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+ CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] = vs2[i] */
@@ -4698,6 +4762,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
{ \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
target_ulong offset = s1, i; \
\
@@ -4708,7 +4773,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
} \
*((ETYPE *)vd + H(i)) = j >= vlmax ? 0 : *((ETYPE *)vs2 + H(j)); \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+ CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1] */
@@ -4723,6 +4788,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
{ \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
@@ -4736,7 +4802,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1)); \
} \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+ CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] */
@@ -4751,6 +4817,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
{ \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
@@ -4764,7 +4831,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + 1)); \
} \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+ CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] */
@@ -4780,6 +4847,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
{ \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t index, i; \
\
@@ -4794,7 +4862,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(index)); \
} \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+ CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; */
@@ -4809,6 +4877,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
{ \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t index = s1, i; \
\
@@ -4822,7 +4891,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(index)); \
} \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+ CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */
@@ -4837,6 +4906,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t num = 0, i; \
\
@@ -4847,7 +4917,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
*((ETYPE *)vd + H(num)) = *((ETYPE *)vs2 + H(i)); \
num++; \
} \
- CLEAR_FN(vd, num, num * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+ CLEAR_FN(vd, vta, num, num * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* Compress into vd elements of vs2 where vs1 is enabled */
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 11/65] target/riscv: rvv-0.9: add fractional LMUL, VTA and VMA
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 25 +++-
target/riscv/insn_trans/trans_rvv.inc.c | 79 ++++++++++-
target/riscv/internals.h | 13 +-
target/riscv/translate.c | 8 ++
target/riscv/vector_helper.c | 166 +++++++++++++++++-------
5 files changed, 232 insertions(+), 59 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 81c85bf4c2..61393c9e2e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -96,8 +96,11 @@ typedef struct CPURISCVState CPURISCVState;
FIELD(VTYPE, VLMUL, 0, 2)
FIELD(VTYPE, VSEW, 2, 3)
-FIELD(VTYPE, VEDIV, 5, 2)
-FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
+FIELD(VTYPE, VFLMUL, 5, 1)
+FIELD(VTYPE, VTA, 6, 1)
+FIELD(VTYPE, VMA, 7, 1)
+FIELD(VTYPE, VEDIV, 8, 2)
+FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
@@ -369,9 +372,13 @@ typedef RISCVCPU ArchCPU;
#include "exec/cpu-all.h"
FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)
-FIELD(TB_FLAGS, LMUL, 3, 2)
-FIELD(TB_FLAGS, SEW, 5, 3)
-FIELD(TB_FLAGS, VILL, 8, 1)
+FIELD(TB_FLAGS, LMUL, 3, 3)
+FIELD(TB_FLAGS, SEW, 6, 3)
+/* Skip MSTATUS_VS (0x600) fields */
+FIELD(TB_FLAGS, VTA, 11, 1)
+FIELD(TB_FLAGS, VMA, 12, 1)
+/* Skip MSTATUS_VS (0x6000) fields */
+FIELD(TB_FLAGS, VILL, 15, 1)
/*
* A simplification for VLMAX
@@ -400,12 +407,18 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
if (riscv_has_ext(env, RVV)) {
uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
+
flags = FIELD_DP32(flags, TB_FLAGS, VILL,
FIELD_EX64(env->vtype, VTYPE, VILL));
flags = FIELD_DP32(flags, TB_FLAGS, SEW,
FIELD_EX64(env->vtype, VTYPE, VSEW));
flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
- FIELD_EX64(env->vtype, VTYPE, VLMUL));
+ (FIELD_EX64(env->vtype, VTYPE, VFLMUL) << 2)
+ | FIELD_EX64(env->vtype, VTYPE, VLMUL));
+ flags = FIELD_DP32(flags, TB_FLAGS, VTA,
+ FIELD_EX64(env->vtype, VTYPE, VTA));
+ flags = FIELD_DP32(flags, TB_FLAGS, VMA,
+ FIELD_EX64(env->vtype, VTYPE, VMA));
flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
} else {
flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index e222bd78a2..1cc58c86b2 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -248,6 +248,9 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
data = FIELD_DP32(data, VDATA, NF, a->nf);
ret = ldst_us_trans(a->rd, a->rs1, data, fn, s);
mark_vs_dirty(s);
@@ -302,6 +305,9 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldst_us_trans(a->rd, a->rs1, data, fn, s);
}
@@ -386,6 +392,9 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
data = FIELD_DP32(data, VDATA, NF, a->nf);
ret = ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
mark_vs_dirty(s);
@@ -431,6 +440,9 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
@@ -516,6 +528,9 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
data = FIELD_DP32(data, VDATA, NF, a->nf);
ret = ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
mark_vs_dirty(s);
@@ -561,6 +576,9 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
@@ -639,6 +657,9 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
data = FIELD_DP32(data, VDATA, NF, a->nf);
ret = ldff_trans(a->rd, a->rs1, data, fn, s);
mark_vs_dirty(s);
@@ -750,6 +771,9 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
data = FIELD_DP32(data, VDATA, WD, a->wd);
ret = amo_trans(a->rd, a->rs1, a->rs2, data, fn, s);
mark_vs_dirty(s);
@@ -830,6 +854,8 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
cpu_env, 0, s->vlen / 8, data, fn);
@@ -875,6 +901,8 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
data = FIELD_DP32(data, VDATA, VM, vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
@@ -1025,6 +1053,8 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
}
data = FIELD_DP32(data, VDATA, VM, vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
@@ -1122,6 +1152,8 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1),
vreg_ofs(s, a->rs2),
@@ -1210,6 +1242,8 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1),
vreg_ofs(s, a->rs2),
@@ -1288,6 +1322,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
@@ -1478,6 +1514,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
@@ -1654,7 +1692,9 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
vreg_ofs(s, a->rs1),
MAXSZ(s), MAXSZ(s));
} else {
- uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+ uint32_t data = 0;
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
static gen_helper_gvec_2_ptr * const fns[4] = {
gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
@@ -1691,7 +1731,9 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
TCGv_i32 desc ;
TCGv_i64 s1_i64 = tcg_temp_new_i64();
TCGv_ptr dest = tcg_temp_new_ptr();
- uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+ uint32_t data = 0;
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
static gen_helper_vmv_vx * const fns[4] = {
gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
@@ -1727,7 +1769,10 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
TCGv_i32 desc;
TCGv_i64 s1;
TCGv_ptr dest;
- uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+ uint32_t data = 0;
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
static gen_helper_vmv_vx * const fns[4] = {
gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
@@ -1843,6 +1888,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
@@ -1914,6 +1961,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_set_rm(s, 7); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
fns[s->sew - 1], s); \
} \
@@ -1954,6 +2003,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
@@ -1991,6 +2042,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_set_rm(s, 7); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
fns[s->sew - 1], s); \
} \
@@ -2027,6 +2080,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
@@ -2062,6 +2117,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_set_rm(s, 7); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
fns[s->sew - 1], s); \
} \
@@ -2141,6 +2198,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
@@ -2281,6 +2340,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
@@ -2329,6 +2390,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
@@ -2390,6 +2453,7 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
@@ -2419,6 +2483,7 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
uint32_t data = 0;
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr();
@@ -2450,6 +2515,7 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
uint32_t data = 0;
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr();
@@ -2485,6 +2551,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
cpu_env, 0, s->vlen / 8, data, fn); \
@@ -2511,6 +2578,8 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
static gen_helper_gvec_3_ptr * const fns[4] = {
gen_helper_viota_m_b, gen_helper_viota_m_h,
gen_helper_viota_m_w, gen_helper_viota_m_d,
@@ -2536,6 +2605,8 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
static gen_helper_gvec_2_ptr * const fns[4] = {
gen_helper_vid_v_b, gen_helper_vid_v_h,
gen_helper_vid_v_w, gen_helper_vid_v_d,
@@ -2893,6 +2964,8 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 89fc0753bc..4538e5faf8 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -24,8 +24,11 @@
/* share data between vector helpers and decode code */
FIELD(VDATA, VM, 0, 1)
FIELD(VDATA, LMUL, 1, 3)
-FIELD(VDATA, NF, 4, 4)
-FIELD(VDATA, WD, 4, 1)
+FIELD(VDATA, SEW, 4, 3)
+FIELD(VDATA, VTA, 7, 1)
+FIELD(VDATA, VMA, 8, 1)
+FIELD(VDATA, NF, 9, 4)
+FIELD(VDATA, WD, 9, 1)
/* float point classify helpers */
target_ulong fclass_h(uint64_t frs1);
@@ -37,4 +40,10 @@ target_ulong fclass_d(uint64_t frs1);
#define SEW32 2
#define SEW64 3
+/* table to convert fractional LMUL value */
+static const float flmul_table[8] = {
+ 1, 2, 4, 8, /* LMUL */
+ -1, /* reserved */
+ 0.125, 0.25, 0.5 /* fractional LMUL */
+};
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 7593b41a1f..4599e3574e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -60,6 +60,11 @@ typedef struct DisasContext {
/* vector extension */
bool vill;
uint8_t lmul;
+ float flmul;
+ uint8_t eew;
+ float emul;
+ uint8_t vta;
+ uint8_t vma;
uint8_t sew;
uint16_t vlen;
bool vl_eq_vlmax;
@@ -823,6 +828,9 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
+ ctx->flmul = flmul_table[ctx->lmul];
+ ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA);
+ ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA);
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 6545f91732..db54288c08 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -86,9 +86,15 @@ static inline uint32_t vext_vm(uint32_t desc)
return FIELD_EX32(simd_data(desc), VDATA, VM);
}
-static inline uint32_t vext_lmul(uint32_t desc)
+static inline uint32_t vext_sew(uint32_t desc)
{
- return FIELD_EX32(simd_data(desc), VDATA, LMUL);
+ return 1 << (FIELD_EX32(simd_data(desc), VDATA, SEW) + 3);
+}
+
+static inline float vext_vflmul(uint32_t desc)
+{
+ uint32_t lmul = FIELD_EX32(simd_data(desc), VDATA, LMUL);
+ return flmul_table[lmul];
}
static uint32_t vext_wd(uint32_t desc)
@@ -96,6 +102,16 @@ static uint32_t vext_wd(uint32_t desc)
return FIELD_EX32(simd_data(desc), VDATA, WD);
}
+static inline uint32_t vext_vta(uint32_t desc)
+{
+ return FIELD_EX32(simd_data(desc), VDATA, VTA);
+}
+
+static inline uint32_t vext_vma(uint32_t desc)
+{
+ return FIELD_EX32(simd_data(desc), VDATA, VMA);
+}
+
/*
* Get vector group length in bytes. Its range is [64, 2048].
*
@@ -135,8 +151,13 @@ static void probe_pages(CPURISCVState *env, target_ulong addr,
}
#ifdef HOST_WORDS_BIGENDIAN
-static void vext_clear(void *tail, uint32_t cnt, uint32_t tot)
+static void vext_clear(void *tail, uint32_t vta, uint32_t cnt, uint32_t tot)
{
+ /* tail element undisturbed */
+ if (vta == 0) {
+ return;
+ }
+
/*
* Split the remaining range to two parts.
* The first part is in the last uint64_t unit.
@@ -153,34 +174,43 @@ static void vext_clear(void *tail, uint32_t cnt, uint32_t tot)
}
}
#else
-static void vext_clear(void *tail, uint32_t cnt, uint32_t tot)
+static void vext_clear(void *tail, uint32_t vta, uint32_t cnt, uint32_t tot)
{
+ /* tail element undisturbed */
+ if (vta == 0) {
+ return;
+ }
+
memset(tail, 0, tot - cnt);
}
#endif
-static void clearb(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
+static void clearb(void *vd, uint32_t vta, uint32_t idx,
+ uint32_t cnt, uint32_t tot)
{
int8_t *cur = ((int8_t *)vd + H1(idx));
- vext_clear(cur, cnt, tot);
+ vext_clear(cur, vta, cnt, tot);
}
-static void clearh(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
+static void clearh(void *vd, uint32_t vta, uint32_t idx,
+ uint32_t cnt, uint32_t tot)
{
int16_t *cur = ((int16_t *)vd + H2(idx));
- vext_clear(cur, cnt, tot);
+ vext_clear(cur, vta, cnt, tot);
}
-static void clearl(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
+static void clearl(void *vd, uint32_t vta, uint32_t idx,
+ uint32_t cnt, uint32_t tot)
{
int32_t *cur = ((int32_t *)vd + H4(idx));
- vext_clear(cur, cnt, tot);
+ vext_clear(cur, vta, cnt, tot);
}
-static void clearq(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
+static void clearq(void *vd, uint32_t vta, uint32_t idx,
+ uint32_t cnt, uint32_t tot)
{
int64_t *cur = (int64_t *)vd + idx;
- vext_clear(cur, cnt, tot);
+ vext_clear(cur, vta, cnt, tot);
}
static inline void vext_set_elem_mask(void *v0, int index,
@@ -207,7 +237,8 @@ static inline int vext_elem_mask(void *v0, int index)
/* elements operations for load and store */
typedef void vext_ldst_elem_fn(CPURISCVState *env, target_ulong addr,
uint32_t idx, void *vd, uintptr_t retaddr);
-typedef void clear_fn(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot);
+typedef void clear_fn(void *vd, uint32_t vta, uint32_t idx,
+ uint32_t cnt, uint32_t tot);
#define GEN_VEXT_LD_ELEM(NAME, MTYPE, ETYPE, H, LDSUF) \
static void NAME(CPURISCVState *env, abi_ptr addr, \
@@ -278,6 +309,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
uint32_t i, k;
uint32_t nf = vext_nf(desc);
uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t vta = vext_vta(desc);
/* probe every access*/
for (i = 0; i < env->vl; i++) {
@@ -301,7 +333,8 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
/* clear tail elements */
if (clear_elem) {
for (k = 0; k < nf; k++) {
- clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
+ clear_elem(vd, vta, env->vl + k * vlmax,
+ env->vl * esz, vlmax * esz);
}
}
}
@@ -379,6 +412,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
uint32_t i, k;
uint32_t nf = vext_nf(desc);
uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t vta = vext_vta(desc);
/* probe every access */
probe_pages(env, base, env->vl * nf * msz, ra, access_type);
@@ -394,7 +428,8 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
/* clear tail elements */
if (clear_elem) {
for (k = 0; k < nf; k++) {
- clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
+ clear_elem(vd, vta, env->vl + k * vlmax,
+ env->vl * esz, vlmax * esz);
}
}
}
@@ -506,6 +541,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
uint32_t nf = vext_nf(desc);
uint32_t vm = vext_vm(desc);
uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t vta = vext_vta(desc);
/* probe every access*/
for (i = 0; i < env->vl; i++) {
@@ -530,7 +566,8 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
/* clear tail elements */
if (clear_elem) {
for (k = 0; k < nf; k++) {
- clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
+ clear_elem(vd, vta, env->vl + k * vlmax,
+ env->vl * esz, vlmax * esz);
}
}
}
@@ -605,6 +642,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
uint32_t nf = vext_nf(desc);
uint32_t vm = vext_vm(desc);
uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t vta = vext_vta(desc);
target_ulong addr, offset, remain;
/* probe every access*/
@@ -664,7 +702,8 @@ ProbeSuccess:
return;
}
for (k = 0; k < nf; k++) {
- clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
+ clear_elem(vd, vta, env->vl + k * vlmax,
+ env->vl * esz, vlmax * esz);
}
}
@@ -782,6 +821,7 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
uint32_t wd = vext_wd(desc);
uint32_t vm = vext_vm(desc);
uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t vta = vext_vta(desc);
for (i = 0; i < env->vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
@@ -797,7 +837,7 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
addr = get_index_addr(base, i, vs2);
noatomic_op(vs3, addr, wd, i, env, ra);
}
- clear_elem(vs3, env->vl, env->vl * esz, vlmax * esz);
+ clear_elem(vs3, vta, env->vl, env->vl * esz, vlmax * esz);
}
#define GEN_VEXT_AMO(NAME, MTYPE, ETYPE, INDEX_FN, CLEAR_FN) \
@@ -908,6 +948,7 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
{
uint32_t vlmax = vext_maxsz(desc) / esz;
uint32_t vm = vext_vm(desc);
+ uint32_t vta = vext_vta(desc);
uint32_t vl = env->vl;
uint32_t i;
@@ -917,7 +958,7 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
}
fn(vd, vs1, vs2, i);
}
- clearfn(vd, vl, vl * dsz, vlmax * dsz);
+ clearfn(vd, vta, vl, vl * dsz, vlmax * dsz);
}
/* generate the helpers for OPIVV */
@@ -972,6 +1013,7 @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
{
uint32_t vlmax = vext_maxsz(desc) / esz;
uint32_t vm = vext_vm(desc);
+ uint32_t vta = vext_vta(desc);
uint32_t vl = env->vl;
uint32_t i;
@@ -981,7 +1023,7 @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
}
fn(vd, s1, vs2, i);
}
- clearfn(vd, vl, vl * dsz, vlmax * dsz);
+ clearfn(vd, vta, vl, vl * dsz, vlmax * dsz);
}
/* generate the helpers for OPIVX */
@@ -1169,6 +1211,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -1178,7 +1221,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
\
*((ETYPE *)vd + H(i)) = DO_OP(s2, s1, carry); \
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
+ CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \
}
GEN_VEXT_VADC_VVM(vadc_vvm_b, uint8_t, H1, DO_VADC, clearb)
@@ -1198,6 +1241,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -1206,7 +1250,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
\
*((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
+ CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \
}
GEN_VEXT_VADC_VXM(vadc_vxm_b, uint8_t, H1, DO_VADC, clearb)
@@ -1347,6 +1391,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(TS1); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -1357,7 +1402,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
*((TS1 *)vd + HS1(i)) = OP(s2, s1 & MASK); \
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
+ CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \
}
GEN_VEXT_SHIFT_VV(vsll_vv_b, uint8_t, uint8_t, H1, H1, DO_SLL, 0x7, clearb)
@@ -1384,6 +1429,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(TD); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -1393,7 +1439,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
*((TD *)vd + HD(i)) = OP(s2, s1 & MASK); \
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
+ CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \
}
GEN_VEXT_SHIFT_VX(vsll_vx_b, uint8_t, int8_t, H1, H1, DO_SLL, 0x7, clearb)
@@ -2026,13 +2072,14 @@ void HELPER(NAME)(void *vd, void *vs1, CPURISCVState *env, \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
*((ETYPE *)vd + H(i)) = s1; \
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
+ CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \
}
GEN_VEXT_VMV_VV(vmv_v_v_b, int8_t, H1, clearb)
@@ -2047,12 +2094,13 @@ void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVState *env, \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
*((ETYPE *)vd + H(i)) = (ETYPE)s1; \
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
+ CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \
}
GEN_VEXT_VMV_VX(vmv_v_x_b, int8_t, H1, clearb)
@@ -2067,13 +2115,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
ETYPE *vt = (!vext_elem_mask(v0, i) ? vs2 : vs1); \
*((ETYPE *)vd + H(i)) = *(vt + H(i)); \
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
+ CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \
}
GEN_VEXT_VMERGE_VV(vmerge_vvm_b, int8_t, H1, clearb)
@@ -2088,6 +2137,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -2096,7 +2146,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
(ETYPE)(target_long)s1); \
*((ETYPE *)vd + H(i)) = d; \
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
+ CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \
}
GEN_VEXT_VMERGE_VX(vmerge_vxm_b, int8_t, H1, clearb)
@@ -2149,6 +2199,7 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
{
uint32_t vlmax = vext_maxsz(desc) / esz;
uint32_t vm = vext_vm(desc);
+ uint32_t vta = vext_vta(desc);
uint32_t vl = env->vl;
switch (env->vxrm) {
@@ -2170,7 +2221,7 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
break;
}
- clearfn(vd, vl, vl * dsz, vlmax * dsz);
+ clearfn(vd, vta, vl, vl * dsz, vlmax * dsz);
}
/* generate helpers for fixed point instructions with OPIVV format */
@@ -2268,6 +2319,7 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
{
uint32_t vlmax = vext_maxsz(desc) / esz;
uint32_t vm = vext_vm(desc);
+ uint32_t vta = vext_vta(desc);
uint32_t vl = env->vl;
switch (env->vxrm) {
@@ -2289,7 +2341,7 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
break;
}
- clearfn(vd, vl, vl * dsz, vlmax * dsz);
+ clearfn(vd, vta, vl, vl * dsz, vlmax * dsz);
}
/* generate helpers for fixed point instructions with OPIVX format */
@@ -3171,6 +3223,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
{ \
uint32_t vlmax = vext_maxsz(desc) / ESZ; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
@@ -3180,7 +3233,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
} \
do_##NAME(vd, vs1, vs2, i, env); \
} \
- CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \
+ CLEAR_FN(vd, vta, vl, vl * DSZ, vlmax * DSZ); \
}
RVVCALL(OPFVV2, vfadd_vv_h, OP_UUU_H, H2, H2, H2, float16_add)
@@ -3205,6 +3258,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \
{ \
uint32_t vlmax = vext_maxsz(desc) / ESZ; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
@@ -3214,7 +3268,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \
} \
do_##NAME(vd, s1, vs2, i, env); \
} \
- CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \
+ CLEAR_FN(vd, vta, vl, vl * DSZ, vlmax * DSZ); \
}
RVVCALL(OPFVF2, vfadd_vf_h, OP_UUU_H, H2, H2, float16_add)
@@ -3775,6 +3829,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
{ \
uint32_t vlmax = vext_maxsz(desc) / ESZ; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
@@ -3787,7 +3842,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
} \
do_##NAME(vd, vs2, i, env); \
} \
- CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \
+ CLEAR_FN(vd, vta, vl, vl * DSZ, vlmax * DSZ); \
}
RVVCALL(OPFVV1, vfsqrt_v_h, OP_UU_H, H2, H2, float16_sqrt)
@@ -4095,6 +4150,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
{ \
uint32_t vlmax = vext_maxsz(desc) / ESZ; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
@@ -4104,7 +4160,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
} \
do_##NAME(vd, vs2, i); \
} \
- CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \
+ CLEAR_FN(vd, vta, vl, vl * DSZ, vlmax * DSZ); \
}
target_ulong fclass_h(uint64_t frs1)
@@ -4180,6 +4236,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -4187,7 +4244,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
*((ETYPE *)vd + H(i)) \
= (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
+ CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \
}
GEN_VFMERGE_VF(vfmerge_vfm_h, int16_t, H2, clearh)
@@ -4317,6 +4374,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
uint32_t tot = env_archcpu(env)->cfg.vlen / 8; \
@@ -4330,7 +4388,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
s1 = OP(s1, (TD)s2); \
} \
*((TD *)vd + HD(0)) = s1; \
- CLEAR_FN(vd, 1, sizeof(TD), tot); \
+ CLEAR_FN(vd, vta, 1, sizeof(TD), tot); \
}
/* vd[0] = sum(vs1[0], vs2[*]) */
@@ -4399,6 +4457,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
uint32_t tot = env_archcpu(env)->cfg.vlen / 8; \
@@ -4412,7 +4471,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
s1 = OP(s1, (TD)s2, &env->fp_status); \
} \
*((TD *)vd + HD(0)) = s1; \
- CLEAR_FN(vd, 1, sizeof(TD), tot); \
+ CLEAR_FN(vd, vta, 1, sizeof(TD), tot); \
}
/* Unordered sum */
@@ -4436,6 +4495,7 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
void *vs2, CPURISCVState *env, uint32_t desc)
{
uint32_t vm = vext_vm(desc);
+ uint32_t vta = vext_vta(desc);
uint32_t vl = env->vl;
uint32_t i;
uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
@@ -4450,13 +4510,14 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
&env->fp_status);
}
*((uint32_t *)vd + H4(0)) = s1;
- clearl(vd, 1, sizeof(uint32_t), tot);
+ clearl(vd, vta, 1, sizeof(uint32_t), tot);
}
void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
void *vs2, CPURISCVState *env, uint32_t desc)
{
uint32_t vm = vext_vm(desc);
+ uint32_t vta = vext_vta(desc);
uint32_t vl = env->vl;
uint32_t i;
uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
@@ -4471,7 +4532,7 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
&env->fp_status);
}
*((uint64_t *)vd) = s1;
- clearq(vd, 1, sizeof(uint64_t), tot);
+ clearq(vd, vta, 1, sizeof(uint64_t), tot);
}
/*
@@ -4619,6 +4680,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \
{ \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t sum = 0; \
int i; \
@@ -4632,7 +4694,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \
sum++; \
} \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+ CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1, clearb)
@@ -4646,6 +4708,7 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
int i; \
\
@@ -4655,7 +4718,7 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \
} \
*((ETYPE *)vd + H(i)) = i; \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+ CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
GEN_VEXT_VID_V(vid_v_b, uint8_t, H1, clearb)
@@ -4674,6 +4737,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
{ \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
target_ulong offset = s1, i; \
\
@@ -4683,7 +4747,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
} \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+ CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] = vs2[i] */
@@ -4698,6 +4762,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
{ \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
target_ulong offset = s1, i; \
\
@@ -4708,7 +4773,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
} \
*((ETYPE *)vd + H(i)) = j >= vlmax ? 0 : *((ETYPE *)vs2 + H(j)); \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+ CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1] */
@@ -4723,6 +4788,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
{ \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
@@ -4736,7 +4802,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1)); \
} \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+ CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] */
@@ -4751,6 +4817,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
{ \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
@@ -4764,7 +4831,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + 1)); \
} \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+ CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] */
@@ -4780,6 +4847,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
{ \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t index, i; \
\
@@ -4794,7 +4862,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(index)); \
} \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+ CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; */
@@ -4809,6 +4877,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
{ \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t index = s1, i; \
\
@@ -4822,7 +4891,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(index)); \
} \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+ CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */
@@ -4837,6 +4906,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t num = 0, i; \
\
@@ -4847,7 +4917,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
*((ETYPE *)vd + H(num)) = *((ETYPE *)vs2 + H(i)); \
num++; \
} \
- CLEAR_FN(vd, num, num * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+ CLEAR_FN(vd, vta, num, num * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* Compress into vd elements of vs2 where vs1 is enabled */
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 12/65] target/riscv: rvv-0.9: update check functions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 507 ++++++++++++++----------
1 file changed, 308 insertions(+), 199 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 1cc58c86b2..fc1908389e 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -19,6 +19,59 @@
#include "tcg/tcg-gvec-desc.h"
#include "internals.h"
+#define NVPR 32
+
+#define require(x) if (unlikely(!(x))) { return false; }
+#define require_align(val, pos) require(is_aligned(val, pos))
+
+/* Destination vector register group cannot overlap source mask register. */
+#define require_vm(vm, rd) do { if (vm == 0) require(rd != 0); } while (0)
+
+#define require_noover(astart, asize, bstart, bsize) \
+ require(!is_overlapped(astart, asize, bstart, bsize))
+#define require_noover_widen(astart, asize, bstart, bsize) \
+ require(!is_overlapped_widen(astart, asize, bstart, bsize))
+
+#define REQUIRE_RVV do { \
+ if (s->mstatus_vs == 0) \
+ return false; \
+} while (0)
+
+static inline bool is_aligned(const unsigned val, const unsigned pos)
+{
+ return pos ? (val & (pos - 1)) == 0 : true;
+}
+
+static inline bool is_overlapped(const int astart, int asize,
+ const int bstart, int bsize)
+{
+ asize = asize == 0 ? 1 : asize;
+ bsize = bsize == 0 ? 1 : bsize;
+
+ const int aend = astart + asize;
+ const int bend = bstart + bsize;
+
+ return MAX(aend, bend) - MIN(astart, bstart) < asize + bsize;
+}
+
+static inline bool is_overlapped_widen(const int astart, int asize,
+ const int bstart, int bsize)
+{
+ asize = asize == 0 ? 1 : asize;
+ bsize = bsize == 0 ? 1 : bsize;
+
+ const int aend = astart + asize;
+ const int bend = bstart + bsize;
+
+ if (astart < bstart &&
+ is_overlapped(astart, asize, bstart, bsize) &&
+ !is_overlapped(astart, asize, bstart + bsize, bsize)) {
+ return false;
+ } else {
+ return MAX(aend, bend) - MIN(astart, bstart) < asize + bsize;
+ }
+}
+
static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
{
TCGv s1, s2, dst;
@@ -103,29 +156,121 @@ static bool vext_check_isa_ill(DisasContext *s)
}
/*
- * There are two rules check here.
+ * Check function for vector instruction with format:
+ * single-width result and single-width sources (SEW = SEW op SEW)
+ *
+ * is_vs1: indicates whether insn[19:15] is a vs1 field or not.
+ */
+#define VEXT_CHECK_SSS(s, rd, rs1, rs2, vm, is_vs1) do { \
+ require_vm(vm, rd); \
+ if (s->flmul > 1) { \
+ require_align(rd, s->flmul); \
+ require_align(rs2, s->flmul); \
+ if (is_vs1) { \
+ require_align(rs1, s->flmul); \
+ } \
+ } \
+} while (0)
+
+/*
+ * Check function for maskable vector instruction with format:
+ * single-width result and single-width sources (SEW = SEW op SEW)
*
- * 1. Vector register numbers are multiples of LMUL. (Section 3.2)
+ * is_vs1: indicates whether insn[19:15] is a vs1 field or not.
+ */
+#define VEXT_CHECK_MSS(s, rd, rs1, rs2, is_vs1) do { \
+ if (rd != rs2) { \
+ require_noover(rd, 1, rs2, s->flmul); \
+ } \
+ require_align(rs2, s->flmul); \
+ if (is_vs1) { \
+ if (rd != rs1) { \
+ require_noover(rd, 1, rs1, s->flmul); \
+ } \
+ require_align(rs1, s->flmul); \
+ } \
+} while (0)
+
+/* Common check function for vector widening instructions */
+#define VEXT_WIDE_CHECK_COMMON(s, rd, vm) do { \
+ require(s->flmul <= 4); \
+ require(s->sew < 3); \
+ require_align(rd, s->flmul * 2); \
+ require_vm(vm, rd); \
+} while (0)
+
+/* Common check function for vector narrowing instructions */
+#define VEXT_NARROW_CHECK_COMMON(s, rd, rs2, vm) do { \
+ require(s->flmul <= 4); \
+ require(s->sew < 3); \
+ require_align(rs2, s->flmul * 2); \
+ require_align(rd, s->flmul); \
+ require_vm(vm, rd); \
+} while (0)
+
+/*
+ * Check function for vector instruction with format:
+ * double-width result and single-width sources (2*SEW = SEW op SEW)
*
- * 2. For all widening instructions, the destination LMUL value must also be
- * a supported LMUL value. (Section 11.2)
+ * is_vs1: indicates whether insn[19:15] is a vs1 field or not.
*/
-static bool vext_check_reg(DisasContext *s, uint32_t reg, bool widen)
-{
- /*
- * The destination vector register group results are arranged as if both
- * SEW and LMUL were at twice their current settings. (Section 11.2).
- */
- int legal = widen ? 2 << s->lmul : 1 << s->lmul;
+#define VEXT_CHECK_DSS(s, rd, rs1, rs2, vm, is_vs1) do { \
+ VEXT_WIDE_CHECK_COMMON(s, rd, vm); \
+ require_align(rs2, s->flmul); \
+ if (s->flmul < 1) { \
+ require_noover(rd, s->flmul * 2, rs2, s->flmul); \
+ } else { \
+ require_noover_widen(rd, s->flmul * 2, rs2, s->flmul); \
+ } \
+ if (is_vs1) { \
+ require_align(rs1, s->flmul); \
+ if (s->flmul < 1) { \
+ require_noover(rd, s->flmul * 2, rs1, s->flmul); \
+ } else { \
+ require_noover_widen(rd, s->flmul * 2, rs1, s->flmul); \
+ } \
+ } \
+} while (0)
- return !((s->lmul == 0x3 && widen) || (reg % legal));
-}
+/*
+ * Check function for vector instruction with format:
+ * double-width result and double-width source1 and single-width
+ * source2 (2*SEW = 2*SEW op SEW)
+ *
+ * is_vs1: indicates whether insn[19:15] is a vs1 field or not.
+ */
+#define VEXT_CHECK_DDS(s, rd, rs1, rs2, vm, is_vs1) do { \
+ VEXT_WIDE_CHECK_COMMON(s, rd, vm); \
+ require_align(rs2, s->flmul * 2); \
+ if (is_vs1) { \
+ require_align(rs1, s->flmul); \
+ if (s->flmul < 1) { \
+ require_noover(rd, s->flmul * 2, rs1, s->flmul); \
+ } else { \
+ require_noover_widen(rd, s->flmul * 2, rs1, s->flmul); \
+ } \
+ } \
+} while (0)
/*
- * There are two rules check here.
+ * Check function for vector instruction with format:
+ * single-width result and double-width source1 and single-width
+ * source2 (SEW = 2*SEW op SEW)
*
- * 1. The destination vector register group for a masked vector instruction can
- * only overlap the source mask register (v0) when LMUL=1. (Section 5.3)
+ * is_vs1: indicates whether insn[19:15] is a vs1 field or not.
+ */
+#define VEXT_CHECK_SDS(s, rd, rs1, rs2, vm, is_vs1) do { \
+ VEXT_NARROW_CHECK_COMMON(s, rd, rs2, vm); \
+ if (rd != rs2) { \
+ require_noover(rd, s->flmul, rs2, s->flmul * 2); \
+ } \
+ if (is_vs1) { \
+ require_align(rs1, s->flmul); \
+ } \
+} while (0)
+
+/*
+ * Check function for vector reduction instructions
*
* 2. In widen instructions and some other insturctions, like vslideup.vx,
* there is no need to check whether LMUL=1.
@@ -136,20 +281,14 @@ static bool vext_check_overlap_mask(DisasContext *s, uint32_t vd, bool vm,
return (vm != 0 || vd != 0) || (!force && (s->lmul == 0));
}
-/* The LMUL setting must be such that LMUL * NFIELDS <= 8. (Section 7.8) */
-static bool vext_check_nf(DisasContext *s, uint32_t nf)
-{
- return (1 << s->lmul) * nf <= 8;
-}
-
/*
- * The destination vector register group cannot overlap a source vector register
- * group of a different element width. (Section 11.2)
+ * In cpu_get_tb_cpu_state(), set VILL if RVV was not present.
+ * So RVV is also be checked in this function.
*/
-static inline bool vext_check_overlap_group(int rd, int dlen, int rs, int slen)
-{
- return ((rd >= rs + slen) || (rs >= rd + dlen));
-}
+#define VEXT_CHECK_ISA_ILL(s) do { \
+ require(!s->vill) \
+} while (0)
+
/* common translation macro */
#define GEN_VEXT_TRANS(NAME, SEQ, ARGTYPE, OP, CHECK) \
static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\
@@ -824,11 +963,10 @@ GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check)
static bool opivv_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_SSS(s, a->rd, a->rs1, a->rs2, a->vm, true);
+ return true;
}
typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
@@ -922,10 +1060,10 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
static bool opivx_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_SSS(s, a->rd, a->rs1, a->rs2, a->vm, false);
+ return true;
}
typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t, TCGv_i64,
@@ -1129,16 +1267,10 @@ GEN_OPIVI_GVEC_TRANS(vrsub_vi, 0, vrsub_vx, rsubi)
/* OPIVV with WIDEN */
static bool opivv_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
- 1 << s->lmul) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_DSS(s, a->rd, a->rs1, a->rs2, a->vm, true);
+ return true;
}
static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
@@ -1185,13 +1317,10 @@ GEN_OPIVV_WIDEN_TRANS(vwsub_vv, opivv_widen_check)
/* OPIVX with WIDEN */
static bool opivx_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_DSS(s, a->rd, a->rs1, a->rs2, a->vm, false);
+ return true;
}
static bool do_opivx_widen(DisasContext *s, arg_rmrr *a,
@@ -1222,14 +1351,10 @@ GEN_OPIVX_WIDEN_TRANS(vwsub_vx)
/* WIDEN OPIVV with WIDEN */
static bool opiwv_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, true) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_DDS(s, a->rd, a->rs1, a->rs2, a->vm, true);
+ return true;
}
static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
@@ -1274,11 +1399,10 @@ GEN_OPIWV_WIDEN_TRANS(vwsub_wv)
/* WIDEN OPIVX with WIDEN */
static bool opiwx_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, true) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_DDS(s, a->rd, a->rs1, a->rs2, a->vm, false);
+ return true;
}
static bool do_opiwx_widen(DisasContext *s, arg_rmrr *a,
@@ -1341,11 +1465,11 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
*/
static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- ((a->rd != 0) || (s->lmul == 0)));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ require(a->rd != 0);
+ VEXT_CHECK_SSS(s, a->rd, a->rs1, a->rs2, a->vm, true);
+ return true;
}
GEN_OPIVV_TRANS(vadc_vvm, opivv_vadc_check)
@@ -1357,11 +1481,10 @@ GEN_OPIVV_TRANS(vsbc_vvm, opivv_vadc_check)
*/
static bool opivv_vmadc_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) &&
- vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_MSS(s, a->rd, a->rs1, a->rs2, true);
+ return true;
}
GEN_OPIVV_TRANS(vmadc_vvm, opivv_vmadc_check)
@@ -1369,10 +1492,11 @@ GEN_OPIVV_TRANS(vmsbc_vvm, opivv_vmadc_check)
static bool opivx_vadc_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- ((a->rd != 0) || (s->lmul == 0)));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ require(a->rd != 0);
+ VEXT_CHECK_SSS(s, a->rd, a->rs1, a->rs2, a->vm, false);
+ return true;
}
/* OPIVX without GVEC IR */
@@ -1395,9 +1519,10 @@ GEN_OPIVX_TRANS(vsbc_vxm, opivx_vadc_check)
static bool opivx_vmadc_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_MSS(s, a->rd, a->rs1, a->rs2, false);
+ return true;
}
GEN_OPIVX_TRANS(vmadc_vxm, opivx_vmadc_check)
@@ -1488,14 +1613,10 @@ GEN_OPIVI_TRANS(vsra_vi, 1, vsra_vx, opivx_check)
/* Vector Narrowing Integer Right Shift Instructions */
static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, true) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
- 2 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_SDS(s, a->rd, a->rs1, a->rs2, a->vm, true);
+ return true;
}
/* OPIVV with NARROW */
@@ -1531,13 +1652,10 @@ GEN_OPIVV_NARROW_TRANS(vnsrl_vv)
static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, true) &&
- vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
- 2 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_SDS(s, a->rd, a->rs1, a->rs2, a->vm, false);
+ return true;
}
/* OPIVX with NARROW */
@@ -1585,13 +1703,12 @@ GEN_OPIVI_NARROW_TRANS(vnsrl_vi, 1, vnsrl_vx)
*/
static bool opivv_cmp_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) &&
- vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) ||
- (s->lmul == 0)));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_MSS(s, a->rd, a->rs1, a->rs2, true);
+ return true;
}
+
GEN_OPIVV_TRANS(vmseq_vv, opivv_cmp_check)
GEN_OPIVV_TRANS(vmsne_vv, opivv_cmp_check)
GEN_OPIVV_TRANS(vmsltu_vv, opivv_cmp_check)
@@ -1601,10 +1718,10 @@ GEN_OPIVV_TRANS(vmsle_vv, opivv_cmp_check)
static bool opivx_cmp_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) ||
- (s->lmul == 0)));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_MSS(s, a->rd, a->rs1, a->rs2, false);
+ return true;
}
GEN_OPIVX_TRANS(vmseq_vx, opivx_cmp_check)
@@ -1863,12 +1980,11 @@ GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx)
*/
static bool opfvv_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- (s->sew != 0));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_SSS(s, a->rd, a->rs1, a->rs2, a->vm, true);
+ require(s->sew != 0);
+ return true;
}
/* OPFVV without GVEC IR */
@@ -1934,17 +2050,17 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
return true;
}
-static bool opfvf_check(DisasContext *s, arg_rmrr *a)
-{
/*
* If the current SEW does not correspond to a supported IEEE floating-point
* type, an illegal instruction exception is raised
*/
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- (s->sew != 0));
+static bool opfvf_check(DisasContext *s, arg_rmrr *a)
+{
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_SSS(s, a->rd, a->rs1, a->rs2, a->vm, false);
+ require(s->sew != 0);
+ return true;
}
/* OPFVF without GVEC IR */
@@ -1976,16 +2092,11 @@ GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check)
/* Vector Widening Floating-Point Add/Subtract Instructions */
static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
- 1 << s->lmul) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_DSS(s, a->rd, a->rs1, a->rs2, a->vm, true);
+ require(s->sew != 0);
+ return true;
}
/* OPFVV with WIDEN */
@@ -2021,13 +2132,11 @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_DSS(s, a->rd, a->rs1, a->rs2, a->vm, false);
+ require(s->sew != 0);
+ return true;
}
/* OPFVF with WIDEN */
@@ -2055,14 +2164,11 @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, true) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_DDS(s, a->rd, a->rs1, a->rs2, a->vm, true);
+ require(s->sew != 0);
+ return true;
}
/* WIDEN OPFVV with WIDEN */
@@ -2098,11 +2204,11 @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, true) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_DDS(s, a->rd, a->rs1, a->rs2, a->vm, false);
+ require(s->sew != 0);
+ return true;
}
/* WIDEN OPFVF with WIDEN */
@@ -2175,11 +2281,12 @@ GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf)
*/
static bool opfv_check(DisasContext *s, arg_rmr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- (s->sew != 0));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ /* OPFV instructions ignore vs1 check */
+ VEXT_CHECK_SSS(s, a->rd, 0, a->rs2, a->vm, false);
+ require(s->sew != 0);
+ return true;
}
#define GEN_OPFV_TRANS(NAME, CHECK) \
@@ -2229,13 +2336,11 @@ GEN_OPFVF_TRANS(vfsgnjx_vf, opfvf_check)
/* Vector Floating-Point Compare Instructions */
static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- (s->sew != 0) &&
- ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) &&
- vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) ||
- (s->lmul == 0)));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_MSS(s, a->rd, a->rs1, a->rs2, true);
+ require(s->sew != 0);
+ return true;
}
GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
@@ -2246,11 +2351,11 @@ GEN_OPFVV_TRANS(vmford_vv, opfvv_cmp_check)
static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- (s->sew != 0) &&
- (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) ||
- (s->lmul == 0)));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_MSS(s, a->rd, a->rs1, a->rs2, false);
+ require(s->sew != 0);
+ return true;
}
GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
@@ -2316,13 +2421,12 @@ GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check)
*/
static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ /* OPFV widening instructions ignore vs1 check */
+ VEXT_CHECK_DSS(s, a->rd, 0, a->rs2, a->vm, false);
+ require(s->sew != 0);
+ return true;
}
#define GEN_OPFV_WIDEN_TRANS(NAME) \
@@ -2366,13 +2470,12 @@ GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v)
*/
static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, true) &&
- vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
- 2 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ /* OPFV narrowing instructions ignore vs1 check */
+ VEXT_CHECK_SDS(s, a->rd, 0, a->rs2, a->vm, false);
+ require(s->sew != 0);
+ return true;
}
#define GEN_OPFV_NARROW_TRANS(NAME) \
@@ -2865,23 +2968,27 @@ GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check)
/* Vector Register Gather Instruction */
static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_reg(s, a->rs2, false) &&
- (a->rd != a->rs2) && (a->rd != a->rs1));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ require_align(a->rd, s->flmul);
+ require_align(a->rs1, s->flmul);
+ require_align(a->rs2, s->flmul);
+ require(a->rd != a->rs2 && a->rd != a->rs1);
+ require_vm(a->vm, a->rd);
+ return true;
}
GEN_OPIVV_TRANS(vrgather_vv, vrgather_vv_check)
static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- (a->rd != a->rs2));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ require_align(a->rd, s->flmul);
+ require_align(a->rs2, s->flmul);
+ require(a->rd != a->rs2);
+ require_vm(a->vm, a->rd);
+ return true;
}
/* vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */
@@ -2945,11 +3052,13 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
/* Vector Compress Instruction */
static bool vcompress_vm_check(DisasContext *s, arg_r *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs1, 1) &&
- (a->rd != a->rs2));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ require_align(a->rd, s->flmul);
+ require_align(a->rs2, s->flmul);
+ require(a->rd != a->rs2);
+ require_noover(a->rd, s->flmul, a->rs1, 1);
+ return true;
}
static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 12/65] target/riscv: rvv-0.9: update check functions
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 507 ++++++++++++++----------
1 file changed, 308 insertions(+), 199 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 1cc58c86b2..fc1908389e 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -19,6 +19,59 @@
#include "tcg/tcg-gvec-desc.h"
#include "internals.h"
+#define NVPR 32
+
+#define require(x) if (unlikely(!(x))) { return false; }
+#define require_align(val, pos) require(is_aligned(val, pos))
+
+/* Destination vector register group cannot overlap source mask register. */
+#define require_vm(vm, rd) do { if (vm == 0) require(rd != 0); } while (0)
+
+#define require_noover(astart, asize, bstart, bsize) \
+ require(!is_overlapped(astart, asize, bstart, bsize))
+#define require_noover_widen(astart, asize, bstart, bsize) \
+ require(!is_overlapped_widen(astart, asize, bstart, bsize))
+
+#define REQUIRE_RVV do { \
+ if (s->mstatus_vs == 0) \
+ return false; \
+} while (0)
+
+static inline bool is_aligned(const unsigned val, const unsigned pos)
+{
+ return pos ? (val & (pos - 1)) == 0 : true;
+}
+
+static inline bool is_overlapped(const int astart, int asize,
+ const int bstart, int bsize)
+{
+ asize = asize == 0 ? 1 : asize;
+ bsize = bsize == 0 ? 1 : bsize;
+
+ const int aend = astart + asize;
+ const int bend = bstart + bsize;
+
+ return MAX(aend, bend) - MIN(astart, bstart) < asize + bsize;
+}
+
+static inline bool is_overlapped_widen(const int astart, int asize,
+ const int bstart, int bsize)
+{
+ asize = asize == 0 ? 1 : asize;
+ bsize = bsize == 0 ? 1 : bsize;
+
+ const int aend = astart + asize;
+ const int bend = bstart + bsize;
+
+ if (astart < bstart &&
+ is_overlapped(astart, asize, bstart, bsize) &&
+ !is_overlapped(astart, asize, bstart + bsize, bsize)) {
+ return false;
+ } else {
+ return MAX(aend, bend) - MIN(astart, bstart) < asize + bsize;
+ }
+}
+
static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
{
TCGv s1, s2, dst;
@@ -103,29 +156,121 @@ static bool vext_check_isa_ill(DisasContext *s)
}
/*
- * There are two rules check here.
+ * Check function for vector instruction with format:
+ * single-width result and single-width sources (SEW = SEW op SEW)
+ *
+ * is_vs1: indicates whether insn[19:15] is a vs1 field or not.
+ */
+#define VEXT_CHECK_SSS(s, rd, rs1, rs2, vm, is_vs1) do { \
+ require_vm(vm, rd); \
+ if (s->flmul > 1) { \
+ require_align(rd, s->flmul); \
+ require_align(rs2, s->flmul); \
+ if (is_vs1) { \
+ require_align(rs1, s->flmul); \
+ } \
+ } \
+} while (0)
+
+/*
+ * Check function for maskable vector instruction with format:
+ * single-width result and single-width sources (SEW = SEW op SEW)
*
- * 1. Vector register numbers are multiples of LMUL. (Section 3.2)
+ * is_vs1: indicates whether insn[19:15] is a vs1 field or not.
+ */
+#define VEXT_CHECK_MSS(s, rd, rs1, rs2, is_vs1) do { \
+ if (rd != rs2) { \
+ require_noover(rd, 1, rs2, s->flmul); \
+ } \
+ require_align(rs2, s->flmul); \
+ if (is_vs1) { \
+ if (rd != rs1) { \
+ require_noover(rd, 1, rs1, s->flmul); \
+ } \
+ require_align(rs1, s->flmul); \
+ } \
+} while (0)
+
+/* Common check function for vector widening instructions */
+#define VEXT_WIDE_CHECK_COMMON(s, rd, vm) do { \
+ require(s->flmul <= 4); \
+ require(s->sew < 3); \
+ require_align(rd, s->flmul * 2); \
+ require_vm(vm, rd); \
+} while (0)
+
+/* Common check function for vector narrowing instructions */
+#define VEXT_NARROW_CHECK_COMMON(s, rd, rs2, vm) do { \
+ require(s->flmul <= 4); \
+ require(s->sew < 3); \
+ require_align(rs2, s->flmul * 2); \
+ require_align(rd, s->flmul); \
+ require_vm(vm, rd); \
+} while (0)
+
+/*
+ * Check function for vector instruction with format:
+ * double-width result and single-width sources (2*SEW = SEW op SEW)
*
- * 2. For all widening instructions, the destination LMUL value must also be
- * a supported LMUL value. (Section 11.2)
+ * is_vs1: indicates whether insn[19:15] is a vs1 field or not.
*/
-static bool vext_check_reg(DisasContext *s, uint32_t reg, bool widen)
-{
- /*
- * The destination vector register group results are arranged as if both
- * SEW and LMUL were at twice their current settings. (Section 11.2).
- */
- int legal = widen ? 2 << s->lmul : 1 << s->lmul;
+#define VEXT_CHECK_DSS(s, rd, rs1, rs2, vm, is_vs1) do { \
+ VEXT_WIDE_CHECK_COMMON(s, rd, vm); \
+ require_align(rs2, s->flmul); \
+ if (s->flmul < 1) { \
+ require_noover(rd, s->flmul * 2, rs2, s->flmul); \
+ } else { \
+ require_noover_widen(rd, s->flmul * 2, rs2, s->flmul); \
+ } \
+ if (is_vs1) { \
+ require_align(rs1, s->flmul); \
+ if (s->flmul < 1) { \
+ require_noover(rd, s->flmul * 2, rs1, s->flmul); \
+ } else { \
+ require_noover_widen(rd, s->flmul * 2, rs1, s->flmul); \
+ } \
+ } \
+} while (0)
- return !((s->lmul == 0x3 && widen) || (reg % legal));
-}
+/*
+ * Check function for vector instruction with format:
+ * double-width result and double-width source1 and single-width
+ * source2 (2*SEW = 2*SEW op SEW)
+ *
+ * is_vs1: indicates whether insn[19:15] is a vs1 field or not.
+ */
+#define VEXT_CHECK_DDS(s, rd, rs1, rs2, vm, is_vs1) do { \
+ VEXT_WIDE_CHECK_COMMON(s, rd, vm); \
+ require_align(rs2, s->flmul * 2); \
+ if (is_vs1) { \
+ require_align(rs1, s->flmul); \
+ if (s->flmul < 1) { \
+ require_noover(rd, s->flmul * 2, rs1, s->flmul); \
+ } else { \
+ require_noover_widen(rd, s->flmul * 2, rs1, s->flmul); \
+ } \
+ } \
+} while (0)
/*
- * There are two rules check here.
+ * Check function for vector instruction with format:
+ * single-width result and double-width source1 and single-width
+ * source2 (SEW = 2*SEW op SEW)
*
- * 1. The destination vector register group for a masked vector instruction can
- * only overlap the source mask register (v0) when LMUL=1. (Section 5.3)
+ * is_vs1: indicates whether insn[19:15] is a vs1 field or not.
+ */
+#define VEXT_CHECK_SDS(s, rd, rs1, rs2, vm, is_vs1) do { \
+ VEXT_NARROW_CHECK_COMMON(s, rd, rs2, vm); \
+ if (rd != rs2) { \
+ require_noover(rd, s->flmul, rs2, s->flmul * 2); \
+ } \
+ if (is_vs1) { \
+ require_align(rs1, s->flmul); \
+ } \
+} while (0)
+
+/*
+ * Check function for vector reduction instructions
*
* 2. In widen instructions and some other insturctions, like vslideup.vx,
* there is no need to check whether LMUL=1.
@@ -136,20 +281,14 @@ static bool vext_check_overlap_mask(DisasContext *s, uint32_t vd, bool vm,
return (vm != 0 || vd != 0) || (!force && (s->lmul == 0));
}
-/* The LMUL setting must be such that LMUL * NFIELDS <= 8. (Section 7.8) */
-static bool vext_check_nf(DisasContext *s, uint32_t nf)
-{
- return (1 << s->lmul) * nf <= 8;
-}
-
/*
- * The destination vector register group cannot overlap a source vector register
- * group of a different element width. (Section 11.2)
+ * In cpu_get_tb_cpu_state(), set VILL if RVV was not present.
+ * So RVV is also be checked in this function.
*/
-static inline bool vext_check_overlap_group(int rd, int dlen, int rs, int slen)
-{
- return ((rd >= rs + slen) || (rs >= rd + dlen));
-}
+#define VEXT_CHECK_ISA_ILL(s) do { \
+ require(!s->vill) \
+} while (0)
+
/* common translation macro */
#define GEN_VEXT_TRANS(NAME, SEQ, ARGTYPE, OP, CHECK) \
static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\
@@ -824,11 +963,10 @@ GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check)
static bool opivv_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_SSS(s, a->rd, a->rs1, a->rs2, a->vm, true);
+ return true;
}
typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
@@ -922,10 +1060,10 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
static bool opivx_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_SSS(s, a->rd, a->rs1, a->rs2, a->vm, false);
+ return true;
}
typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t, TCGv_i64,
@@ -1129,16 +1267,10 @@ GEN_OPIVI_GVEC_TRANS(vrsub_vi, 0, vrsub_vx, rsubi)
/* OPIVV with WIDEN */
static bool opivv_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
- 1 << s->lmul) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_DSS(s, a->rd, a->rs1, a->rs2, a->vm, true);
+ return true;
}
static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
@@ -1185,13 +1317,10 @@ GEN_OPIVV_WIDEN_TRANS(vwsub_vv, opivv_widen_check)
/* OPIVX with WIDEN */
static bool opivx_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_DSS(s, a->rd, a->rs1, a->rs2, a->vm, false);
+ return true;
}
static bool do_opivx_widen(DisasContext *s, arg_rmrr *a,
@@ -1222,14 +1351,10 @@ GEN_OPIVX_WIDEN_TRANS(vwsub_vx)
/* WIDEN OPIVV with WIDEN */
static bool opiwv_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, true) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_DDS(s, a->rd, a->rs1, a->rs2, a->vm, true);
+ return true;
}
static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
@@ -1274,11 +1399,10 @@ GEN_OPIWV_WIDEN_TRANS(vwsub_wv)
/* WIDEN OPIVX with WIDEN */
static bool opiwx_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, true) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_DDS(s, a->rd, a->rs1, a->rs2, a->vm, false);
+ return true;
}
static bool do_opiwx_widen(DisasContext *s, arg_rmrr *a,
@@ -1341,11 +1465,11 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
*/
static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- ((a->rd != 0) || (s->lmul == 0)));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ require(a->rd != 0);
+ VEXT_CHECK_SSS(s, a->rd, a->rs1, a->rs2, a->vm, true);
+ return true;
}
GEN_OPIVV_TRANS(vadc_vvm, opivv_vadc_check)
@@ -1357,11 +1481,10 @@ GEN_OPIVV_TRANS(vsbc_vvm, opivv_vadc_check)
*/
static bool opivv_vmadc_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) &&
- vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_MSS(s, a->rd, a->rs1, a->rs2, true);
+ return true;
}
GEN_OPIVV_TRANS(vmadc_vvm, opivv_vmadc_check)
@@ -1369,10 +1492,11 @@ GEN_OPIVV_TRANS(vmsbc_vvm, opivv_vmadc_check)
static bool opivx_vadc_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- ((a->rd != 0) || (s->lmul == 0)));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ require(a->rd != 0);
+ VEXT_CHECK_SSS(s, a->rd, a->rs1, a->rs2, a->vm, false);
+ return true;
}
/* OPIVX without GVEC IR */
@@ -1395,9 +1519,10 @@ GEN_OPIVX_TRANS(vsbc_vxm, opivx_vadc_check)
static bool opivx_vmadc_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_MSS(s, a->rd, a->rs1, a->rs2, false);
+ return true;
}
GEN_OPIVX_TRANS(vmadc_vxm, opivx_vmadc_check)
@@ -1488,14 +1613,10 @@ GEN_OPIVI_TRANS(vsra_vi, 1, vsra_vx, opivx_check)
/* Vector Narrowing Integer Right Shift Instructions */
static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, true) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
- 2 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_SDS(s, a->rd, a->rs1, a->rs2, a->vm, true);
+ return true;
}
/* OPIVV with NARROW */
@@ -1531,13 +1652,10 @@ GEN_OPIVV_NARROW_TRANS(vnsrl_vv)
static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, true) &&
- vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
- 2 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_SDS(s, a->rd, a->rs1, a->rs2, a->vm, false);
+ return true;
}
/* OPIVX with NARROW */
@@ -1585,13 +1703,12 @@ GEN_OPIVI_NARROW_TRANS(vnsrl_vi, 1, vnsrl_vx)
*/
static bool opivv_cmp_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) &&
- vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) ||
- (s->lmul == 0)));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_MSS(s, a->rd, a->rs1, a->rs2, true);
+ return true;
}
+
GEN_OPIVV_TRANS(vmseq_vv, opivv_cmp_check)
GEN_OPIVV_TRANS(vmsne_vv, opivv_cmp_check)
GEN_OPIVV_TRANS(vmsltu_vv, opivv_cmp_check)
@@ -1601,10 +1718,10 @@ GEN_OPIVV_TRANS(vmsle_vv, opivv_cmp_check)
static bool opivx_cmp_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) ||
- (s->lmul == 0)));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_MSS(s, a->rd, a->rs1, a->rs2, false);
+ return true;
}
GEN_OPIVX_TRANS(vmseq_vx, opivx_cmp_check)
@@ -1863,12 +1980,11 @@ GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx)
*/
static bool opfvv_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- (s->sew != 0));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_SSS(s, a->rd, a->rs1, a->rs2, a->vm, true);
+ require(s->sew != 0);
+ return true;
}
/* OPFVV without GVEC IR */
@@ -1934,17 +2050,17 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
return true;
}
-static bool opfvf_check(DisasContext *s, arg_rmrr *a)
-{
/*
* If the current SEW does not correspond to a supported IEEE floating-point
* type, an illegal instruction exception is raised
*/
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- (s->sew != 0));
+static bool opfvf_check(DisasContext *s, arg_rmrr *a)
+{
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_SSS(s, a->rd, a->rs1, a->rs2, a->vm, false);
+ require(s->sew != 0);
+ return true;
}
/* OPFVF without GVEC IR */
@@ -1976,16 +2092,11 @@ GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check)
/* Vector Widening Floating-Point Add/Subtract Instructions */
static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
- 1 << s->lmul) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_DSS(s, a->rd, a->rs1, a->rs2, a->vm, true);
+ require(s->sew != 0);
+ return true;
}
/* OPFVV with WIDEN */
@@ -2021,13 +2132,11 @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_DSS(s, a->rd, a->rs1, a->rs2, a->vm, false);
+ require(s->sew != 0);
+ return true;
}
/* OPFVF with WIDEN */
@@ -2055,14 +2164,11 @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, true) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_DDS(s, a->rd, a->rs1, a->rs2, a->vm, true);
+ require(s->sew != 0);
+ return true;
}
/* WIDEN OPFVV with WIDEN */
@@ -2098,11 +2204,11 @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, true) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_DDS(s, a->rd, a->rs1, a->rs2, a->vm, false);
+ require(s->sew != 0);
+ return true;
}
/* WIDEN OPFVF with WIDEN */
@@ -2175,11 +2281,12 @@ GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf)
*/
static bool opfv_check(DisasContext *s, arg_rmr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- (s->sew != 0));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ /* OPFV instructions ignore vs1 check */
+ VEXT_CHECK_SSS(s, a->rd, 0, a->rs2, a->vm, false);
+ require(s->sew != 0);
+ return true;
}
#define GEN_OPFV_TRANS(NAME, CHECK) \
@@ -2229,13 +2336,11 @@ GEN_OPFVF_TRANS(vfsgnjx_vf, opfvf_check)
/* Vector Floating-Point Compare Instructions */
static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- (s->sew != 0) &&
- ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) &&
- vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) ||
- (s->lmul == 0)));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_MSS(s, a->rd, a->rs1, a->rs2, true);
+ require(s->sew != 0);
+ return true;
}
GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
@@ -2246,11 +2351,11 @@ GEN_OPFVV_TRANS(vmford_vv, opfvv_cmp_check)
static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- (s->sew != 0) &&
- (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) ||
- (s->lmul == 0)));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_MSS(s, a->rd, a->rs1, a->rs2, false);
+ require(s->sew != 0);
+ return true;
}
GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
@@ -2316,13 +2421,12 @@ GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check)
*/
static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ /* OPFV widening instructions ignore vs1 check */
+ VEXT_CHECK_DSS(s, a->rd, 0, a->rs2, a->vm, false);
+ require(s->sew != 0);
+ return true;
}
#define GEN_OPFV_WIDEN_TRANS(NAME) \
@@ -2366,13 +2470,12 @@ GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v)
*/
static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, true) &&
- vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
- 2 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ /* OPFV narrowing instructions ignore vs1 check */
+ VEXT_CHECK_SDS(s, a->rd, 0, a->rs2, a->vm, false);
+ require(s->sew != 0);
+ return true;
}
#define GEN_OPFV_NARROW_TRANS(NAME) \
@@ -2865,23 +2968,27 @@ GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check)
/* Vector Register Gather Instruction */
static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_reg(s, a->rs2, false) &&
- (a->rd != a->rs2) && (a->rd != a->rs1));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ require_align(a->rd, s->flmul);
+ require_align(a->rs1, s->flmul);
+ require_align(a->rs2, s->flmul);
+ require(a->rd != a->rs2 && a->rd != a->rs1);
+ require_vm(a->vm, a->rd);
+ return true;
}
GEN_OPIVV_TRANS(vrgather_vv, vrgather_vv_check)
static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- (a->rd != a->rs2));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ require_align(a->rd, s->flmul);
+ require_align(a->rs2, s->flmul);
+ require(a->rd != a->rs2);
+ require_vm(a->vm, a->rd);
+ return true;
}
/* vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */
@@ -2945,11 +3052,13 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
/* Vector Compress Instruction */
static bool vcompress_vm_check(DisasContext *s, arg_r *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs1, 1) &&
- (a->rd != a->rs2));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ require_align(a->rd, s->flmul);
+ require_align(a->rs2, s->flmul);
+ require(a->rd != a->rs2);
+ require_noover(a->rd, s->flmul, a->rs1, 1);
+ return true;
}
static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 13/65] target/riscv: rvv-0.9: configure instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 2 +-
target/riscv/insn_trans/trans_rvv.inc.c | 52 ++++++++++++-------------
target/riscv/vector_helper.c | 38 ++++++++++++------
3 files changed, 53 insertions(+), 39 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index acc298219d..5939897a82 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -83,7 +83,7 @@ DEF_HELPER_1(hyp_tlb_flush, void, env)
#endif
/* Vector functions */
-DEF_HELPER_3(vsetvl, tl, env, tl, tl)
+DEF_HELPER_5(vsetvl, tl, env, i32, i32, tl, tl)
DEF_HELPER_5(vlb_v_b, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlb_v_b_mask, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlb_v_h, void, ptr, ptr, tl, env, i32)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index fc1908389e..da8e7598e9 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -72,33 +72,32 @@ static inline bool is_overlapped_widen(const int astart, int asize,
}
}
-static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
+static bool trans_vsetvl(DisasContext *s, arg_vsetvl *a)
{
+ TCGv_i32 rd, rs1;
TCGv s1, s2, dst;
REQUIRE_RVV;
- if (!has_ext(ctx, RVV)) {
+ if (!has_ext(s, RVV)) {
return false;
}
+ rd = tcg_const_i32(a->rd);
+ rs1 = tcg_const_i32(a->rs1);
+ s1 = tcg_temp_new();
s2 = tcg_temp_new();
dst = tcg_temp_new();
- /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
- if (a->rs1 == 0) {
- /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
- s1 = tcg_const_tl(RV_VLEN_MAX);
- } else {
- s1 = tcg_temp_new();
- gen_get_gpr(s1, a->rs1);
- }
+ gen_get_gpr(s1, a->rs1);
gen_get_gpr(s2, a->rs2);
- gen_helper_vsetvl(dst, cpu_env, s1, s2);
+ gen_helper_vsetvl(dst, cpu_env, rd, rs1, s1, s2);
gen_set_gpr(a->rd, dst);
- tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- lookup_and_goto_ptr(ctx);
- ctx->base.is_jmp = DISAS_NORETURN;
+ tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn);
+ lookup_and_goto_ptr(s);
+ s->base.is_jmp = DISAS_NORETURN;
+ tcg_temp_free_i32(rd);
+ tcg_temp_free_i32(rs1);
tcg_temp_free(s1);
tcg_temp_free(s2);
tcg_temp_free(dst);
@@ -106,31 +105,30 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
return true;
}
-static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
+static bool trans_vsetvli(DisasContext *s, arg_vsetvli *a)
{
+ TCGv_i32 rd, rs1;
TCGv s1, s2, dst;
REQUIRE_RVV;
- if (!has_ext(ctx, RVV)) {
+ if (!has_ext(s, RVV)) {
return false;
}
+ rd = tcg_const_i32(a->rd);
+ rs1 = tcg_const_i32(a->rs1);
+ s1 = tcg_temp_new();
s2 = tcg_const_tl(a->zimm);
dst = tcg_temp_new();
- /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
- if (a->rs1 == 0) {
- /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
- s1 = tcg_const_tl(RV_VLEN_MAX);
- } else {
- s1 = tcg_temp_new();
- gen_get_gpr(s1, a->rs1);
- }
- gen_helper_vsetvl(dst, cpu_env, s1, s2);
+ gen_get_gpr(s1, a->rs1);
+ gen_helper_vsetvl(dst, cpu_env, rd, rs1, s1, s2);
gen_set_gpr(a->rd, dst);
- gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
- ctx->base.is_jmp = DISAS_NORETURN;
+ gen_goto_tb(s, 0, s->pc_succ_insn);
+ s->base.is_jmp = DISAS_NORETURN;
+ tcg_temp_free_i32(rd);
+ tcg_temp_free_i32(rs1);
tcg_temp_free(s1);
tcg_temp_free(s2);
tcg_temp_free(dst);
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index db54288c08..1279ef4fb1 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -26,33 +26,49 @@
#include "internals.h"
#include <math.h>
-target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
- target_ulong s2)
+target_ulong HELPER(vsetvl)(CPURISCVState *env, uint32_t rd, uint32_t rs1,
+ target_ulong s1, target_ulong s2)
{
- int vlmax, vl;
+ int vlmax;
+ int vl = 0;
+
RISCVCPU *cpu = env_archcpu(env);
uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW);
uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
bool vill = FIELD_EX64(s2, VTYPE, VILL);
+ vlmax = vext_get_vlmax(cpu, s2);
target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED);
- if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
+ uint64_t lmul = (FIELD_EX64(s2, VTYPE, VFLMUL) << 2)
+ | FIELD_EX64(s2, VTYPE, VLMUL);
+ float vflmul = flmul_table[lmul];
+
+ if ((sew > cpu->cfg.elen)
+ || vill
+ || vflmul < ((float)sew / cpu->cfg.elen)
+ || (ediv != 0)
+ || (reserved != 0)) {
/* only set vill bit. */
env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
- env->vl = 0;
- env->vstart = 0;
return 0;
}
- vlmax = vext_get_vlmax(cpu, s2);
- if (s1 <= vlmax) {
- vl = s1;
- } else {
+ /* set vl */
+ if (rd == 0 && rs1 == 0) {
+ /* keep existing vl */
+ vl = env->vl > vlmax ? vlmax : env->vl;
+ } else if (rd != 0 && rs1 == 0) {
+ /* set vl to vlmax */
vl = vlmax;
+ } else if (rs1 != 0) {
+ /* normal stripmining */
+ vl = s1 > vlmax ? vlmax : s1;
}
- env->vl = vl;
+
env->vtype = s2;
env->vstart = 0;
+ env->vl = vl;
+
return vl;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 13/65] target/riscv: rvv-0.9: configure instructions
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 2 +-
target/riscv/insn_trans/trans_rvv.inc.c | 52 ++++++++++++-------------
target/riscv/vector_helper.c | 38 ++++++++++++------
3 files changed, 53 insertions(+), 39 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index acc298219d..5939897a82 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -83,7 +83,7 @@ DEF_HELPER_1(hyp_tlb_flush, void, env)
#endif
/* Vector functions */
-DEF_HELPER_3(vsetvl, tl, env, tl, tl)
+DEF_HELPER_5(vsetvl, tl, env, i32, i32, tl, tl)
DEF_HELPER_5(vlb_v_b, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlb_v_b_mask, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlb_v_h, void, ptr, ptr, tl, env, i32)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index fc1908389e..da8e7598e9 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -72,33 +72,32 @@ static inline bool is_overlapped_widen(const int astart, int asize,
}
}
-static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
+static bool trans_vsetvl(DisasContext *s, arg_vsetvl *a)
{
+ TCGv_i32 rd, rs1;
TCGv s1, s2, dst;
REQUIRE_RVV;
- if (!has_ext(ctx, RVV)) {
+ if (!has_ext(s, RVV)) {
return false;
}
+ rd = tcg_const_i32(a->rd);
+ rs1 = tcg_const_i32(a->rs1);
+ s1 = tcg_temp_new();
s2 = tcg_temp_new();
dst = tcg_temp_new();
- /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
- if (a->rs1 == 0) {
- /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
- s1 = tcg_const_tl(RV_VLEN_MAX);
- } else {
- s1 = tcg_temp_new();
- gen_get_gpr(s1, a->rs1);
- }
+ gen_get_gpr(s1, a->rs1);
gen_get_gpr(s2, a->rs2);
- gen_helper_vsetvl(dst, cpu_env, s1, s2);
+ gen_helper_vsetvl(dst, cpu_env, rd, rs1, s1, s2);
gen_set_gpr(a->rd, dst);
- tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- lookup_and_goto_ptr(ctx);
- ctx->base.is_jmp = DISAS_NORETURN;
+ tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn);
+ lookup_and_goto_ptr(s);
+ s->base.is_jmp = DISAS_NORETURN;
+ tcg_temp_free_i32(rd);
+ tcg_temp_free_i32(rs1);
tcg_temp_free(s1);
tcg_temp_free(s2);
tcg_temp_free(dst);
@@ -106,31 +105,30 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
return true;
}
-static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
+static bool trans_vsetvli(DisasContext *s, arg_vsetvli *a)
{
+ TCGv_i32 rd, rs1;
TCGv s1, s2, dst;
REQUIRE_RVV;
- if (!has_ext(ctx, RVV)) {
+ if (!has_ext(s, RVV)) {
return false;
}
+ rd = tcg_const_i32(a->rd);
+ rs1 = tcg_const_i32(a->rs1);
+ s1 = tcg_temp_new();
s2 = tcg_const_tl(a->zimm);
dst = tcg_temp_new();
- /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
- if (a->rs1 == 0) {
- /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
- s1 = tcg_const_tl(RV_VLEN_MAX);
- } else {
- s1 = tcg_temp_new();
- gen_get_gpr(s1, a->rs1);
- }
- gen_helper_vsetvl(dst, cpu_env, s1, s2);
+ gen_get_gpr(s1, a->rs1);
+ gen_helper_vsetvl(dst, cpu_env, rd, rs1, s1, s2);
gen_set_gpr(a->rd, dst);
- gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
- ctx->base.is_jmp = DISAS_NORETURN;
+ gen_goto_tb(s, 0, s->pc_succ_insn);
+ s->base.is_jmp = DISAS_NORETURN;
+ tcg_temp_free_i32(rd);
+ tcg_temp_free_i32(rs1);
tcg_temp_free(s1);
tcg_temp_free(s2);
tcg_temp_free(dst);
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index db54288c08..1279ef4fb1 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -26,33 +26,49 @@
#include "internals.h"
#include <math.h>
-target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
- target_ulong s2)
+target_ulong HELPER(vsetvl)(CPURISCVState *env, uint32_t rd, uint32_t rs1,
+ target_ulong s1, target_ulong s2)
{
- int vlmax, vl;
+ int vlmax;
+ int vl = 0;
+
RISCVCPU *cpu = env_archcpu(env);
uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW);
uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
bool vill = FIELD_EX64(s2, VTYPE, VILL);
+ vlmax = vext_get_vlmax(cpu, s2);
target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED);
- if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
+ uint64_t lmul = (FIELD_EX64(s2, VTYPE, VFLMUL) << 2)
+ | FIELD_EX64(s2, VTYPE, VLMUL);
+ float vflmul = flmul_table[lmul];
+
+ if ((sew > cpu->cfg.elen)
+ || vill
+ || vflmul < ((float)sew / cpu->cfg.elen)
+ || (ediv != 0)
+ || (reserved != 0)) {
/* only set vill bit. */
env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
- env->vl = 0;
- env->vstart = 0;
return 0;
}
- vlmax = vext_get_vlmax(cpu, s2);
- if (s1 <= vlmax) {
- vl = s1;
- } else {
+ /* set vl */
+ if (rd == 0 && rs1 == 0) {
+ /* keep existing vl */
+ vl = env->vl > vlmax ? vlmax : env->vl;
+ } else if (rd != 0 && rs1 == 0) {
+ /* set vl to vlmax */
vl = vlmax;
+ } else if (rs1 != 0) {
+ /* normal stripmining */
+ vl = s1 > vlmax ? vlmax : s1;
}
- env->vl = vl;
+
env->vtype = s2;
env->vstart = 0;
+ env->vl = vl;
+
return vl;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 129 +++------------
target/riscv/insn32.decode | 43 +++--
target/riscv/insn_trans/trans_rvv.inc.c | 206 ++++++++++--------------
target/riscv/vector_helper.c | 175 ++++++--------------
4 files changed, 171 insertions(+), 382 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 5939897a82..73386b37c7 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -84,111 +84,30 @@ DEF_HELPER_1(hyp_tlb_flush, void, env)
/* Vector functions */
DEF_HELPER_5(vsetvl, tl, env, i32, i32, tl, tl)
-DEF_HELPER_5(vlb_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlb_v_b_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlb_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlb_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlb_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlb_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlb_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlb_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlh_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlh_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlh_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlh_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlh_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlh_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlw_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlw_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlw_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlw_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_b_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_b_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhu_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhu_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhu_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhu_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhu_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhu_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwu_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwu_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwu_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwu_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_b_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsh_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsh_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsh_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsh_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsh_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsh_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsw_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsw_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsw_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsw_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_b_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_6(vlsb_v_b, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsb_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsb_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsb_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsh_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsh_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsh_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsw_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsw_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlse_v_b, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlse_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlse_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlse_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsbu_v_b, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsbu_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsbu_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsbu_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlshu_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlshu_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlshu_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlswu_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlswu_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssb_v_b, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssb_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssb_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssb_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssh_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssh_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssh_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssw_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssw_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vsse_v_b, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vsse_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vsse_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vsse_v_d, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_5(vle8_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle16_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle32_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle64_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle8_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle16_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle32_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle64_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse8_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse16_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse32_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse64_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse8_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse16_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse32_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse64_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_6(vlse8_v, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_6(vlse16_v, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_6(vlse32_v, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_6(vlse64_v, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_6(vsse8_v, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_6(vsse16_v, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_6(vsse32_v, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_6(vsse64_v, void, ptr, ptr, tl, tl, env, i32)
DEF_HELPER_6(vlxb_v_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vlxb_v_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vlxb_v_w, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index bdd8563067..012c844f60 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -229,13 +229,26 @@ hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
# *** RV32V Extension ***
# *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
-vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
-vlh_v ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm
-vlw_v ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm
-vle_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
-vlbu_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
-vlhu_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
-vlwu_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
+# Vector unit-stride load/store insns.
+vle8_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
+vle16_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
+vle32_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
+vle64_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
+vse8_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
+vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
+vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
+vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
+
+# Vector strided insns.
+vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
+vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
+vlse32_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
+vlse64_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
+vsse8_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
+vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
+vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
+vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
+
vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm
vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm
vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm
@@ -243,22 +256,6 @@ vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
-vsb_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
-vsh_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
-vsw_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
-vse_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
-
-vlsb_v ... 110 . ..... ..... 000 ..... 0000111 @r_nfvm
-vlsh_v ... 110 . ..... ..... 101 ..... 0000111 @r_nfvm
-vlsw_v ... 110 . ..... ..... 110 ..... 0000111 @r_nfvm
-vlse_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
-vlsbu_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
-vlshu_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
-vlswu_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
-vssb_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
-vssh_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
-vssw_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
-vsse_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
vlxb_v ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm
vlxh_v ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index da8e7598e9..6f54b63453 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -145,8 +145,26 @@ static uint32_t vreg_ofs(DisasContext *s, int reg)
/* check functions */
/*
- * In cpu_get_tb_cpu_state(), set VILL if RVV was not present.
- * So RVV is also be checked in this function.
+ * Vector unit-stride, strided, unit-stride segment, strided segment
+ * store check function.
+ */
+#define VEXT_CHECK_STORE(s, rd, nf) do { \
+ uint32_t emul_r = s->emul < 1 ? 1 : s->emul; \
+ require(s->emul >= 0.125 && s->emul <= 8); \
+ require_align(rd, s->emul); \
+ require((nf * emul_r) <= (NVPR / 4) && \
+ (rd + nf * emul_r) <= NVPR); \
+} while (0)
+
+/*
+ * Vector unit-stride, strided, unit-stride segment, strided segment
+ * load check function.
+ */
+#define VEXT_CHECK_LOAD(s, rd, nf, vm) do { \
+ VEXT_CHECK_STORE(s, rd, nf); \
+ require_vm(vm, rd); \
+} while (0)
+
*/
static bool vext_check_isa_ill(DisasContext *s)
{
@@ -288,13 +306,15 @@ static bool vext_check_overlap_mask(DisasContext *s, uint32_t vd, bool vm,
} while (0)
/* common translation macro */
-#define GEN_VEXT_TRANS(NAME, SEQ, ARGTYPE, OP, CHECK) \
-static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\
-{ \
- if (CHECK(s, a)) { \
- return OP(s, a, SEQ); \
- } \
- return false; \
+#define GEN_VEXT_TRANS(NAME, EEW, SEQ, ARGTYPE, OP, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE * a) \
+{ \
+ s->eew = EEW; \
+ s->emul = (float)EEW / (1 << (s->sew + 3)) * s->flmul; \
+ if (CHECK(s, a)) { \
+ return OP(s, a, SEQ); \
+ } \
+ return false; \
}
/*
@@ -344,41 +364,17 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_ldst_us *fn;
- static gen_helper_ldst_us * const fns[2][7][4] = {
+ static gen_helper_ldst_us * const fns[2][4] = {
/* masked unit stride load */
- { { gen_helper_vlb_v_b_mask, gen_helper_vlb_v_h_mask,
- gen_helper_vlb_v_w_mask, gen_helper_vlb_v_d_mask },
- { NULL, gen_helper_vlh_v_h_mask,
- gen_helper_vlh_v_w_mask, gen_helper_vlh_v_d_mask },
- { NULL, NULL,
- gen_helper_vlw_v_w_mask, gen_helper_vlw_v_d_mask },
- { gen_helper_vle_v_b_mask, gen_helper_vle_v_h_mask,
- gen_helper_vle_v_w_mask, gen_helper_vle_v_d_mask },
- { gen_helper_vlbu_v_b_mask, gen_helper_vlbu_v_h_mask,
- gen_helper_vlbu_v_w_mask, gen_helper_vlbu_v_d_mask },
- { NULL, gen_helper_vlhu_v_h_mask,
- gen_helper_vlhu_v_w_mask, gen_helper_vlhu_v_d_mask },
- { NULL, NULL,
- gen_helper_vlwu_v_w_mask, gen_helper_vlwu_v_d_mask } },
+ { gen_helper_vle8_v_mask, gen_helper_vle16_v_mask,
+ gen_helper_vle32_v_mask, gen_helper_vle64_v_mask },
/* unmasked unit stride load */
- { { gen_helper_vlb_v_b, gen_helper_vlb_v_h,
- gen_helper_vlb_v_w, gen_helper_vlb_v_d },
- { NULL, gen_helper_vlh_v_h,
- gen_helper_vlh_v_w, gen_helper_vlh_v_d },
- { NULL, NULL,
- gen_helper_vlw_v_w, gen_helper_vlw_v_d },
- { gen_helper_vle_v_b, gen_helper_vle_v_h,
- gen_helper_vle_v_w, gen_helper_vle_v_d },
- { gen_helper_vlbu_v_b, gen_helper_vlbu_v_h,
- gen_helper_vlbu_v_w, gen_helper_vlbu_v_d },
- { NULL, gen_helper_vlhu_v_h,
- gen_helper_vlhu_v_w, gen_helper_vlhu_v_d },
- { NULL, NULL,
- gen_helper_vlwu_v_w, gen_helper_vlwu_v_d } }
+ { gen_helper_vle8_v, gen_helper_vle16_v,
+ gen_helper_vle32_v, gen_helper_vle64_v }
};
bool ret;
- fn = fns[a->vm][seq][s->sew];
+ fn = fns[a->vm][seq];
if (fn == NULL) {
return false;
}
@@ -396,46 +392,31 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
static bool ld_us_check(DisasContext *s, arg_r2nfvm* a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_nf(s, a->nf));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_LOAD(s, a->rd, a->nf, a->vm);
+ return true;
}
-GEN_VEXT_TRANS(vlb_v, 0, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vlh_v, 1, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vlw_v, 2, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vle_v, 3, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vlbu_v, 4, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vlhu_v, 5, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vlwu_v, 6, r2nfvm, ld_us_op, ld_us_check)
+GEN_VEXT_TRANS(vle8_v, 8, 0, r2nfvm, ld_us_op, ld_us_check)
+GEN_VEXT_TRANS(vle16_v, 16, 1, r2nfvm, ld_us_op, ld_us_check)
+GEN_VEXT_TRANS(vle32_v, 32, 2, r2nfvm, ld_us_op, ld_us_check)
+GEN_VEXT_TRANS(vle64_v, 64, 3, r2nfvm, ld_us_op, ld_us_check)
static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_ldst_us *fn;
- static gen_helper_ldst_us * const fns[2][4][4] = {
- /* masked unit stride load and store */
- { { gen_helper_vsb_v_b_mask, gen_helper_vsb_v_h_mask,
- gen_helper_vsb_v_w_mask, gen_helper_vsb_v_d_mask },
- { NULL, gen_helper_vsh_v_h_mask,
- gen_helper_vsh_v_w_mask, gen_helper_vsh_v_d_mask },
- { NULL, NULL,
- gen_helper_vsw_v_w_mask, gen_helper_vsw_v_d_mask },
- { gen_helper_vse_v_b_mask, gen_helper_vse_v_h_mask,
- gen_helper_vse_v_w_mask, gen_helper_vse_v_d_mask } },
+ static gen_helper_ldst_us * const fns[2][4] = {
+ /* masked unit stride store */
+ { gen_helper_vse8_v_mask, gen_helper_vse16_v_mask,
+ gen_helper_vse32_v_mask, gen_helper_vse64_v_mask },
/* unmasked unit stride store */
- { { gen_helper_vsb_v_b, gen_helper_vsb_v_h,
- gen_helper_vsb_v_w, gen_helper_vsb_v_d },
- { NULL, gen_helper_vsh_v_h,
- gen_helper_vsh_v_w, gen_helper_vsh_v_d },
- { NULL, NULL,
- gen_helper_vsw_v_w, gen_helper_vsw_v_d },
- { gen_helper_vse_v_b, gen_helper_vse_v_h,
- gen_helper_vse_v_w, gen_helper_vse_v_d } }
+ { gen_helper_vse8_v, gen_helper_vse16_v,
+ gen_helper_vse32_v, gen_helper_vse64_v }
};
- fn = fns[a->vm][seq][s->sew];
+ fn = fns[a->vm][seq];
if (fn == NULL) {
return false;
}
@@ -451,15 +432,16 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
static bool st_us_check(DisasContext *s, arg_r2nfvm* a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_nf(s, a->nf));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_STORE(s, a->rd, a->nf);
+ return true;
}
-GEN_VEXT_TRANS(vsb_v, 0, r2nfvm, st_us_op, st_us_check)
-GEN_VEXT_TRANS(vsh_v, 1, r2nfvm, st_us_op, st_us_check)
-GEN_VEXT_TRANS(vsw_v, 2, r2nfvm, st_us_op, st_us_check)
-GEN_VEXT_TRANS(vse_v, 3, r2nfvm, st_us_op, st_us_check)
+GEN_VEXT_TRANS(vse8_v, 8, 0, r2nfvm, st_us_op, st_us_check)
+GEN_VEXT_TRANS(vse16_v, 16, 1, r2nfvm, st_us_op, st_us_check)
+GEN_VEXT_TRANS(vse32_v, 32, 2, r2nfvm, st_us_op, st_us_check)
+GEN_VEXT_TRANS(vse64_v, 64, 3, r2nfvm, st_us_op, st_us_check)
/*
*** stride load and store
@@ -504,28 +486,13 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_ldst_stride *fn;
- static gen_helper_ldst_stride * const fns[7][4] = {
- { gen_helper_vlsb_v_b, gen_helper_vlsb_v_h,
- gen_helper_vlsb_v_w, gen_helper_vlsb_v_d },
- { NULL, gen_helper_vlsh_v_h,
- gen_helper_vlsh_v_w, gen_helper_vlsh_v_d },
- { NULL, NULL,
- gen_helper_vlsw_v_w, gen_helper_vlsw_v_d },
- { gen_helper_vlse_v_b, gen_helper_vlse_v_h,
- gen_helper_vlse_v_w, gen_helper_vlse_v_d },
- { gen_helper_vlsbu_v_b, gen_helper_vlsbu_v_h,
- gen_helper_vlsbu_v_w, gen_helper_vlsbu_v_d },
- { NULL, gen_helper_vlshu_v_h,
- gen_helper_vlshu_v_w, gen_helper_vlshu_v_d },
- { NULL, NULL,
- gen_helper_vlswu_v_w, gen_helper_vlswu_v_d },
+ static gen_helper_ldst_stride * const fns[4] = {
+ gen_helper_vlse8_v, gen_helper_vlse16_v,
+ gen_helper_vlse32_v, gen_helper_vlse64_v
};
bool ret;
- fn = fns[seq][s->sew];
- if (fn == NULL) {
- return false;
- }
+ fn = fns[seq];
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -540,40 +507,28 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
static bool ld_stride_check(DisasContext *s, arg_rnfvm* a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_nf(s, a->nf));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_LOAD(s, a->rd, a->nf, a->vm);
+ return true;
}
-GEN_VEXT_TRANS(vlsb_v, 0, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlsh_v, 1, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlsw_v, 2, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlse_v, 3, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlsbu_v, 4, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlshu_v, 5, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlswu_v, 6, rnfvm, ld_stride_op, ld_stride_check)
+GEN_VEXT_TRANS(vlse8_v, 8, 0, rnfvm, ld_stride_op, ld_stride_check)
+GEN_VEXT_TRANS(vlse16_v, 16, 1, rnfvm, ld_stride_op, ld_stride_check)
+GEN_VEXT_TRANS(vlse32_v, 32, 2, rnfvm, ld_stride_op, ld_stride_check)
+GEN_VEXT_TRANS(vlse64_v, 64, 3, rnfvm, ld_stride_op, ld_stride_check)
static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_ldst_stride *fn;
- static gen_helper_ldst_stride * const fns[4][4] = {
+ static gen_helper_ldst_stride * const fns[4] = {
/* masked stride store */
- { gen_helper_vssb_v_b, gen_helper_vssb_v_h,
- gen_helper_vssb_v_w, gen_helper_vssb_v_d },
- { NULL, gen_helper_vssh_v_h,
- gen_helper_vssh_v_w, gen_helper_vssh_v_d },
- { NULL, NULL,
- gen_helper_vssw_v_w, gen_helper_vssw_v_d },
- { gen_helper_vsse_v_b, gen_helper_vsse_v_h,
- gen_helper_vsse_v_w, gen_helper_vsse_v_d }
+ gen_helper_vsse8_v, gen_helper_vsse16_v,
+ gen_helper_vsse32_v, gen_helper_vsse64_v
};
fn = fns[seq];
- if (fn == NULL) {
- return false;
- }
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -587,15 +542,16 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
static bool st_stride_check(DisasContext *s, arg_rnfvm* a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_nf(s, a->nf));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_STORE(s, a->rd, a->nf);
+ return true;
}
-GEN_VEXT_TRANS(vssb_v, 0, rnfvm, st_stride_op, st_stride_check)
-GEN_VEXT_TRANS(vssh_v, 1, rnfvm, st_stride_op, st_stride_check)
-GEN_VEXT_TRANS(vssw_v, 2, rnfvm, st_stride_op, st_stride_check)
-GEN_VEXT_TRANS(vsse_v, 3, rnfvm, st_stride_op, st_stride_check)
+GEN_VEXT_TRANS(vsse8_v, 8, 0, rnfvm, st_stride_op, st_stride_check)
+GEN_VEXT_TRANS(vsse16_v, 16, 1, rnfvm, st_stride_op, st_stride_check)
+GEN_VEXT_TRANS(vsse32_v, 32, 2, rnfvm, st_stride_op, st_stride_check)
+GEN_VEXT_TRANS(vsse64_v, 64, 3, rnfvm, st_stride_op, st_stride_check)
/*
*** index load and store
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 1279ef4fb1..0b95e851ae 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -256,38 +256,20 @@ typedef void vext_ldst_elem_fn(CPURISCVState *env, target_ulong addr,
typedef void clear_fn(void *vd, uint32_t vta, uint32_t idx,
uint32_t cnt, uint32_t tot);
-#define GEN_VEXT_LD_ELEM(NAME, MTYPE, ETYPE, H, LDSUF) \
+#define GEN_VEXT_LD_ELEM(NAME, ETYPE, H, LDSUF) \
static void NAME(CPURISCVState *env, abi_ptr addr, \
uint32_t idx, void *vd, uintptr_t retaddr)\
{ \
- MTYPE data; \
+ ETYPE data; \
ETYPE *cur = ((ETYPE *)vd + H(idx)); \
data = cpu_##LDSUF##_data_ra(env, addr, retaddr); \
*cur = data; \
} \
-GEN_VEXT_LD_ELEM(ldb_b, int8_t, int8_t, H1, ldsb)
-GEN_VEXT_LD_ELEM(ldb_h, int8_t, int16_t, H2, ldsb)
-GEN_VEXT_LD_ELEM(ldb_w, int8_t, int32_t, H4, ldsb)
-GEN_VEXT_LD_ELEM(ldb_d, int8_t, int64_t, H8, ldsb)
-GEN_VEXT_LD_ELEM(ldh_h, int16_t, int16_t, H2, ldsw)
-GEN_VEXT_LD_ELEM(ldh_w, int16_t, int32_t, H4, ldsw)
-GEN_VEXT_LD_ELEM(ldh_d, int16_t, int64_t, H8, ldsw)
-GEN_VEXT_LD_ELEM(ldw_w, int32_t, int32_t, H4, ldl)
-GEN_VEXT_LD_ELEM(ldw_d, int32_t, int64_t, H8, ldl)
-GEN_VEXT_LD_ELEM(lde_b, int8_t, int8_t, H1, ldsb)
-GEN_VEXT_LD_ELEM(lde_h, int16_t, int16_t, H2, ldsw)
-GEN_VEXT_LD_ELEM(lde_w, int32_t, int32_t, H4, ldl)
-GEN_VEXT_LD_ELEM(lde_d, int64_t, int64_t, H8, ldq)
-GEN_VEXT_LD_ELEM(ldbu_b, uint8_t, uint8_t, H1, ldub)
-GEN_VEXT_LD_ELEM(ldbu_h, uint8_t, uint16_t, H2, ldub)
-GEN_VEXT_LD_ELEM(ldbu_w, uint8_t, uint32_t, H4, ldub)
-GEN_VEXT_LD_ELEM(ldbu_d, uint8_t, uint64_t, H8, ldub)
-GEN_VEXT_LD_ELEM(ldhu_h, uint16_t, uint16_t, H2, lduw)
-GEN_VEXT_LD_ELEM(ldhu_w, uint16_t, uint32_t, H4, lduw)
-GEN_VEXT_LD_ELEM(ldhu_d, uint16_t, uint64_t, H8, lduw)
-GEN_VEXT_LD_ELEM(ldwu_w, uint32_t, uint32_t, H4, ldl)
-GEN_VEXT_LD_ELEM(ldwu_d, uint32_t, uint64_t, H8, ldl)
+GEN_VEXT_LD_ELEM(lde_b, int8_t, H1, ldsb)
+GEN_VEXT_LD_ELEM(lde_h, int16_t, H2, ldsw)
+GEN_VEXT_LD_ELEM(lde_w, int32_t, H4, ldl)
+GEN_VEXT_LD_ELEM(lde_d, int64_t, H8, ldq)
#define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \
static void NAME(CPURISCVState *env, abi_ptr addr, \
@@ -297,15 +279,6 @@ static void NAME(CPURISCVState *env, abi_ptr addr, \
cpu_##STSUF##_data_ra(env, addr, data, retaddr); \
}
-GEN_VEXT_ST_ELEM(stb_b, int8_t, H1, stb)
-GEN_VEXT_ST_ELEM(stb_h, int16_t, H2, stb)
-GEN_VEXT_ST_ELEM(stb_w, int32_t, H4, stb)
-GEN_VEXT_ST_ELEM(stb_d, int64_t, H8, stb)
-GEN_VEXT_ST_ELEM(sth_h, int16_t, H2, stw)
-GEN_VEXT_ST_ELEM(sth_w, int32_t, H4, stw)
-GEN_VEXT_ST_ELEM(sth_d, int64_t, H8, stw)
-GEN_VEXT_ST_ELEM(stw_w, int32_t, H4, stl)
-GEN_VEXT_ST_ELEM(stw_d, int64_t, H8, stl)
GEN_VEXT_ST_ELEM(ste_b, int8_t, H1, stb)
GEN_VEXT_ST_ELEM(ste_h, int16_t, H2, stw)
GEN_VEXT_ST_ELEM(ste_w, int32_t, H4, stl)
@@ -319,8 +292,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
target_ulong stride, CPURISCVState *env,
uint32_t desc, uint32_t vm,
vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
- uint32_t esz, uint32_t msz, uintptr_t ra,
- MMUAccessType access_type)
+ uint32_t esz, uintptr_t ra, MMUAccessType access_type)
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
@@ -332,7 +304,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
- probe_pages(env, base + stride * i, nf * msz, ra, access_type);
+ probe_pages(env, base + stride * i, nf * esz, ra, access_type);
}
/* do real access */
for (i = 0; i < env->vl; i++) {
@@ -341,7 +313,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
continue;
}
while (k < nf) {
- target_ulong addr = base + stride * i + k * msz;
+ target_ulong addr = base + stride * i + k * esz;
ldst_elem(env, addr, i + k * vlmax, vd, ra);
k++;
}
@@ -355,64 +327,37 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
}
}
-#define GEN_VEXT_LD_STRIDE(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
+#define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN, CLEAR_FN) \
void HELPER(NAME)(void *vd, void * v0, target_ulong base, \
target_ulong stride, CPURISCVState *env, \
uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN, \
- CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
+ CLEAR_FN, sizeof(ETYPE), \
GETPC(), MMU_DATA_LOAD); \
}
-GEN_VEXT_LD_STRIDE(vlsb_v_b, int8_t, int8_t, ldb_b, clearb)
-GEN_VEXT_LD_STRIDE(vlsb_v_h, int8_t, int16_t, ldb_h, clearh)
-GEN_VEXT_LD_STRIDE(vlsb_v_w, int8_t, int32_t, ldb_w, clearl)
-GEN_VEXT_LD_STRIDE(vlsb_v_d, int8_t, int64_t, ldb_d, clearq)
-GEN_VEXT_LD_STRIDE(vlsh_v_h, int16_t, int16_t, ldh_h, clearh)
-GEN_VEXT_LD_STRIDE(vlsh_v_w, int16_t, int32_t, ldh_w, clearl)
-GEN_VEXT_LD_STRIDE(vlsh_v_d, int16_t, int64_t, ldh_d, clearq)
-GEN_VEXT_LD_STRIDE(vlsw_v_w, int32_t, int32_t, ldw_w, clearl)
-GEN_VEXT_LD_STRIDE(vlsw_v_d, int32_t, int64_t, ldw_d, clearq)
-GEN_VEXT_LD_STRIDE(vlse_v_b, int8_t, int8_t, lde_b, clearb)
-GEN_VEXT_LD_STRIDE(vlse_v_h, int16_t, int16_t, lde_h, clearh)
-GEN_VEXT_LD_STRIDE(vlse_v_w, int32_t, int32_t, lde_w, clearl)
-GEN_VEXT_LD_STRIDE(vlse_v_d, int64_t, int64_t, lde_d, clearq)
-GEN_VEXT_LD_STRIDE(vlsbu_v_b, uint8_t, uint8_t, ldbu_b, clearb)
-GEN_VEXT_LD_STRIDE(vlsbu_v_h, uint8_t, uint16_t, ldbu_h, clearh)
-GEN_VEXT_LD_STRIDE(vlsbu_v_w, uint8_t, uint32_t, ldbu_w, clearl)
-GEN_VEXT_LD_STRIDE(vlsbu_v_d, uint8_t, uint64_t, ldbu_d, clearq)
-GEN_VEXT_LD_STRIDE(vlshu_v_h, uint16_t, uint16_t, ldhu_h, clearh)
-GEN_VEXT_LD_STRIDE(vlshu_v_w, uint16_t, uint32_t, ldhu_w, clearl)
-GEN_VEXT_LD_STRIDE(vlshu_v_d, uint16_t, uint64_t, ldhu_d, clearq)
-GEN_VEXT_LD_STRIDE(vlswu_v_w, uint32_t, uint32_t, ldwu_w, clearl)
-GEN_VEXT_LD_STRIDE(vlswu_v_d, uint32_t, uint64_t, ldwu_d, clearq)
-
-#define GEN_VEXT_ST_STRIDE(NAME, MTYPE, ETYPE, STORE_FN) \
+GEN_VEXT_LD_STRIDE(vlse8_v, int8_t, lde_b, clearb)
+GEN_VEXT_LD_STRIDE(vlse16_v, int16_t, lde_h, clearh)
+GEN_VEXT_LD_STRIDE(vlse32_v, int32_t, lde_w, clearl)
+GEN_VEXT_LD_STRIDE(vlse64_v, int64_t, lde_d, clearq)
+
+#define GEN_VEXT_ST_STRIDE(NAME, ETYPE, STORE_FN) \
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
target_ulong stride, CPURISCVState *env, \
uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
vext_ldst_stride(vd, v0, base, stride, env, desc, vm, STORE_FN, \
- NULL, sizeof(ETYPE), sizeof(MTYPE), \
+ NULL, sizeof(ETYPE), \
GETPC(), MMU_DATA_STORE); \
}
-GEN_VEXT_ST_STRIDE(vssb_v_b, int8_t, int8_t, stb_b)
-GEN_VEXT_ST_STRIDE(vssb_v_h, int8_t, int16_t, stb_h)
-GEN_VEXT_ST_STRIDE(vssb_v_w, int8_t, int32_t, stb_w)
-GEN_VEXT_ST_STRIDE(vssb_v_d, int8_t, int64_t, stb_d)
-GEN_VEXT_ST_STRIDE(vssh_v_h, int16_t, int16_t, sth_h)
-GEN_VEXT_ST_STRIDE(vssh_v_w, int16_t, int32_t, sth_w)
-GEN_VEXT_ST_STRIDE(vssh_v_d, int16_t, int64_t, sth_d)
-GEN_VEXT_ST_STRIDE(vssw_v_w, int32_t, int32_t, stw_w)
-GEN_VEXT_ST_STRIDE(vssw_v_d, int32_t, int64_t, stw_d)
-GEN_VEXT_ST_STRIDE(vsse_v_b, int8_t, int8_t, ste_b)
-GEN_VEXT_ST_STRIDE(vsse_v_h, int16_t, int16_t, ste_h)
-GEN_VEXT_ST_STRIDE(vsse_v_w, int32_t, int32_t, ste_w)
-GEN_VEXT_ST_STRIDE(vsse_v_d, int64_t, int64_t, ste_d)
+GEN_VEXT_ST_STRIDE(vsse8_v, int8_t, ste_b)
+GEN_VEXT_ST_STRIDE(vsse16_v, int16_t, ste_h)
+GEN_VEXT_ST_STRIDE(vsse32_v, int32_t, ste_w)
+GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d)
/*
*** unit-stride: access elements stored contiguously in memory
@@ -422,8 +367,7 @@ GEN_VEXT_ST_STRIDE(vsse_v_d, int64_t, int64_t, ste_d)
static void
vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
- uint32_t esz, uint32_t msz, uintptr_t ra,
- MMUAccessType access_type)
+ uint32_t esz, uintptr_t ra, MMUAccessType access_type)
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
@@ -431,12 +375,12 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
uint32_t vta = vext_vta(desc);
/* probe every access */
- probe_pages(env, base, env->vl * nf * msz, ra, access_type);
+ probe_pages(env, base, env->vl * nf * esz, ra, access_type);
/* load bytes from guest memory */
for (i = 0; i < env->vl; i++) {
k = 0;
while (k < nf) {
- target_ulong addr = base + (i * nf + k) * msz;
+ target_ulong addr = base + (i * nf + k) * esz;
ldst_elem(env, addr, i + k * vlmax, vd, ra);
k++;
}
@@ -455,13 +399,13 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
* stride = NF * sizeof (MTYPE)
*/
-#define GEN_VEXT_LD_US(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
+#define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN, CLEAR_FN) \
void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \
+ uint32_t stride = vext_nf(desc) * sizeof(ETYPE); \
vext_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN, \
- CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
+ CLEAR_FN, sizeof(ETYPE), \
GETPC(), MMU_DATA_LOAD); \
} \
\
@@ -469,39 +413,21 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_us(vd, base, env, desc, LOAD_FN, CLEAR_FN, \
- sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_LOAD); \
-}
-
-GEN_VEXT_LD_US(vlb_v_b, int8_t, int8_t, ldb_b, clearb)
-GEN_VEXT_LD_US(vlb_v_h, int8_t, int16_t, ldb_h, clearh)
-GEN_VEXT_LD_US(vlb_v_w, int8_t, int32_t, ldb_w, clearl)
-GEN_VEXT_LD_US(vlb_v_d, int8_t, int64_t, ldb_d, clearq)
-GEN_VEXT_LD_US(vlh_v_h, int16_t, int16_t, ldh_h, clearh)
-GEN_VEXT_LD_US(vlh_v_w, int16_t, int32_t, ldh_w, clearl)
-GEN_VEXT_LD_US(vlh_v_d, int16_t, int64_t, ldh_d, clearq)
-GEN_VEXT_LD_US(vlw_v_w, int32_t, int32_t, ldw_w, clearl)
-GEN_VEXT_LD_US(vlw_v_d, int32_t, int64_t, ldw_d, clearq)
-GEN_VEXT_LD_US(vle_v_b, int8_t, int8_t, lde_b, clearb)
-GEN_VEXT_LD_US(vle_v_h, int16_t, int16_t, lde_h, clearh)
-GEN_VEXT_LD_US(vle_v_w, int32_t, int32_t, lde_w, clearl)
-GEN_VEXT_LD_US(vle_v_d, int64_t, int64_t, lde_d, clearq)
-GEN_VEXT_LD_US(vlbu_v_b, uint8_t, uint8_t, ldbu_b, clearb)
-GEN_VEXT_LD_US(vlbu_v_h, uint8_t, uint16_t, ldbu_h, clearh)
-GEN_VEXT_LD_US(vlbu_v_w, uint8_t, uint32_t, ldbu_w, clearl)
-GEN_VEXT_LD_US(vlbu_v_d, uint8_t, uint64_t, ldbu_d, clearq)
-GEN_VEXT_LD_US(vlhu_v_h, uint16_t, uint16_t, ldhu_h, clearh)
-GEN_VEXT_LD_US(vlhu_v_w, uint16_t, uint32_t, ldhu_w, clearl)
-GEN_VEXT_LD_US(vlhu_v_d, uint16_t, uint64_t, ldhu_d, clearq)
-GEN_VEXT_LD_US(vlwu_v_w, uint32_t, uint32_t, ldwu_w, clearl)
-GEN_VEXT_LD_US(vlwu_v_d, uint32_t, uint64_t, ldwu_d, clearq)
-
-#define GEN_VEXT_ST_US(NAME, MTYPE, ETYPE, STORE_FN) \
+ sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \
+}
+
+GEN_VEXT_LD_US(vle8_v, int8_t, lde_b, clearb)
+GEN_VEXT_LD_US(vle16_v, int16_t, lde_h, clearh)
+GEN_VEXT_LD_US(vle32_v, int32_t, lde_w, clearl)
+GEN_VEXT_LD_US(vle64_v, int64_t, lde_d, clearq)
+
+#define GEN_VEXT_ST_US(NAME, ETYPE, STORE_FN) \
void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \
+ uint32_t stride = vext_nf(desc) * sizeof(ETYPE); \
vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \
- NULL, sizeof(ETYPE), sizeof(MTYPE), \
+ NULL, sizeof(ETYPE), \
GETPC(), MMU_DATA_STORE); \
} \
\
@@ -509,22 +435,13 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_us(vd, base, env, desc, STORE_FN, NULL, \
- sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_STORE);\
-}
-
-GEN_VEXT_ST_US(vsb_v_b, int8_t, int8_t , stb_b)
-GEN_VEXT_ST_US(vsb_v_h, int8_t, int16_t, stb_h)
-GEN_VEXT_ST_US(vsb_v_w, int8_t, int32_t, stb_w)
-GEN_VEXT_ST_US(vsb_v_d, int8_t, int64_t, stb_d)
-GEN_VEXT_ST_US(vsh_v_h, int16_t, int16_t, sth_h)
-GEN_VEXT_ST_US(vsh_v_w, int16_t, int32_t, sth_w)
-GEN_VEXT_ST_US(vsh_v_d, int16_t, int64_t, sth_d)
-GEN_VEXT_ST_US(vsw_v_w, int32_t, int32_t, stw_w)
-GEN_VEXT_ST_US(vsw_v_d, int32_t, int64_t, stw_d)
-GEN_VEXT_ST_US(vse_v_b, int8_t, int8_t , ste_b)
-GEN_VEXT_ST_US(vse_v_h, int16_t, int16_t, ste_h)
-GEN_VEXT_ST_US(vse_v_w, int32_t, int32_t, ste_w)
-GEN_VEXT_ST_US(vse_v_d, int64_t, int64_t, ste_d)
+ sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \
+}
+
+GEN_VEXT_ST_US(vse8_v, int8_t, ste_b)
+GEN_VEXT_ST_US(vse16_v, int16_t, ste_h)
+GEN_VEXT_ST_US(vse32_v, int32_t, ste_w)
+GEN_VEXT_ST_US(vse64_v, int64_t, ste_d)
/*
*** index: access vector element from indexed memory
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 129 +++------------
target/riscv/insn32.decode | 43 +++--
target/riscv/insn_trans/trans_rvv.inc.c | 206 ++++++++++--------------
target/riscv/vector_helper.c | 175 ++++++--------------
4 files changed, 171 insertions(+), 382 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 5939897a82..73386b37c7 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -84,111 +84,30 @@ DEF_HELPER_1(hyp_tlb_flush, void, env)
/* Vector functions */
DEF_HELPER_5(vsetvl, tl, env, i32, i32, tl, tl)
-DEF_HELPER_5(vlb_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlb_v_b_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlb_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlb_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlb_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlb_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlb_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlb_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlh_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlh_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlh_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlh_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlh_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlh_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlw_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlw_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlw_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlw_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_b_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_b_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhu_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhu_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhu_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhu_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhu_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhu_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwu_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwu_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwu_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwu_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_b_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsh_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsh_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsh_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsh_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsh_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsh_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsw_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsw_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsw_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsw_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_b_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_6(vlsb_v_b, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsb_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsb_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsb_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsh_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsh_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsh_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsw_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsw_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlse_v_b, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlse_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlse_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlse_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsbu_v_b, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsbu_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsbu_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsbu_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlshu_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlshu_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlshu_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlswu_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlswu_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssb_v_b, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssb_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssb_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssb_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssh_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssh_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssh_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssw_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssw_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vsse_v_b, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vsse_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vsse_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vsse_v_d, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_5(vle8_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle16_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle32_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle64_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle8_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle16_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle32_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle64_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse8_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse16_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse32_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse64_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse8_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse16_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse32_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse64_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_6(vlse8_v, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_6(vlse16_v, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_6(vlse32_v, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_6(vlse64_v, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_6(vsse8_v, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_6(vsse16_v, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_6(vsse32_v, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_6(vsse64_v, void, ptr, ptr, tl, tl, env, i32)
DEF_HELPER_6(vlxb_v_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vlxb_v_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vlxb_v_w, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index bdd8563067..012c844f60 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -229,13 +229,26 @@ hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
# *** RV32V Extension ***
# *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
-vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
-vlh_v ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm
-vlw_v ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm
-vle_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
-vlbu_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
-vlhu_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
-vlwu_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
+# Vector unit-stride load/store insns.
+vle8_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
+vle16_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
+vle32_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
+vle64_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
+vse8_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
+vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
+vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
+vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
+
+# Vector strided insns.
+vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
+vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
+vlse32_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
+vlse64_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
+vsse8_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
+vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
+vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
+vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
+
vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm
vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm
vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm
@@ -243,22 +256,6 @@ vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
-vsb_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
-vsh_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
-vsw_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
-vse_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
-
-vlsb_v ... 110 . ..... ..... 000 ..... 0000111 @r_nfvm
-vlsh_v ... 110 . ..... ..... 101 ..... 0000111 @r_nfvm
-vlsw_v ... 110 . ..... ..... 110 ..... 0000111 @r_nfvm
-vlse_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
-vlsbu_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
-vlshu_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
-vlswu_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
-vssb_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
-vssh_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
-vssw_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
-vsse_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
vlxb_v ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm
vlxh_v ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index da8e7598e9..6f54b63453 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -145,8 +145,26 @@ static uint32_t vreg_ofs(DisasContext *s, int reg)
/* check functions */
/*
- * In cpu_get_tb_cpu_state(), set VILL if RVV was not present.
- * So RVV is also be checked in this function.
+ * Vector unit-stride, strided, unit-stride segment, strided segment
+ * store check function.
+ */
+#define VEXT_CHECK_STORE(s, rd, nf) do { \
+ uint32_t emul_r = s->emul < 1 ? 1 : s->emul; \
+ require(s->emul >= 0.125 && s->emul <= 8); \
+ require_align(rd, s->emul); \
+ require((nf * emul_r) <= (NVPR / 4) && \
+ (rd + nf * emul_r) <= NVPR); \
+} while (0)
+
+/*
+ * Vector unit-stride, strided, unit-stride segment, strided segment
+ * load check function.
+ */
+#define VEXT_CHECK_LOAD(s, rd, nf, vm) do { \
+ VEXT_CHECK_STORE(s, rd, nf); \
+ require_vm(vm, rd); \
+} while (0)
+
*/
static bool vext_check_isa_ill(DisasContext *s)
{
@@ -288,13 +306,15 @@ static bool vext_check_overlap_mask(DisasContext *s, uint32_t vd, bool vm,
} while (0)
/* common translation macro */
-#define GEN_VEXT_TRANS(NAME, SEQ, ARGTYPE, OP, CHECK) \
-static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\
-{ \
- if (CHECK(s, a)) { \
- return OP(s, a, SEQ); \
- } \
- return false; \
+#define GEN_VEXT_TRANS(NAME, EEW, SEQ, ARGTYPE, OP, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE * a) \
+{ \
+ s->eew = EEW; \
+ s->emul = (float)EEW / (1 << (s->sew + 3)) * s->flmul; \
+ if (CHECK(s, a)) { \
+ return OP(s, a, SEQ); \
+ } \
+ return false; \
}
/*
@@ -344,41 +364,17 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_ldst_us *fn;
- static gen_helper_ldst_us * const fns[2][7][4] = {
+ static gen_helper_ldst_us * const fns[2][4] = {
/* masked unit stride load */
- { { gen_helper_vlb_v_b_mask, gen_helper_vlb_v_h_mask,
- gen_helper_vlb_v_w_mask, gen_helper_vlb_v_d_mask },
- { NULL, gen_helper_vlh_v_h_mask,
- gen_helper_vlh_v_w_mask, gen_helper_vlh_v_d_mask },
- { NULL, NULL,
- gen_helper_vlw_v_w_mask, gen_helper_vlw_v_d_mask },
- { gen_helper_vle_v_b_mask, gen_helper_vle_v_h_mask,
- gen_helper_vle_v_w_mask, gen_helper_vle_v_d_mask },
- { gen_helper_vlbu_v_b_mask, gen_helper_vlbu_v_h_mask,
- gen_helper_vlbu_v_w_mask, gen_helper_vlbu_v_d_mask },
- { NULL, gen_helper_vlhu_v_h_mask,
- gen_helper_vlhu_v_w_mask, gen_helper_vlhu_v_d_mask },
- { NULL, NULL,
- gen_helper_vlwu_v_w_mask, gen_helper_vlwu_v_d_mask } },
+ { gen_helper_vle8_v_mask, gen_helper_vle16_v_mask,
+ gen_helper_vle32_v_mask, gen_helper_vle64_v_mask },
/* unmasked unit stride load */
- { { gen_helper_vlb_v_b, gen_helper_vlb_v_h,
- gen_helper_vlb_v_w, gen_helper_vlb_v_d },
- { NULL, gen_helper_vlh_v_h,
- gen_helper_vlh_v_w, gen_helper_vlh_v_d },
- { NULL, NULL,
- gen_helper_vlw_v_w, gen_helper_vlw_v_d },
- { gen_helper_vle_v_b, gen_helper_vle_v_h,
- gen_helper_vle_v_w, gen_helper_vle_v_d },
- { gen_helper_vlbu_v_b, gen_helper_vlbu_v_h,
- gen_helper_vlbu_v_w, gen_helper_vlbu_v_d },
- { NULL, gen_helper_vlhu_v_h,
- gen_helper_vlhu_v_w, gen_helper_vlhu_v_d },
- { NULL, NULL,
- gen_helper_vlwu_v_w, gen_helper_vlwu_v_d } }
+ { gen_helper_vle8_v, gen_helper_vle16_v,
+ gen_helper_vle32_v, gen_helper_vle64_v }
};
bool ret;
- fn = fns[a->vm][seq][s->sew];
+ fn = fns[a->vm][seq];
if (fn == NULL) {
return false;
}
@@ -396,46 +392,31 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
static bool ld_us_check(DisasContext *s, arg_r2nfvm* a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_nf(s, a->nf));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_LOAD(s, a->rd, a->nf, a->vm);
+ return true;
}
-GEN_VEXT_TRANS(vlb_v, 0, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vlh_v, 1, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vlw_v, 2, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vle_v, 3, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vlbu_v, 4, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vlhu_v, 5, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vlwu_v, 6, r2nfvm, ld_us_op, ld_us_check)
+GEN_VEXT_TRANS(vle8_v, 8, 0, r2nfvm, ld_us_op, ld_us_check)
+GEN_VEXT_TRANS(vle16_v, 16, 1, r2nfvm, ld_us_op, ld_us_check)
+GEN_VEXT_TRANS(vle32_v, 32, 2, r2nfvm, ld_us_op, ld_us_check)
+GEN_VEXT_TRANS(vle64_v, 64, 3, r2nfvm, ld_us_op, ld_us_check)
static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_ldst_us *fn;
- static gen_helper_ldst_us * const fns[2][4][4] = {
- /* masked unit stride load and store */
- { { gen_helper_vsb_v_b_mask, gen_helper_vsb_v_h_mask,
- gen_helper_vsb_v_w_mask, gen_helper_vsb_v_d_mask },
- { NULL, gen_helper_vsh_v_h_mask,
- gen_helper_vsh_v_w_mask, gen_helper_vsh_v_d_mask },
- { NULL, NULL,
- gen_helper_vsw_v_w_mask, gen_helper_vsw_v_d_mask },
- { gen_helper_vse_v_b_mask, gen_helper_vse_v_h_mask,
- gen_helper_vse_v_w_mask, gen_helper_vse_v_d_mask } },
+ static gen_helper_ldst_us * const fns[2][4] = {
+ /* masked unit stride store */
+ { gen_helper_vse8_v_mask, gen_helper_vse16_v_mask,
+ gen_helper_vse32_v_mask, gen_helper_vse64_v_mask },
/* unmasked unit stride store */
- { { gen_helper_vsb_v_b, gen_helper_vsb_v_h,
- gen_helper_vsb_v_w, gen_helper_vsb_v_d },
- { NULL, gen_helper_vsh_v_h,
- gen_helper_vsh_v_w, gen_helper_vsh_v_d },
- { NULL, NULL,
- gen_helper_vsw_v_w, gen_helper_vsw_v_d },
- { gen_helper_vse_v_b, gen_helper_vse_v_h,
- gen_helper_vse_v_w, gen_helper_vse_v_d } }
+ { gen_helper_vse8_v, gen_helper_vse16_v,
+ gen_helper_vse32_v, gen_helper_vse64_v }
};
- fn = fns[a->vm][seq][s->sew];
+ fn = fns[a->vm][seq];
if (fn == NULL) {
return false;
}
@@ -451,15 +432,16 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
static bool st_us_check(DisasContext *s, arg_r2nfvm* a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_nf(s, a->nf));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_STORE(s, a->rd, a->nf);
+ return true;
}
-GEN_VEXT_TRANS(vsb_v, 0, r2nfvm, st_us_op, st_us_check)
-GEN_VEXT_TRANS(vsh_v, 1, r2nfvm, st_us_op, st_us_check)
-GEN_VEXT_TRANS(vsw_v, 2, r2nfvm, st_us_op, st_us_check)
-GEN_VEXT_TRANS(vse_v, 3, r2nfvm, st_us_op, st_us_check)
+GEN_VEXT_TRANS(vse8_v, 8, 0, r2nfvm, st_us_op, st_us_check)
+GEN_VEXT_TRANS(vse16_v, 16, 1, r2nfvm, st_us_op, st_us_check)
+GEN_VEXT_TRANS(vse32_v, 32, 2, r2nfvm, st_us_op, st_us_check)
+GEN_VEXT_TRANS(vse64_v, 64, 3, r2nfvm, st_us_op, st_us_check)
/*
*** stride load and store
@@ -504,28 +486,13 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_ldst_stride *fn;
- static gen_helper_ldst_stride * const fns[7][4] = {
- { gen_helper_vlsb_v_b, gen_helper_vlsb_v_h,
- gen_helper_vlsb_v_w, gen_helper_vlsb_v_d },
- { NULL, gen_helper_vlsh_v_h,
- gen_helper_vlsh_v_w, gen_helper_vlsh_v_d },
- { NULL, NULL,
- gen_helper_vlsw_v_w, gen_helper_vlsw_v_d },
- { gen_helper_vlse_v_b, gen_helper_vlse_v_h,
- gen_helper_vlse_v_w, gen_helper_vlse_v_d },
- { gen_helper_vlsbu_v_b, gen_helper_vlsbu_v_h,
- gen_helper_vlsbu_v_w, gen_helper_vlsbu_v_d },
- { NULL, gen_helper_vlshu_v_h,
- gen_helper_vlshu_v_w, gen_helper_vlshu_v_d },
- { NULL, NULL,
- gen_helper_vlswu_v_w, gen_helper_vlswu_v_d },
+ static gen_helper_ldst_stride * const fns[4] = {
+ gen_helper_vlse8_v, gen_helper_vlse16_v,
+ gen_helper_vlse32_v, gen_helper_vlse64_v
};
bool ret;
- fn = fns[seq][s->sew];
- if (fn == NULL) {
- return false;
- }
+ fn = fns[seq];
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -540,40 +507,28 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
static bool ld_stride_check(DisasContext *s, arg_rnfvm* a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_nf(s, a->nf));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_LOAD(s, a->rd, a->nf, a->vm);
+ return true;
}
-GEN_VEXT_TRANS(vlsb_v, 0, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlsh_v, 1, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlsw_v, 2, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlse_v, 3, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlsbu_v, 4, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlshu_v, 5, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlswu_v, 6, rnfvm, ld_stride_op, ld_stride_check)
+GEN_VEXT_TRANS(vlse8_v, 8, 0, rnfvm, ld_stride_op, ld_stride_check)
+GEN_VEXT_TRANS(vlse16_v, 16, 1, rnfvm, ld_stride_op, ld_stride_check)
+GEN_VEXT_TRANS(vlse32_v, 32, 2, rnfvm, ld_stride_op, ld_stride_check)
+GEN_VEXT_TRANS(vlse64_v, 64, 3, rnfvm, ld_stride_op, ld_stride_check)
static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_ldst_stride *fn;
- static gen_helper_ldst_stride * const fns[4][4] = {
+ static gen_helper_ldst_stride * const fns[4] = {
/* masked stride store */
- { gen_helper_vssb_v_b, gen_helper_vssb_v_h,
- gen_helper_vssb_v_w, gen_helper_vssb_v_d },
- { NULL, gen_helper_vssh_v_h,
- gen_helper_vssh_v_w, gen_helper_vssh_v_d },
- { NULL, NULL,
- gen_helper_vssw_v_w, gen_helper_vssw_v_d },
- { gen_helper_vsse_v_b, gen_helper_vsse_v_h,
- gen_helper_vsse_v_w, gen_helper_vsse_v_d }
+ gen_helper_vsse8_v, gen_helper_vsse16_v,
+ gen_helper_vsse32_v, gen_helper_vsse64_v
};
fn = fns[seq];
- if (fn == NULL) {
- return false;
- }
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -587,15 +542,16 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
static bool st_stride_check(DisasContext *s, arg_rnfvm* a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_nf(s, a->nf));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_STORE(s, a->rd, a->nf);
+ return true;
}
-GEN_VEXT_TRANS(vssb_v, 0, rnfvm, st_stride_op, st_stride_check)
-GEN_VEXT_TRANS(vssh_v, 1, rnfvm, st_stride_op, st_stride_check)
-GEN_VEXT_TRANS(vssw_v, 2, rnfvm, st_stride_op, st_stride_check)
-GEN_VEXT_TRANS(vsse_v, 3, rnfvm, st_stride_op, st_stride_check)
+GEN_VEXT_TRANS(vsse8_v, 8, 0, rnfvm, st_stride_op, st_stride_check)
+GEN_VEXT_TRANS(vsse16_v, 16, 1, rnfvm, st_stride_op, st_stride_check)
+GEN_VEXT_TRANS(vsse32_v, 32, 2, rnfvm, st_stride_op, st_stride_check)
+GEN_VEXT_TRANS(vsse64_v, 64, 3, rnfvm, st_stride_op, st_stride_check)
/*
*** index load and store
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 1279ef4fb1..0b95e851ae 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -256,38 +256,20 @@ typedef void vext_ldst_elem_fn(CPURISCVState *env, target_ulong addr,
typedef void clear_fn(void *vd, uint32_t vta, uint32_t idx,
uint32_t cnt, uint32_t tot);
-#define GEN_VEXT_LD_ELEM(NAME, MTYPE, ETYPE, H, LDSUF) \
+#define GEN_VEXT_LD_ELEM(NAME, ETYPE, H, LDSUF) \
static void NAME(CPURISCVState *env, abi_ptr addr, \
uint32_t idx, void *vd, uintptr_t retaddr)\
{ \
- MTYPE data; \
+ ETYPE data; \
ETYPE *cur = ((ETYPE *)vd + H(idx)); \
data = cpu_##LDSUF##_data_ra(env, addr, retaddr); \
*cur = data; \
} \
-GEN_VEXT_LD_ELEM(ldb_b, int8_t, int8_t, H1, ldsb)
-GEN_VEXT_LD_ELEM(ldb_h, int8_t, int16_t, H2, ldsb)
-GEN_VEXT_LD_ELEM(ldb_w, int8_t, int32_t, H4, ldsb)
-GEN_VEXT_LD_ELEM(ldb_d, int8_t, int64_t, H8, ldsb)
-GEN_VEXT_LD_ELEM(ldh_h, int16_t, int16_t, H2, ldsw)
-GEN_VEXT_LD_ELEM(ldh_w, int16_t, int32_t, H4, ldsw)
-GEN_VEXT_LD_ELEM(ldh_d, int16_t, int64_t, H8, ldsw)
-GEN_VEXT_LD_ELEM(ldw_w, int32_t, int32_t, H4, ldl)
-GEN_VEXT_LD_ELEM(ldw_d, int32_t, int64_t, H8, ldl)
-GEN_VEXT_LD_ELEM(lde_b, int8_t, int8_t, H1, ldsb)
-GEN_VEXT_LD_ELEM(lde_h, int16_t, int16_t, H2, ldsw)
-GEN_VEXT_LD_ELEM(lde_w, int32_t, int32_t, H4, ldl)
-GEN_VEXT_LD_ELEM(lde_d, int64_t, int64_t, H8, ldq)
-GEN_VEXT_LD_ELEM(ldbu_b, uint8_t, uint8_t, H1, ldub)
-GEN_VEXT_LD_ELEM(ldbu_h, uint8_t, uint16_t, H2, ldub)
-GEN_VEXT_LD_ELEM(ldbu_w, uint8_t, uint32_t, H4, ldub)
-GEN_VEXT_LD_ELEM(ldbu_d, uint8_t, uint64_t, H8, ldub)
-GEN_VEXT_LD_ELEM(ldhu_h, uint16_t, uint16_t, H2, lduw)
-GEN_VEXT_LD_ELEM(ldhu_w, uint16_t, uint32_t, H4, lduw)
-GEN_VEXT_LD_ELEM(ldhu_d, uint16_t, uint64_t, H8, lduw)
-GEN_VEXT_LD_ELEM(ldwu_w, uint32_t, uint32_t, H4, ldl)
-GEN_VEXT_LD_ELEM(ldwu_d, uint32_t, uint64_t, H8, ldl)
+GEN_VEXT_LD_ELEM(lde_b, int8_t, H1, ldsb)
+GEN_VEXT_LD_ELEM(lde_h, int16_t, H2, ldsw)
+GEN_VEXT_LD_ELEM(lde_w, int32_t, H4, ldl)
+GEN_VEXT_LD_ELEM(lde_d, int64_t, H8, ldq)
#define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \
static void NAME(CPURISCVState *env, abi_ptr addr, \
@@ -297,15 +279,6 @@ static void NAME(CPURISCVState *env, abi_ptr addr, \
cpu_##STSUF##_data_ra(env, addr, data, retaddr); \
}
-GEN_VEXT_ST_ELEM(stb_b, int8_t, H1, stb)
-GEN_VEXT_ST_ELEM(stb_h, int16_t, H2, stb)
-GEN_VEXT_ST_ELEM(stb_w, int32_t, H4, stb)
-GEN_VEXT_ST_ELEM(stb_d, int64_t, H8, stb)
-GEN_VEXT_ST_ELEM(sth_h, int16_t, H2, stw)
-GEN_VEXT_ST_ELEM(sth_w, int32_t, H4, stw)
-GEN_VEXT_ST_ELEM(sth_d, int64_t, H8, stw)
-GEN_VEXT_ST_ELEM(stw_w, int32_t, H4, stl)
-GEN_VEXT_ST_ELEM(stw_d, int64_t, H8, stl)
GEN_VEXT_ST_ELEM(ste_b, int8_t, H1, stb)
GEN_VEXT_ST_ELEM(ste_h, int16_t, H2, stw)
GEN_VEXT_ST_ELEM(ste_w, int32_t, H4, stl)
@@ -319,8 +292,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
target_ulong stride, CPURISCVState *env,
uint32_t desc, uint32_t vm,
vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
- uint32_t esz, uint32_t msz, uintptr_t ra,
- MMUAccessType access_type)
+ uint32_t esz, uintptr_t ra, MMUAccessType access_type)
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
@@ -332,7 +304,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
- probe_pages(env, base + stride * i, nf * msz, ra, access_type);
+ probe_pages(env, base + stride * i, nf * esz, ra, access_type);
}
/* do real access */
for (i = 0; i < env->vl; i++) {
@@ -341,7 +313,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
continue;
}
while (k < nf) {
- target_ulong addr = base + stride * i + k * msz;
+ target_ulong addr = base + stride * i + k * esz;
ldst_elem(env, addr, i + k * vlmax, vd, ra);
k++;
}
@@ -355,64 +327,37 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
}
}
-#define GEN_VEXT_LD_STRIDE(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
+#define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN, CLEAR_FN) \
void HELPER(NAME)(void *vd, void * v0, target_ulong base, \
target_ulong stride, CPURISCVState *env, \
uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN, \
- CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
+ CLEAR_FN, sizeof(ETYPE), \
GETPC(), MMU_DATA_LOAD); \
}
-GEN_VEXT_LD_STRIDE(vlsb_v_b, int8_t, int8_t, ldb_b, clearb)
-GEN_VEXT_LD_STRIDE(vlsb_v_h, int8_t, int16_t, ldb_h, clearh)
-GEN_VEXT_LD_STRIDE(vlsb_v_w, int8_t, int32_t, ldb_w, clearl)
-GEN_VEXT_LD_STRIDE(vlsb_v_d, int8_t, int64_t, ldb_d, clearq)
-GEN_VEXT_LD_STRIDE(vlsh_v_h, int16_t, int16_t, ldh_h, clearh)
-GEN_VEXT_LD_STRIDE(vlsh_v_w, int16_t, int32_t, ldh_w, clearl)
-GEN_VEXT_LD_STRIDE(vlsh_v_d, int16_t, int64_t, ldh_d, clearq)
-GEN_VEXT_LD_STRIDE(vlsw_v_w, int32_t, int32_t, ldw_w, clearl)
-GEN_VEXT_LD_STRIDE(vlsw_v_d, int32_t, int64_t, ldw_d, clearq)
-GEN_VEXT_LD_STRIDE(vlse_v_b, int8_t, int8_t, lde_b, clearb)
-GEN_VEXT_LD_STRIDE(vlse_v_h, int16_t, int16_t, lde_h, clearh)
-GEN_VEXT_LD_STRIDE(vlse_v_w, int32_t, int32_t, lde_w, clearl)
-GEN_VEXT_LD_STRIDE(vlse_v_d, int64_t, int64_t, lde_d, clearq)
-GEN_VEXT_LD_STRIDE(vlsbu_v_b, uint8_t, uint8_t, ldbu_b, clearb)
-GEN_VEXT_LD_STRIDE(vlsbu_v_h, uint8_t, uint16_t, ldbu_h, clearh)
-GEN_VEXT_LD_STRIDE(vlsbu_v_w, uint8_t, uint32_t, ldbu_w, clearl)
-GEN_VEXT_LD_STRIDE(vlsbu_v_d, uint8_t, uint64_t, ldbu_d, clearq)
-GEN_VEXT_LD_STRIDE(vlshu_v_h, uint16_t, uint16_t, ldhu_h, clearh)
-GEN_VEXT_LD_STRIDE(vlshu_v_w, uint16_t, uint32_t, ldhu_w, clearl)
-GEN_VEXT_LD_STRIDE(vlshu_v_d, uint16_t, uint64_t, ldhu_d, clearq)
-GEN_VEXT_LD_STRIDE(vlswu_v_w, uint32_t, uint32_t, ldwu_w, clearl)
-GEN_VEXT_LD_STRIDE(vlswu_v_d, uint32_t, uint64_t, ldwu_d, clearq)
-
-#define GEN_VEXT_ST_STRIDE(NAME, MTYPE, ETYPE, STORE_FN) \
+GEN_VEXT_LD_STRIDE(vlse8_v, int8_t, lde_b, clearb)
+GEN_VEXT_LD_STRIDE(vlse16_v, int16_t, lde_h, clearh)
+GEN_VEXT_LD_STRIDE(vlse32_v, int32_t, lde_w, clearl)
+GEN_VEXT_LD_STRIDE(vlse64_v, int64_t, lde_d, clearq)
+
+#define GEN_VEXT_ST_STRIDE(NAME, ETYPE, STORE_FN) \
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
target_ulong stride, CPURISCVState *env, \
uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
vext_ldst_stride(vd, v0, base, stride, env, desc, vm, STORE_FN, \
- NULL, sizeof(ETYPE), sizeof(MTYPE), \
+ NULL, sizeof(ETYPE), \
GETPC(), MMU_DATA_STORE); \
}
-GEN_VEXT_ST_STRIDE(vssb_v_b, int8_t, int8_t, stb_b)
-GEN_VEXT_ST_STRIDE(vssb_v_h, int8_t, int16_t, stb_h)
-GEN_VEXT_ST_STRIDE(vssb_v_w, int8_t, int32_t, stb_w)
-GEN_VEXT_ST_STRIDE(vssb_v_d, int8_t, int64_t, stb_d)
-GEN_VEXT_ST_STRIDE(vssh_v_h, int16_t, int16_t, sth_h)
-GEN_VEXT_ST_STRIDE(vssh_v_w, int16_t, int32_t, sth_w)
-GEN_VEXT_ST_STRIDE(vssh_v_d, int16_t, int64_t, sth_d)
-GEN_VEXT_ST_STRIDE(vssw_v_w, int32_t, int32_t, stw_w)
-GEN_VEXT_ST_STRIDE(vssw_v_d, int32_t, int64_t, stw_d)
-GEN_VEXT_ST_STRIDE(vsse_v_b, int8_t, int8_t, ste_b)
-GEN_VEXT_ST_STRIDE(vsse_v_h, int16_t, int16_t, ste_h)
-GEN_VEXT_ST_STRIDE(vsse_v_w, int32_t, int32_t, ste_w)
-GEN_VEXT_ST_STRIDE(vsse_v_d, int64_t, int64_t, ste_d)
+GEN_VEXT_ST_STRIDE(vsse8_v, int8_t, ste_b)
+GEN_VEXT_ST_STRIDE(vsse16_v, int16_t, ste_h)
+GEN_VEXT_ST_STRIDE(vsse32_v, int32_t, ste_w)
+GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d)
/*
*** unit-stride: access elements stored contiguously in memory
@@ -422,8 +367,7 @@ GEN_VEXT_ST_STRIDE(vsse_v_d, int64_t, int64_t, ste_d)
static void
vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
- uint32_t esz, uint32_t msz, uintptr_t ra,
- MMUAccessType access_type)
+ uint32_t esz, uintptr_t ra, MMUAccessType access_type)
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
@@ -431,12 +375,12 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
uint32_t vta = vext_vta(desc);
/* probe every access */
- probe_pages(env, base, env->vl * nf * msz, ra, access_type);
+ probe_pages(env, base, env->vl * nf * esz, ra, access_type);
/* load bytes from guest memory */
for (i = 0; i < env->vl; i++) {
k = 0;
while (k < nf) {
- target_ulong addr = base + (i * nf + k) * msz;
+ target_ulong addr = base + (i * nf + k) * esz;
ldst_elem(env, addr, i + k * vlmax, vd, ra);
k++;
}
@@ -455,13 +399,13 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
* stride = NF * sizeof (MTYPE)
*/
-#define GEN_VEXT_LD_US(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
+#define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN, CLEAR_FN) \
void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \
+ uint32_t stride = vext_nf(desc) * sizeof(ETYPE); \
vext_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN, \
- CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
+ CLEAR_FN, sizeof(ETYPE), \
GETPC(), MMU_DATA_LOAD); \
} \
\
@@ -469,39 +413,21 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_us(vd, base, env, desc, LOAD_FN, CLEAR_FN, \
- sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_LOAD); \
-}
-
-GEN_VEXT_LD_US(vlb_v_b, int8_t, int8_t, ldb_b, clearb)
-GEN_VEXT_LD_US(vlb_v_h, int8_t, int16_t, ldb_h, clearh)
-GEN_VEXT_LD_US(vlb_v_w, int8_t, int32_t, ldb_w, clearl)
-GEN_VEXT_LD_US(vlb_v_d, int8_t, int64_t, ldb_d, clearq)
-GEN_VEXT_LD_US(vlh_v_h, int16_t, int16_t, ldh_h, clearh)
-GEN_VEXT_LD_US(vlh_v_w, int16_t, int32_t, ldh_w, clearl)
-GEN_VEXT_LD_US(vlh_v_d, int16_t, int64_t, ldh_d, clearq)
-GEN_VEXT_LD_US(vlw_v_w, int32_t, int32_t, ldw_w, clearl)
-GEN_VEXT_LD_US(vlw_v_d, int32_t, int64_t, ldw_d, clearq)
-GEN_VEXT_LD_US(vle_v_b, int8_t, int8_t, lde_b, clearb)
-GEN_VEXT_LD_US(vle_v_h, int16_t, int16_t, lde_h, clearh)
-GEN_VEXT_LD_US(vle_v_w, int32_t, int32_t, lde_w, clearl)
-GEN_VEXT_LD_US(vle_v_d, int64_t, int64_t, lde_d, clearq)
-GEN_VEXT_LD_US(vlbu_v_b, uint8_t, uint8_t, ldbu_b, clearb)
-GEN_VEXT_LD_US(vlbu_v_h, uint8_t, uint16_t, ldbu_h, clearh)
-GEN_VEXT_LD_US(vlbu_v_w, uint8_t, uint32_t, ldbu_w, clearl)
-GEN_VEXT_LD_US(vlbu_v_d, uint8_t, uint64_t, ldbu_d, clearq)
-GEN_VEXT_LD_US(vlhu_v_h, uint16_t, uint16_t, ldhu_h, clearh)
-GEN_VEXT_LD_US(vlhu_v_w, uint16_t, uint32_t, ldhu_w, clearl)
-GEN_VEXT_LD_US(vlhu_v_d, uint16_t, uint64_t, ldhu_d, clearq)
-GEN_VEXT_LD_US(vlwu_v_w, uint32_t, uint32_t, ldwu_w, clearl)
-GEN_VEXT_LD_US(vlwu_v_d, uint32_t, uint64_t, ldwu_d, clearq)
-
-#define GEN_VEXT_ST_US(NAME, MTYPE, ETYPE, STORE_FN) \
+ sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \
+}
+
+GEN_VEXT_LD_US(vle8_v, int8_t, lde_b, clearb)
+GEN_VEXT_LD_US(vle16_v, int16_t, lde_h, clearh)
+GEN_VEXT_LD_US(vle32_v, int32_t, lde_w, clearl)
+GEN_VEXT_LD_US(vle64_v, int64_t, lde_d, clearq)
+
+#define GEN_VEXT_ST_US(NAME, ETYPE, STORE_FN) \
void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \
+ uint32_t stride = vext_nf(desc) * sizeof(ETYPE); \
vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \
- NULL, sizeof(ETYPE), sizeof(MTYPE), \
+ NULL, sizeof(ETYPE), \
GETPC(), MMU_DATA_STORE); \
} \
\
@@ -509,22 +435,13 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_us(vd, base, env, desc, STORE_FN, NULL, \
- sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_STORE);\
-}
-
-GEN_VEXT_ST_US(vsb_v_b, int8_t, int8_t , stb_b)
-GEN_VEXT_ST_US(vsb_v_h, int8_t, int16_t, stb_h)
-GEN_VEXT_ST_US(vsb_v_w, int8_t, int32_t, stb_w)
-GEN_VEXT_ST_US(vsb_v_d, int8_t, int64_t, stb_d)
-GEN_VEXT_ST_US(vsh_v_h, int16_t, int16_t, sth_h)
-GEN_VEXT_ST_US(vsh_v_w, int16_t, int32_t, sth_w)
-GEN_VEXT_ST_US(vsh_v_d, int16_t, int64_t, sth_d)
-GEN_VEXT_ST_US(vsw_v_w, int32_t, int32_t, stw_w)
-GEN_VEXT_ST_US(vsw_v_d, int32_t, int64_t, stw_d)
-GEN_VEXT_ST_US(vse_v_b, int8_t, int8_t , ste_b)
-GEN_VEXT_ST_US(vse_v_h, int16_t, int16_t, ste_h)
-GEN_VEXT_ST_US(vse_v_w, int32_t, int32_t, ste_w)
-GEN_VEXT_ST_US(vse_v_d, int64_t, int64_t, ste_d)
+ sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \
+}
+
+GEN_VEXT_ST_US(vse8_v, int8_t, ste_b)
+GEN_VEXT_ST_US(vse16_v, int16_t, ste_h)
+GEN_VEXT_ST_US(vse32_v, int32_t, ste_w)
+GEN_VEXT_ST_US(vse64_v, int64_t, ste_d)
/*
*** index: access vector element from indexed memory
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 15/65] target/riscv: rvv-0.9: index load and store instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 67 +++++-----
target/riscv/insn32.decode | 21 ++--
target/riscv/insn_trans/trans_rvv.inc.c | 156 +++++++++++++++---------
target/riscv/vector_helper.c | 84 ++++++-------
4 files changed, 183 insertions(+), 145 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 73386b37c7..99ea68b0b9 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -108,41 +108,38 @@ DEF_HELPER_6(vsse8_v, void, ptr, ptr, tl, tl, env, i32)
DEF_HELPER_6(vsse16_v, void, ptr, ptr, tl, tl, env, i32)
DEF_HELPER_6(vsse32_v, void, ptr, ptr, tl, tl, env, i32)
DEF_HELPER_6(vsse64_v, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlxb_v_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxb_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxb_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxb_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxh_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxh_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxh_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxe_v_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxe_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxe_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxe_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxbu_v_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxbu_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxbu_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxbu_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxhu_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxhu_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxhu_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxwu_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxwu_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxb_v_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxb_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxb_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxb_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxh_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxh_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxh_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxe_v_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxe_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxe_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxe_v_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei8_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei8_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei16_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei16_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei32_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei32_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei64_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei64_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei8_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei8_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei16_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei16_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei32_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei32_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei64_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei64_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_5(vlbff_v_b, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlbff_v_h, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlbff_v_w, void, ptr, ptr, tl, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 012c844f60..46542d162e 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -257,18 +257,17 @@ vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
-vlxb_v ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm
-vlxh_v ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm
-vlxw_v ... 111 . ..... ..... 110 ..... 0000111 @r_nfvm
-vlxe_v ... 011 . ..... ..... 111 ..... 0000111 @r_nfvm
-vlxbu_v ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm
-vlxhu_v ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm
-vlxwu_v ... 011 . ..... ..... 110 ..... 0000111 @r_nfvm
+# Vector indexed load insns.
+vlxei8_v ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm
+vlxei16_v ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm
+vlxei32_v ... 011 . ..... ..... 110 ..... 0000111 @r_nfvm
+vlxei64_v ... 011 . ..... ..... 111 ..... 0000111 @r_nfvm
+
# Vector ordered-indexed and unordered-indexed store insns.
-vsxb_v ... -11 . ..... ..... 000 ..... 0100111 @r_nfvm
-vsxh_v ... -11 . ..... ..... 101 ..... 0100111 @r_nfvm
-vsxw_v ... -11 . ..... ..... 110 ..... 0100111 @r_nfvm
-vsxe_v ... -11 . ..... ..... 111 ..... 0100111 @r_nfvm
+vsxei8_v ... 0-1 . ..... ..... 000 ..... 0100111 @r_nfvm
+vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm
+vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm
+vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm
#*** Vector AMO operations are encoded under the standard AMO major opcode ***
vamoswapw_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 6f54b63453..417edbe5a1 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -165,11 +165,41 @@ static uint32_t vreg_ofs(DisasContext *s, int reg)
require_vm(vm, rd); \
} while (0)
+/*
+ * Vector indexed, indexed segment store check function.
*/
-static bool vext_check_isa_ill(DisasContext *s)
-{
- return !s->vill;
-}
+#define VEXT_CHECK_ST_INDEX(s, rd, rs2, nf) do { \
+ uint32_t flmul_r = s->flmul < 1 ? 1 : s->flmul; \
+ require(s->emul >= 0.125 && s->emul <= 8); \
+ require_align(rs2, s->emul); \
+ require_align(rd, s->flmul); \
+ require((nf * flmul_r) <= (NVPR / 4) && \
+ (rd + nf * flmul_r) <= NVPR); \
+} while (0)
+
+/*
+ * Vector indexed, indexed segment load check function
+ */
+#define VEXT_CHECK_LD_INDEX(s, rd, rs2, nf, vm) do { \
+ VEXT_CHECK_ST_INDEX(s, rd, rs2, nf); \
+ if (s->eew > (1 << (s->sew + 3))) { \
+ if (rd != rs2) { \
+ require_noover(rd, s->flmul, rs2, s->emul); \
+ } \
+ } else if (s->eew < (1 << (s->sew + 3))) { \
+ if (s->emul < 1) { \
+ require_noover(rd, s->flmul, rs2, s->emul); \
+ } else { \
+ require_noover_widen(rd, s->flmul, rs2, s->emul); \
+ } \
+ } \
+ if (nf > 1) { \
+ require_noover(rd, s->flmul, rs2, s->emul); \
+ require_noover(rd, nf, rs2, 1); \
+ } \
+ require_vm(vm, rd); \
+} while (0)
+
/*
* Check function for vector instruction with format:
@@ -596,28 +626,35 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_ldst_index *fn;
- static gen_helper_ldst_index * const fns[7][4] = {
- { gen_helper_vlxb_v_b, gen_helper_vlxb_v_h,
- gen_helper_vlxb_v_w, gen_helper_vlxb_v_d },
- { NULL, gen_helper_vlxh_v_h,
- gen_helper_vlxh_v_w, gen_helper_vlxh_v_d },
- { NULL, NULL,
- gen_helper_vlxw_v_w, gen_helper_vlxw_v_d },
- { gen_helper_vlxe_v_b, gen_helper_vlxe_v_h,
- gen_helper_vlxe_v_w, gen_helper_vlxe_v_d },
- { gen_helper_vlxbu_v_b, gen_helper_vlxbu_v_h,
- gen_helper_vlxbu_v_w, gen_helper_vlxbu_v_d },
- { NULL, gen_helper_vlxhu_v_h,
- gen_helper_vlxhu_v_w, gen_helper_vlxhu_v_d },
- { NULL, NULL,
- gen_helper_vlxwu_v_w, gen_helper_vlxwu_v_d },
+ static gen_helper_ldst_index * const fns[4][4] = {
+ /*
+ * offset vector register group EEW = 8,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vlxei8_8_v, gen_helper_vlxei8_16_v,
+ gen_helper_vlxei8_32_v, gen_helper_vlxei8_64_v },
+ /*
+ * offset vector register group EEW = 16,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vlxei16_8_v, gen_helper_vlxei16_16_v,
+ gen_helper_vlxei16_32_v, gen_helper_vlxei16_64_v },
+ /*
+ * offset vector register group EEW = 32,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vlxei32_8_v, gen_helper_vlxei32_16_v,
+ gen_helper_vlxei32_32_v, gen_helper_vlxei32_64_v },
+ /*
+ * offset vector register group EEW = 64,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vlxei64_8_v, gen_helper_vlxei64_16_v,
+ gen_helper_vlxei64_32_v, gen_helper_vlxei64_64_v }
};
bool ret;
- fn = fns[seq][s->sew];
- if (fn == NULL) {
- return false;
- }
+ fn = fns[seq][s->sew];
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -632,40 +669,49 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
static bool ld_index_check(DisasContext *s, arg_rnfvm* a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_nf(s, a->nf));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_LD_INDEX(s, a->rd, a->rs2, a->nf, a->vm);
+ return true;
}
-GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxh_v, 1, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxw_v, 2, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxe_v, 3, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxbu_v, 4, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxhu_v, 5, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxwu_v, 6, rnfvm, ld_index_op, ld_index_check)
+GEN_VEXT_TRANS(vlxei8_v, 8, 0, rnfvm, ld_index_op, ld_index_check)
+GEN_VEXT_TRANS(vlxei16_v, 16, 1, rnfvm, ld_index_op, ld_index_check)
+GEN_VEXT_TRANS(vlxei32_v, 32, 2, rnfvm, ld_index_op, ld_index_check)
+GEN_VEXT_TRANS(vlxei64_v, 64, 3, rnfvm, ld_index_op, ld_index_check)
static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_ldst_index *fn;
static gen_helper_ldst_index * const fns[4][4] = {
- { gen_helper_vsxb_v_b, gen_helper_vsxb_v_h,
- gen_helper_vsxb_v_w, gen_helper_vsxb_v_d },
- { NULL, gen_helper_vsxh_v_h,
- gen_helper_vsxh_v_w, gen_helper_vsxh_v_d },
- { NULL, NULL,
- gen_helper_vsxw_v_w, gen_helper_vsxw_v_d },
- { gen_helper_vsxe_v_b, gen_helper_vsxe_v_h,
- gen_helper_vsxe_v_w, gen_helper_vsxe_v_d }
+ /*
+ * offset vector register group EEW = 8,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vsxei8_8_v, gen_helper_vsxei8_16_v,
+ gen_helper_vsxei8_32_v, gen_helper_vsxei8_64_v },
+ /*
+ * offset vector register group EEW = 16,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vsxei16_8_v, gen_helper_vsxei16_16_v,
+ gen_helper_vsxei16_32_v, gen_helper_vsxei16_64_v },
+ /*
+ * offset vector register group EEW = 32,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vsxei32_8_v, gen_helper_vsxei32_16_v,
+ gen_helper_vsxei32_32_v, gen_helper_vsxei32_64_v },
+ /*
+ * offset vector register group EEW = 64,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vsxei64_8_v, gen_helper_vsxei64_16_v,
+ gen_helper_vsxei64_32_v, gen_helper_vsxei64_64_v }
};
- fn = fns[seq][s->sew];
- if (fn == NULL) {
- return false;
- }
+ fn = fns[seq][s->sew];
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -678,16 +724,16 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
static bool st_index_check(DisasContext *s, arg_rnfvm* a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_nf(s, a->nf));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_ST_INDEX(s, a->rd, a->rs2, a->nf);
+ return true;
}
-GEN_VEXT_TRANS(vsxb_v, 0, rnfvm, st_index_op, st_index_check)
-GEN_VEXT_TRANS(vsxh_v, 1, rnfvm, st_index_op, st_index_check)
-GEN_VEXT_TRANS(vsxw_v, 2, rnfvm, st_index_op, st_index_check)
-GEN_VEXT_TRANS(vsxe_v, 3, rnfvm, st_index_op, st_index_check)
+GEN_VEXT_TRANS(vsxei8_v, 8, 0, rnfvm, st_index_op, st_index_check)
+GEN_VEXT_TRANS(vsxei16_v, 16, 1, rnfvm, st_index_op, st_index_check)
+GEN_VEXT_TRANS(vsxei32_v, 32, 2, rnfvm, st_index_op, st_index_check)
+GEN_VEXT_TRANS(vsxei64_v, 64, 3, rnfvm, st_index_op, st_index_check)
/*
*** unit stride fault-only-first load
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 0b95e851ae..a2926427ce 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -466,8 +466,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
void *vs2, CPURISCVState *env, uint32_t desc,
vext_get_index_addr get_index_addr,
vext_ldst_elem_fn *ldst_elem,
- clear_fn *clear_elem,
- uint32_t esz, uint32_t msz, uintptr_t ra,
+ clear_fn *clear_elem, uint32_t esz, uintptr_t ra,
MMUAccessType access_type)
{
uint32_t i, k;
@@ -481,7 +480,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
- probe_pages(env, get_index_addr(base, i, vs2), nf * msz, ra,
+ probe_pages(env, get_index_addr(base, i, vs2), nf * esz, ra,
access_type);
}
/* load bytes from guest memory */
@@ -491,7 +490,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
continue;
}
while (k < nf) {
- abi_ptr addr = get_index_addr(base, i, vs2) + k * msz;
+ abi_ptr addr = get_index_addr(base, i, vs2) + k * esz;
ldst_elem(env, addr, i + k * vlmax, vd, ra);
k++;
}
@@ -505,60 +504,57 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
}
}
-#define GEN_VEXT_LD_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, LOAD_FN, CLEAR_FN) \
+#define GEN_VEXT_LD_INDEX(NAME, ETYPE, INDEX_FN, LOAD_FN, CLEAR_FN) \
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
- LOAD_FN, CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
+ LOAD_FN, CLEAR_FN, sizeof(ETYPE), \
GETPC(), MMU_DATA_LOAD); \
}
-GEN_VEXT_LD_INDEX(vlxb_v_b, int8_t, int8_t, idx_b, ldb_b, clearb)
-GEN_VEXT_LD_INDEX(vlxb_v_h, int8_t, int16_t, idx_h, ldb_h, clearh)
-GEN_VEXT_LD_INDEX(vlxb_v_w, int8_t, int32_t, idx_w, ldb_w, clearl)
-GEN_VEXT_LD_INDEX(vlxb_v_d, int8_t, int64_t, idx_d, ldb_d, clearq)
-GEN_VEXT_LD_INDEX(vlxh_v_h, int16_t, int16_t, idx_h, ldh_h, clearh)
-GEN_VEXT_LD_INDEX(vlxh_v_w, int16_t, int32_t, idx_w, ldh_w, clearl)
-GEN_VEXT_LD_INDEX(vlxh_v_d, int16_t, int64_t, idx_d, ldh_d, clearq)
-GEN_VEXT_LD_INDEX(vlxw_v_w, int32_t, int32_t, idx_w, ldw_w, clearl)
-GEN_VEXT_LD_INDEX(vlxw_v_d, int32_t, int64_t, idx_d, ldw_d, clearq)
-GEN_VEXT_LD_INDEX(vlxe_v_b, int8_t, int8_t, idx_b, lde_b, clearb)
-GEN_VEXT_LD_INDEX(vlxe_v_h, int16_t, int16_t, idx_h, lde_h, clearh)
-GEN_VEXT_LD_INDEX(vlxe_v_w, int32_t, int32_t, idx_w, lde_w, clearl)
-GEN_VEXT_LD_INDEX(vlxe_v_d, int64_t, int64_t, idx_d, lde_d, clearq)
-GEN_VEXT_LD_INDEX(vlxbu_v_b, uint8_t, uint8_t, idx_b, ldbu_b, clearb)
-GEN_VEXT_LD_INDEX(vlxbu_v_h, uint8_t, uint16_t, idx_h, ldbu_h, clearh)
-GEN_VEXT_LD_INDEX(vlxbu_v_w, uint8_t, uint32_t, idx_w, ldbu_w, clearl)
-GEN_VEXT_LD_INDEX(vlxbu_v_d, uint8_t, uint64_t, idx_d, ldbu_d, clearq)
-GEN_VEXT_LD_INDEX(vlxhu_v_h, uint16_t, uint16_t, idx_h, ldhu_h, clearh)
-GEN_VEXT_LD_INDEX(vlxhu_v_w, uint16_t, uint32_t, idx_w, ldhu_w, clearl)
-GEN_VEXT_LD_INDEX(vlxhu_v_d, uint16_t, uint64_t, idx_d, ldhu_d, clearq)
-GEN_VEXT_LD_INDEX(vlxwu_v_w, uint32_t, uint32_t, idx_w, ldwu_w, clearl)
-GEN_VEXT_LD_INDEX(vlxwu_v_d, uint32_t, uint64_t, idx_d, ldwu_d, clearq)
-
-#define GEN_VEXT_ST_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, STORE_FN)\
+GEN_VEXT_LD_INDEX(vlxei8_8_v, int8_t, idx_b, lde_b, clearb)
+GEN_VEXT_LD_INDEX(vlxei8_16_v, int16_t, idx_b, lde_h, clearh)
+GEN_VEXT_LD_INDEX(vlxei8_32_v, int32_t, idx_b, lde_w, clearl)
+GEN_VEXT_LD_INDEX(vlxei8_64_v, int64_t, idx_b, lde_d, clearq)
+GEN_VEXT_LD_INDEX(vlxei16_8_v, int8_t, idx_h, lde_b, clearb)
+GEN_VEXT_LD_INDEX(vlxei16_16_v, int16_t, idx_h, lde_h, clearh)
+GEN_VEXT_LD_INDEX(vlxei16_32_v, int32_t, idx_h, lde_w, clearl)
+GEN_VEXT_LD_INDEX(vlxei16_64_v, int64_t, idx_h, lde_d, clearq)
+GEN_VEXT_LD_INDEX(vlxei32_8_v, int8_t, idx_w, lde_b, clearb)
+GEN_VEXT_LD_INDEX(vlxei32_16_v, int16_t, idx_w, lde_h, clearh)
+GEN_VEXT_LD_INDEX(vlxei32_32_v, int32_t, idx_w, lde_w, clearl)
+GEN_VEXT_LD_INDEX(vlxei32_64_v, int64_t, idx_w, lde_d, clearq)
+GEN_VEXT_LD_INDEX(vlxei64_8_v, int8_t, idx_d, lde_b, clearb)
+GEN_VEXT_LD_INDEX(vlxei64_16_v, int16_t, idx_d, lde_h, clearh)
+GEN_VEXT_LD_INDEX(vlxei64_32_v, int32_t, idx_d, lde_w, clearl)
+GEN_VEXT_LD_INDEX(vlxei64_64_v, int64_t, idx_d, lde_d, clearq)
+
+#define GEN_VEXT_ST_INDEX(NAME, ETYPE, INDEX_FN, STORE_FN) \
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
- STORE_FN, NULL, sizeof(ETYPE), sizeof(MTYPE),\
+ STORE_FN, NULL, sizeof(ETYPE), \
GETPC(), MMU_DATA_STORE); \
}
-GEN_VEXT_ST_INDEX(vsxb_v_b, int8_t, int8_t, idx_b, stb_b)
-GEN_VEXT_ST_INDEX(vsxb_v_h, int8_t, int16_t, idx_h, stb_h)
-GEN_VEXT_ST_INDEX(vsxb_v_w, int8_t, int32_t, idx_w, stb_w)
-GEN_VEXT_ST_INDEX(vsxb_v_d, int8_t, int64_t, idx_d, stb_d)
-GEN_VEXT_ST_INDEX(vsxh_v_h, int16_t, int16_t, idx_h, sth_h)
-GEN_VEXT_ST_INDEX(vsxh_v_w, int16_t, int32_t, idx_w, sth_w)
-GEN_VEXT_ST_INDEX(vsxh_v_d, int16_t, int64_t, idx_d, sth_d)
-GEN_VEXT_ST_INDEX(vsxw_v_w, int32_t, int32_t, idx_w, stw_w)
-GEN_VEXT_ST_INDEX(vsxw_v_d, int32_t, int64_t, idx_d, stw_d)
-GEN_VEXT_ST_INDEX(vsxe_v_b, int8_t, int8_t, idx_b, ste_b)
-GEN_VEXT_ST_INDEX(vsxe_v_h, int16_t, int16_t, idx_h, ste_h)
-GEN_VEXT_ST_INDEX(vsxe_v_w, int32_t, int32_t, idx_w, ste_w)
-GEN_VEXT_ST_INDEX(vsxe_v_d, int64_t, int64_t, idx_d, ste_d)
+GEN_VEXT_ST_INDEX(vsxei8_8_v, int8_t, idx_b, ste_b)
+GEN_VEXT_ST_INDEX(vsxei8_16_v, int16_t, idx_b, ste_h)
+GEN_VEXT_ST_INDEX(vsxei8_32_v, int32_t, idx_b, ste_w)
+GEN_VEXT_ST_INDEX(vsxei8_64_v, int64_t, idx_b, ste_d)
+GEN_VEXT_ST_INDEX(vsxei16_8_v, int8_t, idx_h, ste_b)
+GEN_VEXT_ST_INDEX(vsxei16_16_v, int16_t, idx_h, ste_h)
+GEN_VEXT_ST_INDEX(vsxei16_32_v, int32_t, idx_h, ste_w)
+GEN_VEXT_ST_INDEX(vsxei16_64_v, int64_t, idx_h, ste_d)
+GEN_VEXT_ST_INDEX(vsxei32_8_v, int8_t, idx_w, ste_b)
+GEN_VEXT_ST_INDEX(vsxei32_16_v, int16_t, idx_w, ste_h)
+GEN_VEXT_ST_INDEX(vsxei32_32_v, int32_t, idx_w, ste_w)
+GEN_VEXT_ST_INDEX(vsxei32_64_v, int64_t, idx_w, ste_d)
+GEN_VEXT_ST_INDEX(vsxei64_8_v, int8_t, idx_d, ste_b)
+GEN_VEXT_ST_INDEX(vsxei64_16_v, int16_t, idx_d, ste_h)
+GEN_VEXT_ST_INDEX(vsxei64_32_v, int32_t, idx_d, ste_w)
+GEN_VEXT_ST_INDEX(vsxei64_64_v, int64_t, idx_d, ste_d)
/*
*** unit-stride fault-only-fisrt load instructions
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 15/65] target/riscv: rvv-0.9: index load and store instructions
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 67 +++++-----
target/riscv/insn32.decode | 21 ++--
target/riscv/insn_trans/trans_rvv.inc.c | 156 +++++++++++++++---------
target/riscv/vector_helper.c | 84 ++++++-------
4 files changed, 183 insertions(+), 145 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 73386b37c7..99ea68b0b9 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -108,41 +108,38 @@ DEF_HELPER_6(vsse8_v, void, ptr, ptr, tl, tl, env, i32)
DEF_HELPER_6(vsse16_v, void, ptr, ptr, tl, tl, env, i32)
DEF_HELPER_6(vsse32_v, void, ptr, ptr, tl, tl, env, i32)
DEF_HELPER_6(vsse64_v, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlxb_v_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxb_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxb_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxb_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxh_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxh_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxh_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxe_v_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxe_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxe_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxe_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxbu_v_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxbu_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxbu_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxbu_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxhu_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxhu_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxhu_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxwu_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxwu_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxb_v_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxb_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxb_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxb_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxh_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxh_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxh_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxe_v_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxe_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxe_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxe_v_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei8_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei8_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei16_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei16_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei32_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei32_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei64_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei64_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei8_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei8_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei16_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei16_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei32_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei32_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei64_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei64_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_5(vlbff_v_b, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlbff_v_h, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlbff_v_w, void, ptr, ptr, tl, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 012c844f60..46542d162e 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -257,18 +257,17 @@ vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
-vlxb_v ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm
-vlxh_v ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm
-vlxw_v ... 111 . ..... ..... 110 ..... 0000111 @r_nfvm
-vlxe_v ... 011 . ..... ..... 111 ..... 0000111 @r_nfvm
-vlxbu_v ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm
-vlxhu_v ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm
-vlxwu_v ... 011 . ..... ..... 110 ..... 0000111 @r_nfvm
+# Vector indexed load insns.
+vlxei8_v ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm
+vlxei16_v ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm
+vlxei32_v ... 011 . ..... ..... 110 ..... 0000111 @r_nfvm
+vlxei64_v ... 011 . ..... ..... 111 ..... 0000111 @r_nfvm
+
# Vector ordered-indexed and unordered-indexed store insns.
-vsxb_v ... -11 . ..... ..... 000 ..... 0100111 @r_nfvm
-vsxh_v ... -11 . ..... ..... 101 ..... 0100111 @r_nfvm
-vsxw_v ... -11 . ..... ..... 110 ..... 0100111 @r_nfvm
-vsxe_v ... -11 . ..... ..... 111 ..... 0100111 @r_nfvm
+vsxei8_v ... 0-1 . ..... ..... 000 ..... 0100111 @r_nfvm
+vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm
+vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm
+vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm
#*** Vector AMO operations are encoded under the standard AMO major opcode ***
vamoswapw_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 6f54b63453..417edbe5a1 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -165,11 +165,41 @@ static uint32_t vreg_ofs(DisasContext *s, int reg)
require_vm(vm, rd); \
} while (0)
+/*
+ * Vector indexed, indexed segment store check function.
*/
-static bool vext_check_isa_ill(DisasContext *s)
-{
- return !s->vill;
-}
+#define VEXT_CHECK_ST_INDEX(s, rd, rs2, nf) do { \
+ uint32_t flmul_r = s->flmul < 1 ? 1 : s->flmul; \
+ require(s->emul >= 0.125 && s->emul <= 8); \
+ require_align(rs2, s->emul); \
+ require_align(rd, s->flmul); \
+ require((nf * flmul_r) <= (NVPR / 4) && \
+ (rd + nf * flmul_r) <= NVPR); \
+} while (0)
+
+/*
+ * Vector indexed, indexed segment load check function
+ */
+#define VEXT_CHECK_LD_INDEX(s, rd, rs2, nf, vm) do { \
+ VEXT_CHECK_ST_INDEX(s, rd, rs2, nf); \
+ if (s->eew > (1 << (s->sew + 3))) { \
+ if (rd != rs2) { \
+ require_noover(rd, s->flmul, rs2, s->emul); \
+ } \
+ } else if (s->eew < (1 << (s->sew + 3))) { \
+ if (s->emul < 1) { \
+ require_noover(rd, s->flmul, rs2, s->emul); \
+ } else { \
+ require_noover_widen(rd, s->flmul, rs2, s->emul); \
+ } \
+ } \
+ if (nf > 1) { \
+ require_noover(rd, s->flmul, rs2, s->emul); \
+ require_noover(rd, nf, rs2, 1); \
+ } \
+ require_vm(vm, rd); \
+} while (0)
+
/*
* Check function for vector instruction with format:
@@ -596,28 +626,35 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_ldst_index *fn;
- static gen_helper_ldst_index * const fns[7][4] = {
- { gen_helper_vlxb_v_b, gen_helper_vlxb_v_h,
- gen_helper_vlxb_v_w, gen_helper_vlxb_v_d },
- { NULL, gen_helper_vlxh_v_h,
- gen_helper_vlxh_v_w, gen_helper_vlxh_v_d },
- { NULL, NULL,
- gen_helper_vlxw_v_w, gen_helper_vlxw_v_d },
- { gen_helper_vlxe_v_b, gen_helper_vlxe_v_h,
- gen_helper_vlxe_v_w, gen_helper_vlxe_v_d },
- { gen_helper_vlxbu_v_b, gen_helper_vlxbu_v_h,
- gen_helper_vlxbu_v_w, gen_helper_vlxbu_v_d },
- { NULL, gen_helper_vlxhu_v_h,
- gen_helper_vlxhu_v_w, gen_helper_vlxhu_v_d },
- { NULL, NULL,
- gen_helper_vlxwu_v_w, gen_helper_vlxwu_v_d },
+ static gen_helper_ldst_index * const fns[4][4] = {
+ /*
+ * offset vector register group EEW = 8,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vlxei8_8_v, gen_helper_vlxei8_16_v,
+ gen_helper_vlxei8_32_v, gen_helper_vlxei8_64_v },
+ /*
+ * offset vector register group EEW = 16,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vlxei16_8_v, gen_helper_vlxei16_16_v,
+ gen_helper_vlxei16_32_v, gen_helper_vlxei16_64_v },
+ /*
+ * offset vector register group EEW = 32,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vlxei32_8_v, gen_helper_vlxei32_16_v,
+ gen_helper_vlxei32_32_v, gen_helper_vlxei32_64_v },
+ /*
+ * offset vector register group EEW = 64,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vlxei64_8_v, gen_helper_vlxei64_16_v,
+ gen_helper_vlxei64_32_v, gen_helper_vlxei64_64_v }
};
bool ret;
- fn = fns[seq][s->sew];
- if (fn == NULL) {
- return false;
- }
+ fn = fns[seq][s->sew];
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -632,40 +669,49 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
static bool ld_index_check(DisasContext *s, arg_rnfvm* a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_nf(s, a->nf));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_LD_INDEX(s, a->rd, a->rs2, a->nf, a->vm);
+ return true;
}
-GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxh_v, 1, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxw_v, 2, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxe_v, 3, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxbu_v, 4, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxhu_v, 5, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxwu_v, 6, rnfvm, ld_index_op, ld_index_check)
+GEN_VEXT_TRANS(vlxei8_v, 8, 0, rnfvm, ld_index_op, ld_index_check)
+GEN_VEXT_TRANS(vlxei16_v, 16, 1, rnfvm, ld_index_op, ld_index_check)
+GEN_VEXT_TRANS(vlxei32_v, 32, 2, rnfvm, ld_index_op, ld_index_check)
+GEN_VEXT_TRANS(vlxei64_v, 64, 3, rnfvm, ld_index_op, ld_index_check)
static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_ldst_index *fn;
static gen_helper_ldst_index * const fns[4][4] = {
- { gen_helper_vsxb_v_b, gen_helper_vsxb_v_h,
- gen_helper_vsxb_v_w, gen_helper_vsxb_v_d },
- { NULL, gen_helper_vsxh_v_h,
- gen_helper_vsxh_v_w, gen_helper_vsxh_v_d },
- { NULL, NULL,
- gen_helper_vsxw_v_w, gen_helper_vsxw_v_d },
- { gen_helper_vsxe_v_b, gen_helper_vsxe_v_h,
- gen_helper_vsxe_v_w, gen_helper_vsxe_v_d }
+ /*
+ * offset vector register group EEW = 8,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vsxei8_8_v, gen_helper_vsxei8_16_v,
+ gen_helper_vsxei8_32_v, gen_helper_vsxei8_64_v },
+ /*
+ * offset vector register group EEW = 16,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vsxei16_8_v, gen_helper_vsxei16_16_v,
+ gen_helper_vsxei16_32_v, gen_helper_vsxei16_64_v },
+ /*
+ * offset vector register group EEW = 32,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vsxei32_8_v, gen_helper_vsxei32_16_v,
+ gen_helper_vsxei32_32_v, gen_helper_vsxei32_64_v },
+ /*
+ * offset vector register group EEW = 64,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vsxei64_8_v, gen_helper_vsxei64_16_v,
+ gen_helper_vsxei64_32_v, gen_helper_vsxei64_64_v }
};
- fn = fns[seq][s->sew];
- if (fn == NULL) {
- return false;
- }
+ fn = fns[seq][s->sew];
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -678,16 +724,16 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
static bool st_index_check(DisasContext *s, arg_rnfvm* a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_nf(s, a->nf));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_ST_INDEX(s, a->rd, a->rs2, a->nf);
+ return true;
}
-GEN_VEXT_TRANS(vsxb_v, 0, rnfvm, st_index_op, st_index_check)
-GEN_VEXT_TRANS(vsxh_v, 1, rnfvm, st_index_op, st_index_check)
-GEN_VEXT_TRANS(vsxw_v, 2, rnfvm, st_index_op, st_index_check)
-GEN_VEXT_TRANS(vsxe_v, 3, rnfvm, st_index_op, st_index_check)
+GEN_VEXT_TRANS(vsxei8_v, 8, 0, rnfvm, st_index_op, st_index_check)
+GEN_VEXT_TRANS(vsxei16_v, 16, 1, rnfvm, st_index_op, st_index_check)
+GEN_VEXT_TRANS(vsxei32_v, 32, 2, rnfvm, st_index_op, st_index_check)
+GEN_VEXT_TRANS(vsxei64_v, 64, 3, rnfvm, st_index_op, st_index_check)
/*
*** unit stride fault-only-first load
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 0b95e851ae..a2926427ce 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -466,8 +466,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
void *vs2, CPURISCVState *env, uint32_t desc,
vext_get_index_addr get_index_addr,
vext_ldst_elem_fn *ldst_elem,
- clear_fn *clear_elem,
- uint32_t esz, uint32_t msz, uintptr_t ra,
+ clear_fn *clear_elem, uint32_t esz, uintptr_t ra,
MMUAccessType access_type)
{
uint32_t i, k;
@@ -481,7 +480,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
- probe_pages(env, get_index_addr(base, i, vs2), nf * msz, ra,
+ probe_pages(env, get_index_addr(base, i, vs2), nf * esz, ra,
access_type);
}
/* load bytes from guest memory */
@@ -491,7 +490,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
continue;
}
while (k < nf) {
- abi_ptr addr = get_index_addr(base, i, vs2) + k * msz;
+ abi_ptr addr = get_index_addr(base, i, vs2) + k * esz;
ldst_elem(env, addr, i + k * vlmax, vd, ra);
k++;
}
@@ -505,60 +504,57 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
}
}
-#define GEN_VEXT_LD_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, LOAD_FN, CLEAR_FN) \
+#define GEN_VEXT_LD_INDEX(NAME, ETYPE, INDEX_FN, LOAD_FN, CLEAR_FN) \
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
- LOAD_FN, CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
+ LOAD_FN, CLEAR_FN, sizeof(ETYPE), \
GETPC(), MMU_DATA_LOAD); \
}
-GEN_VEXT_LD_INDEX(vlxb_v_b, int8_t, int8_t, idx_b, ldb_b, clearb)
-GEN_VEXT_LD_INDEX(vlxb_v_h, int8_t, int16_t, idx_h, ldb_h, clearh)
-GEN_VEXT_LD_INDEX(vlxb_v_w, int8_t, int32_t, idx_w, ldb_w, clearl)
-GEN_VEXT_LD_INDEX(vlxb_v_d, int8_t, int64_t, idx_d, ldb_d, clearq)
-GEN_VEXT_LD_INDEX(vlxh_v_h, int16_t, int16_t, idx_h, ldh_h, clearh)
-GEN_VEXT_LD_INDEX(vlxh_v_w, int16_t, int32_t, idx_w, ldh_w, clearl)
-GEN_VEXT_LD_INDEX(vlxh_v_d, int16_t, int64_t, idx_d, ldh_d, clearq)
-GEN_VEXT_LD_INDEX(vlxw_v_w, int32_t, int32_t, idx_w, ldw_w, clearl)
-GEN_VEXT_LD_INDEX(vlxw_v_d, int32_t, int64_t, idx_d, ldw_d, clearq)
-GEN_VEXT_LD_INDEX(vlxe_v_b, int8_t, int8_t, idx_b, lde_b, clearb)
-GEN_VEXT_LD_INDEX(vlxe_v_h, int16_t, int16_t, idx_h, lde_h, clearh)
-GEN_VEXT_LD_INDEX(vlxe_v_w, int32_t, int32_t, idx_w, lde_w, clearl)
-GEN_VEXT_LD_INDEX(vlxe_v_d, int64_t, int64_t, idx_d, lde_d, clearq)
-GEN_VEXT_LD_INDEX(vlxbu_v_b, uint8_t, uint8_t, idx_b, ldbu_b, clearb)
-GEN_VEXT_LD_INDEX(vlxbu_v_h, uint8_t, uint16_t, idx_h, ldbu_h, clearh)
-GEN_VEXT_LD_INDEX(vlxbu_v_w, uint8_t, uint32_t, idx_w, ldbu_w, clearl)
-GEN_VEXT_LD_INDEX(vlxbu_v_d, uint8_t, uint64_t, idx_d, ldbu_d, clearq)
-GEN_VEXT_LD_INDEX(vlxhu_v_h, uint16_t, uint16_t, idx_h, ldhu_h, clearh)
-GEN_VEXT_LD_INDEX(vlxhu_v_w, uint16_t, uint32_t, idx_w, ldhu_w, clearl)
-GEN_VEXT_LD_INDEX(vlxhu_v_d, uint16_t, uint64_t, idx_d, ldhu_d, clearq)
-GEN_VEXT_LD_INDEX(vlxwu_v_w, uint32_t, uint32_t, idx_w, ldwu_w, clearl)
-GEN_VEXT_LD_INDEX(vlxwu_v_d, uint32_t, uint64_t, idx_d, ldwu_d, clearq)
-
-#define GEN_VEXT_ST_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, STORE_FN)\
+GEN_VEXT_LD_INDEX(vlxei8_8_v, int8_t, idx_b, lde_b, clearb)
+GEN_VEXT_LD_INDEX(vlxei8_16_v, int16_t, idx_b, lde_h, clearh)
+GEN_VEXT_LD_INDEX(vlxei8_32_v, int32_t, idx_b, lde_w, clearl)
+GEN_VEXT_LD_INDEX(vlxei8_64_v, int64_t, idx_b, lde_d, clearq)
+GEN_VEXT_LD_INDEX(vlxei16_8_v, int8_t, idx_h, lde_b, clearb)
+GEN_VEXT_LD_INDEX(vlxei16_16_v, int16_t, idx_h, lde_h, clearh)
+GEN_VEXT_LD_INDEX(vlxei16_32_v, int32_t, idx_h, lde_w, clearl)
+GEN_VEXT_LD_INDEX(vlxei16_64_v, int64_t, idx_h, lde_d, clearq)
+GEN_VEXT_LD_INDEX(vlxei32_8_v, int8_t, idx_w, lde_b, clearb)
+GEN_VEXT_LD_INDEX(vlxei32_16_v, int16_t, idx_w, lde_h, clearh)
+GEN_VEXT_LD_INDEX(vlxei32_32_v, int32_t, idx_w, lde_w, clearl)
+GEN_VEXT_LD_INDEX(vlxei32_64_v, int64_t, idx_w, lde_d, clearq)
+GEN_VEXT_LD_INDEX(vlxei64_8_v, int8_t, idx_d, lde_b, clearb)
+GEN_VEXT_LD_INDEX(vlxei64_16_v, int16_t, idx_d, lde_h, clearh)
+GEN_VEXT_LD_INDEX(vlxei64_32_v, int32_t, idx_d, lde_w, clearl)
+GEN_VEXT_LD_INDEX(vlxei64_64_v, int64_t, idx_d, lde_d, clearq)
+
+#define GEN_VEXT_ST_INDEX(NAME, ETYPE, INDEX_FN, STORE_FN) \
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
- STORE_FN, NULL, sizeof(ETYPE), sizeof(MTYPE),\
+ STORE_FN, NULL, sizeof(ETYPE), \
GETPC(), MMU_DATA_STORE); \
}
-GEN_VEXT_ST_INDEX(vsxb_v_b, int8_t, int8_t, idx_b, stb_b)
-GEN_VEXT_ST_INDEX(vsxb_v_h, int8_t, int16_t, idx_h, stb_h)
-GEN_VEXT_ST_INDEX(vsxb_v_w, int8_t, int32_t, idx_w, stb_w)
-GEN_VEXT_ST_INDEX(vsxb_v_d, int8_t, int64_t, idx_d, stb_d)
-GEN_VEXT_ST_INDEX(vsxh_v_h, int16_t, int16_t, idx_h, sth_h)
-GEN_VEXT_ST_INDEX(vsxh_v_w, int16_t, int32_t, idx_w, sth_w)
-GEN_VEXT_ST_INDEX(vsxh_v_d, int16_t, int64_t, idx_d, sth_d)
-GEN_VEXT_ST_INDEX(vsxw_v_w, int32_t, int32_t, idx_w, stw_w)
-GEN_VEXT_ST_INDEX(vsxw_v_d, int32_t, int64_t, idx_d, stw_d)
-GEN_VEXT_ST_INDEX(vsxe_v_b, int8_t, int8_t, idx_b, ste_b)
-GEN_VEXT_ST_INDEX(vsxe_v_h, int16_t, int16_t, idx_h, ste_h)
-GEN_VEXT_ST_INDEX(vsxe_v_w, int32_t, int32_t, idx_w, ste_w)
-GEN_VEXT_ST_INDEX(vsxe_v_d, int64_t, int64_t, idx_d, ste_d)
+GEN_VEXT_ST_INDEX(vsxei8_8_v, int8_t, idx_b, ste_b)
+GEN_VEXT_ST_INDEX(vsxei8_16_v, int16_t, idx_b, ste_h)
+GEN_VEXT_ST_INDEX(vsxei8_32_v, int32_t, idx_b, ste_w)
+GEN_VEXT_ST_INDEX(vsxei8_64_v, int64_t, idx_b, ste_d)
+GEN_VEXT_ST_INDEX(vsxei16_8_v, int8_t, idx_h, ste_b)
+GEN_VEXT_ST_INDEX(vsxei16_16_v, int16_t, idx_h, ste_h)
+GEN_VEXT_ST_INDEX(vsxei16_32_v, int32_t, idx_h, ste_w)
+GEN_VEXT_ST_INDEX(vsxei16_64_v, int64_t, idx_h, ste_d)
+GEN_VEXT_ST_INDEX(vsxei32_8_v, int8_t, idx_w, ste_b)
+GEN_VEXT_ST_INDEX(vsxei32_16_v, int16_t, idx_w, ste_h)
+GEN_VEXT_ST_INDEX(vsxei32_32_v, int32_t, idx_w, ste_w)
+GEN_VEXT_ST_INDEX(vsxei32_64_v, int64_t, idx_w, ste_d)
+GEN_VEXT_ST_INDEX(vsxei64_8_v, int8_t, idx_d, ste_b)
+GEN_VEXT_ST_INDEX(vsxei64_16_v, int16_t, idx_d, ste_h)
+GEN_VEXT_ST_INDEX(vsxei64_32_v, int32_t, idx_d, ste_w)
+GEN_VEXT_ST_INDEX(vsxei64_64_v, int64_t, idx_d, ste_d)
/*
*** unit-stride fault-only-fisrt load instructions
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 16/65] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Replace ETYPE from signed int to unsigned int to prevent index overflow
issue, which would lead to wrong index address.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/vector_helper.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a2926427ce..3ec56bb6fc 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -456,10 +456,10 @@ static target_ulong NAME(target_ulong base, \
return (base + *((ETYPE *)vs2 + H(idx))); \
}
-GEN_VEXT_GET_INDEX_ADDR(idx_b, int8_t, H1)
-GEN_VEXT_GET_INDEX_ADDR(idx_h, int16_t, H2)
-GEN_VEXT_GET_INDEX_ADDR(idx_w, int32_t, H4)
-GEN_VEXT_GET_INDEX_ADDR(idx_d, int64_t, H8)
+GEN_VEXT_GET_INDEX_ADDR(idx_b, uint8_t, H1)
+GEN_VEXT_GET_INDEX_ADDR(idx_h, uint16_t, H2)
+GEN_VEXT_GET_INDEX_ADDR(idx_w, uint32_t, H4)
+GEN_VEXT_GET_INDEX_ADDR(idx_d, uint64_t, H8)
static inline void
vext_ldst_index(void *vd, void *v0, target_ulong base,
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 16/65] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Replace ETYPE from signed int to unsigned int to prevent index overflow
issue, which would lead to wrong index address.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/vector_helper.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a2926427ce..3ec56bb6fc 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -456,10 +456,10 @@ static target_ulong NAME(target_ulong base, \
return (base + *((ETYPE *)vs2 + H(idx))); \
}
-GEN_VEXT_GET_INDEX_ADDR(idx_b, int8_t, H1)
-GEN_VEXT_GET_INDEX_ADDR(idx_h, int16_t, H2)
-GEN_VEXT_GET_INDEX_ADDR(idx_w, int32_t, H4)
-GEN_VEXT_GET_INDEX_ADDR(idx_d, int64_t, H8)
+GEN_VEXT_GET_INDEX_ADDR(idx_b, uint8_t, H1)
+GEN_VEXT_GET_INDEX_ADDR(idx_h, uint16_t, H2)
+GEN_VEXT_GET_INDEX_ADDR(idx_w, uint32_t, H4)
+GEN_VEXT_GET_INDEX_ADDR(idx_d, uint64_t, H8)
static inline void
vext_ldst_index(void *vd, void *v0, target_ulong base,
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 17/65] target/riscv: rvv-0.9: fault-only-first unit stride load
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 27 +++---------
target/riscv/insn32.decode | 14 +++----
target/riscv/insn_trans/trans_rvv.inc.c | 31 ++++----------
target/riscv/vector_helper.c | 56 +++++++++----------------
4 files changed, 38 insertions(+), 90 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 99ea68b0b9..d83d1def4e 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -140,28 +140,11 @@ DEF_HELPER_6(vsxei64_8_v, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsxei64_16_v, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsxei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsxei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_5(vlbff_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbff_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbff_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbff_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhff_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhff_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhff_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwff_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwff_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vleff_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vleff_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vleff_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vleff_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbuff_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbuff_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbuff_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbuff_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhuff_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle8ff_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle16ff_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle32ff_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle64ff_v, void, ptr, ptr, tl, env, i32)
+
#ifdef TARGET_RISCV64
DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 46542d162e..b0aaa186b8 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -249,14 +249,6 @@ vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
-vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm
-vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm
-vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm
-vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
-vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
-vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
-vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
-
# Vector indexed load insns.
vlxei8_v ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm
vlxei16_v ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm
@@ -269,6 +261,12 @@ vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm
vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm
vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm
+# Vector unit-stride fault-only-first load insns.
+vle8ff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
+vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
+vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
+vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
+
#*** Vector AMO operations are encoded under the standard AMO major opcode ***
vamoswapw_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamoaddw_v 00000 . . ..... ..... 110 ..... 0101111 @r_wdvm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 417edbe5a1..d8fea3af4c 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -771,25 +771,13 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_ldst_us *fn;
- static gen_helper_ldst_us * const fns[7][4] = {
- { gen_helper_vlbff_v_b, gen_helper_vlbff_v_h,
- gen_helper_vlbff_v_w, gen_helper_vlbff_v_d },
- { NULL, gen_helper_vlhff_v_h,
- gen_helper_vlhff_v_w, gen_helper_vlhff_v_d },
- { NULL, NULL,
- gen_helper_vlwff_v_w, gen_helper_vlwff_v_d },
- { gen_helper_vleff_v_b, gen_helper_vleff_v_h,
- gen_helper_vleff_v_w, gen_helper_vleff_v_d },
- { gen_helper_vlbuff_v_b, gen_helper_vlbuff_v_h,
- gen_helper_vlbuff_v_w, gen_helper_vlbuff_v_d },
- { NULL, gen_helper_vlhuff_v_h,
- gen_helper_vlhuff_v_w, gen_helper_vlhuff_v_d },
- { NULL, NULL,
- gen_helper_vlwuff_v_w, gen_helper_vlwuff_v_d }
+ static gen_helper_ldst_us * const fns[4] = {
+ gen_helper_vle8ff_v, gen_helper_vle16ff_v,
+ gen_helper_vle32ff_v, gen_helper_vle64ff_v
};
bool ret;
- fn = fns[seq][s->sew];
+ fn = fns[seq];
if (fn == NULL) {
return false;
}
@@ -805,13 +793,10 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
return ret;
}
-GEN_VEXT_TRANS(vlbff_v, 0, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vlhff_v, 1, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vlwff_v, 2, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vleff_v, 3, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vlbuff_v, 4, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vlhuff_v, 5, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vlwuff_v, 6, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vle8ff_v, 8, 0, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vle16ff_v, 16, 1, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vle32ff_v, 32, 2, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vle64ff_v, 64, 3, r2nfvm, ldff_op, ld_us_check)
/*
*** vector atomic operation
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 3ec56bb6fc..86d01a96a3 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -564,7 +564,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
CPURISCVState *env, uint32_t desc,
vext_ldst_elem_fn *ldst_elem,
clear_fn *clear_elem,
- uint32_t esz, uint32_t msz, uintptr_t ra)
+ uint32_t esz, uintptr_t ra)
{
void *host;
uint32_t i, k, vl = 0;
@@ -579,24 +579,24 @@ vext_ldff(void *vd, void *v0, target_ulong base,
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
- addr = base + nf * i * msz;
+ addr = base + nf * i * esz;
if (i == 0) {
- probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
+ probe_pages(env, addr, nf * esz, ra, MMU_DATA_LOAD);
} else {
/* if it triggers an exception, no need to check watchpoint */
- remain = nf * msz;
+ remain = nf * esz;
while (remain > 0) {
offset = -(addr | TARGET_PAGE_MASK);
host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD,
cpu_mmu_index(env, false));
if (host) {
#ifdef CONFIG_USER_ONLY
- if (page_check_range(addr, nf * msz, PAGE_READ) < 0) {
+ if (page_check_range(addr, nf * esz, PAGE_READ) < 0) {
vl = i;
goto ProbeSuccess;
}
#else
- probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
+ probe_pages(env, addr, nf * esz, ra, MMU_DATA_LOAD);
#endif
} else {
vl = i;
@@ -621,7 +621,7 @@ ProbeSuccess:
continue;
}
while (k < nf) {
- target_ulong addr = base + (i * nf + k) * msz;
+ target_ulong addr = base + (i * nf + k) * esz;
ldst_elem(env, addr, i + k * vlmax, vd, ra);
k++;
}
@@ -636,36 +636,18 @@ ProbeSuccess:
}
}
-#define GEN_VEXT_LDFF(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
-void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
- CPURISCVState *env, uint32_t desc) \
-{ \
- vext_ldff(vd, v0, base, env, desc, LOAD_FN, CLEAR_FN, \
- sizeof(ETYPE), sizeof(MTYPE), GETPC()); \
-}
-
-GEN_VEXT_LDFF(vlbff_v_b, int8_t, int8_t, ldb_b, clearb)
-GEN_VEXT_LDFF(vlbff_v_h, int8_t, int16_t, ldb_h, clearh)
-GEN_VEXT_LDFF(vlbff_v_w, int8_t, int32_t, ldb_w, clearl)
-GEN_VEXT_LDFF(vlbff_v_d, int8_t, int64_t, ldb_d, clearq)
-GEN_VEXT_LDFF(vlhff_v_h, int16_t, int16_t, ldh_h, clearh)
-GEN_VEXT_LDFF(vlhff_v_w, int16_t, int32_t, ldh_w, clearl)
-GEN_VEXT_LDFF(vlhff_v_d, int16_t, int64_t, ldh_d, clearq)
-GEN_VEXT_LDFF(vlwff_v_w, int32_t, int32_t, ldw_w, clearl)
-GEN_VEXT_LDFF(vlwff_v_d, int32_t, int64_t, ldw_d, clearq)
-GEN_VEXT_LDFF(vleff_v_b, int8_t, int8_t, lde_b, clearb)
-GEN_VEXT_LDFF(vleff_v_h, int16_t, int16_t, lde_h, clearh)
-GEN_VEXT_LDFF(vleff_v_w, int32_t, int32_t, lde_w, clearl)
-GEN_VEXT_LDFF(vleff_v_d, int64_t, int64_t, lde_d, clearq)
-GEN_VEXT_LDFF(vlbuff_v_b, uint8_t, uint8_t, ldbu_b, clearb)
-GEN_VEXT_LDFF(vlbuff_v_h, uint8_t, uint16_t, ldbu_h, clearh)
-GEN_VEXT_LDFF(vlbuff_v_w, uint8_t, uint32_t, ldbu_w, clearl)
-GEN_VEXT_LDFF(vlbuff_v_d, uint8_t, uint64_t, ldbu_d, clearq)
-GEN_VEXT_LDFF(vlhuff_v_h, uint16_t, uint16_t, ldhu_h, clearh)
-GEN_VEXT_LDFF(vlhuff_v_w, uint16_t, uint32_t, ldhu_w, clearl)
-GEN_VEXT_LDFF(vlhuff_v_d, uint16_t, uint64_t, ldhu_d, clearq)
-GEN_VEXT_LDFF(vlwuff_v_w, uint32_t, uint32_t, ldwu_w, clearl)
-GEN_VEXT_LDFF(vlwuff_v_d, uint32_t, uint64_t, ldwu_d, clearq)
+#define GEN_VEXT_LDFF(NAME, ETYPE, LOAD_FN, CLEAR_FN) \
+void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ vext_ldff(vd, v0, base, env, desc, LOAD_FN, CLEAR_FN, \
+ sizeof(ETYPE), GETPC()); \
+}
+
+GEN_VEXT_LDFF(vle8ff_v, int8_t, lde_b, clearb)
+GEN_VEXT_LDFF(vle16ff_v, int16_t, lde_h, clearh)
+GEN_VEXT_LDFF(vle32ff_v, int32_t, lde_w, clearl)
+GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d, clearq)
/*
*** Vector AMO Operations (Zvamo)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 17/65] target/riscv: rvv-0.9: fault-only-first unit stride load
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 27 +++---------
target/riscv/insn32.decode | 14 +++----
target/riscv/insn_trans/trans_rvv.inc.c | 31 ++++----------
target/riscv/vector_helper.c | 56 +++++++++----------------
4 files changed, 38 insertions(+), 90 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 99ea68b0b9..d83d1def4e 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -140,28 +140,11 @@ DEF_HELPER_6(vsxei64_8_v, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsxei64_16_v, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsxei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsxei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_5(vlbff_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbff_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbff_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbff_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhff_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhff_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhff_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwff_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwff_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vleff_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vleff_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vleff_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vleff_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbuff_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbuff_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbuff_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbuff_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhuff_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle8ff_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle16ff_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle32ff_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle64ff_v, void, ptr, ptr, tl, env, i32)
+
#ifdef TARGET_RISCV64
DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 46542d162e..b0aaa186b8 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -249,14 +249,6 @@ vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
-vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm
-vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm
-vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm
-vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
-vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
-vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
-vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
-
# Vector indexed load insns.
vlxei8_v ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm
vlxei16_v ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm
@@ -269,6 +261,12 @@ vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm
vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm
vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm
+# Vector unit-stride fault-only-first load insns.
+vle8ff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
+vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
+vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
+vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
+
#*** Vector AMO operations are encoded under the standard AMO major opcode ***
vamoswapw_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamoaddw_v 00000 . . ..... ..... 110 ..... 0101111 @r_wdvm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 417edbe5a1..d8fea3af4c 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -771,25 +771,13 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_ldst_us *fn;
- static gen_helper_ldst_us * const fns[7][4] = {
- { gen_helper_vlbff_v_b, gen_helper_vlbff_v_h,
- gen_helper_vlbff_v_w, gen_helper_vlbff_v_d },
- { NULL, gen_helper_vlhff_v_h,
- gen_helper_vlhff_v_w, gen_helper_vlhff_v_d },
- { NULL, NULL,
- gen_helper_vlwff_v_w, gen_helper_vlwff_v_d },
- { gen_helper_vleff_v_b, gen_helper_vleff_v_h,
- gen_helper_vleff_v_w, gen_helper_vleff_v_d },
- { gen_helper_vlbuff_v_b, gen_helper_vlbuff_v_h,
- gen_helper_vlbuff_v_w, gen_helper_vlbuff_v_d },
- { NULL, gen_helper_vlhuff_v_h,
- gen_helper_vlhuff_v_w, gen_helper_vlhuff_v_d },
- { NULL, NULL,
- gen_helper_vlwuff_v_w, gen_helper_vlwuff_v_d }
+ static gen_helper_ldst_us * const fns[4] = {
+ gen_helper_vle8ff_v, gen_helper_vle16ff_v,
+ gen_helper_vle32ff_v, gen_helper_vle64ff_v
};
bool ret;
- fn = fns[seq][s->sew];
+ fn = fns[seq];
if (fn == NULL) {
return false;
}
@@ -805,13 +793,10 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
return ret;
}
-GEN_VEXT_TRANS(vlbff_v, 0, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vlhff_v, 1, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vlwff_v, 2, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vleff_v, 3, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vlbuff_v, 4, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vlhuff_v, 5, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vlwuff_v, 6, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vle8ff_v, 8, 0, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vle16ff_v, 16, 1, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vle32ff_v, 32, 2, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vle64ff_v, 64, 3, r2nfvm, ldff_op, ld_us_check)
/*
*** vector atomic operation
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 3ec56bb6fc..86d01a96a3 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -564,7 +564,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
CPURISCVState *env, uint32_t desc,
vext_ldst_elem_fn *ldst_elem,
clear_fn *clear_elem,
- uint32_t esz, uint32_t msz, uintptr_t ra)
+ uint32_t esz, uintptr_t ra)
{
void *host;
uint32_t i, k, vl = 0;
@@ -579,24 +579,24 @@ vext_ldff(void *vd, void *v0, target_ulong base,
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
- addr = base + nf * i * msz;
+ addr = base + nf * i * esz;
if (i == 0) {
- probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
+ probe_pages(env, addr, nf * esz, ra, MMU_DATA_LOAD);
} else {
/* if it triggers an exception, no need to check watchpoint */
- remain = nf * msz;
+ remain = nf * esz;
while (remain > 0) {
offset = -(addr | TARGET_PAGE_MASK);
host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD,
cpu_mmu_index(env, false));
if (host) {
#ifdef CONFIG_USER_ONLY
- if (page_check_range(addr, nf * msz, PAGE_READ) < 0) {
+ if (page_check_range(addr, nf * esz, PAGE_READ) < 0) {
vl = i;
goto ProbeSuccess;
}
#else
- probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
+ probe_pages(env, addr, nf * esz, ra, MMU_DATA_LOAD);
#endif
} else {
vl = i;
@@ -621,7 +621,7 @@ ProbeSuccess:
continue;
}
while (k < nf) {
- target_ulong addr = base + (i * nf + k) * msz;
+ target_ulong addr = base + (i * nf + k) * esz;
ldst_elem(env, addr, i + k * vlmax, vd, ra);
k++;
}
@@ -636,36 +636,18 @@ ProbeSuccess:
}
}
-#define GEN_VEXT_LDFF(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
-void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
- CPURISCVState *env, uint32_t desc) \
-{ \
- vext_ldff(vd, v0, base, env, desc, LOAD_FN, CLEAR_FN, \
- sizeof(ETYPE), sizeof(MTYPE), GETPC()); \
-}
-
-GEN_VEXT_LDFF(vlbff_v_b, int8_t, int8_t, ldb_b, clearb)
-GEN_VEXT_LDFF(vlbff_v_h, int8_t, int16_t, ldb_h, clearh)
-GEN_VEXT_LDFF(vlbff_v_w, int8_t, int32_t, ldb_w, clearl)
-GEN_VEXT_LDFF(vlbff_v_d, int8_t, int64_t, ldb_d, clearq)
-GEN_VEXT_LDFF(vlhff_v_h, int16_t, int16_t, ldh_h, clearh)
-GEN_VEXT_LDFF(vlhff_v_w, int16_t, int32_t, ldh_w, clearl)
-GEN_VEXT_LDFF(vlhff_v_d, int16_t, int64_t, ldh_d, clearq)
-GEN_VEXT_LDFF(vlwff_v_w, int32_t, int32_t, ldw_w, clearl)
-GEN_VEXT_LDFF(vlwff_v_d, int32_t, int64_t, ldw_d, clearq)
-GEN_VEXT_LDFF(vleff_v_b, int8_t, int8_t, lde_b, clearb)
-GEN_VEXT_LDFF(vleff_v_h, int16_t, int16_t, lde_h, clearh)
-GEN_VEXT_LDFF(vleff_v_w, int32_t, int32_t, lde_w, clearl)
-GEN_VEXT_LDFF(vleff_v_d, int64_t, int64_t, lde_d, clearq)
-GEN_VEXT_LDFF(vlbuff_v_b, uint8_t, uint8_t, ldbu_b, clearb)
-GEN_VEXT_LDFF(vlbuff_v_h, uint8_t, uint16_t, ldbu_h, clearh)
-GEN_VEXT_LDFF(vlbuff_v_w, uint8_t, uint32_t, ldbu_w, clearl)
-GEN_VEXT_LDFF(vlbuff_v_d, uint8_t, uint64_t, ldbu_d, clearq)
-GEN_VEXT_LDFF(vlhuff_v_h, uint16_t, uint16_t, ldhu_h, clearh)
-GEN_VEXT_LDFF(vlhuff_v_w, uint16_t, uint32_t, ldhu_w, clearl)
-GEN_VEXT_LDFF(vlhuff_v_d, uint16_t, uint64_t, ldhu_d, clearq)
-GEN_VEXT_LDFF(vlwuff_v_w, uint32_t, uint32_t, ldwu_w, clearl)
-GEN_VEXT_LDFF(vlwuff_v_d, uint32_t, uint64_t, ldwu_d, clearq)
+#define GEN_VEXT_LDFF(NAME, ETYPE, LOAD_FN, CLEAR_FN) \
+void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ vext_ldff(vd, v0, base, env, desc, LOAD_FN, CLEAR_FN, \
+ sizeof(ETYPE), GETPC()); \
+}
+
+GEN_VEXT_LDFF(vle8ff_v, int8_t, lde_b, clearb)
+GEN_VEXT_LDFF(vle16ff_v, int16_t, lde_h, clearh)
+GEN_VEXT_LDFF(vle32ff_v, int32_t, lde_w, clearl)
+GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d, clearq)
/*
*** Vector AMO Operations (Zvamo)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 18/65] target/riscv: rvv-0.9: amo operations
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 100 ++++++++---
target/riscv/insn32-64.decode | 18 +-
target/riscv/insn32.decode | 36 +++-
target/riscv/insn_trans/trans_rvv.inc.c | 191 +++++++++++++-------
target/riscv/vector_helper.c | 228 ++++++++++++++++--------
5 files changed, 388 insertions(+), 185 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index d83d1def4e..22784b2d8c 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -145,36 +145,80 @@ DEF_HELPER_5(vle16ff_v, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vle32ff_v, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vle64ff_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_6(vamoswapei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoswapei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoswapei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoswapei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoswapei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoswapei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
#ifdef TARGET_RISCV64
-DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoaddw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoaddd_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoxorw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoxord_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoandw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoandd_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoorw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoord_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamominw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomind_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomaxw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomaxd_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamominuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamominud_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomaxuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomaxud_v_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoswapei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoswapei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
#endif
-DEF_HELPER_6(vamoswapw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoaddw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoxorw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoandw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoorw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamominw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomaxw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamominuw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomaxuw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-
DEF_HELPER_6(vadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 86153d93fa..c3283a5530 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -58,15 +58,15 @@ amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
#*** Vector AMO operations (in addition to Zvamo) ***
-vamoswapd_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoaddd_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoxord_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoandd_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoord_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoswapei64_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoaddei64_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoxorei64_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoandei64_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoorei64_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamominei64_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamomaxei64_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamominuei64_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamomaxuei64_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
# *** RV64F Standard Extension (in addition to RV32F) ***
fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b0aaa186b8..6a9cf6ad53 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -268,15 +268,33 @@ vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
#*** Vector AMO operations are encoded under the standard AMO major opcode ***
-vamoswapw_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamoaddw_v 00000 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamoxorw_v 00100 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamoandw_v 01100 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamoorw_v 01000 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamominw_v 10000 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamomaxw_v 10100 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamominuw_v 11000 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamomaxuw_v 11100 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamoswapei8_v 00001 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamoswapei16_v 00001 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamoswapei32_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamoaddei8_v 00000 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamoaddei16_v 00000 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamoaddei32_v 00000 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamoxorei8_v 00100 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamoxorei16_v 00100 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamoxorei32_v 00100 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamoandei8_v 01100 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamoandei16_v 01100 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamoandei32_v 01100 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamoorei8_v 01000 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamoorei16_v 01000 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamoorei32_v 01000 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamominei8_v 10000 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamominei16_v 10000 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamominei32_v 10000 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamomaxei8_v 10100 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamomaxei16_v 10100 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamomaxei32_v 10100 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamominuei8_v 11000 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamominuei16_v 11000 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamominuei32_v 11000 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamomaxuei8_v 11100 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamomaxuei16_v 11100 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamomaxuei32_v 11100 . . ..... ..... 110 ..... 0101111 @r_wdvm
# *** new major opcode OP-V ***
vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index d8fea3af4c..1ceac5ef30 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -200,6 +200,31 @@ static uint32_t vreg_ofs(DisasContext *s, int reg)
require_vm(vm, rd); \
} while (0)
+/*
+ * Vector AMO check function.
+ */
+#define VEXT_CHECK_AMO(s, rd, rs2, wd, vm) do { \
+ require(has_ext(s, RVA)); \
+ require((1 << s->sew) >= 4); \
+ require((1 << s->sew) <= sizeof(target_ulong)); \
+ require_align(rd, s->flmul); \
+ require_align(rs2, s->emul); \
+ require(s->emul >= 0.125 && s->emul <= 8); \
+ if (wd) { \
+ require_vm(vm, rd); \
+ if (s->eew > (1 << (s->sew + 3))) { \
+ if (rd != rs2) { \
+ require_noover(rd, s->flmul, rs2, s->emul); \
+ } \
+ } else if (s->eew < (1 << (s->sew + 3))) { \
+ if (s->emul < 1) { \
+ require_noover(rd, s->flmul, rs2, s->emul); \
+ } else { \
+ require_noover_widen(rd, s->flmul, rs2, s->emul); \
+ } \
+ } \
+ } \
+} while (0)
/*
* Check function for vector instruction with format:
@@ -840,38 +865,48 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_amo *fn;
- static gen_helper_amo *const fnsw[9] = {
+ static gen_helper_amo *const fns[27][2] = {
/* no atomic operation */
- gen_helper_vamoswapw_v_w,
- gen_helper_vamoaddw_v_w,
- gen_helper_vamoxorw_v_w,
- gen_helper_vamoandw_v_w,
- gen_helper_vamoorw_v_w,
- gen_helper_vamominw_v_w,
- gen_helper_vamomaxw_v_w,
- gen_helper_vamominuw_v_w,
- gen_helper_vamomaxuw_v_w
+ { gen_helper_vamoswapei8_32_v, gen_helper_vamoswapei8_64_v },
+ { gen_helper_vamoswapei16_32_v, gen_helper_vamoswapei16_64_v },
+ { gen_helper_vamoswapei32_32_v, gen_helper_vamoswapei32_64_v },
+ { gen_helper_vamoaddei8_32_v, gen_helper_vamoaddei8_64_v },
+ { gen_helper_vamoaddei16_32_v, gen_helper_vamoaddei16_64_v },
+ { gen_helper_vamoaddei32_32_v, gen_helper_vamoaddei32_64_v },
+ { gen_helper_vamoxorei8_32_v, gen_helper_vamoxorei8_64_v },
+ { gen_helper_vamoxorei16_32_v, gen_helper_vamoxorei16_64_v },
+ { gen_helper_vamoxorei32_32_v, gen_helper_vamoxorei32_64_v },
+ { gen_helper_vamoandei8_32_v, gen_helper_vamoandei8_64_v },
+ { gen_helper_vamoandei16_32_v, gen_helper_vamoandei16_64_v },
+ { gen_helper_vamoandei32_32_v, gen_helper_vamoandei32_64_v },
+ { gen_helper_vamoorei8_32_v, gen_helper_vamoorei8_64_v },
+ { gen_helper_vamoorei16_32_v, gen_helper_vamoorei16_64_v },
+ { gen_helper_vamoorei32_32_v, gen_helper_vamoorei32_64_v },
+ { gen_helper_vamominei8_32_v, gen_helper_vamominei8_64_v },
+ { gen_helper_vamominei16_32_v, gen_helper_vamominei16_64_v },
+ { gen_helper_vamominei32_32_v, gen_helper_vamominei32_64_v },
+ { gen_helper_vamomaxei8_32_v, gen_helper_vamomaxei8_64_v },
+ { gen_helper_vamomaxei16_32_v, gen_helper_vamomaxei16_64_v },
+ { gen_helper_vamomaxei32_32_v, gen_helper_vamomaxei32_64_v },
+ { gen_helper_vamominuei8_32_v, gen_helper_vamominuei8_64_v },
+ { gen_helper_vamominuei16_32_v, gen_helper_vamominuei16_64_v },
+ { gen_helper_vamominuei32_32_v, gen_helper_vamominuei32_64_v },
+ { gen_helper_vamomaxuei8_32_v, gen_helper_vamomaxuei8_64_v },
+ { gen_helper_vamomaxuei16_32_v, gen_helper_vamomaxuei16_64_v },
+ { gen_helper_vamomaxuei32_32_v, gen_helper_vamomaxuei32_64_v }
};
+
#ifdef TARGET_RISCV64
- static gen_helper_amo *const fnsd[18] = {
- gen_helper_vamoswapw_v_d,
- gen_helper_vamoaddw_v_d,
- gen_helper_vamoxorw_v_d,
- gen_helper_vamoandw_v_d,
- gen_helper_vamoorw_v_d,
- gen_helper_vamominw_v_d,
- gen_helper_vamomaxw_v_d,
- gen_helper_vamominuw_v_d,
- gen_helper_vamomaxuw_v_d,
- gen_helper_vamoswapd_v_d,
- gen_helper_vamoaddd_v_d,
- gen_helper_vamoxord_v_d,
- gen_helper_vamoandd_v_d,
- gen_helper_vamoord_v_d,
- gen_helper_vamomind_v_d,
- gen_helper_vamomaxd_v_d,
- gen_helper_vamominud_v_d,
- gen_helper_vamomaxud_v_d
+ static gen_helper_amo *const fns64[9][2] = {
+ { gen_helper_vamoswapei64_32_v, gen_helper_vamoswapei64_64_v },
+ { gen_helper_vamoaddei64_32_v, gen_helper_vamoaddei64_64_v },
+ { gen_helper_vamoxorei64_32_v, gen_helper_vamoxorei64_64_v },
+ { gen_helper_vamoandei64_32_v, gen_helper_vamoandei64_64_v },
+ { gen_helper_vamoorei64_32_v, gen_helper_vamoorei64_64_v },
+ { gen_helper_vamominei64_32_v, gen_helper_vamominei64_64_v },
+ { gen_helper_vamomaxei64_32_v, gen_helper_vamomaxei64_64_v },
+ { gen_helper_vamominuei64_32_v, gen_helper_vamominuei64_64_v },
+ { gen_helper_vamomaxuei64_32_v, gen_helper_vamomaxuei64_64_v }
};
#endif
bool ret;
@@ -881,15 +916,25 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
s->base.is_jmp = DISAS_NORETURN;
return true;
} else {
- if (s->sew == 3) {
+ if (s->eew == 64) {
#ifdef TARGET_RISCV64
- fn = fnsd[seq];
+ /* EEW == 64. */
+ fn = fns64[seq][s->sew - 2];
+#else
+ /* RV32 does not support EEW = 64 AMO insns. */
+ g_assert_not_reached();
+#endif
+ } else if (s->sew == 3) {
+#ifdef TARGET_RISCV64
+ /* EEW <= 32 && SEW == 64. */
+ fn = fns[seq][s->sew - 2];
#else
/* Check done in amo_check(). */
g_assert_not_reached();
#endif
} else {
- fn = fnsw[seq];
+ /* EEW <= 32 && SEW == 32. */
+ fn = fns[seq][s->sew - 2];
}
}
@@ -903,42 +948,58 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
mark_vs_dirty(s);
return ret;
}
-/*
- * There are two rules check here.
- *
- * 1. SEW must be at least as wide as the AMO memory element size.
- *
- * 2. If SEW is greater than XLEN, an illegal instruction exception is raised.
- */
+
+
static bool amo_check(DisasContext *s, arg_rwdvm* a)
{
- return (!s->vill && has_ext(s, RVA) &&
- (!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- ((1 << s->sew) <= sizeof(target_ulong)) &&
- ((1 << s->sew) >= 4));
-}
-
-GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoandw_v, 3, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoorw_v, 4, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check)
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_AMO(s, a->rd, a->rs2, a->wd, a->vm);
+ return true;
+}
+
+GEN_VEXT_TRANS(vamoswapei8_v, 8, 0, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoswapei16_v, 16, 1, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoswapei32_v, 32, 2, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoaddei8_v, 8, 3, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoaddei16_v, 16, 4, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoaddei32_v, 32, 5, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoxorei8_v, 8, 6, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoxorei16_v, 16, 7, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoxorei32_v, 32, 8, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoandei8_v, 8, 9, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoandei16_v, 16, 10, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoandei32_v, 32, 11, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoorei8_v, 8, 12, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoorei16_v, 16, 13, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoorei32_v, 32, 14, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamominei8_v, 8, 15, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamominei16_v, 16, 16, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamominei32_v, 32, 17, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomaxei8_v, 8, 18, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomaxei16_v, 16, 19, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomaxei32_v, 32, 20, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamominuei8_v, 8, 21, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamominuei16_v, 16, 22, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamominuei32_v, 32, 23, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomaxuei8_v, 8, 24, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomaxuei16_v, 16, 25, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomaxuei32_v, 32, 26, rwdvm, amo_op, amo_check)
+
+/*
+ * Index EEW cannot be greater than XLEN,
+ * else an illegal instruction is raised (Section 8)
+ */
#ifdef TARGET_RISCV64
-GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoswapei64_v, 64, 0, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoaddei64_v, 64, 1, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoxorei64_v, 64, 2, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoandei64_v, 64, 3, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoorei64_v, 64, 4, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamominei64_v, 64, 5, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomaxei64_v, 64, 6, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamominuei64_v, 64, 7, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomaxuei64_v, 64, 8, rwdvm, amo_op, amo_check)
#endif
/*
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 86d01a96a3..dc9bd0b68a 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -656,23 +656,22 @@ typedef void vext_amo_noatomic_fn(void *vs3, target_ulong addr,
uint32_t wd, uint32_t idx, CPURISCVState *env,
uintptr_t retaddr);
-/* no atomic opreation for vector atomic insructions */
+/* no atomic operation for vector atomic instructions */
#define DO_SWAP(N, M) (M)
#define DO_AND(N, M) (N & M)
#define DO_XOR(N, M) (N ^ M)
#define DO_OR(N, M) (N | M)
#define DO_ADD(N, M) (N + M)
+#define DO_MAX(N, M) ((N) >= (M) ? (N) : (M))
+#define DO_MIN(N, M) ((N) >= (M) ? (M) : (N))
-#define GEN_VEXT_AMO_NOATOMIC_OP(NAME, ESZ, MSZ, H, DO_OP, SUF) \
+#define GEN_VEXT_AMO_NOATOMIC_OP(NAME, MTYPE, H, DO_OP, SUF) \
static void \
vext_##NAME##_noatomic_op(void *vs3, target_ulong addr, \
uint32_t wd, uint32_t idx, \
CPURISCVState *env, uintptr_t retaddr)\
{ \
- typedef int##ESZ##_t ETYPE; \
- typedef int##MSZ##_t MTYPE; \
- typedef uint##MSZ##_t UMTYPE __attribute__((unused)); \
- ETYPE *pe3 = (ETYPE *)vs3 + H(idx); \
+ MTYPE *pe3 = (MTYPE *)vs3 + H(idx); \
MTYPE a = cpu_ld##SUF##_data(env, addr), b = *pe3; \
\
cpu_st##SUF##_data(env, addr, DO_OP(a, b)); \
@@ -681,42 +680,79 @@ vext_##NAME##_noatomic_op(void *vs3, target_ulong addr, \
} \
}
-/* Signed min/max */
-#define DO_MAX(N, M) ((N) >= (M) ? (N) : (M))
-#define DO_MIN(N, M) ((N) >= (M) ? (M) : (N))
-
-/* Unsigned min/max */
-#define DO_MAXU(N, M) DO_MAX((UMTYPE)N, (UMTYPE)M)
-#define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M)
-
-GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_w, 32, 32, H4, DO_SWAP, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_w, 32, 32, H4, DO_ADD, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_w, 32, 32, H4, DO_XOR, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_w, 32, 32, H4, DO_AND, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_w, 32, 32, H4, DO_OR, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_w, 32, 32, H4, DO_MIN, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_w, 32, 32, H4, DO_MAX, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_w, 32, 32, H4, DO_MINU, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_w, 32, 32, H4, DO_MAXU, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei8_32_v, uint32_t, H4, DO_SWAP, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei8_64_v, uint64_t, H8, DO_SWAP, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei16_32_v, uint32_t, H4, DO_SWAP, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei16_64_v, uint64_t, H8, DO_SWAP, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei32_32_v, uint32_t, H4, DO_SWAP, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei32_64_v, uint64_t, H8, DO_SWAP, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei8_32_v, uint32_t, H4, DO_ADD, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei8_64_v, uint64_t, H8, DO_ADD, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei16_32_v, uint32_t, H4, DO_ADD, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei16_64_v, uint64_t, H8, DO_ADD, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei32_32_v, uint32_t, H4, DO_ADD, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei32_64_v, uint64_t, H8, DO_ADD, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei8_32_v, uint32_t, H4, DO_XOR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei8_64_v, uint64_t, H8, DO_XOR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei16_32_v, uint32_t, H4, DO_XOR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei16_64_v, uint64_t, H8, DO_XOR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei32_32_v, uint32_t, H4, DO_XOR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei32_64_v, uint64_t, H8, DO_XOR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei8_32_v, uint32_t, H4, DO_AND, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei8_64_v, uint64_t, H8, DO_AND, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei16_32_v, uint32_t, H4, DO_AND, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei16_64_v, uint64_t, H8, DO_AND, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei32_32_v, uint32_t, H4, DO_AND, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei32_64_v, uint64_t, H8, DO_AND, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei8_32_v, uint32_t, H4, DO_OR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei8_64_v, uint64_t, H8, DO_OR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei16_32_v, uint32_t, H4, DO_OR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei16_64_v, uint64_t, H8, DO_OR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei32_32_v, uint32_t, H4, DO_OR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei32_64_v, uint64_t, H8, DO_OR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei8_32_v, int32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei8_64_v, int64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei16_32_v, int32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei16_64_v, int64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei32_32_v, int32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei32_64_v, int64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei8_32_v, int32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei8_64_v, int64_t, H8, DO_MAX, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei16_32_v, int32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei16_64_v, int64_t, H8, DO_MAX, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei32_32_v, int32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei32_64_v, int64_t, H8, DO_MAX, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei8_32_v, uint32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei8_64_v, uint64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei16_32_v, uint32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei16_64_v, uint64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei32_32_v, uint32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei32_64_v, uint64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei8_32_v, uint32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei8_64_v, uint64_t, H8, DO_MAX, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei16_32_v, uint32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei16_64_v, uint64_t, H8, DO_MAX, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei32_32_v, uint32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei32_64_v, uint64_t, H8, DO_MAX, q)
#ifdef TARGET_RISCV64
-GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_d, 64, 32, H8, DO_SWAP, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoswapd_v_d, 64, 64, H8, DO_SWAP, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_d, 64, 32, H8, DO_ADD, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoaddd_v_d, 64, 64, H8, DO_ADD, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_d, 64, 32, H8, DO_XOR, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoxord_v_d, 64, 64, H8, DO_XOR, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_d, 64, 32, H8, DO_AND, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoandd_v_d, 64, 64, H8, DO_AND, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_d, 64, 32, H8, DO_OR, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoord_v_d, 64, 64, H8, DO_OR, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_d, 64, 32, H8, DO_MIN, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamomind_v_d, 64, 64, H8, DO_MIN, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_d, 64, 32, H8, DO_MAX, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamomaxd_v_d, 64, 64, H8, DO_MAX, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_d, 64, 32, H8, DO_MINU, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamominud_v_d, 64, 64, H8, DO_MINU, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_d, 64, 32, H8, DO_MAXU, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamomaxud_v_d, 64, 64, H8, DO_MAXU, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei64_32_v, uint32_t, H4, DO_SWAP, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei64_64_v, uint64_t, H8, DO_SWAP, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei64_32_v, uint32_t, H4, DO_ADD, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei64_64_v, uint64_t, H8, DO_ADD, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei64_32_v, uint32_t, H4, DO_XOR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei64_64_v, uint64_t, H8, DO_XOR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei64_32_v, uint32_t, H4, DO_AND, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei64_64_v, uint64_t, H8, DO_AND, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei64_32_v, uint32_t, H4, DO_OR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei64_64_v, uint64_t, H8, DO_OR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei64_32_v, int32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei64_64_v, int64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei64_32_v, int32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei64_64_v, int64_t, H8, DO_MAX, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei64_32_v, uint32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei64_64_v, uint64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei64_32_v, uint32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei64_64_v, uint64_t, H8, DO_MAX, q)
#endif
static inline void
@@ -724,8 +760,7 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
void *vs2, CPURISCVState *env, uint32_t desc,
vext_get_index_addr get_index_addr,
vext_amo_noatomic_fn *noatomic_op,
- clear_fn *clear_elem,
- uint32_t esz, uint32_t msz, uintptr_t ra)
+ clear_fn *clear_elem, uint32_t esz, uintptr_t ra)
{
uint32_t i;
target_long addr;
@@ -738,8 +773,8 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
- probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_LOAD);
- probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_STORE);
+ probe_pages(env, get_index_addr(base, i, vs2), esz, ra, MMU_DATA_LOAD);
+ probe_pages(env, get_index_addr(base, i, vs2), esz, ra, MMU_DATA_STORE);
}
for (i = 0; i < env->vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
@@ -751,45 +786,90 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
clear_elem(vs3, vta, env->vl, env->vl * esz, vlmax * esz);
}
-#define GEN_VEXT_AMO(NAME, MTYPE, ETYPE, INDEX_FN, CLEAR_FN) \
+#define GEN_VEXT_AMO(NAME, ETYPE, INDEX_FN, CLEAR_FN) \
void HELPER(NAME)(void *vs3, void *v0, target_ulong base, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
vext_amo_noatomic(vs3, v0, base, vs2, env, desc, \
INDEX_FN, vext_##NAME##_noatomic_op, \
- CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
+ CLEAR_FN, sizeof(ETYPE), \
GETPC()); \
}
+GEN_VEXT_AMO(vamoswapei8_32_v, int32_t, idx_b, clearl)
+GEN_VEXT_AMO(vamoswapei8_64_v, int64_t, idx_b, clearq)
+GEN_VEXT_AMO(vamoswapei16_32_v, int32_t, idx_h, clearl)
+GEN_VEXT_AMO(vamoswapei16_64_v, int64_t, idx_h, clearq)
+GEN_VEXT_AMO(vamoswapei32_32_v, int32_t, idx_w, clearl)
+GEN_VEXT_AMO(vamoswapei32_64_v, int64_t, idx_w, clearq)
+GEN_VEXT_AMO(vamoaddei8_32_v, int32_t, idx_b, clearl)
+GEN_VEXT_AMO(vamoaddei8_64_v, int64_t, idx_b, clearq)
+GEN_VEXT_AMO(vamoaddei16_32_v, int32_t, idx_h, clearl)
+GEN_VEXT_AMO(vamoaddei16_64_v, int64_t, idx_h, clearq)
+GEN_VEXT_AMO(vamoaddei32_32_v, int32_t, idx_w, clearl)
+GEN_VEXT_AMO(vamoaddei32_64_v, int64_t, idx_w, clearq)
+GEN_VEXT_AMO(vamoxorei8_32_v, int32_t, idx_b, clearl)
+GEN_VEXT_AMO(vamoxorei8_64_v, int64_t, idx_b, clearq)
+GEN_VEXT_AMO(vamoxorei16_32_v, int32_t, idx_h, clearl)
+GEN_VEXT_AMO(vamoxorei16_64_v, int64_t, idx_h, clearq)
+GEN_VEXT_AMO(vamoxorei32_32_v, int32_t, idx_w, clearl)
+GEN_VEXT_AMO(vamoxorei32_64_v, int64_t, idx_w, clearq)
+GEN_VEXT_AMO(vamoandei8_32_v, int32_t, idx_b, clearl)
+GEN_VEXT_AMO(vamoandei8_64_v, int64_t, idx_b, clearq)
+GEN_VEXT_AMO(vamoandei16_32_v, int32_t, idx_h, clearl)
+GEN_VEXT_AMO(vamoandei16_64_v, int64_t, idx_h, clearq)
+GEN_VEXT_AMO(vamoandei32_32_v, int32_t, idx_w, clearl)
+GEN_VEXT_AMO(vamoandei32_64_v, int64_t, idx_w, clearq)
+GEN_VEXT_AMO(vamoorei8_32_v, int32_t, idx_b, clearl)
+GEN_VEXT_AMO(vamoorei8_64_v, int64_t, idx_b, clearq)
+GEN_VEXT_AMO(vamoorei16_32_v, int32_t, idx_h, clearl)
+GEN_VEXT_AMO(vamoorei16_64_v, int64_t, idx_h, clearq)
+GEN_VEXT_AMO(vamoorei32_32_v, int32_t, idx_w, clearl)
+GEN_VEXT_AMO(vamoorei32_64_v, int64_t, idx_w, clearq)
+GEN_VEXT_AMO(vamominei8_32_v, int32_t, idx_b, clearl)
+GEN_VEXT_AMO(vamominei8_64_v, int64_t, idx_b, clearq)
+GEN_VEXT_AMO(vamominei16_32_v, int32_t, idx_h, clearl)
+GEN_VEXT_AMO(vamominei16_64_v, int64_t, idx_h, clearq)
+GEN_VEXT_AMO(vamominei32_32_v, int32_t, idx_w, clearl)
+GEN_VEXT_AMO(vamominei32_64_v, int64_t, idx_w, clearq)
+GEN_VEXT_AMO(vamomaxei8_32_v, int32_t, idx_b, clearl)
+GEN_VEXT_AMO(vamomaxei8_64_v, int64_t, idx_b, clearq)
+GEN_VEXT_AMO(vamomaxei16_32_v, int32_t, idx_h, clearl)
+GEN_VEXT_AMO(vamomaxei16_64_v, int64_t, idx_h, clearq)
+GEN_VEXT_AMO(vamomaxei32_32_v, int32_t, idx_w, clearl)
+GEN_VEXT_AMO(vamomaxei32_64_v, int64_t, idx_w, clearq)
+GEN_VEXT_AMO(vamominuei8_32_v, int32_t, idx_b, clearl)
+GEN_VEXT_AMO(vamominuei8_64_v, int64_t, idx_b, clearq)
+GEN_VEXT_AMO(vamominuei16_32_v, int32_t, idx_h, clearl)
+GEN_VEXT_AMO(vamominuei16_64_v, int64_t, idx_h, clearq)
+GEN_VEXT_AMO(vamominuei32_32_v, int32_t, idx_w, clearl)
+GEN_VEXT_AMO(vamominuei32_64_v, int64_t, idx_w, clearq)
+GEN_VEXT_AMO(vamomaxuei8_32_v, int32_t, idx_b, clearl)
+GEN_VEXT_AMO(vamomaxuei8_64_v, int64_t, idx_b, clearq)
+GEN_VEXT_AMO(vamomaxuei16_32_v, int32_t, idx_h, clearl)
+GEN_VEXT_AMO(vamomaxuei16_64_v, int64_t, idx_h, clearq)
+GEN_VEXT_AMO(vamomaxuei32_32_v, int32_t, idx_w, clearl)
+GEN_VEXT_AMO(vamomaxuei32_64_v, int64_t, idx_w, clearq)
#ifdef TARGET_RISCV64
-GEN_VEXT_AMO(vamoswapw_v_d, int32_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoswapd_v_d, int64_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoaddw_v_d, int32_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoaddd_v_d, int64_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoxorw_v_d, int32_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoxord_v_d, int64_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoandw_v_d, int32_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoandd_v_d, int64_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoorw_v_d, int32_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoord_v_d, int64_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamominw_v_d, int32_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamomind_v_d, int64_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamomaxw_v_d, int32_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamomaxd_v_d, int64_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d, clearq)
+GEN_VEXT_AMO(vamoswapei64_32_v, int32_t, idx_d, clearl)
+GEN_VEXT_AMO(vamoswapei64_64_v, int64_t, idx_d, clearq)
+GEN_VEXT_AMO(vamoaddei64_32_v, int32_t, idx_d, clearl)
+GEN_VEXT_AMO(vamoaddei64_64_v, int64_t, idx_d, clearq)
+GEN_VEXT_AMO(vamoxorei64_32_v, int32_t, idx_d, clearl)
+GEN_VEXT_AMO(vamoxorei64_64_v, int64_t, idx_d, clearq)
+GEN_VEXT_AMO(vamoandei64_32_v, int32_t, idx_d, clearl)
+GEN_VEXT_AMO(vamoandei64_64_v, int64_t, idx_d, clearq)
+GEN_VEXT_AMO(vamoorei64_32_v, int32_t, idx_d, clearl)
+GEN_VEXT_AMO(vamoorei64_64_v, int64_t, idx_d, clearq)
+GEN_VEXT_AMO(vamominei64_32_v, int32_t, idx_d, clearl)
+GEN_VEXT_AMO(vamominei64_64_v, int64_t, idx_d, clearq)
+GEN_VEXT_AMO(vamomaxei64_32_v, int32_t, idx_d, clearl)
+GEN_VEXT_AMO(vamomaxei64_64_v, int64_t, idx_d, clearq)
+GEN_VEXT_AMO(vamominuei64_32_v, int32_t, idx_d, clearl)
+GEN_VEXT_AMO(vamominuei64_64_v, int64_t, idx_d, clearq)
+GEN_VEXT_AMO(vamomaxuei64_32_v, int32_t, idx_d, clearl)
+GEN_VEXT_AMO(vamomaxuei64_64_v, int64_t, idx_d, clearq)
#endif
-GEN_VEXT_AMO(vamoswapw_v_w, int32_t, int32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamoaddw_v_w, int32_t, int32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamoxorw_v_w, int32_t, int32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamoandw_v_w, int32_t, int32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamoorw_v_w, int32_t, int32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamominw_v_w, int32_t, int32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamomaxw_v_w, int32_t, int32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamominuw_v_w, uint32_t, uint32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w, clearl)
/*
*** Vector Integer Arithmetic Instructions
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 18/65] target/riscv: rvv-0.9: amo operations
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 100 ++++++++---
target/riscv/insn32-64.decode | 18 +-
target/riscv/insn32.decode | 36 +++-
target/riscv/insn_trans/trans_rvv.inc.c | 191 +++++++++++++-------
target/riscv/vector_helper.c | 228 ++++++++++++++++--------
5 files changed, 388 insertions(+), 185 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index d83d1def4e..22784b2d8c 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -145,36 +145,80 @@ DEF_HELPER_5(vle16ff_v, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vle32ff_v, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vle64ff_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_6(vamoswapei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoswapei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoswapei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoswapei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoswapei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoswapei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
#ifdef TARGET_RISCV64
-DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoaddw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoaddd_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoxorw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoxord_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoandw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoandd_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoorw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoord_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamominw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomind_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomaxw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomaxd_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamominuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamominud_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomaxuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomaxud_v_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoswapei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoswapei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
#endif
-DEF_HELPER_6(vamoswapw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoaddw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoxorw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoandw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoorw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamominw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomaxw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamominuw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomaxuw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-
DEF_HELPER_6(vadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 86153d93fa..c3283a5530 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -58,15 +58,15 @@ amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
#*** Vector AMO operations (in addition to Zvamo) ***
-vamoswapd_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoaddd_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoxord_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoandd_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoord_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoswapei64_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoaddei64_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoxorei64_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoandei64_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoorei64_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamominei64_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamomaxei64_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamominuei64_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamomaxuei64_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
# *** RV64F Standard Extension (in addition to RV32F) ***
fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b0aaa186b8..6a9cf6ad53 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -268,15 +268,33 @@ vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
#*** Vector AMO operations are encoded under the standard AMO major opcode ***
-vamoswapw_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamoaddw_v 00000 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamoxorw_v 00100 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamoandw_v 01100 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamoorw_v 01000 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamominw_v 10000 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamomaxw_v 10100 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamominuw_v 11000 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamomaxuw_v 11100 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamoswapei8_v 00001 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamoswapei16_v 00001 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamoswapei32_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamoaddei8_v 00000 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamoaddei16_v 00000 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamoaddei32_v 00000 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamoxorei8_v 00100 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamoxorei16_v 00100 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamoxorei32_v 00100 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamoandei8_v 01100 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamoandei16_v 01100 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamoandei32_v 01100 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamoorei8_v 01000 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamoorei16_v 01000 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamoorei32_v 01000 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamominei8_v 10000 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamominei16_v 10000 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamominei32_v 10000 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamomaxei8_v 10100 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamomaxei16_v 10100 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamomaxei32_v 10100 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamominuei8_v 11000 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamominuei16_v 11000 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamominuei32_v 11000 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamomaxuei8_v 11100 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamomaxuei16_v 11100 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamomaxuei32_v 11100 . . ..... ..... 110 ..... 0101111 @r_wdvm
# *** new major opcode OP-V ***
vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index d8fea3af4c..1ceac5ef30 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -200,6 +200,31 @@ static uint32_t vreg_ofs(DisasContext *s, int reg)
require_vm(vm, rd); \
} while (0)
+/*
+ * Vector AMO check function.
+ */
+#define VEXT_CHECK_AMO(s, rd, rs2, wd, vm) do { \
+ require(has_ext(s, RVA)); \
+ require((1 << s->sew) >= 4); \
+ require((1 << s->sew) <= sizeof(target_ulong)); \
+ require_align(rd, s->flmul); \
+ require_align(rs2, s->emul); \
+ require(s->emul >= 0.125 && s->emul <= 8); \
+ if (wd) { \
+ require_vm(vm, rd); \
+ if (s->eew > (1 << (s->sew + 3))) { \
+ if (rd != rs2) { \
+ require_noover(rd, s->flmul, rs2, s->emul); \
+ } \
+ } else if (s->eew < (1 << (s->sew + 3))) { \
+ if (s->emul < 1) { \
+ require_noover(rd, s->flmul, rs2, s->emul); \
+ } else { \
+ require_noover_widen(rd, s->flmul, rs2, s->emul); \
+ } \
+ } \
+ } \
+} while (0)
/*
* Check function for vector instruction with format:
@@ -840,38 +865,48 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_amo *fn;
- static gen_helper_amo *const fnsw[9] = {
+ static gen_helper_amo *const fns[27][2] = {
/* no atomic operation */
- gen_helper_vamoswapw_v_w,
- gen_helper_vamoaddw_v_w,
- gen_helper_vamoxorw_v_w,
- gen_helper_vamoandw_v_w,
- gen_helper_vamoorw_v_w,
- gen_helper_vamominw_v_w,
- gen_helper_vamomaxw_v_w,
- gen_helper_vamominuw_v_w,
- gen_helper_vamomaxuw_v_w
+ { gen_helper_vamoswapei8_32_v, gen_helper_vamoswapei8_64_v },
+ { gen_helper_vamoswapei16_32_v, gen_helper_vamoswapei16_64_v },
+ { gen_helper_vamoswapei32_32_v, gen_helper_vamoswapei32_64_v },
+ { gen_helper_vamoaddei8_32_v, gen_helper_vamoaddei8_64_v },
+ { gen_helper_vamoaddei16_32_v, gen_helper_vamoaddei16_64_v },
+ { gen_helper_vamoaddei32_32_v, gen_helper_vamoaddei32_64_v },
+ { gen_helper_vamoxorei8_32_v, gen_helper_vamoxorei8_64_v },
+ { gen_helper_vamoxorei16_32_v, gen_helper_vamoxorei16_64_v },
+ { gen_helper_vamoxorei32_32_v, gen_helper_vamoxorei32_64_v },
+ { gen_helper_vamoandei8_32_v, gen_helper_vamoandei8_64_v },
+ { gen_helper_vamoandei16_32_v, gen_helper_vamoandei16_64_v },
+ { gen_helper_vamoandei32_32_v, gen_helper_vamoandei32_64_v },
+ { gen_helper_vamoorei8_32_v, gen_helper_vamoorei8_64_v },
+ { gen_helper_vamoorei16_32_v, gen_helper_vamoorei16_64_v },
+ { gen_helper_vamoorei32_32_v, gen_helper_vamoorei32_64_v },
+ { gen_helper_vamominei8_32_v, gen_helper_vamominei8_64_v },
+ { gen_helper_vamominei16_32_v, gen_helper_vamominei16_64_v },
+ { gen_helper_vamominei32_32_v, gen_helper_vamominei32_64_v },
+ { gen_helper_vamomaxei8_32_v, gen_helper_vamomaxei8_64_v },
+ { gen_helper_vamomaxei16_32_v, gen_helper_vamomaxei16_64_v },
+ { gen_helper_vamomaxei32_32_v, gen_helper_vamomaxei32_64_v },
+ { gen_helper_vamominuei8_32_v, gen_helper_vamominuei8_64_v },
+ { gen_helper_vamominuei16_32_v, gen_helper_vamominuei16_64_v },
+ { gen_helper_vamominuei32_32_v, gen_helper_vamominuei32_64_v },
+ { gen_helper_vamomaxuei8_32_v, gen_helper_vamomaxuei8_64_v },
+ { gen_helper_vamomaxuei16_32_v, gen_helper_vamomaxuei16_64_v },
+ { gen_helper_vamomaxuei32_32_v, gen_helper_vamomaxuei32_64_v }
};
+
#ifdef TARGET_RISCV64
- static gen_helper_amo *const fnsd[18] = {
- gen_helper_vamoswapw_v_d,
- gen_helper_vamoaddw_v_d,
- gen_helper_vamoxorw_v_d,
- gen_helper_vamoandw_v_d,
- gen_helper_vamoorw_v_d,
- gen_helper_vamominw_v_d,
- gen_helper_vamomaxw_v_d,
- gen_helper_vamominuw_v_d,
- gen_helper_vamomaxuw_v_d,
- gen_helper_vamoswapd_v_d,
- gen_helper_vamoaddd_v_d,
- gen_helper_vamoxord_v_d,
- gen_helper_vamoandd_v_d,
- gen_helper_vamoord_v_d,
- gen_helper_vamomind_v_d,
- gen_helper_vamomaxd_v_d,
- gen_helper_vamominud_v_d,
- gen_helper_vamomaxud_v_d
+ static gen_helper_amo *const fns64[9][2] = {
+ { gen_helper_vamoswapei64_32_v, gen_helper_vamoswapei64_64_v },
+ { gen_helper_vamoaddei64_32_v, gen_helper_vamoaddei64_64_v },
+ { gen_helper_vamoxorei64_32_v, gen_helper_vamoxorei64_64_v },
+ { gen_helper_vamoandei64_32_v, gen_helper_vamoandei64_64_v },
+ { gen_helper_vamoorei64_32_v, gen_helper_vamoorei64_64_v },
+ { gen_helper_vamominei64_32_v, gen_helper_vamominei64_64_v },
+ { gen_helper_vamomaxei64_32_v, gen_helper_vamomaxei64_64_v },
+ { gen_helper_vamominuei64_32_v, gen_helper_vamominuei64_64_v },
+ { gen_helper_vamomaxuei64_32_v, gen_helper_vamomaxuei64_64_v }
};
#endif
bool ret;
@@ -881,15 +916,25 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
s->base.is_jmp = DISAS_NORETURN;
return true;
} else {
- if (s->sew == 3) {
+ if (s->eew == 64) {
#ifdef TARGET_RISCV64
- fn = fnsd[seq];
+ /* EEW == 64. */
+ fn = fns64[seq][s->sew - 2];
+#else
+ /* RV32 does not support EEW = 64 AMO insns. */
+ g_assert_not_reached();
+#endif
+ } else if (s->sew == 3) {
+#ifdef TARGET_RISCV64
+ /* EEW <= 32 && SEW == 64. */
+ fn = fns[seq][s->sew - 2];
#else
/* Check done in amo_check(). */
g_assert_not_reached();
#endif
} else {
- fn = fnsw[seq];
+ /* EEW <= 32 && SEW == 32. */
+ fn = fns[seq][s->sew - 2];
}
}
@@ -903,42 +948,58 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
mark_vs_dirty(s);
return ret;
}
-/*
- * There are two rules check here.
- *
- * 1. SEW must be at least as wide as the AMO memory element size.
- *
- * 2. If SEW is greater than XLEN, an illegal instruction exception is raised.
- */
+
+
static bool amo_check(DisasContext *s, arg_rwdvm* a)
{
- return (!s->vill && has_ext(s, RVA) &&
- (!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- ((1 << s->sew) <= sizeof(target_ulong)) &&
- ((1 << s->sew) >= 4));
-}
-
-GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoandw_v, 3, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoorw_v, 4, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check)
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_AMO(s, a->rd, a->rs2, a->wd, a->vm);
+ return true;
+}
+
+GEN_VEXT_TRANS(vamoswapei8_v, 8, 0, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoswapei16_v, 16, 1, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoswapei32_v, 32, 2, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoaddei8_v, 8, 3, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoaddei16_v, 16, 4, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoaddei32_v, 32, 5, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoxorei8_v, 8, 6, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoxorei16_v, 16, 7, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoxorei32_v, 32, 8, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoandei8_v, 8, 9, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoandei16_v, 16, 10, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoandei32_v, 32, 11, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoorei8_v, 8, 12, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoorei16_v, 16, 13, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoorei32_v, 32, 14, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamominei8_v, 8, 15, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamominei16_v, 16, 16, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamominei32_v, 32, 17, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomaxei8_v, 8, 18, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomaxei16_v, 16, 19, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomaxei32_v, 32, 20, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamominuei8_v, 8, 21, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamominuei16_v, 16, 22, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamominuei32_v, 32, 23, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomaxuei8_v, 8, 24, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomaxuei16_v, 16, 25, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomaxuei32_v, 32, 26, rwdvm, amo_op, amo_check)
+
+/*
+ * Index EEW cannot be greater than XLEN,
+ * else an illegal instruction is raised (Section 8)
+ */
#ifdef TARGET_RISCV64
-GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoswapei64_v, 64, 0, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoaddei64_v, 64, 1, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoxorei64_v, 64, 2, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoandei64_v, 64, 3, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoorei64_v, 64, 4, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamominei64_v, 64, 5, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomaxei64_v, 64, 6, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamominuei64_v, 64, 7, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomaxuei64_v, 64, 8, rwdvm, amo_op, amo_check)
#endif
/*
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 86d01a96a3..dc9bd0b68a 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -656,23 +656,22 @@ typedef void vext_amo_noatomic_fn(void *vs3, target_ulong addr,
uint32_t wd, uint32_t idx, CPURISCVState *env,
uintptr_t retaddr);
-/* no atomic opreation for vector atomic insructions */
+/* no atomic operation for vector atomic instructions */
#define DO_SWAP(N, M) (M)
#define DO_AND(N, M) (N & M)
#define DO_XOR(N, M) (N ^ M)
#define DO_OR(N, M) (N | M)
#define DO_ADD(N, M) (N + M)
+#define DO_MAX(N, M) ((N) >= (M) ? (N) : (M))
+#define DO_MIN(N, M) ((N) >= (M) ? (M) : (N))
-#define GEN_VEXT_AMO_NOATOMIC_OP(NAME, ESZ, MSZ, H, DO_OP, SUF) \
+#define GEN_VEXT_AMO_NOATOMIC_OP(NAME, MTYPE, H, DO_OP, SUF) \
static void \
vext_##NAME##_noatomic_op(void *vs3, target_ulong addr, \
uint32_t wd, uint32_t idx, \
CPURISCVState *env, uintptr_t retaddr)\
{ \
- typedef int##ESZ##_t ETYPE; \
- typedef int##MSZ##_t MTYPE; \
- typedef uint##MSZ##_t UMTYPE __attribute__((unused)); \
- ETYPE *pe3 = (ETYPE *)vs3 + H(idx); \
+ MTYPE *pe3 = (MTYPE *)vs3 + H(idx); \
MTYPE a = cpu_ld##SUF##_data(env, addr), b = *pe3; \
\
cpu_st##SUF##_data(env, addr, DO_OP(a, b)); \
@@ -681,42 +680,79 @@ vext_##NAME##_noatomic_op(void *vs3, target_ulong addr, \
} \
}
-/* Signed min/max */
-#define DO_MAX(N, M) ((N) >= (M) ? (N) : (M))
-#define DO_MIN(N, M) ((N) >= (M) ? (M) : (N))
-
-/* Unsigned min/max */
-#define DO_MAXU(N, M) DO_MAX((UMTYPE)N, (UMTYPE)M)
-#define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M)
-
-GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_w, 32, 32, H4, DO_SWAP, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_w, 32, 32, H4, DO_ADD, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_w, 32, 32, H4, DO_XOR, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_w, 32, 32, H4, DO_AND, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_w, 32, 32, H4, DO_OR, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_w, 32, 32, H4, DO_MIN, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_w, 32, 32, H4, DO_MAX, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_w, 32, 32, H4, DO_MINU, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_w, 32, 32, H4, DO_MAXU, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei8_32_v, uint32_t, H4, DO_SWAP, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei8_64_v, uint64_t, H8, DO_SWAP, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei16_32_v, uint32_t, H4, DO_SWAP, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei16_64_v, uint64_t, H8, DO_SWAP, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei32_32_v, uint32_t, H4, DO_SWAP, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei32_64_v, uint64_t, H8, DO_SWAP, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei8_32_v, uint32_t, H4, DO_ADD, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei8_64_v, uint64_t, H8, DO_ADD, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei16_32_v, uint32_t, H4, DO_ADD, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei16_64_v, uint64_t, H8, DO_ADD, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei32_32_v, uint32_t, H4, DO_ADD, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei32_64_v, uint64_t, H8, DO_ADD, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei8_32_v, uint32_t, H4, DO_XOR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei8_64_v, uint64_t, H8, DO_XOR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei16_32_v, uint32_t, H4, DO_XOR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei16_64_v, uint64_t, H8, DO_XOR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei32_32_v, uint32_t, H4, DO_XOR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei32_64_v, uint64_t, H8, DO_XOR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei8_32_v, uint32_t, H4, DO_AND, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei8_64_v, uint64_t, H8, DO_AND, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei16_32_v, uint32_t, H4, DO_AND, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei16_64_v, uint64_t, H8, DO_AND, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei32_32_v, uint32_t, H4, DO_AND, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei32_64_v, uint64_t, H8, DO_AND, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei8_32_v, uint32_t, H4, DO_OR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei8_64_v, uint64_t, H8, DO_OR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei16_32_v, uint32_t, H4, DO_OR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei16_64_v, uint64_t, H8, DO_OR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei32_32_v, uint32_t, H4, DO_OR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei32_64_v, uint64_t, H8, DO_OR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei8_32_v, int32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei8_64_v, int64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei16_32_v, int32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei16_64_v, int64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei32_32_v, int32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei32_64_v, int64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei8_32_v, int32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei8_64_v, int64_t, H8, DO_MAX, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei16_32_v, int32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei16_64_v, int64_t, H8, DO_MAX, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei32_32_v, int32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei32_64_v, int64_t, H8, DO_MAX, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei8_32_v, uint32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei8_64_v, uint64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei16_32_v, uint32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei16_64_v, uint64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei32_32_v, uint32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei32_64_v, uint64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei8_32_v, uint32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei8_64_v, uint64_t, H8, DO_MAX, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei16_32_v, uint32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei16_64_v, uint64_t, H8, DO_MAX, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei32_32_v, uint32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei32_64_v, uint64_t, H8, DO_MAX, q)
#ifdef TARGET_RISCV64
-GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_d, 64, 32, H8, DO_SWAP, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoswapd_v_d, 64, 64, H8, DO_SWAP, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_d, 64, 32, H8, DO_ADD, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoaddd_v_d, 64, 64, H8, DO_ADD, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_d, 64, 32, H8, DO_XOR, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoxord_v_d, 64, 64, H8, DO_XOR, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_d, 64, 32, H8, DO_AND, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoandd_v_d, 64, 64, H8, DO_AND, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_d, 64, 32, H8, DO_OR, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoord_v_d, 64, 64, H8, DO_OR, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_d, 64, 32, H8, DO_MIN, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamomind_v_d, 64, 64, H8, DO_MIN, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_d, 64, 32, H8, DO_MAX, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamomaxd_v_d, 64, 64, H8, DO_MAX, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_d, 64, 32, H8, DO_MINU, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamominud_v_d, 64, 64, H8, DO_MINU, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_d, 64, 32, H8, DO_MAXU, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamomaxud_v_d, 64, 64, H8, DO_MAXU, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei64_32_v, uint32_t, H4, DO_SWAP, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei64_64_v, uint64_t, H8, DO_SWAP, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei64_32_v, uint32_t, H4, DO_ADD, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei64_64_v, uint64_t, H8, DO_ADD, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei64_32_v, uint32_t, H4, DO_XOR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei64_64_v, uint64_t, H8, DO_XOR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei64_32_v, uint32_t, H4, DO_AND, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei64_64_v, uint64_t, H8, DO_AND, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei64_32_v, uint32_t, H4, DO_OR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei64_64_v, uint64_t, H8, DO_OR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei64_32_v, int32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei64_64_v, int64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei64_32_v, int32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei64_64_v, int64_t, H8, DO_MAX, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei64_32_v, uint32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei64_64_v, uint64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei64_32_v, uint32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei64_64_v, uint64_t, H8, DO_MAX, q)
#endif
static inline void
@@ -724,8 +760,7 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
void *vs2, CPURISCVState *env, uint32_t desc,
vext_get_index_addr get_index_addr,
vext_amo_noatomic_fn *noatomic_op,
- clear_fn *clear_elem,
- uint32_t esz, uint32_t msz, uintptr_t ra)
+ clear_fn *clear_elem, uint32_t esz, uintptr_t ra)
{
uint32_t i;
target_long addr;
@@ -738,8 +773,8 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
- probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_LOAD);
- probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_STORE);
+ probe_pages(env, get_index_addr(base, i, vs2), esz, ra, MMU_DATA_LOAD);
+ probe_pages(env, get_index_addr(base, i, vs2), esz, ra, MMU_DATA_STORE);
}
for (i = 0; i < env->vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
@@ -751,45 +786,90 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
clear_elem(vs3, vta, env->vl, env->vl * esz, vlmax * esz);
}
-#define GEN_VEXT_AMO(NAME, MTYPE, ETYPE, INDEX_FN, CLEAR_FN) \
+#define GEN_VEXT_AMO(NAME, ETYPE, INDEX_FN, CLEAR_FN) \
void HELPER(NAME)(void *vs3, void *v0, target_ulong base, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
vext_amo_noatomic(vs3, v0, base, vs2, env, desc, \
INDEX_FN, vext_##NAME##_noatomic_op, \
- CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
+ CLEAR_FN, sizeof(ETYPE), \
GETPC()); \
}
+GEN_VEXT_AMO(vamoswapei8_32_v, int32_t, idx_b, clearl)
+GEN_VEXT_AMO(vamoswapei8_64_v, int64_t, idx_b, clearq)
+GEN_VEXT_AMO(vamoswapei16_32_v, int32_t, idx_h, clearl)
+GEN_VEXT_AMO(vamoswapei16_64_v, int64_t, idx_h, clearq)
+GEN_VEXT_AMO(vamoswapei32_32_v, int32_t, idx_w, clearl)
+GEN_VEXT_AMO(vamoswapei32_64_v, int64_t, idx_w, clearq)
+GEN_VEXT_AMO(vamoaddei8_32_v, int32_t, idx_b, clearl)
+GEN_VEXT_AMO(vamoaddei8_64_v, int64_t, idx_b, clearq)
+GEN_VEXT_AMO(vamoaddei16_32_v, int32_t, idx_h, clearl)
+GEN_VEXT_AMO(vamoaddei16_64_v, int64_t, idx_h, clearq)
+GEN_VEXT_AMO(vamoaddei32_32_v, int32_t, idx_w, clearl)
+GEN_VEXT_AMO(vamoaddei32_64_v, int64_t, idx_w, clearq)
+GEN_VEXT_AMO(vamoxorei8_32_v, int32_t, idx_b, clearl)
+GEN_VEXT_AMO(vamoxorei8_64_v, int64_t, idx_b, clearq)
+GEN_VEXT_AMO(vamoxorei16_32_v, int32_t, idx_h, clearl)
+GEN_VEXT_AMO(vamoxorei16_64_v, int64_t, idx_h, clearq)
+GEN_VEXT_AMO(vamoxorei32_32_v, int32_t, idx_w, clearl)
+GEN_VEXT_AMO(vamoxorei32_64_v, int64_t, idx_w, clearq)
+GEN_VEXT_AMO(vamoandei8_32_v, int32_t, idx_b, clearl)
+GEN_VEXT_AMO(vamoandei8_64_v, int64_t, idx_b, clearq)
+GEN_VEXT_AMO(vamoandei16_32_v, int32_t, idx_h, clearl)
+GEN_VEXT_AMO(vamoandei16_64_v, int64_t, idx_h, clearq)
+GEN_VEXT_AMO(vamoandei32_32_v, int32_t, idx_w, clearl)
+GEN_VEXT_AMO(vamoandei32_64_v, int64_t, idx_w, clearq)
+GEN_VEXT_AMO(vamoorei8_32_v, int32_t, idx_b, clearl)
+GEN_VEXT_AMO(vamoorei8_64_v, int64_t, idx_b, clearq)
+GEN_VEXT_AMO(vamoorei16_32_v, int32_t, idx_h, clearl)
+GEN_VEXT_AMO(vamoorei16_64_v, int64_t, idx_h, clearq)
+GEN_VEXT_AMO(vamoorei32_32_v, int32_t, idx_w, clearl)
+GEN_VEXT_AMO(vamoorei32_64_v, int64_t, idx_w, clearq)
+GEN_VEXT_AMO(vamominei8_32_v, int32_t, idx_b, clearl)
+GEN_VEXT_AMO(vamominei8_64_v, int64_t, idx_b, clearq)
+GEN_VEXT_AMO(vamominei16_32_v, int32_t, idx_h, clearl)
+GEN_VEXT_AMO(vamominei16_64_v, int64_t, idx_h, clearq)
+GEN_VEXT_AMO(vamominei32_32_v, int32_t, idx_w, clearl)
+GEN_VEXT_AMO(vamominei32_64_v, int64_t, idx_w, clearq)
+GEN_VEXT_AMO(vamomaxei8_32_v, int32_t, idx_b, clearl)
+GEN_VEXT_AMO(vamomaxei8_64_v, int64_t, idx_b, clearq)
+GEN_VEXT_AMO(vamomaxei16_32_v, int32_t, idx_h, clearl)
+GEN_VEXT_AMO(vamomaxei16_64_v, int64_t, idx_h, clearq)
+GEN_VEXT_AMO(vamomaxei32_32_v, int32_t, idx_w, clearl)
+GEN_VEXT_AMO(vamomaxei32_64_v, int64_t, idx_w, clearq)
+GEN_VEXT_AMO(vamominuei8_32_v, int32_t, idx_b, clearl)
+GEN_VEXT_AMO(vamominuei8_64_v, int64_t, idx_b, clearq)
+GEN_VEXT_AMO(vamominuei16_32_v, int32_t, idx_h, clearl)
+GEN_VEXT_AMO(vamominuei16_64_v, int64_t, idx_h, clearq)
+GEN_VEXT_AMO(vamominuei32_32_v, int32_t, idx_w, clearl)
+GEN_VEXT_AMO(vamominuei32_64_v, int64_t, idx_w, clearq)
+GEN_VEXT_AMO(vamomaxuei8_32_v, int32_t, idx_b, clearl)
+GEN_VEXT_AMO(vamomaxuei8_64_v, int64_t, idx_b, clearq)
+GEN_VEXT_AMO(vamomaxuei16_32_v, int32_t, idx_h, clearl)
+GEN_VEXT_AMO(vamomaxuei16_64_v, int64_t, idx_h, clearq)
+GEN_VEXT_AMO(vamomaxuei32_32_v, int32_t, idx_w, clearl)
+GEN_VEXT_AMO(vamomaxuei32_64_v, int64_t, idx_w, clearq)
#ifdef TARGET_RISCV64
-GEN_VEXT_AMO(vamoswapw_v_d, int32_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoswapd_v_d, int64_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoaddw_v_d, int32_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoaddd_v_d, int64_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoxorw_v_d, int32_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoxord_v_d, int64_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoandw_v_d, int32_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoandd_v_d, int64_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoorw_v_d, int32_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoord_v_d, int64_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamominw_v_d, int32_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamomind_v_d, int64_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamomaxw_v_d, int32_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamomaxd_v_d, int64_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d, clearq)
+GEN_VEXT_AMO(vamoswapei64_32_v, int32_t, idx_d, clearl)
+GEN_VEXT_AMO(vamoswapei64_64_v, int64_t, idx_d, clearq)
+GEN_VEXT_AMO(vamoaddei64_32_v, int32_t, idx_d, clearl)
+GEN_VEXT_AMO(vamoaddei64_64_v, int64_t, idx_d, clearq)
+GEN_VEXT_AMO(vamoxorei64_32_v, int32_t, idx_d, clearl)
+GEN_VEXT_AMO(vamoxorei64_64_v, int64_t, idx_d, clearq)
+GEN_VEXT_AMO(vamoandei64_32_v, int32_t, idx_d, clearl)
+GEN_VEXT_AMO(vamoandei64_64_v, int64_t, idx_d, clearq)
+GEN_VEXT_AMO(vamoorei64_32_v, int32_t, idx_d, clearl)
+GEN_VEXT_AMO(vamoorei64_64_v, int64_t, idx_d, clearq)
+GEN_VEXT_AMO(vamominei64_32_v, int32_t, idx_d, clearl)
+GEN_VEXT_AMO(vamominei64_64_v, int64_t, idx_d, clearq)
+GEN_VEXT_AMO(vamomaxei64_32_v, int32_t, idx_d, clearl)
+GEN_VEXT_AMO(vamomaxei64_64_v, int64_t, idx_d, clearq)
+GEN_VEXT_AMO(vamominuei64_32_v, int32_t, idx_d, clearl)
+GEN_VEXT_AMO(vamominuei64_64_v, int64_t, idx_d, clearq)
+GEN_VEXT_AMO(vamomaxuei64_32_v, int32_t, idx_d, clearl)
+GEN_VEXT_AMO(vamomaxuei64_64_v, int64_t, idx_d, clearq)
#endif
-GEN_VEXT_AMO(vamoswapw_v_w, int32_t, int32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamoaddw_v_w, int32_t, int32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamoxorw_v_w, int32_t, int32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamoandw_v_w, int32_t, int32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamoorw_v_w, int32_t, int32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamominw_v_w, int32_t, int32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamomaxw_v_w, int32_t, int32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamominuw_v_w, uint32_t, uint32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w, clearl)
/*
*** Vector Integer Arithmetic Instructions
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 19/65] target/riscv: rvv-0.9: load/store whole register instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Add the following instructions:
* vl1r.v
* vs1r.v
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 3 ++
target/riscv/insn32.decode | 4 ++
target/riscv/insn_trans/trans_rvv.inc.c | 55 +++++++++++++++++++++++++
target/riscv/vector_helper.c | 46 +++++++++++++++++++++
4 files changed, 108 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 22784b2d8c..924c334f71 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -145,6 +145,9 @@ DEF_HELPER_5(vle16ff_v, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vle32ff_v, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vle64ff_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_4(vl1r_v, void, ptr, tl, env, i32)
+DEF_HELPER_4(vs1r_v, void, ptr, tl, env, i32)
+
DEF_HELPER_6(vamoswapei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamoswapei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamoswapei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6a9cf6ad53..e3f0fba912 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -267,6 +267,10 @@ vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
+# Vector whole register insns
+vl1r_v 000 000 1 01000 ..... 000 ..... 0000111 @r2
+vs1r_v 000 000 1 01000 ..... 000 ..... 0100111 @r2
+
#*** Vector AMO operations are encoded under the standard AMO major opcode ***
vamoswapei8_v 00001 . . ..... ..... 000 ..... 0101111 @r_wdvm
vamoswapei16_v 00001 . . ..... ..... 101 ..... 0101111 @r_wdvm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 1ceac5ef30..7db62053ab 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -823,6 +823,61 @@ GEN_VEXT_TRANS(vle16ff_v, 16, 1, r2nfvm, ldff_op, ld_us_check)
GEN_VEXT_TRANS(vle32ff_v, 32, 2, r2nfvm, ldff_op, ld_us_check)
GEN_VEXT_TRANS(vle64ff_v, 64, 3, r2nfvm, ldff_op, ld_us_check)
+/*
+ * load and store whole register instructions
+ */
+typedef void gen_helper_ldst_whole(TCGv_ptr, TCGv, TCGv_env, TCGv_i32);
+
+static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t data,
+ gen_helper_ldst_whole *fn, DisasContext *s)
+{
+ TCGv_ptr dest;
+ TCGv base;
+ TCGv_i32 desc;
+
+ dest = tcg_temp_new_ptr();
+ base = tcg_temp_new();
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+
+ gen_get_gpr(base, rs1);
+ tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
+
+ fn(dest, base, cpu_env, desc);
+
+ tcg_temp_free_ptr(dest);
+ tcg_temp_free(base);
+ tcg_temp_free_i32(desc);
+ return true;
+}
+
+/*
+ * load and store whole register instructions ignore vtype and vl setting.
+ * Thus, we don't need to check vill bit. (Section 7.9)
+ */
+#define GEN_LDST_WHOLE_TRANS(NAME, EEW, SEQ, ARGTYPE, ARG_NF) \
+static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE * a) \
+{ \
+ s->eew = EEW; \
+ s->emul = (float)EEW / (1 << (s->sew + 3)) * s->flmul; \
+ \
+ REQUIRE_RVV; \
+ \
+ uint32_t data = 0; \
+ bool ret; \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, SEW, s->sew); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
+ data = FIELD_DP32(data, VDATA, NF, ARG_NF); \
+ ret = ldst_whole_trans(a->rd, a->rs1, data, gen_helper_##NAME, s); \
+ mark_vs_dirty(s); \
+ return ret; \
+}
+
+GEN_LDST_WHOLE_TRANS(vl1r_v, 8, 0, vl1r_v, 1)
+
+GEN_LDST_WHOLE_TRANS(vs1r_v, 8, 1, vs1r_v, 1)
+
/*
*** vector atomic operation
*/
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index dc9bd0b68a..39b9a462ab 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -649,6 +649,52 @@ GEN_VEXT_LDFF(vle16ff_v, int16_t, lde_h, clearh)
GEN_VEXT_LDFF(vle32ff_v, int32_t, lde_w, clearl)
GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d, clearq)
+/*
+ *** load and store whole register instructions
+ */
+static void
+vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
+ vext_ldst_elem_fn *ldst_elem, uint32_t esz, uintptr_t ra,
+ MMUAccessType access_type)
+{
+ uint32_t i, k;
+ uint32_t nf = vext_nf(desc);
+ uint32_t vlmax = vext_maxsz(desc) / esz;
+
+ /* probe every access */
+ probe_pages(env, base, env->vlenb * nf * esz, ra, access_type);
+
+ /* load bytes from guest memory */
+ for (i = 0; i < env->vlenb; i++) {
+ k = 0;
+ while (k < nf) {
+ target_ulong addr = base + (i * nf + k) * esz;
+ ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ k++;
+ }
+ }
+}
+
+#define GEN_VEXT_LD_WHOLE(NAME, ETYPE, LOAD_FN) \
+void HELPER(NAME)(void *vd, target_ulong base, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ vext_ldst_whole(vd, base, env, desc, LOAD_FN, \
+ sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \
+}
+
+GEN_VEXT_LD_WHOLE(vl1r_v, int8_t, lde_b)
+
+#define GEN_VEXT_ST_WHOLE(NAME, ETYPE, STORE_FN) \
+void HELPER(NAME)(void *vd, target_ulong base, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ vext_ldst_whole(vd, base, env, desc, STORE_FN, \
+ sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \
+}
+
+GEN_VEXT_ST_WHOLE(vs1r_v, int8_t, ste_b)
+
/*
*** Vector AMO Operations (Zvamo)
*/
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 19/65] target/riscv: rvv-0.9: load/store whole register instructions
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Add the following instructions:
* vl1r.v
* vs1r.v
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 3 ++
target/riscv/insn32.decode | 4 ++
target/riscv/insn_trans/trans_rvv.inc.c | 55 +++++++++++++++++++++++++
target/riscv/vector_helper.c | 46 +++++++++++++++++++++
4 files changed, 108 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 22784b2d8c..924c334f71 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -145,6 +145,9 @@ DEF_HELPER_5(vle16ff_v, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vle32ff_v, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vle64ff_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_4(vl1r_v, void, ptr, tl, env, i32)
+DEF_HELPER_4(vs1r_v, void, ptr, tl, env, i32)
+
DEF_HELPER_6(vamoswapei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamoswapei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamoswapei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6a9cf6ad53..e3f0fba912 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -267,6 +267,10 @@ vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
+# Vector whole register insns
+vl1r_v 000 000 1 01000 ..... 000 ..... 0000111 @r2
+vs1r_v 000 000 1 01000 ..... 000 ..... 0100111 @r2
+
#*** Vector AMO operations are encoded under the standard AMO major opcode ***
vamoswapei8_v 00001 . . ..... ..... 000 ..... 0101111 @r_wdvm
vamoswapei16_v 00001 . . ..... ..... 101 ..... 0101111 @r_wdvm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 1ceac5ef30..7db62053ab 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -823,6 +823,61 @@ GEN_VEXT_TRANS(vle16ff_v, 16, 1, r2nfvm, ldff_op, ld_us_check)
GEN_VEXT_TRANS(vle32ff_v, 32, 2, r2nfvm, ldff_op, ld_us_check)
GEN_VEXT_TRANS(vle64ff_v, 64, 3, r2nfvm, ldff_op, ld_us_check)
+/*
+ * load and store whole register instructions
+ */
+typedef void gen_helper_ldst_whole(TCGv_ptr, TCGv, TCGv_env, TCGv_i32);
+
+static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t data,
+ gen_helper_ldst_whole *fn, DisasContext *s)
+{
+ TCGv_ptr dest;
+ TCGv base;
+ TCGv_i32 desc;
+
+ dest = tcg_temp_new_ptr();
+ base = tcg_temp_new();
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+
+ gen_get_gpr(base, rs1);
+ tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
+
+ fn(dest, base, cpu_env, desc);
+
+ tcg_temp_free_ptr(dest);
+ tcg_temp_free(base);
+ tcg_temp_free_i32(desc);
+ return true;
+}
+
+/*
+ * load and store whole register instructions ignore vtype and vl setting.
+ * Thus, we don't need to check vill bit. (Section 7.9)
+ */
+#define GEN_LDST_WHOLE_TRANS(NAME, EEW, SEQ, ARGTYPE, ARG_NF) \
+static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE * a) \
+{ \
+ s->eew = EEW; \
+ s->emul = (float)EEW / (1 << (s->sew + 3)) * s->flmul; \
+ \
+ REQUIRE_RVV; \
+ \
+ uint32_t data = 0; \
+ bool ret; \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, SEW, s->sew); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
+ data = FIELD_DP32(data, VDATA, NF, ARG_NF); \
+ ret = ldst_whole_trans(a->rd, a->rs1, data, gen_helper_##NAME, s); \
+ mark_vs_dirty(s); \
+ return ret; \
+}
+
+GEN_LDST_WHOLE_TRANS(vl1r_v, 8, 0, vl1r_v, 1)
+
+GEN_LDST_WHOLE_TRANS(vs1r_v, 8, 1, vs1r_v, 1)
+
/*
*** vector atomic operation
*/
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index dc9bd0b68a..39b9a462ab 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -649,6 +649,52 @@ GEN_VEXT_LDFF(vle16ff_v, int16_t, lde_h, clearh)
GEN_VEXT_LDFF(vle32ff_v, int32_t, lde_w, clearl)
GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d, clearq)
+/*
+ *** load and store whole register instructions
+ */
+static void
+vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
+ vext_ldst_elem_fn *ldst_elem, uint32_t esz, uintptr_t ra,
+ MMUAccessType access_type)
+{
+ uint32_t i, k;
+ uint32_t nf = vext_nf(desc);
+ uint32_t vlmax = vext_maxsz(desc) / esz;
+
+ /* probe every access */
+ probe_pages(env, base, env->vlenb * nf * esz, ra, access_type);
+
+ /* load bytes from guest memory */
+ for (i = 0; i < env->vlenb; i++) {
+ k = 0;
+ while (k < nf) {
+ target_ulong addr = base + (i * nf + k) * esz;
+ ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ k++;
+ }
+ }
+}
+
+#define GEN_VEXT_LD_WHOLE(NAME, ETYPE, LOAD_FN) \
+void HELPER(NAME)(void *vd, target_ulong base, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ vext_ldst_whole(vd, base, env, desc, LOAD_FN, \
+ sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \
+}
+
+GEN_VEXT_LD_WHOLE(vl1r_v, int8_t, lde_b)
+
+#define GEN_VEXT_ST_WHOLE(NAME, ETYPE, STORE_FN) \
+void HELPER(NAME)(void *vd, target_ulong base, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ vext_ldst_whole(vd, base, env, desc, STORE_FN, \
+ sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \
+}
+
+GEN_VEXT_ST_WHOLE(vs1r_v, int8_t, ste_b)
+
/*
*** Vector AMO Operations (Zvamo)
*/
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 20/65] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/vector_helper.c | 118 ++++++++++++++++++++---------------
1 file changed, 68 insertions(+), 50 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 39b9a462ab..2a006f956c 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -129,14 +129,32 @@ static inline uint32_t vext_vma(uint32_t desc)
}
/*
- * Get vector group length in bytes. Its range is [64, 2048].
- *
- * As simd_desc support at most 256, the max vlen is 512 bits.
- * So vlen in bytes is encoded as maxsz.
+ * Get the maximum number of elements can be operated.
*/
-static inline uint32_t vext_maxsz(uint32_t desc)
+static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz, bool is_ldst)
{
- return simd_maxsz(desc) << vext_lmul(desc);
+ /*
+ * As simd_desc support at most 256, the max vlen is 512 bits,
+ * so vlen in bytes (vlenb) is encoded as maxsz.
+ */
+ uint32_t vlenb = simd_maxsz(desc);
+
+ if (is_ldst) {
+ /*
+ * Vector load/store instructions have the EEW encoded
+ * directly in the instructions. The maximum vector size is
+ * calculated with EMUL rather than LMUL.
+ */
+ uint32_t eew = esz << 3;
+ uint32_t sew = vext_sew(desc);
+ float flmul = vext_vflmul(desc);
+ float emul = (float)eew / sew * flmul;
+ uint32_t emul_r = emul < 1 ? 1 : emul;
+ return vlenb * emul_r / esz;
+ } else {
+ /* Return VLMAX */
+ return vlenb * vext_vflmul(desc) / esz;
+ }
}
/*
@@ -296,7 +314,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t max_elems = vext_max_elems(desc, esz, true);
uint32_t vta = vext_vta(desc);
/* probe every access*/
@@ -314,15 +332,15 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
}
while (k < nf) {
target_ulong addr = base + stride * i + k * esz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ ldst_elem(env, addr, i + k * max_elems, vd, ra);
k++;
}
}
/* clear tail elements */
if (clear_elem) {
for (k = 0; k < nf; k++) {
- clear_elem(vd, vta, env->vl + k * vlmax,
- env->vl * esz, vlmax * esz);
+ clear_elem(vd, vta, env->vl + k * max_elems,
+ env->vl * esz, max_elems * esz);
}
}
}
@@ -371,7 +389,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t max_elems = vext_max_elems(desc, esz, true);
uint32_t vta = vext_vta(desc);
/* probe every access */
@@ -381,15 +399,15 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
k = 0;
while (k < nf) {
target_ulong addr = base + (i * nf + k) * esz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ ldst_elem(env, addr, i + k * max_elems, vd, ra);
k++;
}
}
/* clear tail elements */
if (clear_elem) {
for (k = 0; k < nf; k++) {
- clear_elem(vd, vta, env->vl + k * vlmax,
- env->vl * esz, vlmax * esz);
+ clear_elem(vd, vta, env->vl + k * max_elems,
+ env->vl * esz, max_elems * esz);
}
}
}
@@ -472,7 +490,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
uint32_t i, k;
uint32_t nf = vext_nf(desc);
uint32_t vm = vext_vm(desc);
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t max_elems = vext_max_elems(desc, esz, true);
uint32_t vta = vext_vta(desc);
/* probe every access*/
@@ -491,15 +509,15 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
}
while (k < nf) {
abi_ptr addr = get_index_addr(base, i, vs2) + k * esz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ ldst_elem(env, addr, i + k * max_elems, vd, ra);
k++;
}
}
/* clear tail elements */
if (clear_elem) {
for (k = 0; k < nf; k++) {
- clear_elem(vd, vta, env->vl + k * vlmax,
- env->vl * esz, vlmax * esz);
+ clear_elem(vd, vta, env->vl + k * max_elems,
+ env->vl * esz, max_elems * esz);
}
}
}
@@ -570,7 +588,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
uint32_t i, k, vl = 0;
uint32_t nf = vext_nf(desc);
uint32_t vm = vext_vm(desc);
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t max_elems = vext_max_elems(desc, esz, true);
uint32_t vta = vext_vta(desc);
target_ulong addr, offset, remain;
@@ -622,7 +640,7 @@ ProbeSuccess:
}
while (k < nf) {
target_ulong addr = base + (i * nf + k) * esz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ ldst_elem(env, addr, i + k * max_elems, vd, ra);
k++;
}
}
@@ -631,8 +649,8 @@ ProbeSuccess:
return;
}
for (k = 0; k < nf; k++) {
- clear_elem(vd, vta, env->vl + k * vlmax,
- env->vl * esz, vlmax * esz);
+ clear_elem(vd, vta, env->vl + k * max_elems,
+ env->vl * esz, max_elems * esz);
}
}
@@ -659,7 +677,7 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t max_elems = vext_max_elems(desc, esz, true);
/* probe every access */
probe_pages(env, base, env->vlenb * nf * esz, ra, access_type);
@@ -669,7 +687,7 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
k = 0;
while (k < nf) {
target_ulong addr = base + (i * nf + k) * esz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ ldst_elem(env, addr, i + k * max_elems, vd, ra);
k++;
}
}
@@ -812,7 +830,7 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
target_long addr;
uint32_t wd = vext_wd(desc);
uint32_t vm = vext_vm(desc);
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t vlmax = vext_max_elems(desc, esz, false);
uint32_t vta = vext_vta(desc);
for (i = 0; i < env->vl; i++) {
@@ -983,7 +1001,7 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
uint32_t esz, uint32_t dsz,
opivv2_fn *fn, clear_fn *clearfn)
{
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t vlmax = vext_max_elems(desc, esz, false);
uint32_t vm = vext_vm(desc);
uint32_t vta = vext_vta(desc);
uint32_t vl = env->vl;
@@ -995,7 +1013,7 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
}
fn(vd, vs1, vs2, i);
}
- clearfn(vd, vta, vl, vl * dsz, vlmax * dsz);
+ clearfn(vd, vta, vl, vl * dsz, vlmax * dsz);
}
/* generate the helpers for OPIVV */
@@ -1048,7 +1066,7 @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
uint32_t esz, uint32_t dsz,
opivx2_fn fn, clear_fn *clearfn)
{
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t vlmax = vext_max_elems(desc, esz, false);
uint32_t vm = vext_vm(desc);
uint32_t vta = vext_vta(desc);
uint32_t vl = env->vl;
@@ -1060,7 +1078,7 @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
}
fn(vd, s1, vs2, i);
}
- clearfn(vd, vta, vl, vl * dsz, vlmax * dsz);
+ clearfn(vd, vta, vl, vl * dsz, vlmax * dsz);
}
/* generate the helpers for OPIVX */
@@ -1247,7 +1265,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
{ \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vlmax = vext_max_elems(desc, esz, false); \
uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
@@ -1277,7 +1295,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
{ \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vlmax = vext_max_elems(desc, esz, false); \
uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
@@ -1339,7 +1357,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vl = env->vl; \
- uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false);\
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -1427,7 +1445,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(TS1); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vlmax = vext_max_elems(desc, esz, false); \
uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
@@ -1465,7 +1483,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(TD); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vlmax = vext_max_elems(desc, esz, false); \
uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
@@ -2108,7 +2126,7 @@ void HELPER(NAME)(void *vd, void *vs1, CPURISCVState *env, \
{ \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vlmax = vext_max_elems(desc, esz, false); \
uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
@@ -2130,7 +2148,7 @@ void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVState *env, \
{ \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vlmax = vext_max_elems(desc, esz, false); \
uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
@@ -2151,7 +2169,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
{ \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vlmax = vext_max_elems(desc, esz, false); \
uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
@@ -2173,7 +2191,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
{ \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vlmax = vext_max_elems(desc, esz, false); \
uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
@@ -2234,7 +2252,7 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
uint32_t desc, uint32_t esz, uint32_t dsz,
opivv2_rm_fn *fn, clear_fn *clearfn)
{
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t vlmax = vext_max_elems(desc, esz, false);
uint32_t vm = vext_vm(desc);
uint32_t vta = vext_vta(desc);
uint32_t vl = env->vl;
@@ -2354,7 +2372,7 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
uint32_t desc, uint32_t esz, uint32_t dsz,
opivx2_rm_fn *fn, clear_fn *clearfn)
{
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t vlmax = vext_max_elems(desc, esz, false);
uint32_t vm = vext_vm(desc);
uint32_t vta = vext_vta(desc);
uint32_t vl = env->vl;
@@ -3258,7 +3276,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
- uint32_t vlmax = vext_maxsz(desc) / ESZ; \
+ uint32_t vlmax = vext_max_elems(desc, ESZ, false); \
uint32_t vm = vext_vm(desc); \
uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
@@ -3293,7 +3311,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \
void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
- uint32_t vlmax = vext_maxsz(desc) / ESZ; \
+ uint32_t vlmax = vext_max_elems(desc, ESZ, false); \
uint32_t vm = vext_vm(desc); \
uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
@@ -3864,7 +3882,7 @@ static void do_##NAME(void *vd, void *vs2, int i, \
void HELPER(NAME)(void *vd, void *v0, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = vext_maxsz(desc) / ESZ; \
+ uint32_t vlmax = vext_max_elems(desc, ESZ, false); \
uint32_t vm = vext_vm(desc); \
uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
@@ -4041,7 +4059,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -4185,7 +4203,7 @@ static void do_##NAME(void *vd, void *vs2, int i) \
void HELPER(NAME)(void *vd, void *v0, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = vext_maxsz(desc) / ESZ; \
+ uint32_t vlmax = vext_max_elems(desc, ESZ, false); \
uint32_t vm = vext_vm(desc); \
uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
@@ -4272,7 +4290,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vlmax = vext_max_elems(desc, esz, false); \
uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
@@ -4772,7 +4790,7 @@ GEN_VEXT_VID_V(vid_v_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
uint32_t vm = vext_vm(desc); \
uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
@@ -4882,7 +4900,7 @@ GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
uint32_t vm = vext_vm(desc); \
uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
@@ -4912,7 +4930,7 @@ GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
uint32_t vm = vext_vm(desc); \
uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
@@ -4942,7 +4960,7 @@ GEN_VEXT_VRGATHER_VX(vrgather_vx_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t num = 0, i; \
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 20/65] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/vector_helper.c | 118 ++++++++++++++++++++---------------
1 file changed, 68 insertions(+), 50 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 39b9a462ab..2a006f956c 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -129,14 +129,32 @@ static inline uint32_t vext_vma(uint32_t desc)
}
/*
- * Get vector group length in bytes. Its range is [64, 2048].
- *
- * As simd_desc support at most 256, the max vlen is 512 bits.
- * So vlen in bytes is encoded as maxsz.
+ * Get the maximum number of elements can be operated.
*/
-static inline uint32_t vext_maxsz(uint32_t desc)
+static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz, bool is_ldst)
{
- return simd_maxsz(desc) << vext_lmul(desc);
+ /*
+ * As simd_desc support at most 256, the max vlen is 512 bits,
+ * so vlen in bytes (vlenb) is encoded as maxsz.
+ */
+ uint32_t vlenb = simd_maxsz(desc);
+
+ if (is_ldst) {
+ /*
+ * Vector load/store instructions have the EEW encoded
+ * directly in the instructions. The maximum vector size is
+ * calculated with EMUL rather than LMUL.
+ */
+ uint32_t eew = esz << 3;
+ uint32_t sew = vext_sew(desc);
+ float flmul = vext_vflmul(desc);
+ float emul = (float)eew / sew * flmul;
+ uint32_t emul_r = emul < 1 ? 1 : emul;
+ return vlenb * emul_r / esz;
+ } else {
+ /* Return VLMAX */
+ return vlenb * vext_vflmul(desc) / esz;
+ }
}
/*
@@ -296,7 +314,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t max_elems = vext_max_elems(desc, esz, true);
uint32_t vta = vext_vta(desc);
/* probe every access*/
@@ -314,15 +332,15 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
}
while (k < nf) {
target_ulong addr = base + stride * i + k * esz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ ldst_elem(env, addr, i + k * max_elems, vd, ra);
k++;
}
}
/* clear tail elements */
if (clear_elem) {
for (k = 0; k < nf; k++) {
- clear_elem(vd, vta, env->vl + k * vlmax,
- env->vl * esz, vlmax * esz);
+ clear_elem(vd, vta, env->vl + k * max_elems,
+ env->vl * esz, max_elems * esz);
}
}
}
@@ -371,7 +389,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t max_elems = vext_max_elems(desc, esz, true);
uint32_t vta = vext_vta(desc);
/* probe every access */
@@ -381,15 +399,15 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
k = 0;
while (k < nf) {
target_ulong addr = base + (i * nf + k) * esz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ ldst_elem(env, addr, i + k * max_elems, vd, ra);
k++;
}
}
/* clear tail elements */
if (clear_elem) {
for (k = 0; k < nf; k++) {
- clear_elem(vd, vta, env->vl + k * vlmax,
- env->vl * esz, vlmax * esz);
+ clear_elem(vd, vta, env->vl + k * max_elems,
+ env->vl * esz, max_elems * esz);
}
}
}
@@ -472,7 +490,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
uint32_t i, k;
uint32_t nf = vext_nf(desc);
uint32_t vm = vext_vm(desc);
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t max_elems = vext_max_elems(desc, esz, true);
uint32_t vta = vext_vta(desc);
/* probe every access*/
@@ -491,15 +509,15 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
}
while (k < nf) {
abi_ptr addr = get_index_addr(base, i, vs2) + k * esz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ ldst_elem(env, addr, i + k * max_elems, vd, ra);
k++;
}
}
/* clear tail elements */
if (clear_elem) {
for (k = 0; k < nf; k++) {
- clear_elem(vd, vta, env->vl + k * vlmax,
- env->vl * esz, vlmax * esz);
+ clear_elem(vd, vta, env->vl + k * max_elems,
+ env->vl * esz, max_elems * esz);
}
}
}
@@ -570,7 +588,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
uint32_t i, k, vl = 0;
uint32_t nf = vext_nf(desc);
uint32_t vm = vext_vm(desc);
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t max_elems = vext_max_elems(desc, esz, true);
uint32_t vta = vext_vta(desc);
target_ulong addr, offset, remain;
@@ -622,7 +640,7 @@ ProbeSuccess:
}
while (k < nf) {
target_ulong addr = base + (i * nf + k) * esz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ ldst_elem(env, addr, i + k * max_elems, vd, ra);
k++;
}
}
@@ -631,8 +649,8 @@ ProbeSuccess:
return;
}
for (k = 0; k < nf; k++) {
- clear_elem(vd, vta, env->vl + k * vlmax,
- env->vl * esz, vlmax * esz);
+ clear_elem(vd, vta, env->vl + k * max_elems,
+ env->vl * esz, max_elems * esz);
}
}
@@ -659,7 +677,7 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t max_elems = vext_max_elems(desc, esz, true);
/* probe every access */
probe_pages(env, base, env->vlenb * nf * esz, ra, access_type);
@@ -669,7 +687,7 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
k = 0;
while (k < nf) {
target_ulong addr = base + (i * nf + k) * esz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ ldst_elem(env, addr, i + k * max_elems, vd, ra);
k++;
}
}
@@ -812,7 +830,7 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
target_long addr;
uint32_t wd = vext_wd(desc);
uint32_t vm = vext_vm(desc);
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t vlmax = vext_max_elems(desc, esz, false);
uint32_t vta = vext_vta(desc);
for (i = 0; i < env->vl; i++) {
@@ -983,7 +1001,7 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
uint32_t esz, uint32_t dsz,
opivv2_fn *fn, clear_fn *clearfn)
{
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t vlmax = vext_max_elems(desc, esz, false);
uint32_t vm = vext_vm(desc);
uint32_t vta = vext_vta(desc);
uint32_t vl = env->vl;
@@ -995,7 +1013,7 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
}
fn(vd, vs1, vs2, i);
}
- clearfn(vd, vta, vl, vl * dsz, vlmax * dsz);
+ clearfn(vd, vta, vl, vl * dsz, vlmax * dsz);
}
/* generate the helpers for OPIVV */
@@ -1048,7 +1066,7 @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
uint32_t esz, uint32_t dsz,
opivx2_fn fn, clear_fn *clearfn)
{
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t vlmax = vext_max_elems(desc, esz, false);
uint32_t vm = vext_vm(desc);
uint32_t vta = vext_vta(desc);
uint32_t vl = env->vl;
@@ -1060,7 +1078,7 @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
}
fn(vd, s1, vs2, i);
}
- clearfn(vd, vta, vl, vl * dsz, vlmax * dsz);
+ clearfn(vd, vta, vl, vl * dsz, vlmax * dsz);
}
/* generate the helpers for OPIVX */
@@ -1247,7 +1265,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
{ \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vlmax = vext_max_elems(desc, esz, false); \
uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
@@ -1277,7 +1295,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
{ \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vlmax = vext_max_elems(desc, esz, false); \
uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
@@ -1339,7 +1357,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vl = env->vl; \
- uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false);\
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -1427,7 +1445,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(TS1); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vlmax = vext_max_elems(desc, esz, false); \
uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
@@ -1465,7 +1483,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(TD); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vlmax = vext_max_elems(desc, esz, false); \
uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
@@ -2108,7 +2126,7 @@ void HELPER(NAME)(void *vd, void *vs1, CPURISCVState *env, \
{ \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vlmax = vext_max_elems(desc, esz, false); \
uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
@@ -2130,7 +2148,7 @@ void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVState *env, \
{ \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vlmax = vext_max_elems(desc, esz, false); \
uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
@@ -2151,7 +2169,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
{ \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vlmax = vext_max_elems(desc, esz, false); \
uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
@@ -2173,7 +2191,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
{ \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vlmax = vext_max_elems(desc, esz, false); \
uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
@@ -2234,7 +2252,7 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
uint32_t desc, uint32_t esz, uint32_t dsz,
opivv2_rm_fn *fn, clear_fn *clearfn)
{
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t vlmax = vext_max_elems(desc, esz, false);
uint32_t vm = vext_vm(desc);
uint32_t vta = vext_vta(desc);
uint32_t vl = env->vl;
@@ -2354,7 +2372,7 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
uint32_t desc, uint32_t esz, uint32_t dsz,
opivx2_rm_fn *fn, clear_fn *clearfn)
{
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t vlmax = vext_max_elems(desc, esz, false);
uint32_t vm = vext_vm(desc);
uint32_t vta = vext_vta(desc);
uint32_t vl = env->vl;
@@ -3258,7 +3276,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
- uint32_t vlmax = vext_maxsz(desc) / ESZ; \
+ uint32_t vlmax = vext_max_elems(desc, ESZ, false); \
uint32_t vm = vext_vm(desc); \
uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
@@ -3293,7 +3311,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \
void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
- uint32_t vlmax = vext_maxsz(desc) / ESZ; \
+ uint32_t vlmax = vext_max_elems(desc, ESZ, false); \
uint32_t vm = vext_vm(desc); \
uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
@@ -3864,7 +3882,7 @@ static void do_##NAME(void *vd, void *vs2, int i, \
void HELPER(NAME)(void *vd, void *v0, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = vext_maxsz(desc) / ESZ; \
+ uint32_t vlmax = vext_max_elems(desc, ESZ, false); \
uint32_t vm = vext_vm(desc); \
uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
@@ -4041,7 +4059,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -4185,7 +4203,7 @@ static void do_##NAME(void *vd, void *vs2, int i) \
void HELPER(NAME)(void *vd, void *v0, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = vext_maxsz(desc) / ESZ; \
+ uint32_t vlmax = vext_max_elems(desc, ESZ, false); \
uint32_t vm = vext_vm(desc); \
uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
@@ -4272,7 +4290,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t vlmax = vext_max_elems(desc, esz, false); \
uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
@@ -4772,7 +4790,7 @@ GEN_VEXT_VID_V(vid_v_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
uint32_t vm = vext_vm(desc); \
uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
@@ -4882,7 +4900,7 @@ GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
uint32_t vm = vext_vm(desc); \
uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
@@ -4912,7 +4930,7 @@ GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
uint32_t vm = vext_vm(desc); \
uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
@@ -4942,7 +4960,7 @@ GEN_VEXT_VRGATHER_VX(vrgather_vx_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t num = 0, i; \
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 21/65] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into
calculation for RVV 0.9.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 32 +++++++++++++++----------
target/riscv/insn_trans/trans_rvv.inc.c | 11 ++++++++-
2 files changed, 29 insertions(+), 14 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 61393c9e2e..8b4a370572 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -25,6 +25,8 @@
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
+#include "internals.h"
+
#define TCG_GUEST_DEFAULT_MO 0
#define TYPE_RISCV_CPU "riscv-cpu"
@@ -380,20 +382,14 @@ FIELD(TB_FLAGS, VMA, 12, 1)
/* Skip MSTATUS_VS (0x6000) fields */
FIELD(TB_FLAGS, VILL, 15, 1)
-/*
- * A simplification for VLMAX
- * = (1 << LMUL) * VLEN / (8 * (1 << SEW))
- * = (VLEN << LMUL) / (8 << SEW)
- * = (VLEN << LMUL) >> (SEW + 3)
- * = VLEN >> (SEW + 3 - LMUL)
- */
static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
{
uint8_t sew, lmul;
-
sew = FIELD_EX64(vtype, VTYPE, VSEW);
- lmul = FIELD_EX64(vtype, VTYPE, VLMUL);
- return cpu->cfg.vlen >> (sew + 3 - lmul);
+ lmul = (FIELD_EX64(vtype, VTYPE, VFLMUL) << 2)
+ | FIELD_EX64(vtype, VTYPE, VLMUL);
+ float flmul = flmul_table[lmul];
+ return cpu->cfg.vlen * flmul / (1 << (sew + 3));
}
static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
@@ -405,13 +401,23 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
*cs_base = 0;
if (riscv_has_ext(env, RVV)) {
+ /*
+ * If env->vl equals to VLMAX, we can use generic vector operation
+ * expanders (GVEC) to accerlate the vector operations.
+ * However, as LMUL could be a fractional number. The maximum
+ * vector size can be operated might be less than 8 bytes,
+ * which is not supported by GVEC. So we set vl_eq_vlmax flag to true
+ * only when maxsz >= 8 bytes.
+ */
uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
- bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
+ uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW);
+ uint32_t maxsz = vlmax * (1 << sew);
+ bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl)
+ && (maxsz >= 8);
flags = FIELD_DP32(flags, TB_FLAGS, VILL,
FIELD_EX64(env->vtype, VTYPE, VILL));
- flags = FIELD_DP32(flags, TB_FLAGS, SEW,
- FIELD_EX64(env->vtype, VTYPE, VSEW));
+ flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew);
flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
(FIELD_EX64(env->vtype, VTYPE, VFLMUL) << 2)
| FIELD_EX64(env->vtype, VTYPE, VLMUL));
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 7db62053ab..5b061c303b 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1060,7 +1060,16 @@ GEN_VEXT_TRANS(vamomaxuei64_v, 64, 8, rwdvm, amo_op, amo_check)
/*
*** Vector Integer Arithmetic Instructions
*/
-#define MAXSZ(s) (s->vlen >> (3 - s->lmul))
+
+/*
+ * MAXSZ returns the maximum vector size can be operated in bytes,
+ * which is used in GVEC IR when vl_eq_vlmax flag is set to true
+ * to accerlate vector operation.
+ */
+static inline uint32_t MAXSZ(DisasContext *s)
+{
+ return (s->vlen >> 3) * s->flmul;
+}
static bool opivv_check(DisasContext *s, arg_rmrr *a)
{
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 21/65] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into
calculation for RVV 0.9.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 32 +++++++++++++++----------
target/riscv/insn_trans/trans_rvv.inc.c | 11 ++++++++-
2 files changed, 29 insertions(+), 14 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 61393c9e2e..8b4a370572 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -25,6 +25,8 @@
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
+#include "internals.h"
+
#define TCG_GUEST_DEFAULT_MO 0
#define TYPE_RISCV_CPU "riscv-cpu"
@@ -380,20 +382,14 @@ FIELD(TB_FLAGS, VMA, 12, 1)
/* Skip MSTATUS_VS (0x6000) fields */
FIELD(TB_FLAGS, VILL, 15, 1)
-/*
- * A simplification for VLMAX
- * = (1 << LMUL) * VLEN / (8 * (1 << SEW))
- * = (VLEN << LMUL) / (8 << SEW)
- * = (VLEN << LMUL) >> (SEW + 3)
- * = VLEN >> (SEW + 3 - LMUL)
- */
static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
{
uint8_t sew, lmul;
-
sew = FIELD_EX64(vtype, VTYPE, VSEW);
- lmul = FIELD_EX64(vtype, VTYPE, VLMUL);
- return cpu->cfg.vlen >> (sew + 3 - lmul);
+ lmul = (FIELD_EX64(vtype, VTYPE, VFLMUL) << 2)
+ | FIELD_EX64(vtype, VTYPE, VLMUL);
+ float flmul = flmul_table[lmul];
+ return cpu->cfg.vlen * flmul / (1 << (sew + 3));
}
static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
@@ -405,13 +401,23 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
*cs_base = 0;
if (riscv_has_ext(env, RVV)) {
+ /*
+ * If env->vl equals to VLMAX, we can use generic vector operation
+ * expanders (GVEC) to accerlate the vector operations.
+ * However, as LMUL could be a fractional number. The maximum
+ * vector size can be operated might be less than 8 bytes,
+ * which is not supported by GVEC. So we set vl_eq_vlmax flag to true
+ * only when maxsz >= 8 bytes.
+ */
uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
- bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
+ uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW);
+ uint32_t maxsz = vlmax * (1 << sew);
+ bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl)
+ && (maxsz >= 8);
flags = FIELD_DP32(flags, TB_FLAGS, VILL,
FIELD_EX64(env->vtype, VTYPE, VILL));
- flags = FIELD_DP32(flags, TB_FLAGS, SEW,
- FIELD_EX64(env->vtype, VTYPE, VSEW));
+ flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew);
flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
(FIELD_EX64(env->vtype, VTYPE, VFLMUL) << 2)
| FIELD_EX64(env->vtype, VTYPE, VLMUL));
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 7db62053ab..5b061c303b 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1060,7 +1060,16 @@ GEN_VEXT_TRANS(vamomaxuei64_v, 64, 8, rwdvm, amo_op, amo_check)
/*
*** Vector Integer Arithmetic Instructions
*/
-#define MAXSZ(s) (s->vlen >> (3 - s->lmul))
+
+/*
+ * MAXSZ returns the maximum vector size can be operated in bytes,
+ * which is used in GVEC IR when vl_eq_vlmax flag is set to true
+ * to accerlate vector operation.
+ */
+static inline uint32_t MAXSZ(DisasContext *s)
+{
+ return (s->vlen >> 3) * s->flmul;
+}
static bool opivv_check(DisasContext *s, arg_rmrr *a)
{
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 22/65] target/riscv: rvv-0.9: floating-point square-root instruction
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e3f0fba912..1d34fa647b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -509,7 +509,7 @@ vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm
vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm
vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
-vfsqrt_v 100011 . ..... 00000 001 ..... 1010111 @r2_vm
+vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm
vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 22/65] target/riscv: rvv-0.9: floating-point square-root instruction
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e3f0fba912..1d34fa647b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -509,7 +509,7 @@ vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm
vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm
vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
-vfsqrt_v 100011 . ..... 00000 001 ..... 1010111 @r2_vm
+vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm
vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 23/65] target/riscv: rvv-0.9: floating-point classify instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 1d34fa647b..7ad936e605 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -532,7 +532,7 @@ vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm
vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm
vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm
-vfclass_v 100011 . ..... 10000 001 ..... 1010111 @r2_vm
+vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm
vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
vfcvt_xu_f_v 100010 . ..... 00000 001 ..... 1010111 @r2_vm
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 23/65] target/riscv: rvv-0.9: floating-point classify instructions
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 1d34fa647b..7ad936e605 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -532,7 +532,7 @@ vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm
vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm
vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm
-vfclass_v 100011 . ..... 10000 001 ..... 1010111 @r2_vm
+vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm
vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
vfcvt_xu_f_v 100010 . ..... 00000 001 ..... 1010111 @r2_vm
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 24/65] target/riscv: rvv-0.9: mask population count instruction
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 2 +-
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.inc.c | 51 +++++++++++++------------
target/riscv/vector_helper.c | 6 +--
4 files changed, 31 insertions(+), 30 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 924c334f71..226f8e96a5 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1048,7 +1048,7 @@ DEF_HELPER_6(vmnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmornot_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_4(vmpopc_m, tl, ptr, ptr, env, i32)
+DEF_HELPER_4(vpopc_m, tl, ptr, ptr, env, i32)
DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 7ad936e605..c9c9f30742 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -573,7 +573,7 @@ vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r
vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r
vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
-vmpopc_m 010100 . ..... ----- 010 ..... 1010111 @r2_vm
+vpopc_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm
vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm
vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 5b061c303b..8191326e94 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2686,36 +2686,37 @@ GEN_MM_TRANS(vmnor_mm)
GEN_MM_TRANS(vmornot_mm)
GEN_MM_TRANS(vmxnor_mm)
-/* Vector mask population count vmpopc */
-static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
+/* Vector mask population count vpopc */
+static bool trans_vpopc_m(DisasContext *s, arg_rmr *a)
{
- if (vext_check_isa_ill(s)) {
- TCGv_ptr src2, mask;
- TCGv dst;
- TCGv_i32 desc;
- uint32_t data = 0;
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, VMA, s->vma);
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
- mask = tcg_temp_new_ptr();
- src2 = tcg_temp_new_ptr();
- dst = tcg_temp_new();
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+ TCGv_ptr src2, mask;
+ TCGv dst;
+ TCGv_i32 desc;
+ uint32_t data = 0;
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
- tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+ mask = tcg_temp_new_ptr();
+ src2 = tcg_temp_new_ptr();
+ dst = tcg_temp_new();
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- gen_helper_vmpopc_m(dst, mask, src2, cpu_env, desc);
- gen_set_gpr(a->rd, dst);
+ tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
+ tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
- tcg_temp_free_ptr(mask);
- tcg_temp_free_ptr(src2);
- tcg_temp_free(dst);
- tcg_temp_free_i32(desc);
- return true;
- }
- return false;
+ gen_helper_vpopc_m(dst, mask, src2, cpu_env, desc);
+ gen_set_gpr(a->rd, dst);
+
+ tcg_temp_free_ptr(mask);
+ tcg_temp_free_ptr(src2);
+ tcg_temp_free(dst);
+ tcg_temp_free_i32(desc);
+
+ return true;
}
/* vmfirst find-first-set mask bit */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 2a006f956c..bb7ca8aca7 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4629,9 +4629,9 @@ GEN_VEXT_MASK_VV(vmnor_mm, DO_NOR)
GEN_VEXT_MASK_VV(vmornot_mm, DO_ORNOT)
GEN_VEXT_MASK_VV(vmxnor_mm, DO_XNOR)
-/* Vector mask population count vmpopc */
-target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, CPURISCVState *env,
- uint32_t desc)
+/* Vector mask population count vpopc */
+target_ulong HELPER(vpopc_m)(void *v0, void *vs2, CPURISCVState *env,
+ uint32_t desc)
{
target_ulong cnt = 0;
uint32_t vm = vext_vm(desc);
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 24/65] target/riscv: rvv-0.9: mask population count instruction
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 2 +-
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.inc.c | 51 +++++++++++++------------
target/riscv/vector_helper.c | 6 +--
4 files changed, 31 insertions(+), 30 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 924c334f71..226f8e96a5 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1048,7 +1048,7 @@ DEF_HELPER_6(vmnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmornot_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_4(vmpopc_m, tl, ptr, ptr, env, i32)
+DEF_HELPER_4(vpopc_m, tl, ptr, ptr, env, i32)
DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 7ad936e605..c9c9f30742 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -573,7 +573,7 @@ vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r
vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r
vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
-vmpopc_m 010100 . ..... ----- 010 ..... 1010111 @r2_vm
+vpopc_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm
vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm
vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 5b061c303b..8191326e94 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2686,36 +2686,37 @@ GEN_MM_TRANS(vmnor_mm)
GEN_MM_TRANS(vmornot_mm)
GEN_MM_TRANS(vmxnor_mm)
-/* Vector mask population count vmpopc */
-static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
+/* Vector mask population count vpopc */
+static bool trans_vpopc_m(DisasContext *s, arg_rmr *a)
{
- if (vext_check_isa_ill(s)) {
- TCGv_ptr src2, mask;
- TCGv dst;
- TCGv_i32 desc;
- uint32_t data = 0;
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, VMA, s->vma);
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
- mask = tcg_temp_new_ptr();
- src2 = tcg_temp_new_ptr();
- dst = tcg_temp_new();
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+ TCGv_ptr src2, mask;
+ TCGv dst;
+ TCGv_i32 desc;
+ uint32_t data = 0;
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
- tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+ mask = tcg_temp_new_ptr();
+ src2 = tcg_temp_new_ptr();
+ dst = tcg_temp_new();
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- gen_helper_vmpopc_m(dst, mask, src2, cpu_env, desc);
- gen_set_gpr(a->rd, dst);
+ tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
+ tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
- tcg_temp_free_ptr(mask);
- tcg_temp_free_ptr(src2);
- tcg_temp_free(dst);
- tcg_temp_free_i32(desc);
- return true;
- }
- return false;
+ gen_helper_vpopc_m(dst, mask, src2, cpu_env, desc);
+ gen_set_gpr(a->rd, dst);
+
+ tcg_temp_free_ptr(mask);
+ tcg_temp_free_ptr(src2);
+ tcg_temp_free(dst);
+ tcg_temp_free_i32(desc);
+
+ return true;
}
/* vmfirst find-first-set mask bit */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 2a006f956c..bb7ca8aca7 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4629,9 +4629,9 @@ GEN_VEXT_MASK_VV(vmnor_mm, DO_NOR)
GEN_VEXT_MASK_VV(vmornot_mm, DO_ORNOT)
GEN_VEXT_MASK_VV(vmxnor_mm, DO_XNOR)
-/* Vector mask population count vmpopc */
-target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, CPURISCVState *env,
- uint32_t desc)
+/* Vector mask population count vpopc */
+target_ulong HELPER(vpopc_m)(void *v0, void *vs2, CPURISCVState *env,
+ uint32_t desc)
{
target_ulong cnt = 0;
uint32_t vm = vext_vm(desc);
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 25/65] target/riscv: rvv-0.9: find-first-set mask bit instruction
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 2 +-
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.inc.c | 49 +++++++++++++------------
target/riscv/vector_helper.c | 6 +--
4 files changed, 30 insertions(+), 29 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 226f8e96a5..f759d4cbc6 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1050,7 +1050,7 @@ DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_4(vpopc_m, tl, ptr, ptr, env, i32)
-DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32)
+DEF_HELPER_4(vfirst_m, tl, ptr, ptr, env, i32)
DEF_HELPER_5(vmsbf_m, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vmsif_m, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c9c9f30742..b5b59fe6dd 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -574,7 +574,7 @@ vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r
vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
vpopc_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
-vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm
+vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm
vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 8191326e94..2db7e7f58f 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2720,35 +2720,36 @@ static bool trans_vpopc_m(DisasContext *s, arg_rmr *a)
}
/* vmfirst find-first-set mask bit */
-static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
+static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
{
- if (vext_check_isa_ill(s)) {
- TCGv_ptr src2, mask;
- TCGv dst;
- TCGv_i32 desc;
- uint32_t data = 0;
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, VMA, s->vma);
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
- mask = tcg_temp_new_ptr();
- src2 = tcg_temp_new_ptr();
- dst = tcg_temp_new();
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+ TCGv_ptr src2, mask;
+ TCGv dst;
+ TCGv_i32 desc;
+ uint32_t data = 0;
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
- tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+ mask = tcg_temp_new_ptr();
+ src2 = tcg_temp_new_ptr();
+ dst = tcg_temp_new();
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- gen_helper_vmfirst_m(dst, mask, src2, cpu_env, desc);
- gen_set_gpr(a->rd, dst);
+ tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
+ tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
- tcg_temp_free_ptr(mask);
- tcg_temp_free_ptr(src2);
- tcg_temp_free(dst);
- tcg_temp_free_i32(desc);
- return true;
- }
- return false;
+ gen_helper_vfirst_m(dst, mask, src2, cpu_env, desc);
+ gen_set_gpr(a->rd, dst);
+
+ tcg_temp_free_ptr(mask);
+ tcg_temp_free_ptr(src2);
+ tcg_temp_free(dst);
+ tcg_temp_free_i32(desc);
+
+ return true;
}
/* vmsbf.m set-before-first mask bit */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index bb7ca8aca7..f13f6c6dda 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4648,9 +4648,9 @@ target_ulong HELPER(vpopc_m)(void *v0, void *vs2, CPURISCVState *env,
return cnt;
}
-/* vmfirst find-first-set mask bit*/
-target_ulong HELPER(vmfirst_m)(void *v0, void *vs2, CPURISCVState *env,
- uint32_t desc)
+/* vfirst find-first-set mask bit*/
+target_ulong HELPER(vfirst_m)(void *v0, void *vs2, CPURISCVState *env,
+ uint32_t desc)
{
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 25/65] target/riscv: rvv-0.9: find-first-set mask bit instruction
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 2 +-
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.inc.c | 49 +++++++++++++------------
target/riscv/vector_helper.c | 6 +--
4 files changed, 30 insertions(+), 29 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 226f8e96a5..f759d4cbc6 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1050,7 +1050,7 @@ DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_4(vpopc_m, tl, ptr, ptr, env, i32)
-DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32)
+DEF_HELPER_4(vfirst_m, tl, ptr, ptr, env, i32)
DEF_HELPER_5(vmsbf_m, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vmsif_m, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c9c9f30742..b5b59fe6dd 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -574,7 +574,7 @@ vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r
vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
vpopc_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
-vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm
+vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm
vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 8191326e94..2db7e7f58f 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2720,35 +2720,36 @@ static bool trans_vpopc_m(DisasContext *s, arg_rmr *a)
}
/* vmfirst find-first-set mask bit */
-static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
+static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
{
- if (vext_check_isa_ill(s)) {
- TCGv_ptr src2, mask;
- TCGv dst;
- TCGv_i32 desc;
- uint32_t data = 0;
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, VMA, s->vma);
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
- mask = tcg_temp_new_ptr();
- src2 = tcg_temp_new_ptr();
- dst = tcg_temp_new();
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+ TCGv_ptr src2, mask;
+ TCGv dst;
+ TCGv_i32 desc;
+ uint32_t data = 0;
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
- tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+ mask = tcg_temp_new_ptr();
+ src2 = tcg_temp_new_ptr();
+ dst = tcg_temp_new();
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- gen_helper_vmfirst_m(dst, mask, src2, cpu_env, desc);
- gen_set_gpr(a->rd, dst);
+ tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
+ tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
- tcg_temp_free_ptr(mask);
- tcg_temp_free_ptr(src2);
- tcg_temp_free(dst);
- tcg_temp_free_i32(desc);
- return true;
- }
- return false;
+ gen_helper_vfirst_m(dst, mask, src2, cpu_env, desc);
+ gen_set_gpr(a->rd, dst);
+
+ tcg_temp_free_ptr(mask);
+ tcg_temp_free_ptr(src2);
+ tcg_temp_free(dst);
+ tcg_temp_free_i32(desc);
+
+ return true;
}
/* vmsbf.m set-before-first mask bit */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index bb7ca8aca7..f13f6c6dda 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4648,9 +4648,9 @@ target_ulong HELPER(vpopc_m)(void *v0, void *vs2, CPURISCVState *env,
return cnt;
}
-/* vmfirst find-first-set mask bit*/
-target_ulong HELPER(vmfirst_m)(void *v0, void *vs2, CPURISCVState *env,
- uint32_t desc)
+/* vfirst find-first-set mask bit*/
+target_ulong HELPER(vfirst_m)(void *v0, void *vs2, CPURISCVState *env,
+ uint32_t desc)
{
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 26/65] target/riscv: rvv-0.9: set-X-first mask bit instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 6 ++---
target/riscv/insn_trans/trans_rvv.inc.c | 32 +++++++++++++------------
target/riscv/vector_helper.c | 4 ----
3 files changed, 20 insertions(+), 22 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b5b59fe6dd..37b2582981 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -575,9 +575,9 @@ vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
vpopc_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
-vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm
-vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm
-vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm
+vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
+vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
+vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 2db7e7f58f..c1efb87e8d 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2758,22 +2758,24 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
#define GEN_M_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
- if (vext_check_isa_ill(s)) { \
- uint32_t data = 0; \
- gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
- TCGLabel *over = gen_new_label(); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ REQUIRE_RVV; \
+ VEXT_CHECK_ISA_ILL(s); \
+ require_vm(a->vm, a->rd); \
+ require(a->rd != a->rs2); \
\
- data = FIELD_DP32(data, VDATA, VM, a->vm); \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- data = FIELD_DP32(data, VDATA, VMA, s->vma); \
- tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
- vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
- cpu_env, 0, s->vlen / 8, data, fn); \
- gen_set_label(over); \
- return true; \
- } \
- return false; \
+ uint32_t data = 0; \
+ gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
+ TCGLabel *over = gen_new_label(); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
+ vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
+ cpu_env, 0, s->vlen / 8, data, fn); \
+ gen_set_label(over); \
+ return true; \
}
GEN_M_TRANS(vmsbf_m)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index f13f6c6dda..bc1363fb7d 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4675,7 +4675,6 @@ enum set_mask_type {
static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
uint32_t desc, enum set_mask_type type)
{
- uint32_t vlmax = env_archcpu(env)->cfg.vlen;
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
int i;
@@ -4705,9 +4704,6 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
}
}
}
- for (; i < vlmax; i++) {
- vext_set_elem_mask(vd, i, 0);
- }
}
void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 26/65] target/riscv: rvv-0.9: set-X-first mask bit instructions
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 6 ++---
target/riscv/insn_trans/trans_rvv.inc.c | 32 +++++++++++++------------
target/riscv/vector_helper.c | 4 ----
3 files changed, 20 insertions(+), 22 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b5b59fe6dd..37b2582981 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -575,9 +575,9 @@ vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
vpopc_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
-vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm
-vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm
-vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm
+vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
+vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
+vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 2db7e7f58f..c1efb87e8d 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2758,22 +2758,24 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
#define GEN_M_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
- if (vext_check_isa_ill(s)) { \
- uint32_t data = 0; \
- gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
- TCGLabel *over = gen_new_label(); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ REQUIRE_RVV; \
+ VEXT_CHECK_ISA_ILL(s); \
+ require_vm(a->vm, a->rd); \
+ require(a->rd != a->rs2); \
\
- data = FIELD_DP32(data, VDATA, VM, a->vm); \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- data = FIELD_DP32(data, VDATA, VMA, s->vma); \
- tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
- vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
- cpu_env, 0, s->vlen / 8, data, fn); \
- gen_set_label(over); \
- return true; \
- } \
- return false; \
+ uint32_t data = 0; \
+ gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
+ TCGLabel *over = gen_new_label(); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
+ vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
+ cpu_env, 0, s->vlen / 8, data, fn); \
+ gen_set_label(over); \
+ return true; \
}
GEN_M_TRANS(vmsbf_m)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index f13f6c6dda..bc1363fb7d 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4675,7 +4675,6 @@ enum set_mask_type {
static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
uint32_t desc, enum set_mask_type type)
{
- uint32_t vlmax = env_archcpu(env)->cfg.vlen;
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
int i;
@@ -4705,9 +4704,6 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
}
}
}
- for (; i < vlmax; i++) {
- vext_set_elem_mask(vd, i, 0);
- }
}
void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 27/65] target/riscv: rvv-0.9: iota instruction
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.inc.c | 44 ++++++++++++-------------
target/riscv/vector_helper.c | 2 +-
3 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 37b2582981..4560bc4379 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -578,7 +578,7 @@ vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
-viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
+viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index c1efb87e8d..0e552c3660 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2785,29 +2785,29 @@ GEN_M_TRANS(vmsof_m)
/* Vector Iota Instruction */
static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, 1) &&
- (a->vm != 0 || a->rd != 0)) {
- uint32_t data = 0;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ require_noover(a->rd, s->flmul, a->rs2, 1);
+ require_vm(a->vm, a->rd);
+ require_align(a->rd, s->flmul);
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, VTA, s->vta);
- data = FIELD_DP32(data, VDATA, VMA, s->vma);
- static gen_helper_gvec_3_ptr * const fns[4] = {
- gen_helper_viota_m_b, gen_helper_viota_m_h,
- gen_helper_viota_m_w, gen_helper_viota_m_d,
- };
- tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- vreg_ofs(s, a->rs2), cpu_env, 0,
- s->vlen / 8, data, fns[s->sew]);
- gen_set_label(over);
- return true;
- }
- return false;
+ uint32_t data = 0;
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
+ static gen_helper_gvec_3_ptr * const fns[4] = {
+ gen_helper_viota_m_b, gen_helper_viota_m_h,
+ gen_helper_viota_m_w, gen_helper_viota_m_d,
+ };
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
+ vreg_ofs(s, a->rs2), cpu_env, 0,
+ s->vlen / 8, data, fns[s->sew]);
+ gen_set_label(over);
+ return true;
}
/* Vector Element Index Instruction */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index bc1363fb7d..71a12c6c9b 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4748,7 +4748,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \
CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
-GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1, clearb)
+GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1, clearb)
GEN_VEXT_VIOTA_M(viota_m_h, uint16_t, H2, clearh)
GEN_VEXT_VIOTA_M(viota_m_w, uint32_t, H4, clearl)
GEN_VEXT_VIOTA_M(viota_m_d, uint64_t, H8, clearq)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 27/65] target/riscv: rvv-0.9: iota instruction
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.inc.c | 44 ++++++++++++-------------
target/riscv/vector_helper.c | 2 +-
3 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 37b2582981..4560bc4379 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -578,7 +578,7 @@ vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
-viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
+viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index c1efb87e8d..0e552c3660 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2785,29 +2785,29 @@ GEN_M_TRANS(vmsof_m)
/* Vector Iota Instruction */
static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, 1) &&
- (a->vm != 0 || a->rd != 0)) {
- uint32_t data = 0;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ require_noover(a->rd, s->flmul, a->rs2, 1);
+ require_vm(a->vm, a->rd);
+ require_align(a->rd, s->flmul);
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, VTA, s->vta);
- data = FIELD_DP32(data, VDATA, VMA, s->vma);
- static gen_helper_gvec_3_ptr * const fns[4] = {
- gen_helper_viota_m_b, gen_helper_viota_m_h,
- gen_helper_viota_m_w, gen_helper_viota_m_d,
- };
- tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- vreg_ofs(s, a->rs2), cpu_env, 0,
- s->vlen / 8, data, fns[s->sew]);
- gen_set_label(over);
- return true;
- }
- return false;
+ uint32_t data = 0;
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
+ static gen_helper_gvec_3_ptr * const fns[4] = {
+ gen_helper_viota_m_b, gen_helper_viota_m_h,
+ gen_helper_viota_m_w, gen_helper_viota_m_d,
+ };
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
+ vreg_ofs(s, a->rs2), cpu_env, 0,
+ s->vlen / 8, data, fns[s->sew]);
+ gen_set_label(over);
+ return true;
}
/* Vector Element Index Instruction */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index bc1363fb7d..71a12c6c9b 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4748,7 +4748,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \
CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
-GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1, clearb)
+GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1, clearb)
GEN_VEXT_VIOTA_M(viota_m_h, uint16_t, H2, clearh)
GEN_VEXT_VIOTA_M(viota_m_w, uint32_t, H4, clearl)
GEN_VEXT_VIOTA_M(viota_m_d, uint64_t, H8, clearq)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 28/65] target/riscv: rvv-0.9: element index instruction
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.inc.c | 40 ++++++++++++-------------
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 4560bc4379..01316c908d 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -579,7 +579,7 @@ vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
-vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
+vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 0e552c3660..c03f3326cc 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2813,27 +2813,27 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
/* Vector Element Index Instruction */
static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false)) {
- uint32_t data = 0;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ require_align(a->rd, s->flmul);
+ require_vm(a->vm, a->rd);
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, VTA, s->vta);
- data = FIELD_DP32(data, VDATA, VMA, s->vma);
- static gen_helper_gvec_2_ptr * const fns[4] = {
- gen_helper_vid_v_b, gen_helper_vid_v_h,
- gen_helper_vid_v_w, gen_helper_vid_v_d,
- };
- tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
- gen_set_label(over);
- return true;
- }
- return false;
+ uint32_t data = 0;
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
+ static gen_helper_gvec_2_ptr * const fns[4] = {
+ gen_helper_vid_v_b, gen_helper_vid_v_h,
+ gen_helper_vid_v_w, gen_helper_vid_v_d,
+ };
+ tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
+ cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
+ gen_set_label(over);
+ return true;
}
/*
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 28/65] target/riscv: rvv-0.9: element index instruction
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.inc.c | 40 ++++++++++++-------------
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 4560bc4379..01316c908d 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -579,7 +579,7 @@ vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
-vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
+vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 0e552c3660..c03f3326cc 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2813,27 +2813,27 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
/* Vector Element Index Instruction */
static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false)) {
- uint32_t data = 0;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ require_align(a->rd, s->flmul);
+ require_vm(a->vm, a->rd);
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, VTA, s->vta);
- data = FIELD_DP32(data, VDATA, VMA, s->vma);
- static gen_helper_gvec_2_ptr * const fns[4] = {
- gen_helper_vid_v_b, gen_helper_vid_v_h,
- gen_helper_vid_v_w, gen_helper_vid_v_d,
- };
- tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
- gen_set_label(over);
- return true;
- }
- return false;
+ uint32_t data = 0;
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
+ static gen_helper_gvec_2_ptr * const fns[4] = {
+ gen_helper_vid_v_b, gen_helper_vid_v_h,
+ gen_helper_vid_v_w, gen_helper_vid_v_d,
+ };
+ tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
+ cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
+ gen_set_label(over);
+ return true;
}
/*
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 29/65] target/riscv: rvv-0.9: integer scalar move instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvv.inc.c | 59 +++++++++++++++++--------
2 files changed, 43 insertions(+), 19 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 01316c908d..ef53df7c73 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -580,8 +580,9 @@ vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
+vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd
+vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
-vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd
vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2
vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index c03f3326cc..801b9319a5 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2986,30 +2986,53 @@ static void vec_element_storei(DisasContext *s, int vreg,
store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew);
}
+/* vmv.x.s rd, vs2 # x[rd] = vs2[0] */
+static bool trans_vmv_x_s(DisasContext *s, arg_vmv_x_s *a)
+{
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+
+ TCGv_i64 t1;
+ TCGv dest;
+
+ t1 = tcg_temp_new_i64();
+ dest = tcg_temp_new();
+ /*
+ * load vreg and sign-extend to 64 bits,
+ * then truncate to XLEN bits before storing to gpr.
+ */
+ vec_element_loadi(s, t1, a->rs2, 0, true);
+ tcg_gen_trunc_i64_tl(dest, t1);
+ gen_set_gpr(a->rd, dest);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free(dest);
+ mark_vs_dirty(s);
+
+ return true;
+}
+
/* vmv.s.x vd, rs1 # vd[0] = rs1 */
static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
{
- if (vext_check_isa_ill(s)) {
- /* This instruction ignores LMUL and vector register groups */
- int maxsz = s->vlen >> 3;
- TCGv_i64 t1;
- TCGLabel *over = gen_new_label();
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), maxsz, maxsz, 0);
- if (a->rs1 == 0) {
- goto done;
- }
+ /* This instruction ignores LMUL and vector register groups */
+ TCGv_i64 t1;
+ TCGLabel *over = gen_new_label();
- t1 = tcg_temp_new_i64();
- tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
- vec_element_storei(s, a->rd, 0, t1);
- tcg_temp_free_i64(t1);
- done:
- gen_set_label(over);
- return true;
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ if (a->rs1 == 0) {
+ goto done;
}
- return false;
+
+ t1 = tcg_temp_new_i64();
+ tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
+ vec_element_storei(s, a->rd, 0, t1);
+ tcg_temp_free_i64(t1);
+done:
+ gen_set_label(over);
+ return true;
}
/* Floating-Point Scalar Move Instructions */
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 29/65] target/riscv: rvv-0.9: integer scalar move instructions
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvv.inc.c | 59 +++++++++++++++++--------
2 files changed, 43 insertions(+), 19 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 01316c908d..ef53df7c73 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -580,8 +580,9 @@ vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
+vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd
+vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
-vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd
vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2
vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index c03f3326cc..801b9319a5 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2986,30 +2986,53 @@ static void vec_element_storei(DisasContext *s, int vreg,
store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew);
}
+/* vmv.x.s rd, vs2 # x[rd] = vs2[0] */
+static bool trans_vmv_x_s(DisasContext *s, arg_vmv_x_s *a)
+{
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+
+ TCGv_i64 t1;
+ TCGv dest;
+
+ t1 = tcg_temp_new_i64();
+ dest = tcg_temp_new();
+ /*
+ * load vreg and sign-extend to 64 bits,
+ * then truncate to XLEN bits before storing to gpr.
+ */
+ vec_element_loadi(s, t1, a->rs2, 0, true);
+ tcg_gen_trunc_i64_tl(dest, t1);
+ gen_set_gpr(a->rd, dest);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free(dest);
+ mark_vs_dirty(s);
+
+ return true;
+}
+
/* vmv.s.x vd, rs1 # vd[0] = rs1 */
static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
{
- if (vext_check_isa_ill(s)) {
- /* This instruction ignores LMUL and vector register groups */
- int maxsz = s->vlen >> 3;
- TCGv_i64 t1;
- TCGLabel *over = gen_new_label();
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), maxsz, maxsz, 0);
- if (a->rs1 == 0) {
- goto done;
- }
+ /* This instruction ignores LMUL and vector register groups */
+ TCGv_i64 t1;
+ TCGLabel *over = gen_new_label();
- t1 = tcg_temp_new_i64();
- tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
- vec_element_storei(s, a->rd, 0, t1);
- tcg_temp_free_i64(t1);
- done:
- gen_set_label(over);
- return true;
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ if (a->rs1 == 0) {
+ goto done;
}
- return false;
+
+ t1 = tcg_temp_new_i64();
+ tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
+ vec_element_storei(s, a->rd, 0, t1);
+ tcg_temp_free_i64(t1);
+done:
+ gen_set_label(over);
+ return true;
}
/* Floating-Point Scalar Move Instructions */
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 30/65] target/riscv: rvv-0.9: floating-point scalar move instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 4 +-
target/riscv/insn_trans/trans_rvv.inc.c | 66 ++++++++++++-------------
2 files changed, 35 insertions(+), 35 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index ef53df7c73..4be1b88e2d 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -583,8 +583,8 @@ vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd
vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
-vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd
-vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2
+vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd
+vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2
vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm
vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm
vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 801b9319a5..fcbcfda050 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -3038,50 +3038,50 @@ done:
/* Floating-Point Scalar Move Instructions */
static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
{
- if (!s->vill && has_ext(s, RVF) &&
- (s->mstatus_fs != 0) && (s->sew != 0)) {
- unsigned int len = 8 << s->sew;
-
- vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0);
- if (len < 64) {
- tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
- MAKE_64BIT_MASK(len, 64 - len));
- }
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ require(has_ext(s, RVF));
+ require(s->mstatus_fs != 0);
+ require(s->sew != 0);
- mark_fs_dirty(s);
- return true;
+ unsigned int len = 8 << s->sew;
+
+ vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0, false);
+ if (len < 64) {
+ tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
+ MAKE_64BIT_MASK(len, 64 - len));
}
- return false;
+
+ mark_fs_dirty(s);
+ return true;
}
/* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */
static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
{
- if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) {
- TCGv_i64 t1;
- /* The instructions ignore LMUL and vector register group. */
- uint32_t vlmax = s->vlen >> 3;
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ require(has_ext(s, RVF));
+ require(s->sew != 0);
- /* if vl == 0, skip vector register write back */
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ /* The instructions ignore LMUL and vector register group. */
+ TCGv_i64 t1;
+ TCGLabel *over = gen_new_label();
- /* zeroed all elements */
- tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0);
+ /* if vl == 0, skip vector register write back */
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- /* NaN-box f[rs1] as necessary for SEW */
- t1 = tcg_temp_new_i64();
- if (s->sew == MO_64 && !has_ext(s, RVD)) {
- tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32));
- } else {
- tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]);
- }
- vec_element_storei(s, a->rd, 0, t1);
- tcg_temp_free_i64(t1);
- gen_set_label(over);
- return true;
+ /* NaN-box f[rs1] as necessary for SEW */
+ t1 = tcg_temp_new_i64();
+ if (s->sew == MO_64 && !has_ext(s, RVD)) {
+ tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32));
+ } else {
+ tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]);
}
- return false;
+ vec_element_storei(s, a->rd, 0, t1);
+ tcg_temp_free_i64(t1);
+ gen_set_label(over);
+ return true;
}
/* Vector Slide Instructions */
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 30/65] target/riscv: rvv-0.9: floating-point scalar move instructions
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 4 +-
target/riscv/insn_trans/trans_rvv.inc.c | 66 ++++++++++++-------------
2 files changed, 35 insertions(+), 35 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index ef53df7c73..4be1b88e2d 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -583,8 +583,8 @@ vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd
vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
-vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd
-vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2
+vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd
+vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2
vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm
vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm
vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 801b9319a5..fcbcfda050 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -3038,50 +3038,50 @@ done:
/* Floating-Point Scalar Move Instructions */
static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
{
- if (!s->vill && has_ext(s, RVF) &&
- (s->mstatus_fs != 0) && (s->sew != 0)) {
- unsigned int len = 8 << s->sew;
-
- vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0);
- if (len < 64) {
- tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
- MAKE_64BIT_MASK(len, 64 - len));
- }
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ require(has_ext(s, RVF));
+ require(s->mstatus_fs != 0);
+ require(s->sew != 0);
- mark_fs_dirty(s);
- return true;
+ unsigned int len = 8 << s->sew;
+
+ vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0, false);
+ if (len < 64) {
+ tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
+ MAKE_64BIT_MASK(len, 64 - len));
}
- return false;
+
+ mark_fs_dirty(s);
+ return true;
}
/* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */
static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
{
- if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) {
- TCGv_i64 t1;
- /* The instructions ignore LMUL and vector register group. */
- uint32_t vlmax = s->vlen >> 3;
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ require(has_ext(s, RVF));
+ require(s->sew != 0);
- /* if vl == 0, skip vector register write back */
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ /* The instructions ignore LMUL and vector register group. */
+ TCGv_i64 t1;
+ TCGLabel *over = gen_new_label();
- /* zeroed all elements */
- tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0);
+ /* if vl == 0, skip vector register write back */
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- /* NaN-box f[rs1] as necessary for SEW */
- t1 = tcg_temp_new_i64();
- if (s->sew == MO_64 && !has_ext(s, RVD)) {
- tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32));
- } else {
- tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]);
- }
- vec_element_storei(s, a->rd, 0, t1);
- tcg_temp_free_i64(t1);
- gen_set_label(over);
- return true;
+ /* NaN-box f[rs1] as necessary for SEW */
+ t1 = tcg_temp_new_i64();
+ if (s->sew == MO_64 && !has_ext(s, RVD)) {
+ tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32));
+ } else {
+ tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]);
}
- return false;
+ vec_element_storei(s, a->rd, 0, t1);
+ tcg_temp_free_i64(t1);
+ gen_set_label(over);
+ return true;
}
/* Vector Slide Instructions */
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 31/65] target/riscv: rvv-0.9: whole register move instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Add the following instructions:
* vmv1r.v
* vmv2r.v
* vmv4r.v
* vmv8r.v
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 4 ++++
target/riscv/insn_trans/trans_rvv.inc.c | 26 +++++++++++++++++++++++++
2 files changed, 30 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 4be1b88e2d..0e1d6b3ead 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -595,6 +595,10 @@ vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm
vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm
vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm
vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
+vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd
+vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd
+vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd
+vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index fcbcfda050..41777c7f93 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -3221,3 +3221,29 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
}
return false;
}
+
+/*
+ * Whole Vector Register Move Instructions ignore vtype and vl setting.
+ * Thus, we don't need to check vill bit. (Section 17.6)
+ */
+#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \
+static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
+{ \
+ REQUIRE_RVV; \
+ require((a->rd & ((LEN) - 1)) == 0); \
+ require((a->rs2 & ((LEN) - 1)) == 0); \
+ \
+ for (int i = 0; i < LEN; ++i) { \
+ /* EEW = 8 */ \
+ tcg_gen_gvec_mov(8, vreg_ofs(s, a->rd + i), \
+ vreg_ofs(s, a->rs2 + i), \
+ s->vlen / 8, s->vlen / 8); \
+ } \
+ mark_vs_dirty(s); \
+ return true; \
+}
+
+GEN_VMV_WHOLE_TRANS(vmv1r_v, 1)
+GEN_VMV_WHOLE_TRANS(vmv2r_v, 2)
+GEN_VMV_WHOLE_TRANS(vmv4r_v, 4)
+GEN_VMV_WHOLE_TRANS(vmv8r_v, 8)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 31/65] target/riscv: rvv-0.9: whole register move instructions
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Add the following instructions:
* vmv1r.v
* vmv2r.v
* vmv4r.v
* vmv8r.v
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 4 ++++
target/riscv/insn_trans/trans_rvv.inc.c | 26 +++++++++++++++++++++++++
2 files changed, 30 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 4be1b88e2d..0e1d6b3ead 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -595,6 +595,10 @@ vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm
vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm
vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm
vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
+vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd
+vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd
+vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd
+vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index fcbcfda050..41777c7f93 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -3221,3 +3221,29 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
}
return false;
}
+
+/*
+ * Whole Vector Register Move Instructions ignore vtype and vl setting.
+ * Thus, we don't need to check vill bit. (Section 17.6)
+ */
+#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \
+static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
+{ \
+ REQUIRE_RVV; \
+ require((a->rd & ((LEN) - 1)) == 0); \
+ require((a->rs2 & ((LEN) - 1)) == 0); \
+ \
+ for (int i = 0; i < LEN; ++i) { \
+ /* EEW = 8 */ \
+ tcg_gen_gvec_mov(8, vreg_ofs(s, a->rd + i), \
+ vreg_ofs(s, a->rs2 + i), \
+ s->vlen / 8, s->vlen / 8); \
+ } \
+ mark_vs_dirty(s); \
+ return true; \
+}
+
+GEN_VMV_WHOLE_TRANS(vmv1r_v, 1)
+GEN_VMV_WHOLE_TRANS(vmv2r_v, 2)
+GEN_VMV_WHOLE_TRANS(vmv4r_v, 4)
+GEN_VMV_WHOLE_TRANS(vmv8r_v, 8)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 32/65] target/riscv: rvv-0.9: integer extension instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Add the following instructions:
* vzext.vf2
* vzext.vf4
* vzext.vf8
* vsext.vf2
* vsext.vf4
* vsext.vf8
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 14 ++++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 94 +++++++++++++++++++++++++
target/riscv/vector_helper.c | 34 +++++++++
4 files changed, 150 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index f759d4cbc6..e53fad1fd5 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1096,3 +1096,17 @@ DEF_HELPER_6(vcompress_vm_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_5(vzext_vf2_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vzext_vf2_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vzext_vf2_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vzext_vf4_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vzext_vf4_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vzext_vf8_d, void, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_5(vsext_vf2_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsext_vf2_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsext_vf2_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsext_vf4_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsext_vf4_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsext_vf8_d, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0e1d6b3ead..5c31936a92 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -600,5 +600,13 @@ vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd
vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd
vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd
+# Vector Integer Extension
+vzext_vf2 010010 . ..... 00110 010 ..... 1010111 @r2_vm
+vzext_vf4 010010 . ..... 00100 010 ..... 1010111 @r2_vm
+vzext_vf8 010010 . ..... 00010 010 ..... 1010111 @r2_vm
+vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm
+vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm
+vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm
+
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 41777c7f93..dc9064e868 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -352,6 +352,23 @@ static bool vext_check_overlap_mask(DisasContext *s, uint32_t vd, bool vm,
return (vm != 0 || vd != 0) || (!force && (s->lmul == 0));
}
+/*
+ * Check function for vector integer extension instructions.
+ */
+#define VEXT_CHECK_EXT(s, rd, rs2, vm, div) do { \
+ uint32_t from = (1 << (s->sew + 3)) / div; \
+ require(from >= 8 && from <= 64); \
+ require(rd != rs2); \
+ require_align(rd, s->flmul); \
+ require_align(rs2, s->flmul / div); \
+ if ((s->flmul / div) < 1) { \
+ require_noover(rd, s->flmul, rs2, s->flmul / div); \
+ } else { \
+ require_noover_widen(rd, s->flmul, rs2, s->flmul / div); \
+ } \
+ require_vm(vm, rd); \
+} while (0)
+
/*
* In cpu_get_tb_cpu_state(), set VILL if RVV was not present.
* So RVV is also be checked in this function.
@@ -3247,3 +3264,80 @@ GEN_VMV_WHOLE_TRANS(vmv1r_v, 1)
GEN_VMV_WHOLE_TRANS(vmv2r_v, 2)
GEN_VMV_WHOLE_TRANS(vmv4r_v, 4)
GEN_VMV_WHOLE_TRANS(vmv8r_v, 8)
+
+static bool int_ext_check(DisasContext *s, arg_rmr *a, uint8_t div)
+{
+ REQUIRE_RVV;
+ VEXT_CHECK_EXT(s, a->rd, a->rs2, a->vm, div);
+ return true;
+}
+
+static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
+{
+ uint32_t data = 0;
+ gen_helper_gvec_3_ptr *fn;
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ static gen_helper_gvec_3_ptr * const fns[6][4] = {
+ {
+ NULL, gen_helper_vzext_vf2_h,
+ gen_helper_vzext_vf2_w, gen_helper_vzext_vf2_d
+ },
+ {
+ NULL, NULL,
+ gen_helper_vzext_vf4_w, gen_helper_vzext_vf4_d,
+ },
+ {
+ NULL, NULL,
+ NULL, gen_helper_vzext_vf8_d
+ },
+ {
+ NULL, gen_helper_vsext_vf2_h,
+ gen_helper_vsext_vf2_w, gen_helper_vsext_vf2_d
+ },
+ {
+ NULL, NULL,
+ gen_helper_vsext_vf4_w, gen_helper_vsext_vf4_d,
+ },
+ {
+ NULL, NULL,
+ NULL, gen_helper_vsext_vf8_d
+ }
+ };
+
+ fn = fns[seq][s->sew];
+ if (fn == NULL) {
+ return false;
+ }
+
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
+
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
+ vreg_ofs(s, a->rs2), cpu_env, 0,
+ s->vlen / 8, data, fn);
+
+ mark_vs_dirty(s);
+ gen_set_label(over);
+ return true;
+}
+
+/* Vector Integer Extension */
+#define GEN_INT_EXT_TRANS(NAME, DIV, SEQ) \
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+ if (int_ext_check(s, a, DIV)) { \
+ return int_ext_op(s, a, SEQ); \
+ } \
+ return false; \
+}
+
+GEN_INT_EXT_TRANS(vzext_vf2, 2, 0)
+GEN_INT_EXT_TRANS(vzext_vf4, 4, 1)
+GEN_INT_EXT_TRANS(vzext_vf8, 8, 2)
+GEN_INT_EXT_TRANS(vsext_vf2, 2, 3)
+GEN_INT_EXT_TRANS(vsext_vf4, 4, 4)
+GEN_INT_EXT_TRANS(vsext_vf8, 8, 5)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 71a12c6c9b..70a4505736 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4976,3 +4976,37 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_b, uint8_t, H1, clearb)
GEN_VEXT_VCOMPRESS_VM(vcompress_vm_h, uint16_t, H2, clearh)
GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4, clearl)
GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8, clearq)
+
+/* Vector Integer Extension */
+#define GEN_VEXT_INT_EXT(NAME, ETYPE, DTYPE, HD, HS1, CLEAR_FN) \
+void HELPER(NAME)(void *vd, void *v0, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
+ uint32_t vta = vext_vta(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ continue; \
+ } \
+ *((ETYPE *)vd + HD(i)) = *((DTYPE *)vs2 + HS1(i)); \
+ } \
+ CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+}
+
+GEN_VEXT_INT_EXT(vzext_vf2_h, uint16_t, uint8_t, H2, H1, clearh)
+GEN_VEXT_INT_EXT(vzext_vf2_w, uint32_t, uint16_t, H4, H2, clearl)
+GEN_VEXT_INT_EXT(vzext_vf2_d, uint64_t, uint32_t, H8, H4, clearq)
+GEN_VEXT_INT_EXT(vzext_vf4_w, uint32_t, uint8_t, H4, H1, clearl)
+GEN_VEXT_INT_EXT(vzext_vf4_d, uint64_t, uint16_t, H8, H2, clearq)
+GEN_VEXT_INT_EXT(vzext_vf8_d, uint64_t, uint8_t, H8, H1, clearq)
+
+GEN_VEXT_INT_EXT(vsext_vf2_h, int16_t, int8_t, H2, H1, clearh)
+GEN_VEXT_INT_EXT(vsext_vf2_w, int32_t, int16_t, H4, H2, clearl)
+GEN_VEXT_INT_EXT(vsext_vf2_d, int64_t, int32_t, H8, H4, clearq)
+GEN_VEXT_INT_EXT(vsext_vf4_w, int32_t, int8_t, H4, H1, clearl)
+GEN_VEXT_INT_EXT(vsext_vf4_d, int64_t, int16_t, H8, H2, clearq)
+GEN_VEXT_INT_EXT(vsext_vf8_d, int64_t, int8_t, H8, H1, clearq)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 32/65] target/riscv: rvv-0.9: integer extension instructions
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Add the following instructions:
* vzext.vf2
* vzext.vf4
* vzext.vf8
* vsext.vf2
* vsext.vf4
* vsext.vf8
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 14 ++++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 94 +++++++++++++++++++++++++
target/riscv/vector_helper.c | 34 +++++++++
4 files changed, 150 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index f759d4cbc6..e53fad1fd5 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1096,3 +1096,17 @@ DEF_HELPER_6(vcompress_vm_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_5(vzext_vf2_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vzext_vf2_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vzext_vf2_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vzext_vf4_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vzext_vf4_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vzext_vf8_d, void, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_5(vsext_vf2_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsext_vf2_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsext_vf2_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsext_vf4_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsext_vf4_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsext_vf8_d, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0e1d6b3ead..5c31936a92 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -600,5 +600,13 @@ vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd
vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd
vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd
+# Vector Integer Extension
+vzext_vf2 010010 . ..... 00110 010 ..... 1010111 @r2_vm
+vzext_vf4 010010 . ..... 00100 010 ..... 1010111 @r2_vm
+vzext_vf8 010010 . ..... 00010 010 ..... 1010111 @r2_vm
+vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm
+vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm
+vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm
+
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 41777c7f93..dc9064e868 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -352,6 +352,23 @@ static bool vext_check_overlap_mask(DisasContext *s, uint32_t vd, bool vm,
return (vm != 0 || vd != 0) || (!force && (s->lmul == 0));
}
+/*
+ * Check function for vector integer extension instructions.
+ */
+#define VEXT_CHECK_EXT(s, rd, rs2, vm, div) do { \
+ uint32_t from = (1 << (s->sew + 3)) / div; \
+ require(from >= 8 && from <= 64); \
+ require(rd != rs2); \
+ require_align(rd, s->flmul); \
+ require_align(rs2, s->flmul / div); \
+ if ((s->flmul / div) < 1) { \
+ require_noover(rd, s->flmul, rs2, s->flmul / div); \
+ } else { \
+ require_noover_widen(rd, s->flmul, rs2, s->flmul / div); \
+ } \
+ require_vm(vm, rd); \
+} while (0)
+
/*
* In cpu_get_tb_cpu_state(), set VILL if RVV was not present.
* So RVV is also be checked in this function.
@@ -3247,3 +3264,80 @@ GEN_VMV_WHOLE_TRANS(vmv1r_v, 1)
GEN_VMV_WHOLE_TRANS(vmv2r_v, 2)
GEN_VMV_WHOLE_TRANS(vmv4r_v, 4)
GEN_VMV_WHOLE_TRANS(vmv8r_v, 8)
+
+static bool int_ext_check(DisasContext *s, arg_rmr *a, uint8_t div)
+{
+ REQUIRE_RVV;
+ VEXT_CHECK_EXT(s, a->rd, a->rs2, a->vm, div);
+ return true;
+}
+
+static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
+{
+ uint32_t data = 0;
+ gen_helper_gvec_3_ptr *fn;
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ static gen_helper_gvec_3_ptr * const fns[6][4] = {
+ {
+ NULL, gen_helper_vzext_vf2_h,
+ gen_helper_vzext_vf2_w, gen_helper_vzext_vf2_d
+ },
+ {
+ NULL, NULL,
+ gen_helper_vzext_vf4_w, gen_helper_vzext_vf4_d,
+ },
+ {
+ NULL, NULL,
+ NULL, gen_helper_vzext_vf8_d
+ },
+ {
+ NULL, gen_helper_vsext_vf2_h,
+ gen_helper_vsext_vf2_w, gen_helper_vsext_vf2_d
+ },
+ {
+ NULL, NULL,
+ gen_helper_vsext_vf4_w, gen_helper_vsext_vf4_d,
+ },
+ {
+ NULL, NULL,
+ NULL, gen_helper_vsext_vf8_d
+ }
+ };
+
+ fn = fns[seq][s->sew];
+ if (fn == NULL) {
+ return false;
+ }
+
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
+
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
+ vreg_ofs(s, a->rs2), cpu_env, 0,
+ s->vlen / 8, data, fn);
+
+ mark_vs_dirty(s);
+ gen_set_label(over);
+ return true;
+}
+
+/* Vector Integer Extension */
+#define GEN_INT_EXT_TRANS(NAME, DIV, SEQ) \
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+ if (int_ext_check(s, a, DIV)) { \
+ return int_ext_op(s, a, SEQ); \
+ } \
+ return false; \
+}
+
+GEN_INT_EXT_TRANS(vzext_vf2, 2, 0)
+GEN_INT_EXT_TRANS(vzext_vf4, 4, 1)
+GEN_INT_EXT_TRANS(vzext_vf8, 8, 2)
+GEN_INT_EXT_TRANS(vsext_vf2, 2, 3)
+GEN_INT_EXT_TRANS(vsext_vf4, 4, 4)
+GEN_INT_EXT_TRANS(vsext_vf8, 8, 5)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 71a12c6c9b..70a4505736 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4976,3 +4976,37 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_b, uint8_t, H1, clearb)
GEN_VEXT_VCOMPRESS_VM(vcompress_vm_h, uint16_t, H2, clearh)
GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4, clearl)
GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8, clearq)
+
+/* Vector Integer Extension */
+#define GEN_VEXT_INT_EXT(NAME, ETYPE, DTYPE, HD, HS1, CLEAR_FN) \
+void HELPER(NAME)(void *vd, void *v0, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
+ uint32_t vta = vext_vta(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ continue; \
+ } \
+ *((ETYPE *)vd + HD(i)) = *((DTYPE *)vs2 + HS1(i)); \
+ } \
+ CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+}
+
+GEN_VEXT_INT_EXT(vzext_vf2_h, uint16_t, uint8_t, H2, H1, clearh)
+GEN_VEXT_INT_EXT(vzext_vf2_w, uint32_t, uint16_t, H4, H2, clearl)
+GEN_VEXT_INT_EXT(vzext_vf2_d, uint64_t, uint32_t, H8, H4, clearq)
+GEN_VEXT_INT_EXT(vzext_vf4_w, uint32_t, uint8_t, H4, H1, clearl)
+GEN_VEXT_INT_EXT(vzext_vf4_d, uint64_t, uint16_t, H8, H2, clearq)
+GEN_VEXT_INT_EXT(vzext_vf8_d, uint64_t, uint8_t, H8, H1, clearq)
+
+GEN_VEXT_INT_EXT(vsext_vf2_h, int16_t, int8_t, H2, H1, clearh)
+GEN_VEXT_INT_EXT(vsext_vf2_w, int32_t, int16_t, H4, H2, clearl)
+GEN_VEXT_INT_EXT(vsext_vf2_d, int64_t, int32_t, H8, H4, clearq)
+GEN_VEXT_INT_EXT(vsext_vf4_w, int32_t, int8_t, H4, H1, clearl)
+GEN_VEXT_INT_EXT(vsext_vf4_d, int64_t, int16_t, H8, H2, clearq)
+GEN_VEXT_INT_EXT(vsext_vf8_d, int64_t, int8_t, H8, H1, clearq)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 33/65] target/riscv: rvv-0.9: single-width averaging add and subtract instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 16 ++++++
target/riscv/insn32.decode | 13 +++--
target/riscv/insn_trans/trans_rvv.inc.c | 5 +-
target/riscv/vector_helper.c | 74 +++++++++++++++++++++++++
4 files changed, 102 insertions(+), 6 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index e53fad1fd5..b253fee76d 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -676,18 +676,34 @@ DEF_HELPER_6(vaadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vaadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vaadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vaadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vasub_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vasub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vasub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vasub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vasubu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vasubu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vasubu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vasubu_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vaadd_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vaadd_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vaadd_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vaadd_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vx_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vasub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vasub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vasub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vasub_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vasubu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vasubu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vasubu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vasubu_vx_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vsmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 5c31936a92..0521ca4ab4 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -439,11 +439,14 @@ vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm
vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm
vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm
vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm
-vaadd_vv 100100 . ..... ..... 000 ..... 1010111 @r_vm
-vaadd_vx 100100 . ..... ..... 100 ..... 1010111 @r_vm
-vaadd_vi 100100 . ..... ..... 011 ..... 1010111 @r_vm
-vasub_vv 100110 . ..... ..... 000 ..... 1010111 @r_vm
-vasub_vx 100110 . ..... ..... 100 ..... 1010111 @r_vm
+vaadd_vv 001001 . ..... ..... 010 ..... 1010111 @r_vm
+vaadd_vx 001001 . ..... ..... 110 ..... 1010111 @r_vm
+vaaddu_vv 001000 . ..... ..... 010 ..... 1010111 @r_vm
+vaaddu_vx 001000 . ..... ..... 110 ..... 1010111 @r_vm
+vasub_vv 001011 . ..... ..... 010 ..... 1010111 @r_vm
+vasub_vx 001011 . ..... ..... 110 ..... 1010111 @r_vm
+vasubu_vv 001010 . ..... ..... 010 ..... 1010111 @r_vm
+vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm
vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm
vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm
vwsmaccu_vv 111100 . ..... ..... 000 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index dc9064e868..d90820ff6a 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2062,10 +2062,13 @@ GEN_OPIVI_TRANS(vsadd_vi, 0, vsadd_vx, opivx_check)
/* Vector Single-Width Averaging Add and Subtract */
GEN_OPIVV_TRANS(vaadd_vv, opivv_check)
+GEN_OPIVV_TRANS(vaaddu_vv, opivv_check)
GEN_OPIVV_TRANS(vasub_vv, opivv_check)
+GEN_OPIVV_TRANS(vasubu_vv, opivv_check)
GEN_OPIVX_TRANS(vaadd_vx, opivx_check)
+GEN_OPIVX_TRANS(vaaddu_vx, opivx_check)
GEN_OPIVX_TRANS(vasub_vx, opivx_check)
-GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check)
+GEN_OPIVX_TRANS(vasubu_vx, opivx_check)
/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 70a4505736..17cc1a96e9 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2658,6 +2658,43 @@ GEN_VEXT_VX_RM(vaadd_vx_h, 2, 2, clearh)
GEN_VEXT_VX_RM(vaadd_vx_w, 4, 4, clearl)
GEN_VEXT_VX_RM(vaadd_vx_d, 8, 8, clearq)
+static inline uint32_t aaddu32(CPURISCVState *env, int vxrm,
+ uint32_t a, uint32_t b)
+{
+ uint64_t res = (uint64_t)a + b;
+ uint8_t round = get_round(vxrm, res, 1);
+
+ return (res >> 1) + round;
+}
+
+static inline uint64_t aaddu64(CPURISCVState *env, int vxrm,
+ uint64_t a, uint64_t b)
+{
+ uint64_t res = a + b;
+ uint8_t round = get_round(vxrm, res, 1);
+ uint64_t over = res < a ? ((uint64_t)1 << 63) : 0;
+
+ return ((res >> 1) | over) + round;
+}
+
+RVVCALL(OPIVV2_RM, vaaddu_vv_b, OP_UUU_B, H1, H1, H1, aaddu32)
+RVVCALL(OPIVV2_RM, vaaddu_vv_h, OP_UUU_H, H2, H2, H2, aaddu32)
+RVVCALL(OPIVV2_RM, vaaddu_vv_w, OP_UUU_W, H4, H4, H4, aaddu32)
+RVVCALL(OPIVV2_RM, vaaddu_vv_d, OP_UUU_D, H8, H8, H8, aaddu64)
+GEN_VEXT_VV_RM(vaaddu_vv_b, 1, 1, clearb)
+GEN_VEXT_VV_RM(vaaddu_vv_h, 2, 2, clearh)
+GEN_VEXT_VV_RM(vaaddu_vv_w, 4, 4, clearl)
+GEN_VEXT_VV_RM(vaaddu_vv_d, 8, 8, clearq)
+
+RVVCALL(OPIVX2_RM, vaaddu_vx_b, OP_UUU_B, H1, H1, aaddu32)
+RVVCALL(OPIVX2_RM, vaaddu_vx_h, OP_UUU_H, H2, H2, aaddu32)
+RVVCALL(OPIVX2_RM, vaaddu_vx_w, OP_UUU_W, H4, H4, aaddu32)
+RVVCALL(OPIVX2_RM, vaaddu_vx_d, OP_UUU_D, H8, H8, aaddu64)
+GEN_VEXT_VX_RM(vaaddu_vx_b, 1, 1, clearb)
+GEN_VEXT_VX_RM(vaaddu_vx_h, 2, 2, clearh)
+GEN_VEXT_VX_RM(vaaddu_vx_w, 4, 4, clearl)
+GEN_VEXT_VX_RM(vaaddu_vx_d, 8, 8, clearq)
+
static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
{
int64_t res = (int64_t)a - b;
@@ -2694,6 +2731,43 @@ GEN_VEXT_VX_RM(vasub_vx_h, 2, 2, clearh)
GEN_VEXT_VX_RM(vasub_vx_w, 4, 4, clearl)
GEN_VEXT_VX_RM(vasub_vx_d, 8, 8, clearq)
+static inline uint32_t asubu32(CPURISCVState *env, int vxrm,
+ uint32_t a, uint32_t b)
+{
+ int64_t res = (int64_t)a - b;
+ uint8_t round = get_round(vxrm, res, 1);
+
+ return (res >> 1) + round;
+}
+
+static inline uint64_t asubu64(CPURISCVState *env, int vxrm,
+ uint64_t a, uint64_t b)
+{
+ uint64_t res = (uint64_t)a - b;
+ uint8_t round = get_round(vxrm, res, 1);
+ uint64_t over = res > a ? ((uint64_t)1 << 63) : 0;
+
+ return ((res >> 1) | over) + round;
+}
+
+RVVCALL(OPIVV2_RM, vasubu_vv_b, OP_UUU_B, H1, H1, H1, asubu32)
+RVVCALL(OPIVV2_RM, vasubu_vv_h, OP_UUU_H, H2, H2, H2, asubu32)
+RVVCALL(OPIVV2_RM, vasubu_vv_w, OP_UUU_W, H4, H4, H4, asubu32)
+RVVCALL(OPIVV2_RM, vasubu_vv_d, OP_UUU_D, H8, H8, H8, asubu64)
+GEN_VEXT_VV_RM(vasubu_vv_b, 1, 1, clearb)
+GEN_VEXT_VV_RM(vasubu_vv_h, 2, 2, clearh)
+GEN_VEXT_VV_RM(vasubu_vv_w, 4, 4, clearl)
+GEN_VEXT_VV_RM(vasubu_vv_d, 8, 8, clearq)
+
+RVVCALL(OPIVX2_RM, vasubu_vx_b, OP_UUU_B, H1, H1, asubu32)
+RVVCALL(OPIVX2_RM, vasubu_vx_h, OP_UUU_H, H2, H2, asubu32)
+RVVCALL(OPIVX2_RM, vasubu_vx_w, OP_UUU_W, H4, H4, asubu32)
+RVVCALL(OPIVX2_RM, vasubu_vx_d, OP_UUU_D, H8, H8, asubu64)
+GEN_VEXT_VX_RM(vasubu_vx_b, 1, 1, clearb)
+GEN_VEXT_VX_RM(vasubu_vx_h, 2, 2, clearh)
+GEN_VEXT_VX_RM(vasubu_vx_w, 4, 4, clearl)
+GEN_VEXT_VX_RM(vasubu_vx_d, 8, 8, clearq)
+
/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
{
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 33/65] target/riscv: rvv-0.9: single-width averaging add and subtract instructions
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 16 ++++++
target/riscv/insn32.decode | 13 +++--
target/riscv/insn_trans/trans_rvv.inc.c | 5 +-
target/riscv/vector_helper.c | 74 +++++++++++++++++++++++++
4 files changed, 102 insertions(+), 6 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index e53fad1fd5..b253fee76d 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -676,18 +676,34 @@ DEF_HELPER_6(vaadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vaadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vaadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vaadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vasub_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vasub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vasub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vasub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vasubu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vasubu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vasubu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vasubu_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vaadd_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vaadd_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vaadd_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vaadd_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vx_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vasub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vasub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vasub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vasub_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vasubu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vasubu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vasubu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vasubu_vx_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vsmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 5c31936a92..0521ca4ab4 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -439,11 +439,14 @@ vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm
vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm
vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm
vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm
-vaadd_vv 100100 . ..... ..... 000 ..... 1010111 @r_vm
-vaadd_vx 100100 . ..... ..... 100 ..... 1010111 @r_vm
-vaadd_vi 100100 . ..... ..... 011 ..... 1010111 @r_vm
-vasub_vv 100110 . ..... ..... 000 ..... 1010111 @r_vm
-vasub_vx 100110 . ..... ..... 100 ..... 1010111 @r_vm
+vaadd_vv 001001 . ..... ..... 010 ..... 1010111 @r_vm
+vaadd_vx 001001 . ..... ..... 110 ..... 1010111 @r_vm
+vaaddu_vv 001000 . ..... ..... 010 ..... 1010111 @r_vm
+vaaddu_vx 001000 . ..... ..... 110 ..... 1010111 @r_vm
+vasub_vv 001011 . ..... ..... 010 ..... 1010111 @r_vm
+vasub_vx 001011 . ..... ..... 110 ..... 1010111 @r_vm
+vasubu_vv 001010 . ..... ..... 010 ..... 1010111 @r_vm
+vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm
vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm
vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm
vwsmaccu_vv 111100 . ..... ..... 000 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index dc9064e868..d90820ff6a 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2062,10 +2062,13 @@ GEN_OPIVI_TRANS(vsadd_vi, 0, vsadd_vx, opivx_check)
/* Vector Single-Width Averaging Add and Subtract */
GEN_OPIVV_TRANS(vaadd_vv, opivv_check)
+GEN_OPIVV_TRANS(vaaddu_vv, opivv_check)
GEN_OPIVV_TRANS(vasub_vv, opivv_check)
+GEN_OPIVV_TRANS(vasubu_vv, opivv_check)
GEN_OPIVX_TRANS(vaadd_vx, opivx_check)
+GEN_OPIVX_TRANS(vaaddu_vx, opivx_check)
GEN_OPIVX_TRANS(vasub_vx, opivx_check)
-GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check)
+GEN_OPIVX_TRANS(vasubu_vx, opivx_check)
/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 70a4505736..17cc1a96e9 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2658,6 +2658,43 @@ GEN_VEXT_VX_RM(vaadd_vx_h, 2, 2, clearh)
GEN_VEXT_VX_RM(vaadd_vx_w, 4, 4, clearl)
GEN_VEXT_VX_RM(vaadd_vx_d, 8, 8, clearq)
+static inline uint32_t aaddu32(CPURISCVState *env, int vxrm,
+ uint32_t a, uint32_t b)
+{
+ uint64_t res = (uint64_t)a + b;
+ uint8_t round = get_round(vxrm, res, 1);
+
+ return (res >> 1) + round;
+}
+
+static inline uint64_t aaddu64(CPURISCVState *env, int vxrm,
+ uint64_t a, uint64_t b)
+{
+ uint64_t res = a + b;
+ uint8_t round = get_round(vxrm, res, 1);
+ uint64_t over = res < a ? ((uint64_t)1 << 63) : 0;
+
+ return ((res >> 1) | over) + round;
+}
+
+RVVCALL(OPIVV2_RM, vaaddu_vv_b, OP_UUU_B, H1, H1, H1, aaddu32)
+RVVCALL(OPIVV2_RM, vaaddu_vv_h, OP_UUU_H, H2, H2, H2, aaddu32)
+RVVCALL(OPIVV2_RM, vaaddu_vv_w, OP_UUU_W, H4, H4, H4, aaddu32)
+RVVCALL(OPIVV2_RM, vaaddu_vv_d, OP_UUU_D, H8, H8, H8, aaddu64)
+GEN_VEXT_VV_RM(vaaddu_vv_b, 1, 1, clearb)
+GEN_VEXT_VV_RM(vaaddu_vv_h, 2, 2, clearh)
+GEN_VEXT_VV_RM(vaaddu_vv_w, 4, 4, clearl)
+GEN_VEXT_VV_RM(vaaddu_vv_d, 8, 8, clearq)
+
+RVVCALL(OPIVX2_RM, vaaddu_vx_b, OP_UUU_B, H1, H1, aaddu32)
+RVVCALL(OPIVX2_RM, vaaddu_vx_h, OP_UUU_H, H2, H2, aaddu32)
+RVVCALL(OPIVX2_RM, vaaddu_vx_w, OP_UUU_W, H4, H4, aaddu32)
+RVVCALL(OPIVX2_RM, vaaddu_vx_d, OP_UUU_D, H8, H8, aaddu64)
+GEN_VEXT_VX_RM(vaaddu_vx_b, 1, 1, clearb)
+GEN_VEXT_VX_RM(vaaddu_vx_h, 2, 2, clearh)
+GEN_VEXT_VX_RM(vaaddu_vx_w, 4, 4, clearl)
+GEN_VEXT_VX_RM(vaaddu_vx_d, 8, 8, clearq)
+
static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
{
int64_t res = (int64_t)a - b;
@@ -2694,6 +2731,43 @@ GEN_VEXT_VX_RM(vasub_vx_h, 2, 2, clearh)
GEN_VEXT_VX_RM(vasub_vx_w, 4, 4, clearl)
GEN_VEXT_VX_RM(vasub_vx_d, 8, 8, clearq)
+static inline uint32_t asubu32(CPURISCVState *env, int vxrm,
+ uint32_t a, uint32_t b)
+{
+ int64_t res = (int64_t)a - b;
+ uint8_t round = get_round(vxrm, res, 1);
+
+ return (res >> 1) + round;
+}
+
+static inline uint64_t asubu64(CPURISCVState *env, int vxrm,
+ uint64_t a, uint64_t b)
+{
+ uint64_t res = (uint64_t)a - b;
+ uint8_t round = get_round(vxrm, res, 1);
+ uint64_t over = res > a ? ((uint64_t)1 << 63) : 0;
+
+ return ((res >> 1) | over) + round;
+}
+
+RVVCALL(OPIVV2_RM, vasubu_vv_b, OP_UUU_B, H1, H1, H1, asubu32)
+RVVCALL(OPIVV2_RM, vasubu_vv_h, OP_UUU_H, H2, H2, H2, asubu32)
+RVVCALL(OPIVV2_RM, vasubu_vv_w, OP_UUU_W, H4, H4, H4, asubu32)
+RVVCALL(OPIVV2_RM, vasubu_vv_d, OP_UUU_D, H8, H8, H8, asubu64)
+GEN_VEXT_VV_RM(vasubu_vv_b, 1, 1, clearb)
+GEN_VEXT_VV_RM(vasubu_vv_h, 2, 2, clearh)
+GEN_VEXT_VV_RM(vasubu_vv_w, 4, 4, clearl)
+GEN_VEXT_VV_RM(vasubu_vv_d, 8, 8, clearq)
+
+RVVCALL(OPIVX2_RM, vasubu_vx_b, OP_UUU_B, H1, H1, asubu32)
+RVVCALL(OPIVX2_RM, vasubu_vx_h, OP_UUU_H, H2, H2, asubu32)
+RVVCALL(OPIVX2_RM, vasubu_vx_w, OP_UUU_W, H4, H4, asubu32)
+RVVCALL(OPIVX2_RM, vasubu_vx_d, OP_UUU_D, H8, H8, asubu64)
+GEN_VEXT_VX_RM(vasubu_vx_b, 1, 1, clearb)
+GEN_VEXT_VX_RM(vasubu_vx_h, 2, 2, clearh)
+GEN_VEXT_VX_RM(vasubu_vx_w, 4, 4, clearl)
+GEN_VEXT_VX_RM(vasubu_vx_d, 8, 8, clearq)
+
/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
{
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 34/65] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 20 +++++-----
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
target/riscv/vector_helper.c | 50 ++++++++++++++-----------
3 files changed, 40 insertions(+), 32 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0521ca4ab4..481f909d47 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -324,16 +324,16 @@ vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm
vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm
vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm
vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm
-vadc_vvm 010000 1 ..... ..... 000 ..... 1010111 @r_vm_1
-vadc_vxm 010000 1 ..... ..... 100 ..... 1010111 @r_vm_1
-vadc_vim 010000 1 ..... ..... 011 ..... 1010111 @r_vm_1
-vmadc_vvm 010001 1 ..... ..... 000 ..... 1010111 @r_vm_1
-vmadc_vxm 010001 1 ..... ..... 100 ..... 1010111 @r_vm_1
-vmadc_vim 010001 1 ..... ..... 011 ..... 1010111 @r_vm_1
-vsbc_vvm 010010 1 ..... ..... 000 ..... 1010111 @r_vm_1
-vsbc_vxm 010010 1 ..... ..... 100 ..... 1010111 @r_vm_1
-vmsbc_vvm 010011 1 ..... ..... 000 ..... 1010111 @r_vm_1
-vmsbc_vxm 010011 1 ..... ..... 100 ..... 1010111 @r_vm_1
+vadc_vvm 010000 0 ..... ..... 000 ..... 1010111 @r_vm_1
+vadc_vxm 010000 0 ..... ..... 100 ..... 1010111 @r_vm_1
+vadc_vim 010000 0 ..... ..... 011 ..... 1010111 @r_vm_1
+vmadc_vvm 010001 . ..... ..... 000 ..... 1010111 @r_vm
+vmadc_vxm 010001 . ..... ..... 100 ..... 1010111 @r_vm
+vmadc_vim 010001 . ..... ..... 011 ..... 1010111 @r_vm
+vsbc_vvm 010010 0 ..... ..... 000 ..... 1010111 @r_vm_1
+vsbc_vxm 010010 0 ..... ..... 100 ..... 1010111 @r_vm_1
+vmsbc_vvm 010011 . ..... ..... 000 ..... 1010111 @r_vm
+vmsbc_vxm 010011 . ..... ..... 100 ..... 1010111 @r_vm
vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm
vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm
vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index d90820ff6a..89a909b312 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1588,7 +1588,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
/*
* For vadc and vsbc, an illegal instruction exception is raised if the
- * destination vector register is v0 and LMUL > 1. (Section 12.3)
+ * destination vector register is v0 and LMUL > 1. (Section 12.4)
*/
static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a)
{
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 17cc1a96e9..af4d3c6441 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1322,24 +1322,28 @@ GEN_VEXT_VADC_VXM(vsbc_vxm_d, uint64_t, H8, DO_VSBC, clearq)
(__typeof(N))(N + M) < N)
#define DO_MSBC(N, M, C) (C ? N <= M : N < M)
-#define GEN_VEXT_VMADC_VVM(NAME, ETYPE, H, DO_OP) \
-void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
- CPURISCVState *env, uint32_t desc) \
-{ \
- uint32_t vl = env->vl; \
- uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
- uint32_t i; \
- \
- for (i = 0; i < vl; i++) { \
- ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
- ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, i); \
- \
- vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \
- } \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
+#define GEN_VEXT_VMADC_VVM(NAME, ETYPE, H, DO_OP) \
+void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vl = env->vl; \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false);\
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
+ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
+ uint8_t carry = !vm ? vext_elem_mask(v0, i) : 0; \
+ \
+ vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \
+ } \
+ if (vta == 1) { \
+ for (; i < vlmax; i++) { \
+ vext_set_elem_mask(vd, i, 0); \
+ } \
+ } \
}
GEN_VEXT_VMADC_VVM(vmadc_vvm_b, uint8_t, H1, DO_MADC)
@@ -1358,17 +1362,21 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
{ \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false);\
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, i); \
+ uint8_t carry = !vm ? vext_elem_mask(v0, i) : 0; \
\
vext_set_elem_mask(vd, i, \
DO_OP(s2, (ETYPE)(target_long)s1, carry)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
+ if (vta == 1) { \
+ for (; i < vlmax; i++) { \
+ vext_set_elem_mask(vd, i, 0); \
+ } \
} \
}
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 34/65] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 20 +++++-----
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
target/riscv/vector_helper.c | 50 ++++++++++++++-----------
3 files changed, 40 insertions(+), 32 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0521ca4ab4..481f909d47 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -324,16 +324,16 @@ vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm
vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm
vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm
vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm
-vadc_vvm 010000 1 ..... ..... 000 ..... 1010111 @r_vm_1
-vadc_vxm 010000 1 ..... ..... 100 ..... 1010111 @r_vm_1
-vadc_vim 010000 1 ..... ..... 011 ..... 1010111 @r_vm_1
-vmadc_vvm 010001 1 ..... ..... 000 ..... 1010111 @r_vm_1
-vmadc_vxm 010001 1 ..... ..... 100 ..... 1010111 @r_vm_1
-vmadc_vim 010001 1 ..... ..... 011 ..... 1010111 @r_vm_1
-vsbc_vvm 010010 1 ..... ..... 000 ..... 1010111 @r_vm_1
-vsbc_vxm 010010 1 ..... ..... 100 ..... 1010111 @r_vm_1
-vmsbc_vvm 010011 1 ..... ..... 000 ..... 1010111 @r_vm_1
-vmsbc_vxm 010011 1 ..... ..... 100 ..... 1010111 @r_vm_1
+vadc_vvm 010000 0 ..... ..... 000 ..... 1010111 @r_vm_1
+vadc_vxm 010000 0 ..... ..... 100 ..... 1010111 @r_vm_1
+vadc_vim 010000 0 ..... ..... 011 ..... 1010111 @r_vm_1
+vmadc_vvm 010001 . ..... ..... 000 ..... 1010111 @r_vm
+vmadc_vxm 010001 . ..... ..... 100 ..... 1010111 @r_vm
+vmadc_vim 010001 . ..... ..... 011 ..... 1010111 @r_vm
+vsbc_vvm 010010 0 ..... ..... 000 ..... 1010111 @r_vm_1
+vsbc_vxm 010010 0 ..... ..... 100 ..... 1010111 @r_vm_1
+vmsbc_vvm 010011 . ..... ..... 000 ..... 1010111 @r_vm
+vmsbc_vxm 010011 . ..... ..... 100 ..... 1010111 @r_vm
vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm
vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm
vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index d90820ff6a..89a909b312 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1588,7 +1588,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
/*
* For vadc and vsbc, an illegal instruction exception is raised if the
- * destination vector register is v0 and LMUL > 1. (Section 12.3)
+ * destination vector register is v0 and LMUL > 1. (Section 12.4)
*/
static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a)
{
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 17cc1a96e9..af4d3c6441 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1322,24 +1322,28 @@ GEN_VEXT_VADC_VXM(vsbc_vxm_d, uint64_t, H8, DO_VSBC, clearq)
(__typeof(N))(N + M) < N)
#define DO_MSBC(N, M, C) (C ? N <= M : N < M)
-#define GEN_VEXT_VMADC_VVM(NAME, ETYPE, H, DO_OP) \
-void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
- CPURISCVState *env, uint32_t desc) \
-{ \
- uint32_t vl = env->vl; \
- uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
- uint32_t i; \
- \
- for (i = 0; i < vl; i++) { \
- ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
- ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, i); \
- \
- vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \
- } \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
+#define GEN_VEXT_VMADC_VVM(NAME, ETYPE, H, DO_OP) \
+void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vl = env->vl; \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false);\
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
+ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
+ uint8_t carry = !vm ? vext_elem_mask(v0, i) : 0; \
+ \
+ vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \
+ } \
+ if (vta == 1) { \
+ for (; i < vlmax; i++) { \
+ vext_set_elem_mask(vd, i, 0); \
+ } \
+ } \
}
GEN_VEXT_VMADC_VVM(vmadc_vvm_b, uint8_t, H1, DO_MADC)
@@ -1358,17 +1362,21 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
{ \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false);\
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, i); \
+ uint8_t carry = !vm ? vext_elem_mask(v0, i) : 0; \
\
vext_set_elem_mask(vd, i, \
DO_OP(s2, (ETYPE)(target_long)s1, carry)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
+ if (vta == 1) { \
+ for (; i < vlmax; i++) { \
+ vext_set_elem_mask(vd, i, 0); \
+ } \
} \
}
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 35/65] target/riscv: rvv-0.9: narrowing integer right shift instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 24 ++++++++++----------
target/riscv/insn32.decode | 12 +++++-----
target/riscv/insn_trans/trans_rvv.inc.c | 30 ++++++++++++-------------
target/riscv/vector_helper.c | 24 ++++++++++----------
4 files changed, 45 insertions(+), 45 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index b253fee76d..151ed5ac64 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -379,18 +379,18 @@ DEF_HELPER_6(vsra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsra_vx_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsra_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsra_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsra_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vx_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsra_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsra_wv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsra_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsra_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsra_wx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsra_wx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsra_wx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vmseq_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmseq_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 481f909d47..bc6c788edf 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -352,12 +352,12 @@ vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm
vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm
vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm
vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm
-vnsrl_vv 101100 . ..... ..... 000 ..... 1010111 @r_vm
-vnsrl_vx 101100 . ..... ..... 100 ..... 1010111 @r_vm
-vnsrl_vi 101100 . ..... ..... 011 ..... 1010111 @r_vm
-vnsra_vv 101101 . ..... ..... 000 ..... 1010111 @r_vm
-vnsra_vx 101101 . ..... ..... 100 ..... 1010111 @r_vm
-vnsra_vi 101101 . ..... ..... 011 ..... 1010111 @r_vm
+vnsrl_wv 101100 . ..... ..... 000 ..... 1010111 @r_vm
+vnsrl_wx 101100 . ..... ..... 100 ..... 1010111 @r_vm
+vnsrl_wi 101100 . ..... ..... 011 ..... 1010111 @r_vm
+vnsra_wv 101101 . ..... ..... 000 ..... 1010111 @r_vm
+vnsra_wx 101101 . ..... ..... 100 ..... 1010111 @r_vm
+vnsra_wi 101101 . ..... ..... 011 ..... 1010111 @r_vm
vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm
vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm
vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 89a909b312..48b376c133 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1738,7 +1738,7 @@ GEN_OPIVI_TRANS(vsrl_vi, 1, vsrl_vx, opivx_check)
GEN_OPIVI_TRANS(vsra_vi, 1, vsra_vx, opivx_check)
/* Vector Narrowing Integer Right Shift Instructions */
-static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
+static bool opiwv_narrow_check(DisasContext *s, arg_rmrr *a)
{
REQUIRE_RVV;
VEXT_CHECK_ISA_ILL(s);
@@ -1747,10 +1747,10 @@ static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
}
/* OPIVV with NARROW */
-#define GEN_OPIVV_NARROW_TRANS(NAME) \
+#define GEN_OPIWV_NARROW_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
{ \
- if (opivv_narrow_check(s, a)) { \
+ if (opiwv_narrow_check(s, a)) { \
uint32_t data = 0; \
static gen_helper_gvec_4_ptr * const fns[3] = { \
gen_helper_##NAME##_b, \
@@ -1774,10 +1774,10 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
} \
return false; \
}
-GEN_OPIVV_NARROW_TRANS(vnsra_vv)
-GEN_OPIVV_NARROW_TRANS(vnsrl_vv)
+GEN_OPIWV_NARROW_TRANS(vnsra_wv)
+GEN_OPIWV_NARROW_TRANS(vnsrl_wv)
-static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a)
+static bool opiwx_narrow_check(DisasContext *s, arg_rmrr *a)
{
REQUIRE_RVV;
VEXT_CHECK_ISA_ILL(s);
@@ -1786,10 +1786,10 @@ static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a)
}
/* OPIVX with NARROW */
-#define GEN_OPIVX_NARROW_TRANS(NAME) \
+#define GEN_OPIWX_NARROW_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
{ \
- if (opivx_narrow_check(s, a)) { \
+ if (opiwx_narrow_check(s, a)) { \
static gen_helper_opivx * const fns[3] = { \
gen_helper_##NAME##_b, \
gen_helper_##NAME##_h, \
@@ -1800,14 +1800,14 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
return false; \
}
-GEN_OPIVX_NARROW_TRANS(vnsra_vx)
-GEN_OPIVX_NARROW_TRANS(vnsrl_vx)
+GEN_OPIWX_NARROW_TRANS(vnsra_wx)
+GEN_OPIWX_NARROW_TRANS(vnsrl_wx)
-/* OPIVI with NARROW */
-#define GEN_OPIVI_NARROW_TRANS(NAME, ZX, OPIVX) \
+/* OPIWI with NARROW */
+#define GEN_OPIWI_NARROW_TRANS(NAME, ZX, OPIVX) \
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
{ \
- if (opivx_narrow_check(s, a)) { \
+ if (opiwx_narrow_check(s, a)) { \
static gen_helper_opivx * const fns[3] = { \
gen_helper_##OPIVX##_b, \
gen_helper_##OPIVX##_h, \
@@ -1819,8 +1819,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
return false; \
}
-GEN_OPIVI_NARROW_TRANS(vnsra_vi, 1, vnsra_vx)
-GEN_OPIVI_NARROW_TRANS(vnsrl_vi, 1, vnsrl_vx)
+GEN_OPIWI_NARROW_TRANS(vnsra_wi, 1, vnsra_wx)
+GEN_OPIWI_NARROW_TRANS(vnsrl_wi, 1, vnsrl_wx)
/* Vector Integer Comparison Instructions */
/*
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index af4d3c6441..454864a90b 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1521,18 +1521,18 @@ GEN_VEXT_SHIFT_VX(vsra_vx_w, int32_t, int32_t, H4, H4, DO_SRL, 0x1f, clearl)
GEN_VEXT_SHIFT_VX(vsra_vx_d, int64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq)
/* Vector Narrowing Integer Right Shift Instructions */
-GEN_VEXT_SHIFT_VV(vnsrl_vv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb)
-GEN_VEXT_SHIFT_VV(vnsrl_vv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh)
-GEN_VEXT_SHIFT_VV(vnsrl_vv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl)
-GEN_VEXT_SHIFT_VV(vnsra_vv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb)
-GEN_VEXT_SHIFT_VV(vnsra_vv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh)
-GEN_VEXT_SHIFT_VV(vnsra_vv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
-GEN_VEXT_SHIFT_VX(vnsrl_vx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb)
-GEN_VEXT_SHIFT_VX(vnsrl_vx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh)
-GEN_VEXT_SHIFT_VX(vnsrl_vx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl)
-GEN_VEXT_SHIFT_VX(vnsra_vx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb)
-GEN_VEXT_SHIFT_VX(vnsra_vx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh)
-GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
+GEN_VEXT_SHIFT_VV(vnsrl_wv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb)
+GEN_VEXT_SHIFT_VV(vnsrl_wv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh)
+GEN_VEXT_SHIFT_VV(vnsrl_wv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl)
+GEN_VEXT_SHIFT_VV(vnsra_wv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb)
+GEN_VEXT_SHIFT_VV(vnsra_wv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh)
+GEN_VEXT_SHIFT_VV(vnsra_wv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
+GEN_VEXT_SHIFT_VX(vnsrl_wx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb)
+GEN_VEXT_SHIFT_VX(vnsrl_wx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh)
+GEN_VEXT_SHIFT_VX(vnsrl_wx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl)
+GEN_VEXT_SHIFT_VX(vnsra_wx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb)
+GEN_VEXT_SHIFT_VX(vnsra_wx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh)
+GEN_VEXT_SHIFT_VX(vnsra_wx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
/* Vector Integer Comparison Instructions */
#define DO_MSEQ(N, M) (N == M)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 35/65] target/riscv: rvv-0.9: narrowing integer right shift instructions
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 24 ++++++++++----------
target/riscv/insn32.decode | 12 +++++-----
target/riscv/insn_trans/trans_rvv.inc.c | 30 ++++++++++++-------------
target/riscv/vector_helper.c | 24 ++++++++++----------
4 files changed, 45 insertions(+), 45 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index b253fee76d..151ed5ac64 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -379,18 +379,18 @@ DEF_HELPER_6(vsra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsra_vx_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsra_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsra_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsra_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vx_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsra_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsra_wv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsra_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsra_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsra_wx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsra_wx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsra_wx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vmseq_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmseq_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 481f909d47..bc6c788edf 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -352,12 +352,12 @@ vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm
vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm
vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm
vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm
-vnsrl_vv 101100 . ..... ..... 000 ..... 1010111 @r_vm
-vnsrl_vx 101100 . ..... ..... 100 ..... 1010111 @r_vm
-vnsrl_vi 101100 . ..... ..... 011 ..... 1010111 @r_vm
-vnsra_vv 101101 . ..... ..... 000 ..... 1010111 @r_vm
-vnsra_vx 101101 . ..... ..... 100 ..... 1010111 @r_vm
-vnsra_vi 101101 . ..... ..... 011 ..... 1010111 @r_vm
+vnsrl_wv 101100 . ..... ..... 000 ..... 1010111 @r_vm
+vnsrl_wx 101100 . ..... ..... 100 ..... 1010111 @r_vm
+vnsrl_wi 101100 . ..... ..... 011 ..... 1010111 @r_vm
+vnsra_wv 101101 . ..... ..... 000 ..... 1010111 @r_vm
+vnsra_wx 101101 . ..... ..... 100 ..... 1010111 @r_vm
+vnsra_wi 101101 . ..... ..... 011 ..... 1010111 @r_vm
vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm
vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm
vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 89a909b312..48b376c133 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1738,7 +1738,7 @@ GEN_OPIVI_TRANS(vsrl_vi, 1, vsrl_vx, opivx_check)
GEN_OPIVI_TRANS(vsra_vi, 1, vsra_vx, opivx_check)
/* Vector Narrowing Integer Right Shift Instructions */
-static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
+static bool opiwv_narrow_check(DisasContext *s, arg_rmrr *a)
{
REQUIRE_RVV;
VEXT_CHECK_ISA_ILL(s);
@@ -1747,10 +1747,10 @@ static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
}
/* OPIVV with NARROW */
-#define GEN_OPIVV_NARROW_TRANS(NAME) \
+#define GEN_OPIWV_NARROW_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
{ \
- if (opivv_narrow_check(s, a)) { \
+ if (opiwv_narrow_check(s, a)) { \
uint32_t data = 0; \
static gen_helper_gvec_4_ptr * const fns[3] = { \
gen_helper_##NAME##_b, \
@@ -1774,10 +1774,10 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
} \
return false; \
}
-GEN_OPIVV_NARROW_TRANS(vnsra_vv)
-GEN_OPIVV_NARROW_TRANS(vnsrl_vv)
+GEN_OPIWV_NARROW_TRANS(vnsra_wv)
+GEN_OPIWV_NARROW_TRANS(vnsrl_wv)
-static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a)
+static bool opiwx_narrow_check(DisasContext *s, arg_rmrr *a)
{
REQUIRE_RVV;
VEXT_CHECK_ISA_ILL(s);
@@ -1786,10 +1786,10 @@ static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a)
}
/* OPIVX with NARROW */
-#define GEN_OPIVX_NARROW_TRANS(NAME) \
+#define GEN_OPIWX_NARROW_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
{ \
- if (opivx_narrow_check(s, a)) { \
+ if (opiwx_narrow_check(s, a)) { \
static gen_helper_opivx * const fns[3] = { \
gen_helper_##NAME##_b, \
gen_helper_##NAME##_h, \
@@ -1800,14 +1800,14 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
return false; \
}
-GEN_OPIVX_NARROW_TRANS(vnsra_vx)
-GEN_OPIVX_NARROW_TRANS(vnsrl_vx)
+GEN_OPIWX_NARROW_TRANS(vnsra_wx)
+GEN_OPIWX_NARROW_TRANS(vnsrl_wx)
-/* OPIVI with NARROW */
-#define GEN_OPIVI_NARROW_TRANS(NAME, ZX, OPIVX) \
+/* OPIWI with NARROW */
+#define GEN_OPIWI_NARROW_TRANS(NAME, ZX, OPIVX) \
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
{ \
- if (opivx_narrow_check(s, a)) { \
+ if (opiwx_narrow_check(s, a)) { \
static gen_helper_opivx * const fns[3] = { \
gen_helper_##OPIVX##_b, \
gen_helper_##OPIVX##_h, \
@@ -1819,8 +1819,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
return false; \
}
-GEN_OPIVI_NARROW_TRANS(vnsra_vi, 1, vnsra_vx)
-GEN_OPIVI_NARROW_TRANS(vnsrl_vi, 1, vnsrl_vx)
+GEN_OPIWI_NARROW_TRANS(vnsra_wi, 1, vnsra_wx)
+GEN_OPIWI_NARROW_TRANS(vnsrl_wi, 1, vnsrl_wx)
/* Vector Integer Comparison Instructions */
/*
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index af4d3c6441..454864a90b 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1521,18 +1521,18 @@ GEN_VEXT_SHIFT_VX(vsra_vx_w, int32_t, int32_t, H4, H4, DO_SRL, 0x1f, clearl)
GEN_VEXT_SHIFT_VX(vsra_vx_d, int64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq)
/* Vector Narrowing Integer Right Shift Instructions */
-GEN_VEXT_SHIFT_VV(vnsrl_vv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb)
-GEN_VEXT_SHIFT_VV(vnsrl_vv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh)
-GEN_VEXT_SHIFT_VV(vnsrl_vv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl)
-GEN_VEXT_SHIFT_VV(vnsra_vv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb)
-GEN_VEXT_SHIFT_VV(vnsra_vv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh)
-GEN_VEXT_SHIFT_VV(vnsra_vv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
-GEN_VEXT_SHIFT_VX(vnsrl_vx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb)
-GEN_VEXT_SHIFT_VX(vnsrl_vx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh)
-GEN_VEXT_SHIFT_VX(vnsrl_vx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl)
-GEN_VEXT_SHIFT_VX(vnsra_vx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb)
-GEN_VEXT_SHIFT_VX(vnsra_vx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh)
-GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
+GEN_VEXT_SHIFT_VV(vnsrl_wv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb)
+GEN_VEXT_SHIFT_VV(vnsrl_wv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh)
+GEN_VEXT_SHIFT_VV(vnsrl_wv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl)
+GEN_VEXT_SHIFT_VV(vnsra_wv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb)
+GEN_VEXT_SHIFT_VV(vnsra_wv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh)
+GEN_VEXT_SHIFT_VV(vnsra_wv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
+GEN_VEXT_SHIFT_VX(vnsrl_wx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb)
+GEN_VEXT_SHIFT_VX(vnsrl_wx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh)
+GEN_VEXT_SHIFT_VX(vnsrl_wx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl)
+GEN_VEXT_SHIFT_VX(vnsra_wx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb)
+GEN_VEXT_SHIFT_VX(vnsra_wx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh)
+GEN_VEXT_SHIFT_VX(vnsra_wx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
/* Vector Integer Comparison Instructions */
#define DO_MSEQ(N, M) (N == M)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 36/65] target/riscv: rvv-0.9: widening integer multiply-add instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index bc6c788edf..c6a7145aa5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -420,9 +420,9 @@ vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 @r_vm
vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm
vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm
vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm
-vwmaccsu_vv 111110 . ..... ..... 010 ..... 1010111 @r_vm
-vwmaccsu_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm
-vwmaccus_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm
+vwmaccsu_vv 111111 . ..... ..... 010 ..... 1010111 @r_vm
+vwmaccsu_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm
+vwmaccus_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm
vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2
vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2
vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 36/65] target/riscv: rvv-0.9: widening integer multiply-add instructions
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index bc6c788edf..c6a7145aa5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -420,9 +420,9 @@ vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 @r_vm
vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm
vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm
vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm
-vwmaccsu_vv 111110 . ..... ..... 010 ..... 1010111 @r_vm
-vwmaccsu_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm
-vwmaccus_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm
+vwmaccsu_vv 111111 . ..... ..... 010 ..... 1010111 @r_vm
+vwmaccsu_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm
+vwmaccus_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm
vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2
vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2
vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 37/65] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Add the following instructions:
* vqmaccu.vv
* vqmaccu.vx
* vqmacc.vv
* vqmacc.vx
* vqmaccsu.vv
* vqmaccsu.vx
* vqmaccus.vx
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 15 +++++
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_rvv.inc.c | 85 ++++++++++++++++++++++++-
target/riscv/vector_helper.c | 40 ++++++++++++
4 files changed, 146 insertions(+), 1 deletion(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 151ed5ac64..2a4e1ea773 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -622,6 +622,21 @@ DEF_HELPER_6(vwmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vqmaccu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vqmaccu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vqmacc_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vqmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vqmaccsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vqmaccsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vqmaccu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vqmaccu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vqmacc_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vqmacc_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vqmaccsu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vqmaccsu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vqmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vqmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+
DEF_HELPER_6(vmerge_vvm_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmerge_vvm_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmerge_vvm_w, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c6a7145aa5..acd65cb3a7 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -423,6 +423,13 @@ vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm
vwmaccsu_vv 111111 . ..... ..... 010 ..... 1010111 @r_vm
vwmaccsu_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm
vwmaccus_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm
+vqmaccu_vv 111100 . ..... ..... 000 ..... 1010111 @r_vm
+vqmaccu_vx 111100 . ..... ..... 100 ..... 1010111 @r_vm
+vqmacc_vv 111101 . ..... ..... 000 ..... 1010111 @r_vm
+vqmacc_vx 111101 . ..... ..... 100 ..... 1010111 @r_vm
+vqmaccsu_vv 111111 . ..... ..... 000 ..... 1010111 @r_vm
+vqmaccsu_vx 111111 . ..... ..... 100 ..... 1010111 @r_vm
+vqmaccus_vx 111110 . ..... ..... 100 ..... 1010111 @r_vm
vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2
vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2
vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 48b376c133..89718fdbc7 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -303,6 +303,33 @@ static uint32_t vreg_ofs(DisasContext *s, int reg)
} \
} while (0)
+/*
+ * Check function for vector instruction with format:
+ * quad-width result and single-width sources (4*SEW = SEW op SEW)
+ *
+ * is_vs1: indicates whether insn[19:15] is a vs1 field or not.
+ */
+#define VEXT_CHECK_QSS(s, rd, rs1, rs2, vm, is_vs1) do { \
+ require(s->flmul <= 2); \
+ require(s->sew < 2); \
+ require_align(rd, s->flmul * 4); \
+ require_align(rs2, s->flmul); \
+ require_vm(rd, vm); \
+ if (s->flmul < 1) { \
+ require_noover(rd, s->flmul * 4, rs2, s->flmul); \
+ } else { \
+ require_noover_widen(rd, s->flmul * 4, rs2, s->flmul); \
+ } \
+ if (is_vs1) { \
+ require_align(rs1, s->flmul); \
+ if (s->flmul < 1) { \
+ require_noover(rd, s->flmul * 4, rs1, s->flmul); \
+ } else { \
+ require_noover_widen(rd, s->flmul * 4, rs1, s->flmul); \
+ } \
+ } \
+} while (0)
+
/*
* Check function for vector instruction with format:
* double-width result and double-width source1 and single-width
@@ -1924,7 +1951,63 @@ GEN_OPIVX_WIDEN_TRANS(vwmacc_vx)
GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx)
GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx)
-/* Vector Integer Merge and Move Instructions */
+/* Vector Quad-Widening Integer Multiply-Add Instructions (Extension Zvqmac) */
+/* OPIVV with QUAD-WIDEN */
+static bool opivv_quad_widen_check(DisasContext *s, arg_rmrr *a)
+{
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_QSS(s, a->rd, a->rs1, a->rs2, a->vm, true);
+ return true;
+}
+
+#define GEN_OPIVV_QUAD_WIDEN_TRANS(NAME, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ static gen_helper_gvec_4_ptr * const fns[2] = { \
+ gen_helper_##NAME##_b, \
+ gen_helper_##NAME##_h \
+ }; \
+ return do_opivv_widen(s, a, fns[s->sew], CHECK); \
+}
+
+GEN_OPIVV_QUAD_WIDEN_TRANS(vqmaccu_vv, opivv_quad_widen_check)
+GEN_OPIVV_QUAD_WIDEN_TRANS(vqmacc_vv, opivv_quad_widen_check)
+GEN_OPIVV_QUAD_WIDEN_TRANS(vqmaccsu_vv, opivv_quad_widen_check)
+
+/* OPIVX with QUAD-WIDEN */
+static bool opivx_quad_widen_check(DisasContext *s, arg_rmrr *a)
+{
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_QSS(s, a->rd, a->rs1, a->rs2, a->vm, false);
+ return true;
+}
+
+static bool do_opivx_quad_widen(DisasContext *s, arg_rmrr *a,
+ gen_helper_opivx *fn)
+{
+ if (opivx_quad_widen_check(s, a)) {
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
+ }
+ return false;
+}
+
+#define GEN_OPIVX_QUAD_WIDEN_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ static gen_helper_opivx * const fns[3] = { \
+ gen_helper_##NAME##_b, \
+ gen_helper_##NAME##_h \
+ }; \
+ return do_opivx_quad_widen(s, a, fns[s->sew]); \
+}
+
+GEN_OPIVX_QUAD_WIDEN_TRANS(vqmaccu_vx)
+GEN_OPIVX_QUAD_WIDEN_TRANS(vqmacc_vx)
+GEN_OPIVX_QUAD_WIDEN_TRANS(vqmaccsu_vx)
+GEN_OPIVX_QUAD_WIDEN_TRANS(vqmaccus_vx)
+
static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
{
if (vext_check_isa_ill(s) &&
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 454864a90b..47ba264f1f 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2127,6 +2127,46 @@ GEN_VEXT_VX(vwmaccus_vx_b, 1, 2, clearh)
GEN_VEXT_VX(vwmaccus_vx_h, 2, 4, clearl)
GEN_VEXT_VX(vwmaccus_vx_w, 4, 8, clearq)
+/* Vector Quad-Widening Integer Multiply-Add Instructions */
+#define QOP_UUU_B uint32_t, uint8_t, uint8_t, uint32_t, uint32_t
+#define QOP_UUU_H uint64_t, uint16_t, uint16_t, uint64_t, uint64_t
+#define QOP_SSS_B int32_t, int8_t, int8_t, int32_t, int32_t
+#define QOP_SSS_H int64_t, int16_t, int16_t, int64_t, int64_t
+#define QOP_SUS_B int32_t, uint8_t, int8_t, uint32_t, int32_t
+#define QOP_SUS_H int64_t, uint16_t, int16_t, uint64_t, int64_t
+#define QOP_SSU_B int32_t, int8_t, uint8_t, int32_t, uint32_t
+#define QOP_SSU_H int64_t, int16_t, uint16_t, int64_t, uint64_t
+
+RVVCALL(OPIVV3, vqmaccu_vv_b, QOP_UUU_B, H4, H1, H1, DO_MACC)
+RVVCALL(OPIVV3, vqmaccu_vv_h, QOP_UUU_H, H8, H2, H2, DO_MACC)
+RVVCALL(OPIVV3, vqmacc_vv_b, QOP_SSS_B, H4, H1, H1, DO_MACC)
+RVVCALL(OPIVV3, vqmacc_vv_h, QOP_SSS_H, H8, H2, H2, DO_MACC)
+RVVCALL(OPIVV3, vqmaccsu_vv_b, QOP_SSU_B, H4, H1, H1, DO_MACC)
+RVVCALL(OPIVV3, vqmaccsu_vv_h, QOP_SSU_H, H8, H2, H2, DO_MACC)
+GEN_VEXT_VV(vqmaccu_vv_b, 1, 4, clearl)
+GEN_VEXT_VV(vqmaccu_vv_h, 2, 8, clearq)
+GEN_VEXT_VV(vqmacc_vv_b, 1, 4, clearl)
+GEN_VEXT_VV(vqmacc_vv_h, 2, 8, clearq)
+GEN_VEXT_VV(vqmaccsu_vv_b, 1, 4, clearl)
+GEN_VEXT_VV(vqmaccsu_vv_h, 2, 8, clearq)
+
+RVVCALL(OPIVX3, vqmaccu_vx_b, QOP_UUU_B, H4, H1, DO_MACC)
+RVVCALL(OPIVX3, vqmaccu_vx_h, QOP_UUU_H, H8, H2, DO_MACC)
+RVVCALL(OPIVX3, vqmacc_vx_b, QOP_SSS_B, H4, H1, DO_MACC)
+RVVCALL(OPIVX3, vqmacc_vx_h, QOP_SSS_H, H8, H2, DO_MACC)
+RVVCALL(OPIVX3, vqmaccsu_vx_b, QOP_SSU_B, H4, H1, DO_MACC)
+RVVCALL(OPIVX3, vqmaccsu_vx_h, QOP_SSU_H, H8, H2, DO_MACC)
+RVVCALL(OPIVX3, vqmaccus_vx_b, QOP_SUS_B, H4, H1, DO_MACC)
+RVVCALL(OPIVX3, vqmaccus_vx_h, QOP_SUS_H, H8, H2, DO_MACC)
+GEN_VEXT_VX(vqmaccu_vx_b, 1, 4, clearl)
+GEN_VEXT_VX(vqmaccu_vx_h, 2, 8, clearq)
+GEN_VEXT_VX(vqmacc_vx_b, 1, 4, clearl)
+GEN_VEXT_VX(vqmacc_vx_h, 2, 8, clearq)
+GEN_VEXT_VX(vqmaccsu_vx_b, 1, 4, clearl)
+GEN_VEXT_VX(vqmaccsu_vx_h, 2, 8, clearq)
+GEN_VEXT_VX(vqmaccus_vx_b, 1, 4, clearl)
+GEN_VEXT_VX(vqmaccus_vx_h, 2, 8, clearq)
+
/* Vector Integer Merge and Move Instructions */
#define GEN_VEXT_VMV_VV(NAME, ETYPE, H, CLEAR_FN) \
void HELPER(NAME)(void *vd, void *vs1, CPURISCVState *env, \
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 37/65] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Add the following instructions:
* vqmaccu.vv
* vqmaccu.vx
* vqmacc.vv
* vqmacc.vx
* vqmaccsu.vv
* vqmaccsu.vx
* vqmaccus.vx
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 15 +++++
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_rvv.inc.c | 85 ++++++++++++++++++++++++-
target/riscv/vector_helper.c | 40 ++++++++++++
4 files changed, 146 insertions(+), 1 deletion(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 151ed5ac64..2a4e1ea773 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -622,6 +622,21 @@ DEF_HELPER_6(vwmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vqmaccu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vqmaccu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vqmacc_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vqmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vqmaccsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vqmaccsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vqmaccu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vqmaccu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vqmacc_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vqmacc_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vqmaccsu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vqmaccsu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vqmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vqmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+
DEF_HELPER_6(vmerge_vvm_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmerge_vvm_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmerge_vvm_w, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c6a7145aa5..acd65cb3a7 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -423,6 +423,13 @@ vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm
vwmaccsu_vv 111111 . ..... ..... 010 ..... 1010111 @r_vm
vwmaccsu_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm
vwmaccus_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm
+vqmaccu_vv 111100 . ..... ..... 000 ..... 1010111 @r_vm
+vqmaccu_vx 111100 . ..... ..... 100 ..... 1010111 @r_vm
+vqmacc_vv 111101 . ..... ..... 000 ..... 1010111 @r_vm
+vqmacc_vx 111101 . ..... ..... 100 ..... 1010111 @r_vm
+vqmaccsu_vv 111111 . ..... ..... 000 ..... 1010111 @r_vm
+vqmaccsu_vx 111111 . ..... ..... 100 ..... 1010111 @r_vm
+vqmaccus_vx 111110 . ..... ..... 100 ..... 1010111 @r_vm
vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2
vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2
vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 48b376c133..89718fdbc7 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -303,6 +303,33 @@ static uint32_t vreg_ofs(DisasContext *s, int reg)
} \
} while (0)
+/*
+ * Check function for vector instruction with format:
+ * quad-width result and single-width sources (4*SEW = SEW op SEW)
+ *
+ * is_vs1: indicates whether insn[19:15] is a vs1 field or not.
+ */
+#define VEXT_CHECK_QSS(s, rd, rs1, rs2, vm, is_vs1) do { \
+ require(s->flmul <= 2); \
+ require(s->sew < 2); \
+ require_align(rd, s->flmul * 4); \
+ require_align(rs2, s->flmul); \
+ require_vm(rd, vm); \
+ if (s->flmul < 1) { \
+ require_noover(rd, s->flmul * 4, rs2, s->flmul); \
+ } else { \
+ require_noover_widen(rd, s->flmul * 4, rs2, s->flmul); \
+ } \
+ if (is_vs1) { \
+ require_align(rs1, s->flmul); \
+ if (s->flmul < 1) { \
+ require_noover(rd, s->flmul * 4, rs1, s->flmul); \
+ } else { \
+ require_noover_widen(rd, s->flmul * 4, rs1, s->flmul); \
+ } \
+ } \
+} while (0)
+
/*
* Check function for vector instruction with format:
* double-width result and double-width source1 and single-width
@@ -1924,7 +1951,63 @@ GEN_OPIVX_WIDEN_TRANS(vwmacc_vx)
GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx)
GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx)
-/* Vector Integer Merge and Move Instructions */
+/* Vector Quad-Widening Integer Multiply-Add Instructions (Extension Zvqmac) */
+/* OPIVV with QUAD-WIDEN */
+static bool opivv_quad_widen_check(DisasContext *s, arg_rmrr *a)
+{
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_QSS(s, a->rd, a->rs1, a->rs2, a->vm, true);
+ return true;
+}
+
+#define GEN_OPIVV_QUAD_WIDEN_TRANS(NAME, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ static gen_helper_gvec_4_ptr * const fns[2] = { \
+ gen_helper_##NAME##_b, \
+ gen_helper_##NAME##_h \
+ }; \
+ return do_opivv_widen(s, a, fns[s->sew], CHECK); \
+}
+
+GEN_OPIVV_QUAD_WIDEN_TRANS(vqmaccu_vv, opivv_quad_widen_check)
+GEN_OPIVV_QUAD_WIDEN_TRANS(vqmacc_vv, opivv_quad_widen_check)
+GEN_OPIVV_QUAD_WIDEN_TRANS(vqmaccsu_vv, opivv_quad_widen_check)
+
+/* OPIVX with QUAD-WIDEN */
+static bool opivx_quad_widen_check(DisasContext *s, arg_rmrr *a)
+{
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_QSS(s, a->rd, a->rs1, a->rs2, a->vm, false);
+ return true;
+}
+
+static bool do_opivx_quad_widen(DisasContext *s, arg_rmrr *a,
+ gen_helper_opivx *fn)
+{
+ if (opivx_quad_widen_check(s, a)) {
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
+ }
+ return false;
+}
+
+#define GEN_OPIVX_QUAD_WIDEN_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ static gen_helper_opivx * const fns[3] = { \
+ gen_helper_##NAME##_b, \
+ gen_helper_##NAME##_h \
+ }; \
+ return do_opivx_quad_widen(s, a, fns[s->sew]); \
+}
+
+GEN_OPIVX_QUAD_WIDEN_TRANS(vqmaccu_vx)
+GEN_OPIVX_QUAD_WIDEN_TRANS(vqmacc_vx)
+GEN_OPIVX_QUAD_WIDEN_TRANS(vqmaccsu_vx)
+GEN_OPIVX_QUAD_WIDEN_TRANS(vqmaccus_vx)
+
static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
{
if (vext_check_isa_ill(s) &&
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 454864a90b..47ba264f1f 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2127,6 +2127,46 @@ GEN_VEXT_VX(vwmaccus_vx_b, 1, 2, clearh)
GEN_VEXT_VX(vwmaccus_vx_h, 2, 4, clearl)
GEN_VEXT_VX(vwmaccus_vx_w, 4, 8, clearq)
+/* Vector Quad-Widening Integer Multiply-Add Instructions */
+#define QOP_UUU_B uint32_t, uint8_t, uint8_t, uint32_t, uint32_t
+#define QOP_UUU_H uint64_t, uint16_t, uint16_t, uint64_t, uint64_t
+#define QOP_SSS_B int32_t, int8_t, int8_t, int32_t, int32_t
+#define QOP_SSS_H int64_t, int16_t, int16_t, int64_t, int64_t
+#define QOP_SUS_B int32_t, uint8_t, int8_t, uint32_t, int32_t
+#define QOP_SUS_H int64_t, uint16_t, int16_t, uint64_t, int64_t
+#define QOP_SSU_B int32_t, int8_t, uint8_t, int32_t, uint32_t
+#define QOP_SSU_H int64_t, int16_t, uint16_t, int64_t, uint64_t
+
+RVVCALL(OPIVV3, vqmaccu_vv_b, QOP_UUU_B, H4, H1, H1, DO_MACC)
+RVVCALL(OPIVV3, vqmaccu_vv_h, QOP_UUU_H, H8, H2, H2, DO_MACC)
+RVVCALL(OPIVV3, vqmacc_vv_b, QOP_SSS_B, H4, H1, H1, DO_MACC)
+RVVCALL(OPIVV3, vqmacc_vv_h, QOP_SSS_H, H8, H2, H2, DO_MACC)
+RVVCALL(OPIVV3, vqmaccsu_vv_b, QOP_SSU_B, H4, H1, H1, DO_MACC)
+RVVCALL(OPIVV3, vqmaccsu_vv_h, QOP_SSU_H, H8, H2, H2, DO_MACC)
+GEN_VEXT_VV(vqmaccu_vv_b, 1, 4, clearl)
+GEN_VEXT_VV(vqmaccu_vv_h, 2, 8, clearq)
+GEN_VEXT_VV(vqmacc_vv_b, 1, 4, clearl)
+GEN_VEXT_VV(vqmacc_vv_h, 2, 8, clearq)
+GEN_VEXT_VV(vqmaccsu_vv_b, 1, 4, clearl)
+GEN_VEXT_VV(vqmaccsu_vv_h, 2, 8, clearq)
+
+RVVCALL(OPIVX3, vqmaccu_vx_b, QOP_UUU_B, H4, H1, DO_MACC)
+RVVCALL(OPIVX3, vqmaccu_vx_h, QOP_UUU_H, H8, H2, DO_MACC)
+RVVCALL(OPIVX3, vqmacc_vx_b, QOP_SSS_B, H4, H1, DO_MACC)
+RVVCALL(OPIVX3, vqmacc_vx_h, QOP_SSS_H, H8, H2, DO_MACC)
+RVVCALL(OPIVX3, vqmaccsu_vx_b, QOP_SSU_B, H4, H1, DO_MACC)
+RVVCALL(OPIVX3, vqmaccsu_vx_h, QOP_SSU_H, H8, H2, DO_MACC)
+RVVCALL(OPIVX3, vqmaccus_vx_b, QOP_SUS_B, H4, H1, DO_MACC)
+RVVCALL(OPIVX3, vqmaccus_vx_h, QOP_SUS_H, H8, H2, DO_MACC)
+GEN_VEXT_VX(vqmaccu_vx_b, 1, 4, clearl)
+GEN_VEXT_VX(vqmaccu_vx_h, 2, 8, clearq)
+GEN_VEXT_VX(vqmacc_vx_b, 1, 4, clearl)
+GEN_VEXT_VX(vqmacc_vx_h, 2, 8, clearq)
+GEN_VEXT_VX(vqmaccsu_vx_b, 1, 4, clearl)
+GEN_VEXT_VX(vqmaccsu_vx_h, 2, 8, clearq)
+GEN_VEXT_VX(vqmaccus_vx_b, 1, 4, clearl)
+GEN_VEXT_VX(vqmaccus_vx_h, 2, 8, clearq)
+
/* Vector Integer Merge and Move Instructions */
#define GEN_VEXT_VMV_VV(NAME, ETYPE, H, CLEAR_FN) \
void HELPER(NAME)(void *vd, void *vs1, CPURISCVState *env, \
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 38/65] target/riscv: rvv-0.9: integer merge and move instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 179 ++++++++++++------------
1 file changed, 90 insertions(+), 89 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 89718fdbc7..53c8dce159 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2008,121 +2008,122 @@ GEN_OPIVX_QUAD_WIDEN_TRANS(vqmacc_vx)
GEN_OPIVX_QUAD_WIDEN_TRANS(vqmaccsu_vx)
GEN_OPIVX_QUAD_WIDEN_TRANS(vqmaccus_vx)
+/* Vector Integer Move Instructions */
static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs1, false)) {
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ /* vmv.v.v has rs2 = 0 and vm = 1 */
+ VEXT_CHECK_SSS(s, a->rd, a->rs1, 0, 1, true);
- if (s->vl_eq_vlmax) {
- tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd),
- vreg_ofs(s, a->rs1),
- MAXSZ(s), MAXSZ(s));
- } else {
- uint32_t data = 0;
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, VTA, s->vta);
- static gen_helper_gvec_2_ptr * const fns[4] = {
- gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
- gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
- };
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ if (s->vl_eq_vlmax) {
+ tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd),
+ vreg_ofs(s, a->rs1),
+ MAXSZ(s), MAXSZ(s));
+ } else {
+ uint32_t data = 0;
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ static gen_helper_gvec_2_ptr * const fns[4] = {
+ gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
+ gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
+ };
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
- cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
- gen_set_label(over);
- }
- return true;
+ tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
+ cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
+ gen_set_label(over);
}
- return false;
+ return true;
}
typedef void gen_helper_vmv_vx(TCGv_ptr, TCGv_i64, TCGv_env, TCGv_i32);
static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false)) {
-
- TCGv s1;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ /* vmv.v.x has rs2 = 0 and vm = 1 */
+ VEXT_CHECK_SSS(s, a->rd, a->rs1, 0, 1, false);
- s1 = tcg_temp_new();
- gen_get_gpr(s1, a->rs1);
+ TCGv s1;
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- if (s->vl_eq_vlmax) {
- tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
- MAXSZ(s), MAXSZ(s), s1);
- } else {
- TCGv_i32 desc ;
- TCGv_i64 s1_i64 = tcg_temp_new_i64();
- TCGv_ptr dest = tcg_temp_new_ptr();
- uint32_t data = 0;
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, VTA, s->vta);
- static gen_helper_vmv_vx * const fns[4] = {
- gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
- gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
- };
+ s1 = tcg_temp_new();
+ gen_get_gpr(s1, a->rs1);
- tcg_gen_ext_tl_i64(s1_i64, s1);
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
- fns[s->sew](dest, s1_i64, cpu_env, desc);
+ if (s->vl_eq_vlmax) {
+ tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
+ MAXSZ(s), MAXSZ(s), s1);
+ } else {
+ TCGv_i32 desc ;
+ TCGv_i64 s1_i64 = tcg_temp_new_i64();
+ TCGv_ptr dest = tcg_temp_new_ptr();
+ uint32_t data = 0;
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ static gen_helper_vmv_vx * const fns[4] = {
+ gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
+ gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
+ };
- tcg_temp_free_ptr(dest);
- tcg_temp_free_i32(desc);
- tcg_temp_free_i64(s1_i64);
- }
+ tcg_gen_ext_tl_i64(s1_i64, s1);
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+ tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
+ fns[s->sew](dest, s1_i64, cpu_env, desc);
- tcg_temp_free(s1);
- gen_set_label(over);
- return true;
+ tcg_temp_free_ptr(dest);
+ tcg_temp_free_i32(desc);
+ tcg_temp_free_i64(s1_i64);
}
- return false;
+
+ tcg_temp_free(s1);
+ gen_set_label(over);
+ return true;
}
static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false)) {
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ /* vmv.v.i has rs2 = 0 and vm = 1 */
+ VEXT_CHECK_SSS(s, a->rd, a->rs1, 0, 1, false);
- int64_t simm = sextract64(a->rs1, 0, 5);
- if (s->vl_eq_vlmax) {
- tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd),
- MAXSZ(s), MAXSZ(s), simm);
- } else {
- TCGv_i32 desc;
- TCGv_i64 s1;
- TCGv_ptr dest;
- uint32_t data = 0;
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, VTA, s->vta);
- data = FIELD_DP32(data, VDATA, VMA, s->vma);
- static gen_helper_vmv_vx * const fns[4] = {
- gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
- gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
- };
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ int64_t simm = sextract64(a->rs1, 0, 5);
+ if (s->vl_eq_vlmax) {
+ tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd),
+ MAXSZ(s), MAXSZ(s), simm);
+ } else {
+ TCGv_i32 desc;
+ TCGv_i64 s1;
+ TCGv_ptr dest;
+ uint32_t data = 0;
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
+ static gen_helper_vmv_vx * const fns[4] = {
+ gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
+ gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
+ };
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- s1 = tcg_const_i64(simm);
- dest = tcg_temp_new_ptr();
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
- fns[s->sew](dest, s1, cpu_env, desc);
+ s1 = tcg_const_i64(simm);
+ dest = tcg_temp_new_ptr();
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+ tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
+ fns[s->sew](dest, s1, cpu_env, desc);
- tcg_temp_free_ptr(dest);
- tcg_temp_free_i32(desc);
- tcg_temp_free_i64(s1);
- gen_set_label(over);
- }
- return true;
+ tcg_temp_free_ptr(dest);
+ tcg_temp_free_i32(desc);
+ tcg_temp_free_i64(s1);
+ gen_set_label(over);
}
- return false;
+ return true;
}
+/* Vector Integer Merge Instructions */
GEN_OPIVV_TRANS(vmerge_vvm, opivv_vadc_check)
GEN_OPIVX_TRANS(vmerge_vxm, opivx_vadc_check)
GEN_OPIVI_TRANS(vmerge_vim, 0, vmerge_vxm, opivx_vadc_check)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 38/65] target/riscv: rvv-0.9: integer merge and move instructions
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 179 ++++++++++++------------
1 file changed, 90 insertions(+), 89 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 89718fdbc7..53c8dce159 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2008,121 +2008,122 @@ GEN_OPIVX_QUAD_WIDEN_TRANS(vqmacc_vx)
GEN_OPIVX_QUAD_WIDEN_TRANS(vqmaccsu_vx)
GEN_OPIVX_QUAD_WIDEN_TRANS(vqmaccus_vx)
+/* Vector Integer Move Instructions */
static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs1, false)) {
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ /* vmv.v.v has rs2 = 0 and vm = 1 */
+ VEXT_CHECK_SSS(s, a->rd, a->rs1, 0, 1, true);
- if (s->vl_eq_vlmax) {
- tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd),
- vreg_ofs(s, a->rs1),
- MAXSZ(s), MAXSZ(s));
- } else {
- uint32_t data = 0;
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, VTA, s->vta);
- static gen_helper_gvec_2_ptr * const fns[4] = {
- gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
- gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
- };
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ if (s->vl_eq_vlmax) {
+ tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd),
+ vreg_ofs(s, a->rs1),
+ MAXSZ(s), MAXSZ(s));
+ } else {
+ uint32_t data = 0;
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ static gen_helper_gvec_2_ptr * const fns[4] = {
+ gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
+ gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
+ };
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
- cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
- gen_set_label(over);
- }
- return true;
+ tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
+ cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
+ gen_set_label(over);
}
- return false;
+ return true;
}
typedef void gen_helper_vmv_vx(TCGv_ptr, TCGv_i64, TCGv_env, TCGv_i32);
static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false)) {
-
- TCGv s1;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ /* vmv.v.x has rs2 = 0 and vm = 1 */
+ VEXT_CHECK_SSS(s, a->rd, a->rs1, 0, 1, false);
- s1 = tcg_temp_new();
- gen_get_gpr(s1, a->rs1);
+ TCGv s1;
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- if (s->vl_eq_vlmax) {
- tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
- MAXSZ(s), MAXSZ(s), s1);
- } else {
- TCGv_i32 desc ;
- TCGv_i64 s1_i64 = tcg_temp_new_i64();
- TCGv_ptr dest = tcg_temp_new_ptr();
- uint32_t data = 0;
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, VTA, s->vta);
- static gen_helper_vmv_vx * const fns[4] = {
- gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
- gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
- };
+ s1 = tcg_temp_new();
+ gen_get_gpr(s1, a->rs1);
- tcg_gen_ext_tl_i64(s1_i64, s1);
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
- fns[s->sew](dest, s1_i64, cpu_env, desc);
+ if (s->vl_eq_vlmax) {
+ tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
+ MAXSZ(s), MAXSZ(s), s1);
+ } else {
+ TCGv_i32 desc ;
+ TCGv_i64 s1_i64 = tcg_temp_new_i64();
+ TCGv_ptr dest = tcg_temp_new_ptr();
+ uint32_t data = 0;
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ static gen_helper_vmv_vx * const fns[4] = {
+ gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
+ gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
+ };
- tcg_temp_free_ptr(dest);
- tcg_temp_free_i32(desc);
- tcg_temp_free_i64(s1_i64);
- }
+ tcg_gen_ext_tl_i64(s1_i64, s1);
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+ tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
+ fns[s->sew](dest, s1_i64, cpu_env, desc);
- tcg_temp_free(s1);
- gen_set_label(over);
- return true;
+ tcg_temp_free_ptr(dest);
+ tcg_temp_free_i32(desc);
+ tcg_temp_free_i64(s1_i64);
}
- return false;
+
+ tcg_temp_free(s1);
+ gen_set_label(over);
+ return true;
}
static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false)) {
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ /* vmv.v.i has rs2 = 0 and vm = 1 */
+ VEXT_CHECK_SSS(s, a->rd, a->rs1, 0, 1, false);
- int64_t simm = sextract64(a->rs1, 0, 5);
- if (s->vl_eq_vlmax) {
- tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd),
- MAXSZ(s), MAXSZ(s), simm);
- } else {
- TCGv_i32 desc;
- TCGv_i64 s1;
- TCGv_ptr dest;
- uint32_t data = 0;
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, VTA, s->vta);
- data = FIELD_DP32(data, VDATA, VMA, s->vma);
- static gen_helper_vmv_vx * const fns[4] = {
- gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
- gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
- };
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ int64_t simm = sextract64(a->rs1, 0, 5);
+ if (s->vl_eq_vlmax) {
+ tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd),
+ MAXSZ(s), MAXSZ(s), simm);
+ } else {
+ TCGv_i32 desc;
+ TCGv_i64 s1;
+ TCGv_ptr dest;
+ uint32_t data = 0;
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
+ static gen_helper_vmv_vx * const fns[4] = {
+ gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
+ gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
+ };
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- s1 = tcg_const_i64(simm);
- dest = tcg_temp_new_ptr();
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
- fns[s->sew](dest, s1, cpu_env, desc);
+ s1 = tcg_const_i64(simm);
+ dest = tcg_temp_new_ptr();
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+ tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
+ fns[s->sew](dest, s1, cpu_env, desc);
- tcg_temp_free_ptr(dest);
- tcg_temp_free_i32(desc);
- tcg_temp_free_i64(s1);
- gen_set_label(over);
- }
- return true;
+ tcg_temp_free_ptr(dest);
+ tcg_temp_free_i32(desc);
+ tcg_temp_free_i64(s1);
+ gen_set_label(over);
}
- return false;
+ return true;
}
+/* Vector Integer Merge Instructions */
GEN_OPIVV_TRANS(vmerge_vvm, opivv_vadc_check)
GEN_OPIVX_TRANS(vmerge_vxm, opivx_vadc_check)
GEN_OPIVI_TRANS(vmerge_vim, 0, vmerge_vxm, opivx_vadc_check)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 39/65] target/riscv: rvv-0.9: single-width saturating add and subtract instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Sign-extend vsaddu.vi immediate value.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
target/riscv/vector_helper.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 53c8dce159..152da0bd30 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2141,7 +2141,7 @@ GEN_OPIVX_TRANS(vsaddu_vx, opivx_check)
GEN_OPIVX_TRANS(vsadd_vx, opivx_check)
GEN_OPIVX_TRANS(vssubu_vx, opivx_check)
GEN_OPIVX_TRANS(vssub_vx, opivx_check)
-GEN_OPIVI_TRANS(vsaddu_vi, 1, vsaddu_vx, opivx_check)
+GEN_OPIVI_TRANS(vsaddu_vi, 0, vsaddu_vx, opivx_check)
GEN_OPIVI_TRANS(vsadd_vi, 0, vsadd_vx, opivx_check)
/* Vector Single-Width Averaging Add and Subtract */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 47ba264f1f..17a98bebe1 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2324,7 +2324,7 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
break;
}
- clearfn(vd, vta, vl, vl * dsz, vlmax * dsz);
+ clearfn(vd, vta, vl, vl * dsz, vlmax * dsz);
}
/* generate helpers for fixed point instructions with OPIVV format */
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 39/65] target/riscv: rvv-0.9: single-width saturating add and subtract instructions
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Sign-extend vsaddu.vi immediate value.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
target/riscv/vector_helper.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 53c8dce159..152da0bd30 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2141,7 +2141,7 @@ GEN_OPIVX_TRANS(vsaddu_vx, opivx_check)
GEN_OPIVX_TRANS(vsadd_vx, opivx_check)
GEN_OPIVX_TRANS(vssubu_vx, opivx_check)
GEN_OPIVX_TRANS(vssub_vx, opivx_check)
-GEN_OPIVI_TRANS(vsaddu_vi, 1, vsaddu_vx, opivx_check)
+GEN_OPIVI_TRANS(vsaddu_vi, 0, vsaddu_vx, opivx_check)
GEN_OPIVI_TRANS(vsadd_vi, 0, vsadd_vx, opivx_check)
/* Vector Single-Width Averaging Add and Subtract */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 47ba264f1f..17a98bebe1 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2324,7 +2324,7 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
break;
}
- clearfn(vd, vta, vl, vl * dsz, vlmax * dsz);
+ clearfn(vd, vta, vl, vl * dsz, vlmax * dsz);
}
/* generate helpers for fixed point instructions with OPIVV format */
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 40/65] target/riscv: rvv-0.9: integer comparison instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Sign-extend vmselu.vi and vmsgtu.vi immediate values.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 4 +-
target/riscv/vector_helper.c | 86 +++++++++++++------------
2 files changed, 48 insertions(+), 42 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 152da0bd30..b2552f920e 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1889,9 +1889,9 @@ GEN_OPIVX_TRANS(vmsgt_vx, opivx_cmp_check)
GEN_OPIVI_TRANS(vmseq_vi, 0, vmseq_vx, opivx_cmp_check)
GEN_OPIVI_TRANS(vmsne_vi, 0, vmsne_vx, opivx_cmp_check)
-GEN_OPIVI_TRANS(vmsleu_vi, 1, vmsleu_vx, opivx_cmp_check)
+GEN_OPIVI_TRANS(vmsleu_vi, 0, vmsleu_vx, opivx_cmp_check)
GEN_OPIVI_TRANS(vmsle_vi, 0, vmsle_vx, opivx_cmp_check)
-GEN_OPIVI_TRANS(vmsgtu_vi, 1, vmsgtu_vx, opivx_cmp_check)
+GEN_OPIVI_TRANS(vmsgtu_vi, 0, vmsgtu_vx, opivx_cmp_check)
GEN_OPIVI_TRANS(vmsgt_vi, 0, vmsgt_vx, opivx_cmp_check)
/* Vector Integer Min/Max Instructions */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 17a98bebe1..8d251dee58 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1541,26 +1541,29 @@ GEN_VEXT_SHIFT_VX(vnsra_wx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
#define DO_MSLE(N, M) (N <= M)
#define DO_MSGT(N, M) (N > M)
-#define GEN_VEXT_CMP_VV(NAME, ETYPE, H, DO_OP) \
-void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
- CPURISCVState *env, uint32_t desc) \
-{ \
- uint32_t vm = vext_vm(desc); \
- uint32_t vl = env->vl; \
- uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
- uint32_t i; \
- \
- for (i = 0; i < vl; i++) { \
- ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
- ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- if (!vm && !vext_elem_mask(v0, i)) { \
- continue; \
- } \
- vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
- } \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
+#define GEN_VEXT_CMP_VV(NAME, ETYPE, H, DO_OP) \
+void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
+ uint32_t vta = vext_vta(desc); \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
+ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ continue; \
+ } \
+ vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
+ } \
+ if (vta == 1) { \
+ for (; i < vlmax; i++) { \
+ vext_set_elem_mask(vd, i, 0); \
+ } \
+ } \
}
GEN_VEXT_CMP_VV(vmseq_vv_b, uint8_t, H1, DO_MSEQ)
@@ -1593,26 +1596,29 @@ GEN_VEXT_CMP_VV(vmsle_vv_h, int16_t, H2, DO_MSLE)
GEN_VEXT_CMP_VV(vmsle_vv_w, int32_t, H4, DO_MSLE)
GEN_VEXT_CMP_VV(vmsle_vv_d, int64_t, H8, DO_MSLE)
-#define GEN_VEXT_CMP_VX(NAME, ETYPE, H, DO_OP) \
-void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
- CPURISCVState *env, uint32_t desc) \
-{ \
- uint32_t vm = vext_vm(desc); \
- uint32_t vl = env->vl; \
- uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
- uint32_t i; \
- \
- for (i = 0; i < vl; i++) { \
- ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- if (!vm && !vext_elem_mask(v0, i)) { \
- continue; \
- } \
- vext_set_elem_mask(vd, i, \
- DO_OP(s2, (ETYPE)(target_long)s1)); \
- } \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
+#define GEN_VEXT_CMP_VX(NAME, ETYPE, H, DO_OP) \
+void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
+ uint32_t vta = vext_vta(desc); \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ continue; \
+ } \
+ vext_set_elem_mask(vd, i, \
+ DO_OP(s2, (ETYPE)(target_long)s1)); \
+ } \
+ if (vta == 1) { \
+ for (; i < vlmax; i++) { \
+ vext_set_elem_mask(vd, i, 0); \
+ } \
+ } \
}
GEN_VEXT_CMP_VX(vmseq_vx_b, uint8_t, H1, DO_MSEQ)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 40/65] target/riscv: rvv-0.9: integer comparison instructions
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Sign-extend vmselu.vi and vmsgtu.vi immediate values.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 4 +-
target/riscv/vector_helper.c | 86 +++++++++++++------------
2 files changed, 48 insertions(+), 42 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 152da0bd30..b2552f920e 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1889,9 +1889,9 @@ GEN_OPIVX_TRANS(vmsgt_vx, opivx_cmp_check)
GEN_OPIVI_TRANS(vmseq_vi, 0, vmseq_vx, opivx_cmp_check)
GEN_OPIVI_TRANS(vmsne_vi, 0, vmsne_vx, opivx_cmp_check)
-GEN_OPIVI_TRANS(vmsleu_vi, 1, vmsleu_vx, opivx_cmp_check)
+GEN_OPIVI_TRANS(vmsleu_vi, 0, vmsleu_vx, opivx_cmp_check)
GEN_OPIVI_TRANS(vmsle_vi, 0, vmsle_vx, opivx_cmp_check)
-GEN_OPIVI_TRANS(vmsgtu_vi, 1, vmsgtu_vx, opivx_cmp_check)
+GEN_OPIVI_TRANS(vmsgtu_vi, 0, vmsgtu_vx, opivx_cmp_check)
GEN_OPIVI_TRANS(vmsgt_vi, 0, vmsgt_vx, opivx_cmp_check)
/* Vector Integer Min/Max Instructions */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 17a98bebe1..8d251dee58 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1541,26 +1541,29 @@ GEN_VEXT_SHIFT_VX(vnsra_wx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
#define DO_MSLE(N, M) (N <= M)
#define DO_MSGT(N, M) (N > M)
-#define GEN_VEXT_CMP_VV(NAME, ETYPE, H, DO_OP) \
-void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
- CPURISCVState *env, uint32_t desc) \
-{ \
- uint32_t vm = vext_vm(desc); \
- uint32_t vl = env->vl; \
- uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
- uint32_t i; \
- \
- for (i = 0; i < vl; i++) { \
- ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
- ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- if (!vm && !vext_elem_mask(v0, i)) { \
- continue; \
- } \
- vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
- } \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
+#define GEN_VEXT_CMP_VV(NAME, ETYPE, H, DO_OP) \
+void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
+ uint32_t vta = vext_vta(desc); \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
+ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ continue; \
+ } \
+ vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
+ } \
+ if (vta == 1) { \
+ for (; i < vlmax; i++) { \
+ vext_set_elem_mask(vd, i, 0); \
+ } \
+ } \
}
GEN_VEXT_CMP_VV(vmseq_vv_b, uint8_t, H1, DO_MSEQ)
@@ -1593,26 +1596,29 @@ GEN_VEXT_CMP_VV(vmsle_vv_h, int16_t, H2, DO_MSLE)
GEN_VEXT_CMP_VV(vmsle_vv_w, int32_t, H4, DO_MSLE)
GEN_VEXT_CMP_VV(vmsle_vv_d, int64_t, H8, DO_MSLE)
-#define GEN_VEXT_CMP_VX(NAME, ETYPE, H, DO_OP) \
-void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
- CPURISCVState *env, uint32_t desc) \
-{ \
- uint32_t vm = vext_vm(desc); \
- uint32_t vl = env->vl; \
- uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
- uint32_t i; \
- \
- for (i = 0; i < vl; i++) { \
- ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- if (!vm && !vext_elem_mask(v0, i)) { \
- continue; \
- } \
- vext_set_elem_mask(vd, i, \
- DO_OP(s2, (ETYPE)(target_long)s1)); \
- } \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
+#define GEN_VEXT_CMP_VX(NAME, ETYPE, H, DO_OP) \
+void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
+ uint32_t vta = vext_vta(desc); \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ continue; \
+ } \
+ vext_set_elem_mask(vd, i, \
+ DO_OP(s2, (ETYPE)(target_long)s1)); \
+ } \
+ if (vta == 1) { \
+ for (; i < vlmax; i++) { \
+ vext_set_elem_mask(vd, i, 0); \
+ } \
+ } \
}
GEN_VEXT_CMP_VX(vmseq_vx_b, uint8_t, H1, DO_MSEQ)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 41/65] target/riscv: rvv-0.9: floating-point compare instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/vector_helper.c | 52 ++++++++++++++++++++----------------
1 file changed, 29 insertions(+), 23 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8d251dee58..11c962431e 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4148,27 +4148,30 @@ GEN_VEXT_VF(vfsgnjx_vf_w, 4, 4, clearl)
GEN_VEXT_VF(vfsgnjx_vf_d, 8, 8, clearq)
/* Vector Floating-Point Compare Instructions */
-#define GEN_VEXT_CMP_VV_ENV(NAME, ETYPE, H, DO_OP) \
-void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
- CPURISCVState *env, uint32_t desc) \
-{ \
- uint32_t vm = vext_vm(desc); \
- uint32_t vl = env->vl; \
- uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
- uint32_t i; \
- \
- for (i = 0; i < vl; i++) { \
- ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
- ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- if (!vm && !vext_elem_mask(v0, i)) { \
- continue; \
- } \
- vext_set_elem_mask(vd, i, \
- DO_OP(s2, s1, &env->fp_status)); \
- } \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
+#define GEN_VEXT_CMP_VV_ENV(NAME, ETYPE, H, DO_OP) \
+void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
+ uint32_t vta = vext_vta(desc); \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
+ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ continue; \
+ } \
+ vext_set_elem_mask(vd, i, \
+ DO_OP(s2, s1, &env->fp_status)); \
+ } \
+ if (vta == 1) { \
+ for (; i < vlmax; i++) { \
+ vext_set_elem_mask(vd, i, 0); \
+ } \
+ } \
}
static bool float16_eq_quiet(uint16_t a, uint16_t b, float_status *s)
@@ -4188,6 +4191,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -4198,8 +4202,10 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
vext_set_elem_mask(vd, i, \
DO_OP(s2, (ETYPE)s1, &env->fp_status)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
+ if (vta == 1) { \
+ for (; i < vlmax; i++) { \
+ vext_set_elem_mask(vd, i, 0); \
+ } \
} \
}
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 41/65] target/riscv: rvv-0.9: floating-point compare instructions
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/vector_helper.c | 52 ++++++++++++++++++++----------------
1 file changed, 29 insertions(+), 23 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8d251dee58..11c962431e 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4148,27 +4148,30 @@ GEN_VEXT_VF(vfsgnjx_vf_w, 4, 4, clearl)
GEN_VEXT_VF(vfsgnjx_vf_d, 8, 8, clearq)
/* Vector Floating-Point Compare Instructions */
-#define GEN_VEXT_CMP_VV_ENV(NAME, ETYPE, H, DO_OP) \
-void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
- CPURISCVState *env, uint32_t desc) \
-{ \
- uint32_t vm = vext_vm(desc); \
- uint32_t vl = env->vl; \
- uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
- uint32_t i; \
- \
- for (i = 0; i < vl; i++) { \
- ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
- ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- if (!vm && !vext_elem_mask(v0, i)) { \
- continue; \
- } \
- vext_set_elem_mask(vd, i, \
- DO_OP(s2, s1, &env->fp_status)); \
- } \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
+#define GEN_VEXT_CMP_VV_ENV(NAME, ETYPE, H, DO_OP) \
+void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
+ uint32_t vta = vext_vta(desc); \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
+ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ continue; \
+ } \
+ vext_set_elem_mask(vd, i, \
+ DO_OP(s2, s1, &env->fp_status)); \
+ } \
+ if (vta == 1) { \
+ for (; i < vlmax; i++) { \
+ vext_set_elem_mask(vd, i, 0); \
+ } \
+ } \
}
static bool float16_eq_quiet(uint16_t a, uint16_t b, float_status *s)
@@ -4188,6 +4191,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -4198,8 +4202,10 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
vext_set_elem_mask(vd, i, \
DO_OP(s2, (ETYPE)s1, &env->fp_status)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
+ if (vta == 1) { \
+ for (; i < vlmax; i++) { \
+ vext_set_elem_mask(vd, i, 0); \
+ } \
} \
}
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 42/65] target/riscv: rvv-0.9: single-width integer reduction instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 21 ++++----
target/riscv/vector_helper.c | 69 ++++++++++++-------------
2 files changed, 45 insertions(+), 45 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index b2552f920e..7d44ce7e0a 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -368,16 +368,16 @@ static uint32_t vreg_ofs(DisasContext *s, int reg)
} while (0)
/*
- * Check function for vector reduction instructions
+ * Check function for vector reduction instructions.
*
- * 2. In widen instructions and some other insturctions, like vslideup.vx,
- * there is no need to check whether LMUL=1.
+ * TODO: Check vstart == 0
*/
-static bool vext_check_overlap_mask(DisasContext *s, uint32_t vd, bool vm,
- bool force)
-{
- return (vm != 0 || vd != 0) || (!force && (s->lmul == 0));
-}
+#define VEXT_CHECK_REDUCTION(s, rs2, is_wide) do { \
+ if (is_wide) { \
+ require(s->sew < 3); \
+ } \
+ require_align(rs2, s->flmul) \
+} while (0)
/*
* Check function for vector integer extension instructions.
@@ -2731,7 +2731,10 @@ GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v)
/* Vector Single-Width Integer Reduction Instructions */
static bool reduction_check(DisasContext *s, arg_rmrr *a)
{
- return vext_check_isa_ill(s) && vext_check_reg(s, a->rs2, false);
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_REDUCTION(s, a->rs2, false);
+ return true;
}
GEN_OPIVV_TRANS(vredsum_vs, reduction_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 11c962431e..a7f960184b 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4558,15 +4558,13 @@ GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4, clearl)
*** Vector Reduction Operations
*/
/* Vector Single-Width Integer Reduction Instructions */
-#define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP, CLEAR_FN)\
+#define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP) \
void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
- uint32_t vta = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
- uint32_t tot = env_archcpu(env)->cfg.vlen / 8; \
TD s1 = *((TD *)vs1 + HD(0)); \
\
for (i = 0; i < vl; i++) { \
@@ -4577,56 +4575,55 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
s1 = OP(s1, (TD)s2); \
} \
*((TD *)vd + HD(0)) = s1; \
- CLEAR_FN(vd, vta, 1, sizeof(TD), tot); \
}
/* vd[0] = sum(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredsum_vs_b, int8_t, int8_t, H1, H1, DO_ADD, clearb)
-GEN_VEXT_RED(vredsum_vs_h, int16_t, int16_t, H2, H2, DO_ADD, clearh)
-GEN_VEXT_RED(vredsum_vs_w, int32_t, int32_t, H4, H4, DO_ADD, clearl)
-GEN_VEXT_RED(vredsum_vs_d, int64_t, int64_t, H8, H8, DO_ADD, clearq)
+GEN_VEXT_RED(vredsum_vs_b, int8_t, int8_t, H1, H1, DO_ADD)
+GEN_VEXT_RED(vredsum_vs_h, int16_t, int16_t, H2, H2, DO_ADD)
+GEN_VEXT_RED(vredsum_vs_w, int32_t, int32_t, H4, H4, DO_ADD)
+GEN_VEXT_RED(vredsum_vs_d, int64_t, int64_t, H8, H8, DO_ADD)
/* vd[0] = maxu(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredmaxu_vs_b, uint8_t, uint8_t, H1, H1, DO_MAX, clearb)
-GEN_VEXT_RED(vredmaxu_vs_h, uint16_t, uint16_t, H2, H2, DO_MAX, clearh)
-GEN_VEXT_RED(vredmaxu_vs_w, uint32_t, uint32_t, H4, H4, DO_MAX, clearl)
-GEN_VEXT_RED(vredmaxu_vs_d, uint64_t, uint64_t, H8, H8, DO_MAX, clearq)
+GEN_VEXT_RED(vredmaxu_vs_b, uint8_t, uint8_t, H1, H1, DO_MAX)
+GEN_VEXT_RED(vredmaxu_vs_h, uint16_t, uint16_t, H2, H2, DO_MAX)
+GEN_VEXT_RED(vredmaxu_vs_w, uint32_t, uint32_t, H4, H4, DO_MAX)
+GEN_VEXT_RED(vredmaxu_vs_d, uint64_t, uint64_t, H8, H8, DO_MAX)
/* vd[0] = max(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredmax_vs_b, int8_t, int8_t, H1, H1, DO_MAX, clearb)
-GEN_VEXT_RED(vredmax_vs_h, int16_t, int16_t, H2, H2, DO_MAX, clearh)
-GEN_VEXT_RED(vredmax_vs_w, int32_t, int32_t, H4, H4, DO_MAX, clearl)
-GEN_VEXT_RED(vredmax_vs_d, int64_t, int64_t, H8, H8, DO_MAX, clearq)
+GEN_VEXT_RED(vredmax_vs_b, int8_t, int8_t, H1, H1, DO_MAX)
+GEN_VEXT_RED(vredmax_vs_h, int16_t, int16_t, H2, H2, DO_MAX)
+GEN_VEXT_RED(vredmax_vs_w, int32_t, int32_t, H4, H4, DO_MAX)
+GEN_VEXT_RED(vredmax_vs_d, int64_t, int64_t, H8, H8, DO_MAX)
/* vd[0] = minu(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredminu_vs_b, uint8_t, uint8_t, H1, H1, DO_MIN, clearb)
-GEN_VEXT_RED(vredminu_vs_h, uint16_t, uint16_t, H2, H2, DO_MIN, clearh)
-GEN_VEXT_RED(vredminu_vs_w, uint32_t, uint32_t, H4, H4, DO_MIN, clearl)
-GEN_VEXT_RED(vredminu_vs_d, uint64_t, uint64_t, H8, H8, DO_MIN, clearq)
+GEN_VEXT_RED(vredminu_vs_b, uint8_t, uint8_t, H1, H1, DO_MIN)
+GEN_VEXT_RED(vredminu_vs_h, uint16_t, uint16_t, H2, H2, DO_MIN)
+GEN_VEXT_RED(vredminu_vs_w, uint32_t, uint32_t, H4, H4, DO_MIN)
+GEN_VEXT_RED(vredminu_vs_d, uint64_t, uint64_t, H8, H8, DO_MIN)
/* vd[0] = min(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredmin_vs_b, int8_t, int8_t, H1, H1, DO_MIN, clearb)
-GEN_VEXT_RED(vredmin_vs_h, int16_t, int16_t, H2, H2, DO_MIN, clearh)
-GEN_VEXT_RED(vredmin_vs_w, int32_t, int32_t, H4, H4, DO_MIN, clearl)
-GEN_VEXT_RED(vredmin_vs_d, int64_t, int64_t, H8, H8, DO_MIN, clearq)
+GEN_VEXT_RED(vredmin_vs_b, int8_t, int8_t, H1, H1, DO_MIN)
+GEN_VEXT_RED(vredmin_vs_h, int16_t, int16_t, H2, H2, DO_MIN)
+GEN_VEXT_RED(vredmin_vs_w, int32_t, int32_t, H4, H4, DO_MIN)
+GEN_VEXT_RED(vredmin_vs_d, int64_t, int64_t, H8, H8, DO_MIN)
/* vd[0] = and(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredand_vs_b, int8_t, int8_t, H1, H1, DO_AND, clearb)
-GEN_VEXT_RED(vredand_vs_h, int16_t, int16_t, H2, H2, DO_AND, clearh)
-GEN_VEXT_RED(vredand_vs_w, int32_t, int32_t, H4, H4, DO_AND, clearl)
-GEN_VEXT_RED(vredand_vs_d, int64_t, int64_t, H8, H8, DO_AND, clearq)
+GEN_VEXT_RED(vredand_vs_b, int8_t, int8_t, H1, H1, DO_AND)
+GEN_VEXT_RED(vredand_vs_h, int16_t, int16_t, H2, H2, DO_AND)
+GEN_VEXT_RED(vredand_vs_w, int32_t, int32_t, H4, H4, DO_AND)
+GEN_VEXT_RED(vredand_vs_d, int64_t, int64_t, H8, H8, DO_AND)
/* vd[0] = or(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredor_vs_b, int8_t, int8_t, H1, H1, DO_OR, clearb)
-GEN_VEXT_RED(vredor_vs_h, int16_t, int16_t, H2, H2, DO_OR, clearh)
-GEN_VEXT_RED(vredor_vs_w, int32_t, int32_t, H4, H4, DO_OR, clearl)
-GEN_VEXT_RED(vredor_vs_d, int64_t, int64_t, H8, H8, DO_OR, clearq)
+GEN_VEXT_RED(vredor_vs_b, int8_t, int8_t, H1, H1, DO_OR)
+GEN_VEXT_RED(vredor_vs_h, int16_t, int16_t, H2, H2, DO_OR)
+GEN_VEXT_RED(vredor_vs_w, int32_t, int32_t, H4, H4, DO_OR)
+GEN_VEXT_RED(vredor_vs_d, int64_t, int64_t, H8, H8, DO_OR)
/* vd[0] = xor(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredxor_vs_b, int8_t, int8_t, H1, H1, DO_XOR, clearb)
-GEN_VEXT_RED(vredxor_vs_h, int16_t, int16_t, H2, H2, DO_XOR, clearh)
-GEN_VEXT_RED(vredxor_vs_w, int32_t, int32_t, H4, H4, DO_XOR, clearl)
-GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR, clearq)
+GEN_VEXT_RED(vredxor_vs_b, int8_t, int8_t, H1, H1, DO_XOR)
+GEN_VEXT_RED(vredxor_vs_h, int16_t, int16_t, H2, H2, DO_XOR)
+GEN_VEXT_RED(vredxor_vs_w, int32_t, int32_t, H4, H4, DO_XOR)
+GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR)
/* Vector Widening Integer Reduction Instructions */
/* signed sum reduction into double-width accumulator */
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 42/65] target/riscv: rvv-0.9: single-width integer reduction instructions
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 21 ++++----
target/riscv/vector_helper.c | 69 ++++++++++++-------------
2 files changed, 45 insertions(+), 45 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index b2552f920e..7d44ce7e0a 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -368,16 +368,16 @@ static uint32_t vreg_ofs(DisasContext *s, int reg)
} while (0)
/*
- * Check function for vector reduction instructions
+ * Check function for vector reduction instructions.
*
- * 2. In widen instructions and some other insturctions, like vslideup.vx,
- * there is no need to check whether LMUL=1.
+ * TODO: Check vstart == 0
*/
-static bool vext_check_overlap_mask(DisasContext *s, uint32_t vd, bool vm,
- bool force)
-{
- return (vm != 0 || vd != 0) || (!force && (s->lmul == 0));
-}
+#define VEXT_CHECK_REDUCTION(s, rs2, is_wide) do { \
+ if (is_wide) { \
+ require(s->sew < 3); \
+ } \
+ require_align(rs2, s->flmul) \
+} while (0)
/*
* Check function for vector integer extension instructions.
@@ -2731,7 +2731,10 @@ GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v)
/* Vector Single-Width Integer Reduction Instructions */
static bool reduction_check(DisasContext *s, arg_rmrr *a)
{
- return vext_check_isa_ill(s) && vext_check_reg(s, a->rs2, false);
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_REDUCTION(s, a->rs2, false);
+ return true;
}
GEN_OPIVV_TRANS(vredsum_vs, reduction_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 11c962431e..a7f960184b 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4558,15 +4558,13 @@ GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4, clearl)
*** Vector Reduction Operations
*/
/* Vector Single-Width Integer Reduction Instructions */
-#define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP, CLEAR_FN)\
+#define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP) \
void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
- uint32_t vta = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
- uint32_t tot = env_archcpu(env)->cfg.vlen / 8; \
TD s1 = *((TD *)vs1 + HD(0)); \
\
for (i = 0; i < vl; i++) { \
@@ -4577,56 +4575,55 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
s1 = OP(s1, (TD)s2); \
} \
*((TD *)vd + HD(0)) = s1; \
- CLEAR_FN(vd, vta, 1, sizeof(TD), tot); \
}
/* vd[0] = sum(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredsum_vs_b, int8_t, int8_t, H1, H1, DO_ADD, clearb)
-GEN_VEXT_RED(vredsum_vs_h, int16_t, int16_t, H2, H2, DO_ADD, clearh)
-GEN_VEXT_RED(vredsum_vs_w, int32_t, int32_t, H4, H4, DO_ADD, clearl)
-GEN_VEXT_RED(vredsum_vs_d, int64_t, int64_t, H8, H8, DO_ADD, clearq)
+GEN_VEXT_RED(vredsum_vs_b, int8_t, int8_t, H1, H1, DO_ADD)
+GEN_VEXT_RED(vredsum_vs_h, int16_t, int16_t, H2, H2, DO_ADD)
+GEN_VEXT_RED(vredsum_vs_w, int32_t, int32_t, H4, H4, DO_ADD)
+GEN_VEXT_RED(vredsum_vs_d, int64_t, int64_t, H8, H8, DO_ADD)
/* vd[0] = maxu(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredmaxu_vs_b, uint8_t, uint8_t, H1, H1, DO_MAX, clearb)
-GEN_VEXT_RED(vredmaxu_vs_h, uint16_t, uint16_t, H2, H2, DO_MAX, clearh)
-GEN_VEXT_RED(vredmaxu_vs_w, uint32_t, uint32_t, H4, H4, DO_MAX, clearl)
-GEN_VEXT_RED(vredmaxu_vs_d, uint64_t, uint64_t, H8, H8, DO_MAX, clearq)
+GEN_VEXT_RED(vredmaxu_vs_b, uint8_t, uint8_t, H1, H1, DO_MAX)
+GEN_VEXT_RED(vredmaxu_vs_h, uint16_t, uint16_t, H2, H2, DO_MAX)
+GEN_VEXT_RED(vredmaxu_vs_w, uint32_t, uint32_t, H4, H4, DO_MAX)
+GEN_VEXT_RED(vredmaxu_vs_d, uint64_t, uint64_t, H8, H8, DO_MAX)
/* vd[0] = max(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredmax_vs_b, int8_t, int8_t, H1, H1, DO_MAX, clearb)
-GEN_VEXT_RED(vredmax_vs_h, int16_t, int16_t, H2, H2, DO_MAX, clearh)
-GEN_VEXT_RED(vredmax_vs_w, int32_t, int32_t, H4, H4, DO_MAX, clearl)
-GEN_VEXT_RED(vredmax_vs_d, int64_t, int64_t, H8, H8, DO_MAX, clearq)
+GEN_VEXT_RED(vredmax_vs_b, int8_t, int8_t, H1, H1, DO_MAX)
+GEN_VEXT_RED(vredmax_vs_h, int16_t, int16_t, H2, H2, DO_MAX)
+GEN_VEXT_RED(vredmax_vs_w, int32_t, int32_t, H4, H4, DO_MAX)
+GEN_VEXT_RED(vredmax_vs_d, int64_t, int64_t, H8, H8, DO_MAX)
/* vd[0] = minu(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredminu_vs_b, uint8_t, uint8_t, H1, H1, DO_MIN, clearb)
-GEN_VEXT_RED(vredminu_vs_h, uint16_t, uint16_t, H2, H2, DO_MIN, clearh)
-GEN_VEXT_RED(vredminu_vs_w, uint32_t, uint32_t, H4, H4, DO_MIN, clearl)
-GEN_VEXT_RED(vredminu_vs_d, uint64_t, uint64_t, H8, H8, DO_MIN, clearq)
+GEN_VEXT_RED(vredminu_vs_b, uint8_t, uint8_t, H1, H1, DO_MIN)
+GEN_VEXT_RED(vredminu_vs_h, uint16_t, uint16_t, H2, H2, DO_MIN)
+GEN_VEXT_RED(vredminu_vs_w, uint32_t, uint32_t, H4, H4, DO_MIN)
+GEN_VEXT_RED(vredminu_vs_d, uint64_t, uint64_t, H8, H8, DO_MIN)
/* vd[0] = min(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredmin_vs_b, int8_t, int8_t, H1, H1, DO_MIN, clearb)
-GEN_VEXT_RED(vredmin_vs_h, int16_t, int16_t, H2, H2, DO_MIN, clearh)
-GEN_VEXT_RED(vredmin_vs_w, int32_t, int32_t, H4, H4, DO_MIN, clearl)
-GEN_VEXT_RED(vredmin_vs_d, int64_t, int64_t, H8, H8, DO_MIN, clearq)
+GEN_VEXT_RED(vredmin_vs_b, int8_t, int8_t, H1, H1, DO_MIN)
+GEN_VEXT_RED(vredmin_vs_h, int16_t, int16_t, H2, H2, DO_MIN)
+GEN_VEXT_RED(vredmin_vs_w, int32_t, int32_t, H4, H4, DO_MIN)
+GEN_VEXT_RED(vredmin_vs_d, int64_t, int64_t, H8, H8, DO_MIN)
/* vd[0] = and(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredand_vs_b, int8_t, int8_t, H1, H1, DO_AND, clearb)
-GEN_VEXT_RED(vredand_vs_h, int16_t, int16_t, H2, H2, DO_AND, clearh)
-GEN_VEXT_RED(vredand_vs_w, int32_t, int32_t, H4, H4, DO_AND, clearl)
-GEN_VEXT_RED(vredand_vs_d, int64_t, int64_t, H8, H8, DO_AND, clearq)
+GEN_VEXT_RED(vredand_vs_b, int8_t, int8_t, H1, H1, DO_AND)
+GEN_VEXT_RED(vredand_vs_h, int16_t, int16_t, H2, H2, DO_AND)
+GEN_VEXT_RED(vredand_vs_w, int32_t, int32_t, H4, H4, DO_AND)
+GEN_VEXT_RED(vredand_vs_d, int64_t, int64_t, H8, H8, DO_AND)
/* vd[0] = or(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredor_vs_b, int8_t, int8_t, H1, H1, DO_OR, clearb)
-GEN_VEXT_RED(vredor_vs_h, int16_t, int16_t, H2, H2, DO_OR, clearh)
-GEN_VEXT_RED(vredor_vs_w, int32_t, int32_t, H4, H4, DO_OR, clearl)
-GEN_VEXT_RED(vredor_vs_d, int64_t, int64_t, H8, H8, DO_OR, clearq)
+GEN_VEXT_RED(vredor_vs_b, int8_t, int8_t, H1, H1, DO_OR)
+GEN_VEXT_RED(vredor_vs_h, int16_t, int16_t, H2, H2, DO_OR)
+GEN_VEXT_RED(vredor_vs_w, int32_t, int32_t, H4, H4, DO_OR)
+GEN_VEXT_RED(vredor_vs_d, int64_t, int64_t, H8, H8, DO_OR)
/* vd[0] = xor(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredxor_vs_b, int8_t, int8_t, H1, H1, DO_XOR, clearb)
-GEN_VEXT_RED(vredxor_vs_h, int16_t, int16_t, H2, H2, DO_XOR, clearh)
-GEN_VEXT_RED(vredxor_vs_w, int32_t, int32_t, H4, H4, DO_XOR, clearl)
-GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR, clearq)
+GEN_VEXT_RED(vredxor_vs_b, int8_t, int8_t, H1, H1, DO_XOR)
+GEN_VEXT_RED(vredxor_vs_h, int16_t, int16_t, H2, H2, DO_XOR)
+GEN_VEXT_RED(vredxor_vs_w, int32_t, int32_t, H4, H4, DO_XOR)
+GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR)
/* Vector Widening Integer Reduction Instructions */
/* signed sum reduction into double-width accumulator */
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 43/65] target/riscv: rvv-0.9: widening integer reduction instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 12 ++++++++++--
target/riscv/vector_helper.c | 12 ++++++------
2 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 7d44ce7e0a..f441385f3a 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2747,8 +2747,16 @@ GEN_OPIVV_TRANS(vredor_vs, reduction_check)
GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
/* Vector Widening Integer Reduction Instructions */
-GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_check)
-GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check)
+static bool reduction_widen_check(DisasContext *s, arg_rmrr *a)
+{
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_REDUCTION(s, a->rs2, true);
+ return true;
+}
+
+GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check)
+GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check)
/* Vector Single-Width Floating-Point Reduction Instructions */
GEN_OPFVV_TRANS(vfredsum_vs, reduction_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a7f960184b..7a10b957df 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4627,14 +4627,14 @@ GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR)
/* Vector Widening Integer Reduction Instructions */
/* signed sum reduction into double-width accumulator */
-GEN_VEXT_RED(vwredsum_vs_b, int16_t, int8_t, H2, H1, DO_ADD, clearh)
-GEN_VEXT_RED(vwredsum_vs_h, int32_t, int16_t, H4, H2, DO_ADD, clearl)
-GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4, DO_ADD, clearq)
+GEN_VEXT_RED(vwredsum_vs_b, int16_t, int8_t, H2, H1, DO_ADD)
+GEN_VEXT_RED(vwredsum_vs_h, int32_t, int16_t, H4, H2, DO_ADD)
+GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4, DO_ADD)
/* Unsigned sum reduction into double-width accumulator */
-GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD, clearh)
-GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD, clearl)
-GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD, clearq)
+GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD)
+GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD)
+GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD)
/* Vector Single-Width Floating-Point Reduction Instructions */
#define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, OP, CLEAR_FN)\
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 43/65] target/riscv: rvv-0.9: widening integer reduction instructions
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 12 ++++++++++--
target/riscv/vector_helper.c | 12 ++++++------
2 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 7d44ce7e0a..f441385f3a 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2747,8 +2747,16 @@ GEN_OPIVV_TRANS(vredor_vs, reduction_check)
GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
/* Vector Widening Integer Reduction Instructions */
-GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_check)
-GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check)
+static bool reduction_widen_check(DisasContext *s, arg_rmrr *a)
+{
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_REDUCTION(s, a->rs2, true);
+ return true;
+}
+
+GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check)
+GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check)
/* Vector Single-Width Floating-Point Reduction Instructions */
GEN_OPFVV_TRANS(vfredsum_vs, reduction_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a7f960184b..7a10b957df 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4627,14 +4627,14 @@ GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR)
/* Vector Widening Integer Reduction Instructions */
/* signed sum reduction into double-width accumulator */
-GEN_VEXT_RED(vwredsum_vs_b, int16_t, int8_t, H2, H1, DO_ADD, clearh)
-GEN_VEXT_RED(vwredsum_vs_h, int32_t, int16_t, H4, H2, DO_ADD, clearl)
-GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4, DO_ADD, clearq)
+GEN_VEXT_RED(vwredsum_vs_b, int16_t, int8_t, H2, H1, DO_ADD)
+GEN_VEXT_RED(vwredsum_vs_h, int32_t, int16_t, H4, H2, DO_ADD)
+GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4, DO_ADD)
/* Unsigned sum reduction into double-width accumulator */
-GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD, clearh)
-GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD, clearl)
-GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD, clearq)
+GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD)
+GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD)
+GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD)
/* Vector Single-Width Floating-Point Reduction Instructions */
#define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, OP, CLEAR_FN)\
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 44/65] target/riscv: rvv-0.9: mask-register logical instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 30 ++++++++++++-------------
target/riscv/vector_helper.c | 7 ++++--
2 files changed, 20 insertions(+), 17 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index f441385f3a..59b25e17f8 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2774,22 +2774,22 @@ GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
#define GEN_MM_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_r *a) \
{ \
- if (vext_check_isa_ill(s)) { \
- uint32_t data = 0; \
- gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
- TCGLabel *over = gen_new_label(); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ REQUIRE_RVV; \
+ VEXT_CHECK_ISA_ILL(s); \
\
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- data = FIELD_DP32(data, VDATA, VMA, s->vma); \
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs1), \
- vreg_ofs(s, a->rs2), cpu_env, 0, \
- s->vlen / 8, data, fn); \
- gen_set_label(over); \
- return true; \
- } \
- return false; \
+ uint32_t data = 0; \
+ gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
+ TCGLabel *over = gen_new_label(); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
+ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs1), \
+ vreg_ofs(s, a->rs2), cpu_env, 0, \
+ s->vlen / 8, data, fn); \
+ gen_set_label(over); \
+ return true; \
}
GEN_MM_TRANS(vmand_mm)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 7a10b957df..6484c660c6 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4731,6 +4731,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t desc) \
{ \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
int a, b; \
@@ -4740,8 +4741,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
b = vext_elem_mask(vs2, i); \
vext_set_elem_mask(vd, i, OP(b, a)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
+ if (vta == 1) { \
+ for (; i < vlmax; i++) { \
+ vext_set_elem_mask(vd, i, 0); \
+ } \
} \
}
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 44/65] target/riscv: rvv-0.9: mask-register logical instructions
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 30 ++++++++++++-------------
target/riscv/vector_helper.c | 7 ++++--
2 files changed, 20 insertions(+), 17 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index f441385f3a..59b25e17f8 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2774,22 +2774,22 @@ GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
#define GEN_MM_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_r *a) \
{ \
- if (vext_check_isa_ill(s)) { \
- uint32_t data = 0; \
- gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
- TCGLabel *over = gen_new_label(); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ REQUIRE_RVV; \
+ VEXT_CHECK_ISA_ILL(s); \
\
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- data = FIELD_DP32(data, VDATA, VMA, s->vma); \
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs1), \
- vreg_ofs(s, a->rs2), cpu_env, 0, \
- s->vlen / 8, data, fn); \
- gen_set_label(over); \
- return true; \
- } \
- return false; \
+ uint32_t data = 0; \
+ gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
+ TCGLabel *over = gen_new_label(); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
+ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs1), \
+ vreg_ofs(s, a->rs2), cpu_env, 0, \
+ s->vlen / 8, data, fn); \
+ gen_set_label(over); \
+ return true; \
}
GEN_MM_TRANS(vmand_mm)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 7a10b957df..6484c660c6 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4731,6 +4731,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t desc) \
{ \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
int a, b; \
@@ -4740,8 +4741,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
b = vext_elem_mask(vs2, i); \
vext_set_elem_mask(vd, i, OP(b, a)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
+ if (vta == 1) { \
+ for (; i < vlmax; i++) { \
+ vext_set_elem_mask(vd, i, 0); \
+ } \
} \
}
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 45/65] target/riscv: rvv-0.9: register gather instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 33 +++++++++++++++++--------
1 file changed, 23 insertions(+), 10 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 59b25e17f8..50f9782a96 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2958,17 +2958,29 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
/* Integer Extract Instruction */
static void load_element(TCGv_i64 dest, TCGv_ptr base,
- int ofs, int sew)
+ int ofs, int sew, bool sign)
{
switch (sew) {
case MO_8:
- tcg_gen_ld8u_i64(dest, base, ofs);
+ if (!sign) {
+ tcg_gen_ld8u_i64(dest, base, ofs);
+ } else {
+ tcg_gen_ld8s_i64(dest, base, ofs);
+ }
break;
case MO_16:
- tcg_gen_ld16u_i64(dest, base, ofs);
+ if (!sign) {
+ tcg_gen_ld16u_i64(dest, base, ofs);
+ } else {
+ tcg_gen_ld16s_i64(dest, base, ofs);
+ }
break;
case MO_32:
- tcg_gen_ld32u_i64(dest, base, ofs);
+ if (!sign) {
+ tcg_gen_ld32u_i64(dest, base, ofs);
+ } else {
+ tcg_gen_ld32s_i64(dest, base, ofs);
+ }
break;
case MO_64:
tcg_gen_ld_i64(dest, base, ofs);
@@ -3023,7 +3035,7 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64 dest,
/* Perform the load. */
load_element(dest, base,
- vreg_ofs(s, vreg), s->sew);
+ vreg_ofs(s, vreg), s->sew, false);
tcg_temp_free_ptr(base);
tcg_temp_free_i32(ofs);
@@ -3041,9 +3053,9 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64 dest,
}
static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
- int vreg, int idx)
+ int vreg, int idx, bool sign)
{
- load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew);
+ load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew, sign);
}
static bool trans_vext_x_v(DisasContext *s, arg_r *a)
@@ -3251,11 +3263,11 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
}
if (a->vm && s->vl_eq_vlmax) {
- int vlmax = s->vlen;
+ int vlmax = s->vlen * s->flmul / (1 << (s->sew + 3));
TCGv_i64 dest = tcg_temp_new_i64();
if (a->rs1 == 0) {
- vec_element_loadi(s, dest, a->rs2, 0);
+ vec_element_loadi(s, dest, a->rs2, 0, false);
} else {
vec_element_loadx(s, dest, a->rs2, cpu_gpr[a->rs1], vlmax);
}
@@ -3282,7 +3294,8 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
}
if (a->vm && s->vl_eq_vlmax) {
- if (a->rs1 >= s->vlen) {
+ int vlmax = s->vlen * s->flmul / (1 << (s->sew + 3));
+ if (a->rs1 >= vlmax) {
tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), 0);
} else {
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 45/65] target/riscv: rvv-0.9: register gather instructions
@ 2020-07-10 10:48 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 33 +++++++++++++++++--------
1 file changed, 23 insertions(+), 10 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 59b25e17f8..50f9782a96 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2958,17 +2958,29 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
/* Integer Extract Instruction */
static void load_element(TCGv_i64 dest, TCGv_ptr base,
- int ofs, int sew)
+ int ofs, int sew, bool sign)
{
switch (sew) {
case MO_8:
- tcg_gen_ld8u_i64(dest, base, ofs);
+ if (!sign) {
+ tcg_gen_ld8u_i64(dest, base, ofs);
+ } else {
+ tcg_gen_ld8s_i64(dest, base, ofs);
+ }
break;
case MO_16:
- tcg_gen_ld16u_i64(dest, base, ofs);
+ if (!sign) {
+ tcg_gen_ld16u_i64(dest, base, ofs);
+ } else {
+ tcg_gen_ld16s_i64(dest, base, ofs);
+ }
break;
case MO_32:
- tcg_gen_ld32u_i64(dest, base, ofs);
+ if (!sign) {
+ tcg_gen_ld32u_i64(dest, base, ofs);
+ } else {
+ tcg_gen_ld32s_i64(dest, base, ofs);
+ }
break;
case MO_64:
tcg_gen_ld_i64(dest, base, ofs);
@@ -3023,7 +3035,7 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64 dest,
/* Perform the load. */
load_element(dest, base,
- vreg_ofs(s, vreg), s->sew);
+ vreg_ofs(s, vreg), s->sew, false);
tcg_temp_free_ptr(base);
tcg_temp_free_i32(ofs);
@@ -3041,9 +3053,9 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64 dest,
}
static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
- int vreg, int idx)
+ int vreg, int idx, bool sign)
{
- load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew);
+ load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew, sign);
}
static bool trans_vext_x_v(DisasContext *s, arg_r *a)
@@ -3251,11 +3263,11 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
}
if (a->vm && s->vl_eq_vlmax) {
- int vlmax = s->vlen;
+ int vlmax = s->vlen * s->flmul / (1 << (s->sew + 3));
TCGv_i64 dest = tcg_temp_new_i64();
if (a->rs1 == 0) {
- vec_element_loadi(s, dest, a->rs2, 0);
+ vec_element_loadi(s, dest, a->rs2, 0, false);
} else {
vec_element_loadx(s, dest, a->rs2, cpu_gpr[a->rs1], vlmax);
}
@@ -3282,7 +3294,8 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
}
if (a->vm && s->vl_eq_vlmax) {
- if (a->rs1 >= s->vlen) {
+ int vlmax = s->vlen * s->flmul / (1 << (s->sew + 3));
+ if (a->rs1 >= vlmax) {
tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), 0);
} else {
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 46/65] target/riscv: rvv-0.9: slide instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:49 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 35 ++++++++---
target/riscv/vector_helper.c | 83 +++++++++++--------------
2 files changed, 64 insertions(+), 54 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 50f9782a96..dab642ab7a 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -379,6 +379,18 @@ static uint32_t vreg_ofs(DisasContext *s, int reg)
require_align(rs2, s->flmul) \
} while (0)
+/*
+ * Check function for vector slide instructions.
+ */
+#define VEXT_CHECK_SLIDE(s, rd, rs2, vm, is_over) do { \
+ require_align(rs2, s->flmul); \
+ require_align(rd, s->flmul); \
+ require_vm(vm, rd); \
+ if (is_over) { \
+ require(rd != rs2); \
+ } \
+} while (0)
+
/*
* Check function for vector integer extension instructions.
*/
@@ -3214,20 +3226,27 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
/* Vector Slide Instructions */
static bool slideup_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- (a->rd != a->rs2));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_SLIDE(s, a->rd, a->rs2, a->vm, true);
+ return true;
}
GEN_OPIVX_TRANS(vslideup_vx, slideup_check)
GEN_OPIVX_TRANS(vslide1up_vx, slideup_check)
GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check)
-GEN_OPIVX_TRANS(vslidedown_vx, opivx_check)
-GEN_OPIVX_TRANS(vslide1down_vx, opivx_check)
-GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check)
+static bool slidedown_check(DisasContext *s, arg_rmrr *a)
+{
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_SLIDE(s, a->rd, a->rs2, a->vm, false);
+ return true;
+}
+
+GEN_OPIVX_TRANS(vslidedown_vx, slidedown_check)
+GEN_OPIVX_TRANS(vslide1down_vx, slidedown_check)
+GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, slidedown_check)
/* Vector Register Gather Instruction */
static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 6484c660c6..050f4fd895 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4916,64 +4916,59 @@ GEN_VEXT_VID_V(vid_v_d, uint64_t, H8, clearq)
*/
/* Vector Slide Instructions */
-#define GEN_VEXT_VSLIDEUP_VX(NAME, ETYPE, H, CLEAR_FN) \
-void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
- CPURISCVState *env, uint32_t desc) \
-{ \
- uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
- uint32_t vm = vext_vm(desc); \
- uint32_t vta = vext_vta(desc); \
- uint32_t vl = env->vl; \
- target_ulong offset = s1, i; \
- \
- for (i = offset; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, i)) { \
- continue; \
- } \
- *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \
- } \
- CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+#define GEN_VEXT_VSLIDEUP_VX(NAME, ETYPE, H) \
+void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vl = env->vl; \
+ target_ulong offset = s1, i; \
+ \
+ for (i = offset; i < vl; i++) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ continue; \
+ } \
+ *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \
+ } \
}
/* vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] = vs2[i] */
-GEN_VEXT_VSLIDEUP_VX(vslideup_vx_b, uint8_t, H1, clearb)
-GEN_VEXT_VSLIDEUP_VX(vslideup_vx_h, uint16_t, H2, clearh)
-GEN_VEXT_VSLIDEUP_VX(vslideup_vx_w, uint32_t, H4, clearl)
-GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8, clearq)
+GEN_VEXT_VSLIDEUP_VX(vslideup_vx_b, uint8_t, H1)
+GEN_VEXT_VSLIDEUP_VX(vslideup_vx_h, uint16_t, H2)
+GEN_VEXT_VSLIDEUP_VX(vslideup_vx_w, uint32_t, H4)
+GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8)
-#define GEN_VEXT_VSLIDEDOWN_VX(NAME, ETYPE, H, CLEAR_FN) \
+#define GEN_VEXT_VSLIDEDOWN_VX(NAME, ETYPE, H) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
uint32_t vm = vext_vm(desc); \
- uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
target_ulong offset = s1, i; \
\
for (i = 0; i < vl; ++i) { \
+ /* offset may be a large value, which j may overflow */ \
target_ulong j = i + offset; \
+ bool is_valid = (offset >= vlmax || j >= vlmax) ? false : true; \
if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
- *((ETYPE *)vd + H(i)) = j >= vlmax ? 0 : *((ETYPE *)vs2 + H(j)); \
+ *((ETYPE *)vd + H(i)) = is_valid ? *((ETYPE *)vs2 + H(j)) : 0; \
} \
- CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1] */
-GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_b, uint8_t, H1, clearb)
-GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_h, uint16_t, H2, clearh)
-GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4, clearl)
-GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8, clearq)
+GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_b, uint8_t, H1)
+GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_h, uint16_t, H2)
+GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4)
+GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8)
-#define GEN_VEXT_VSLIDE1UP_VX(NAME, ETYPE, H, CLEAR_FN) \
+#define GEN_VEXT_VSLIDE1UP_VX(NAME, ETYPE, H) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
- uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
@@ -4987,22 +4982,19 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1)); \
} \
} \
- CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] */
-GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_b, uint8_t, H1, clearb)
-GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, uint16_t, H2, clearh)
-GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, uint32_t, H4, clearl)
-GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, uint64_t, H8, clearq)
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_b, uint8_t, H1)
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, uint16_t, H2)
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, uint32_t, H4)
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, uint64_t, H8)
-#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ETYPE, H, CLEAR_FN) \
+#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ETYPE, H) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
- uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
@@ -5016,14 +5008,13 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + 1)); \
} \
} \
- CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] */
-GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_b, uint8_t, H1, clearb)
-GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, uint16_t, H2, clearh)
-GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4, clearl)
-GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8, clearq)
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_b, uint8_t, H1)
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, uint16_t, H2)
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4)
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8)
/* Vector Register Gather Instruction */
#define GEN_VEXT_VRGATHER_VV(NAME, ETYPE, H, CLEAR_FN) \
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 46/65] target/riscv: rvv-0.9: slide instructions
@ 2020-07-10 10:49 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 35 ++++++++---
target/riscv/vector_helper.c | 83 +++++++++++--------------
2 files changed, 64 insertions(+), 54 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 50f9782a96..dab642ab7a 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -379,6 +379,18 @@ static uint32_t vreg_ofs(DisasContext *s, int reg)
require_align(rs2, s->flmul) \
} while (0)
+/*
+ * Check function for vector slide instructions.
+ */
+#define VEXT_CHECK_SLIDE(s, rd, rs2, vm, is_over) do { \
+ require_align(rs2, s->flmul); \
+ require_align(rd, s->flmul); \
+ require_vm(vm, rd); \
+ if (is_over) { \
+ require(rd != rs2); \
+ } \
+} while (0)
+
/*
* Check function for vector integer extension instructions.
*/
@@ -3214,20 +3226,27 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
/* Vector Slide Instructions */
static bool slideup_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- (a->rd != a->rs2));
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_SLIDE(s, a->rd, a->rs2, a->vm, true);
+ return true;
}
GEN_OPIVX_TRANS(vslideup_vx, slideup_check)
GEN_OPIVX_TRANS(vslide1up_vx, slideup_check)
GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check)
-GEN_OPIVX_TRANS(vslidedown_vx, opivx_check)
-GEN_OPIVX_TRANS(vslide1down_vx, opivx_check)
-GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check)
+static bool slidedown_check(DisasContext *s, arg_rmrr *a)
+{
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ VEXT_CHECK_SLIDE(s, a->rd, a->rs2, a->vm, false);
+ return true;
+}
+
+GEN_OPIVX_TRANS(vslidedown_vx, slidedown_check)
+GEN_OPIVX_TRANS(vslide1down_vx, slidedown_check)
+GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, slidedown_check)
/* Vector Register Gather Instruction */
static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 6484c660c6..050f4fd895 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4916,64 +4916,59 @@ GEN_VEXT_VID_V(vid_v_d, uint64_t, H8, clearq)
*/
/* Vector Slide Instructions */
-#define GEN_VEXT_VSLIDEUP_VX(NAME, ETYPE, H, CLEAR_FN) \
-void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
- CPURISCVState *env, uint32_t desc) \
-{ \
- uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
- uint32_t vm = vext_vm(desc); \
- uint32_t vta = vext_vta(desc); \
- uint32_t vl = env->vl; \
- target_ulong offset = s1, i; \
- \
- for (i = offset; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, i)) { \
- continue; \
- } \
- *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \
- } \
- CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+#define GEN_VEXT_VSLIDEUP_VX(NAME, ETYPE, H) \
+void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vl = env->vl; \
+ target_ulong offset = s1, i; \
+ \
+ for (i = offset; i < vl; i++) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ continue; \
+ } \
+ *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \
+ } \
}
/* vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] = vs2[i] */
-GEN_VEXT_VSLIDEUP_VX(vslideup_vx_b, uint8_t, H1, clearb)
-GEN_VEXT_VSLIDEUP_VX(vslideup_vx_h, uint16_t, H2, clearh)
-GEN_VEXT_VSLIDEUP_VX(vslideup_vx_w, uint32_t, H4, clearl)
-GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8, clearq)
+GEN_VEXT_VSLIDEUP_VX(vslideup_vx_b, uint8_t, H1)
+GEN_VEXT_VSLIDEUP_VX(vslideup_vx_h, uint16_t, H2)
+GEN_VEXT_VSLIDEUP_VX(vslideup_vx_w, uint32_t, H4)
+GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8)
-#define GEN_VEXT_VSLIDEDOWN_VX(NAME, ETYPE, H, CLEAR_FN) \
+#define GEN_VEXT_VSLIDEDOWN_VX(NAME, ETYPE, H) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
uint32_t vm = vext_vm(desc); \
- uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
target_ulong offset = s1, i; \
\
for (i = 0; i < vl; ++i) { \
+ /* offset may be a large value, which j may overflow */ \
target_ulong j = i + offset; \
+ bool is_valid = (offset >= vlmax || j >= vlmax) ? false : true; \
if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
- *((ETYPE *)vd + H(i)) = j >= vlmax ? 0 : *((ETYPE *)vs2 + H(j)); \
+ *((ETYPE *)vd + H(i)) = is_valid ? *((ETYPE *)vs2 + H(j)) : 0; \
} \
- CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1] */
-GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_b, uint8_t, H1, clearb)
-GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_h, uint16_t, H2, clearh)
-GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4, clearl)
-GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8, clearq)
+GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_b, uint8_t, H1)
+GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_h, uint16_t, H2)
+GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4)
+GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8)
-#define GEN_VEXT_VSLIDE1UP_VX(NAME, ETYPE, H, CLEAR_FN) \
+#define GEN_VEXT_VSLIDE1UP_VX(NAME, ETYPE, H) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
- uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
@@ -4987,22 +4982,19 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1)); \
} \
} \
- CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] */
-GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_b, uint8_t, H1, clearb)
-GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, uint16_t, H2, clearh)
-GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, uint32_t, H4, clearl)
-GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, uint64_t, H8, clearq)
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_b, uint8_t, H1)
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, uint16_t, H2)
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, uint32_t, H4)
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, uint64_t, H8)
-#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ETYPE, H, CLEAR_FN) \
+#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ETYPE, H) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
- uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
@@ -5016,14 +5008,13 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + 1)); \
} \
} \
- CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] */
-GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_b, uint8_t, H1, clearb)
-GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, uint16_t, H2, clearh)
-GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4, clearl)
-GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8, clearq)
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_b, uint8_t, H1)
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, uint16_t, H2)
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4)
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8)
/* Vector Register Gather Instruction */
#define GEN_VEXT_VRGATHER_VV(NAME, ETYPE, H, CLEAR_FN) \
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 47/65] target/riscv: rvv-0.9: floating-point slide instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:49 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Add the following instructions:
* vfslide1up.vf
* vfslide1down.vf
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 7 ++++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.inc.c | 4 ++
target/riscv/vector_helper.c | 51 +++++++++++++++++++++++++
4 files changed, 64 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 2a4e1ea773..d2bf9be551 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1114,6 +1114,13 @@ DEF_HELPER_6(vslide1down_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vslide1down_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vslide1down_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vfslide1up_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfslide1up_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfslide1up_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfslide1down_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfslide1down_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfslide1down_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+
DEF_HELPER_6(vrgather_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vrgather_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vrgather_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index acd65cb3a7..ed34ccd0e3 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -530,6 +530,8 @@ vfsgnjn_vv 001001 . ..... ..... 001 ..... 1010111 @r_vm
vfsgnjn_vf 001001 . ..... ..... 101 ..... 1010111 @r_vm
vfsgnjx_vv 001010 . ..... ..... 001 ..... 1010111 @r_vm
vfsgnjx_vf 001010 . ..... ..... 101 ..... 1010111 @r_vm
+vfslide1up_vf 001110 . ..... ..... 101 ..... 1010111 @r_vm
+vfslide1down_vf 001111 . ..... ..... 101 ..... 1010111 @r_vm
vmfeq_vv 011000 . ..... ..... 001 ..... 1010111 @r_vm
vmfeq_vf 011000 . ..... ..... 101 ..... 1010111 @r_vm
vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index dab642ab7a..f46cccc9bb 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -3248,6 +3248,10 @@ GEN_OPIVX_TRANS(vslidedown_vx, slidedown_check)
GEN_OPIVX_TRANS(vslide1down_vx, slidedown_check)
GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, slidedown_check)
+/* Vector Floating-Point Slide Instructions */
+GEN_OPFVF_TRANS(vfslide1up_vf, slideup_check)
+GEN_OPFVF_TRANS(vfslide1down_vf, slidedown_check)
+
/* Vector Register Gather Instruction */
static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a)
{
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 050f4fd895..cf245e0145 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -5016,6 +5016,57 @@ GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, uint16_t, H2)
GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4)
GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8)
+/* Vector Floating-Point Slide Instructions */
+#define GEN_VEXT_VFSLIDE1UP_VF(NAME, ETYPE, H) \
+void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ continue; \
+ } \
+ if (i == 0) { \
+ *((ETYPE *)vd + H(i)) = s1; \
+ } else { \
+ *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1)); \
+ } \
+ } \
+}
+
+/* vfslide1up.vf vd, vs2, rs1, vm # vd[0]=f[rs1], vd[i+1] = vs2[i] */
+GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_h, uint16_t, H1)
+GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_w, uint32_t, H1)
+GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_d, uint64_t, H1)
+
+#define GEN_VEXT_VFSLIDE1DOWN_VF(NAME, ETYPE, H) \
+void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ continue; \
+ } \
+ if (i == vl - 1) { \
+ *((ETYPE *)vd + H(i)) = s1; \
+ } else { \
+ *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + 1)); \
+ } \
+ } \
+}
+
+/* vfslide1down.vf vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=f[rs1] */
+GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_h, uint16_t, H1)
+GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_w, uint32_t, H1)
+GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_d, uint64_t, H1)
+
/* Vector Register Gather Instruction */
#define GEN_VEXT_VRGATHER_VV(NAME, ETYPE, H, CLEAR_FN) \
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 47/65] target/riscv: rvv-0.9: floating-point slide instructions
@ 2020-07-10 10:49 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Add the following instructions:
* vfslide1up.vf
* vfslide1down.vf
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 7 ++++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.inc.c | 4 ++
target/riscv/vector_helper.c | 51 +++++++++++++++++++++++++
4 files changed, 64 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 2a4e1ea773..d2bf9be551 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1114,6 +1114,13 @@ DEF_HELPER_6(vslide1down_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vslide1down_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vslide1down_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vfslide1up_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfslide1up_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfslide1up_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfslide1down_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfslide1down_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfslide1down_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+
DEF_HELPER_6(vrgather_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vrgather_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vrgather_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index acd65cb3a7..ed34ccd0e3 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -530,6 +530,8 @@ vfsgnjn_vv 001001 . ..... ..... 001 ..... 1010111 @r_vm
vfsgnjn_vf 001001 . ..... ..... 101 ..... 1010111 @r_vm
vfsgnjx_vv 001010 . ..... ..... 001 ..... 1010111 @r_vm
vfsgnjx_vf 001010 . ..... ..... 101 ..... 1010111 @r_vm
+vfslide1up_vf 001110 . ..... ..... 101 ..... 1010111 @r_vm
+vfslide1down_vf 001111 . ..... ..... 101 ..... 1010111 @r_vm
vmfeq_vv 011000 . ..... ..... 001 ..... 1010111 @r_vm
vmfeq_vf 011000 . ..... ..... 101 ..... 1010111 @r_vm
vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index dab642ab7a..f46cccc9bb 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -3248,6 +3248,10 @@ GEN_OPIVX_TRANS(vslidedown_vx, slidedown_check)
GEN_OPIVX_TRANS(vslide1down_vx, slidedown_check)
GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, slidedown_check)
+/* Vector Floating-Point Slide Instructions */
+GEN_OPFVF_TRANS(vfslide1up_vf, slideup_check)
+GEN_OPFVF_TRANS(vfslide1down_vf, slidedown_check)
+
/* Vector Register Gather Instruction */
static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a)
{
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 050f4fd895..cf245e0145 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -5016,6 +5016,57 @@ GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, uint16_t, H2)
GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4)
GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8)
+/* Vector Floating-Point Slide Instructions */
+#define GEN_VEXT_VFSLIDE1UP_VF(NAME, ETYPE, H) \
+void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ continue; \
+ } \
+ if (i == 0) { \
+ *((ETYPE *)vd + H(i)) = s1; \
+ } else { \
+ *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1)); \
+ } \
+ } \
+}
+
+/* vfslide1up.vf vd, vs2, rs1, vm # vd[0]=f[rs1], vd[i+1] = vs2[i] */
+GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_h, uint16_t, H1)
+GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_w, uint32_t, H1)
+GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_d, uint64_t, H1)
+
+#define GEN_VEXT_VFSLIDE1DOWN_VF(NAME, ETYPE, H) \
+void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ continue; \
+ } \
+ if (i == vl - 1) { \
+ *((ETYPE *)vd + H(i)) = s1; \
+ } else { \
+ *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + 1)); \
+ } \
+ } \
+}
+
+/* vfslide1down.vf vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=f[rs1] */
+GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_h, uint16_t, H1)
+GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_w, uint32_t, H1)
+GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_d, uint64_t, H1)
+
/* Vector Register Gather Instruction */
#define GEN_VEXT_VRGATHER_VV(NAME, ETYPE, H, CLEAR_FN) \
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 48/65] target/riscv: rvv-0.9: narrowing fixed-point clip instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:49 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 24 ++++++------
target/riscv/insn32.decode | 12 +++---
target/riscv/insn_trans/trans_rvv.inc.c | 12 +++---
target/riscv/vector_helper.c | 52 ++++++++++++-------------
4 files changed, 50 insertions(+), 50 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index d2bf9be551..353a1b7868 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -768,18 +768,18 @@ DEF_HELPER_6(vssra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vssra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vssra_vx_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnclip_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnclip_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnclip_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnclipu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnclipu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnclipu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnclipu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnclipu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnclipu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnclip_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnclip_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnclip_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclip_wv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclip_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclip_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclipu_wv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclipu_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclipu_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclipu_wx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclipu_wx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclipu_wx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclip_wx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclip_wx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclip_wx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vfadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index ed34ccd0e3..dc3965c050 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -469,12 +469,12 @@ vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm
vssra_vv 101011 . ..... ..... 000 ..... 1010111 @r_vm
vssra_vx 101011 . ..... ..... 100 ..... 1010111 @r_vm
vssra_vi 101011 . ..... ..... 011 ..... 1010111 @r_vm
-vnclipu_vv 101110 . ..... ..... 000 ..... 1010111 @r_vm
-vnclipu_vx 101110 . ..... ..... 100 ..... 1010111 @r_vm
-vnclipu_vi 101110 . ..... ..... 011 ..... 1010111 @r_vm
-vnclip_vv 101111 . ..... ..... 000 ..... 1010111 @r_vm
-vnclip_vx 101111 . ..... ..... 100 ..... 1010111 @r_vm
-vnclip_vi 101111 . ..... ..... 011 ..... 1010111 @r_vm
+vnclipu_wv 101110 . ..... ..... 000 ..... 1010111 @r_vm
+vnclipu_wx 101110 . ..... ..... 100 ..... 1010111 @r_vm
+vnclipu_wi 101110 . ..... ..... 011 ..... 1010111 @r_vm
+vnclip_wv 101111 . ..... ..... 000 ..... 1010111 @r_vm
+vnclip_wx 101111 . ..... ..... 100 ..... 1010111 @r_vm
+vnclip_wi 101111 . ..... ..... 011 ..... 1010111 @r_vm
vfadd_vv 000000 . ..... ..... 001 ..... 1010111 @r_vm
vfadd_vf 000000 . ..... ..... 101 ..... 1010111 @r_vm
vfsub_vv 000010 . ..... ..... 001 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index f46cccc9bb..986f62dabc 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2188,12 +2188,12 @@ GEN_OPIVI_TRANS(vssrl_vi, 1, vssrl_vx, opivx_check)
GEN_OPIVI_TRANS(vssra_vi, 0, vssra_vx, opivx_check)
/* Vector Narrowing Fixed-Point Clip Instructions */
-GEN_OPIVV_NARROW_TRANS(vnclipu_vv)
-GEN_OPIVV_NARROW_TRANS(vnclip_vv)
-GEN_OPIVX_NARROW_TRANS(vnclipu_vx)
-GEN_OPIVX_NARROW_TRANS(vnclip_vx)
-GEN_OPIVI_NARROW_TRANS(vnclipu_vi, 1, vnclipu_vx)
-GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx)
+GEN_OPIWV_NARROW_TRANS(vnclipu_wv)
+GEN_OPIWV_NARROW_TRANS(vnclip_wv)
+GEN_OPIWX_NARROW_TRANS(vnclipu_wx)
+GEN_OPIWX_NARROW_TRANS(vnclip_wx)
+GEN_OPIWI_NARROW_TRANS(vnclipu_wi, 1, vnclipu_wx)
+GEN_OPIWI_NARROW_TRANS(vnclip_wi, 1, vnclip_wx)
/*
*** Vector Float Point Arithmetic Instructions
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index cf245e0145..035ccef9c3 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3310,19 +3310,19 @@ vnclip32(CPURISCVState *env, int vxrm, int64_t a, int32_t b)
}
}
-RVVCALL(OPIVV2_RM, vnclip_vv_b, NOP_SSS_B, H1, H2, H1, vnclip8)
-RVVCALL(OPIVV2_RM, vnclip_vv_h, NOP_SSS_H, H2, H4, H2, vnclip16)
-RVVCALL(OPIVV2_RM, vnclip_vv_w, NOP_SSS_W, H4, H8, H4, vnclip32)
-GEN_VEXT_VV_RM(vnclip_vv_b, 1, 1, clearb)
-GEN_VEXT_VV_RM(vnclip_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_RM(vnclip_vv_w, 4, 4, clearl)
-
-RVVCALL(OPIVX2_RM, vnclip_vx_b, NOP_SSS_B, H1, H2, vnclip8)
-RVVCALL(OPIVX2_RM, vnclip_vx_h, NOP_SSS_H, H2, H4, vnclip16)
-RVVCALL(OPIVX2_RM, vnclip_vx_w, NOP_SSS_W, H4, H8, vnclip32)
-GEN_VEXT_VX_RM(vnclip_vx_b, 1, 1, clearb)
-GEN_VEXT_VX_RM(vnclip_vx_h, 2, 2, clearh)
-GEN_VEXT_VX_RM(vnclip_vx_w, 4, 4, clearl)
+RVVCALL(OPIVV2_RM, vnclip_wv_b, NOP_SSS_B, H1, H2, H1, vnclip8)
+RVVCALL(OPIVV2_RM, vnclip_wv_h, NOP_SSS_H, H2, H4, H2, vnclip16)
+RVVCALL(OPIVV2_RM, vnclip_wv_w, NOP_SSS_W, H4, H8, H4, vnclip32)
+GEN_VEXT_VV_RM(vnclip_wv_b, 1, 1, clearb)
+GEN_VEXT_VV_RM(vnclip_wv_h, 2, 2, clearh)
+GEN_VEXT_VV_RM(vnclip_wv_w, 4, 4, clearl)
+
+RVVCALL(OPIVX2_RM, vnclip_wx_b, NOP_SSS_B, H1, H2, vnclip8)
+RVVCALL(OPIVX2_RM, vnclip_wx_h, NOP_SSS_H, H2, H4, vnclip16)
+RVVCALL(OPIVX2_RM, vnclip_wx_w, NOP_SSS_W, H4, H8, vnclip32)
+GEN_VEXT_VX_RM(vnclip_wx_b, 1, 1, clearb)
+GEN_VEXT_VX_RM(vnclip_wx_h, 2, 2, clearh)
+GEN_VEXT_VX_RM(vnclip_wx_w, 4, 4, clearl)
static inline uint8_t
vnclipu8(CPURISCVState *env, int vxrm, uint16_t a, uint8_t b)
@@ -3360,7 +3360,7 @@ static inline uint32_t
vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b)
{
uint8_t round, shift = b & 0x3f;
- int64_t res;
+ uint64_t res;
round = get_round(vxrm, a, shift);
res = (a >> shift) + round;
@@ -3372,19 +3372,19 @@ vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b)
}
}
-RVVCALL(OPIVV2_RM, vnclipu_vv_b, NOP_UUU_B, H1, H2, H1, vnclipu8)
-RVVCALL(OPIVV2_RM, vnclipu_vv_h, NOP_UUU_H, H2, H4, H2, vnclipu16)
-RVVCALL(OPIVV2_RM, vnclipu_vv_w, NOP_UUU_W, H4, H8, H4, vnclipu32)
-GEN_VEXT_VV_RM(vnclipu_vv_b, 1, 1, clearb)
-GEN_VEXT_VV_RM(vnclipu_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_RM(vnclipu_vv_w, 4, 4, clearl)
+RVVCALL(OPIVV2_RM, vnclipu_wv_b, NOP_UUU_B, H1, H2, H1, vnclipu8)
+RVVCALL(OPIVV2_RM, vnclipu_wv_h, NOP_UUU_H, H2, H4, H2, vnclipu16)
+RVVCALL(OPIVV2_RM, vnclipu_wv_w, NOP_UUU_W, H4, H8, H4, vnclipu32)
+GEN_VEXT_VV_RM(vnclipu_wv_b, 1, 1, clearb)
+GEN_VEXT_VV_RM(vnclipu_wv_h, 2, 2, clearh)
+GEN_VEXT_VV_RM(vnclipu_wv_w, 4, 4, clearl)
-RVVCALL(OPIVX2_RM, vnclipu_vx_b, NOP_UUU_B, H1, H2, vnclipu8)
-RVVCALL(OPIVX2_RM, vnclipu_vx_h, NOP_UUU_H, H2, H4, vnclipu16)
-RVVCALL(OPIVX2_RM, vnclipu_vx_w, NOP_UUU_W, H4, H8, vnclipu32)
-GEN_VEXT_VX_RM(vnclipu_vx_b, 1, 1, clearb)
-GEN_VEXT_VX_RM(vnclipu_vx_h, 2, 2, clearh)
-GEN_VEXT_VX_RM(vnclipu_vx_w, 4, 4, clearl)
+RVVCALL(OPIVX2_RM, vnclipu_wx_b, NOP_UUU_B, H1, H2, vnclipu8)
+RVVCALL(OPIVX2_RM, vnclipu_wx_h, NOP_UUU_H, H2, H4, vnclipu16)
+RVVCALL(OPIVX2_RM, vnclipu_wx_w, NOP_UUU_W, H4, H8, vnclipu32)
+GEN_VEXT_VX_RM(vnclipu_wx_b, 1, 1, clearb)
+GEN_VEXT_VX_RM(vnclipu_wx_h, 2, 2, clearh)
+GEN_VEXT_VX_RM(vnclipu_wx_w, 4, 4, clearl)
/*
*** Vector Float Point Arithmetic Instructions
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 48/65] target/riscv: rvv-0.9: narrowing fixed-point clip instructions
@ 2020-07-10 10:49 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 24 ++++++------
target/riscv/insn32.decode | 12 +++---
target/riscv/insn_trans/trans_rvv.inc.c | 12 +++---
target/riscv/vector_helper.c | 52 ++++++++++++-------------
4 files changed, 50 insertions(+), 50 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index d2bf9be551..353a1b7868 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -768,18 +768,18 @@ DEF_HELPER_6(vssra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vssra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vssra_vx_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnclip_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnclip_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnclip_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnclipu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnclipu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnclipu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnclipu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnclipu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnclipu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnclip_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnclip_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnclip_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclip_wv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclip_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclip_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclipu_wv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclipu_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclipu_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclipu_wx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclipu_wx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclipu_wx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclip_wx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclip_wx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclip_wx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vfadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index ed34ccd0e3..dc3965c050 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -469,12 +469,12 @@ vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm
vssra_vv 101011 . ..... ..... 000 ..... 1010111 @r_vm
vssra_vx 101011 . ..... ..... 100 ..... 1010111 @r_vm
vssra_vi 101011 . ..... ..... 011 ..... 1010111 @r_vm
-vnclipu_vv 101110 . ..... ..... 000 ..... 1010111 @r_vm
-vnclipu_vx 101110 . ..... ..... 100 ..... 1010111 @r_vm
-vnclipu_vi 101110 . ..... ..... 011 ..... 1010111 @r_vm
-vnclip_vv 101111 . ..... ..... 000 ..... 1010111 @r_vm
-vnclip_vx 101111 . ..... ..... 100 ..... 1010111 @r_vm
-vnclip_vi 101111 . ..... ..... 011 ..... 1010111 @r_vm
+vnclipu_wv 101110 . ..... ..... 000 ..... 1010111 @r_vm
+vnclipu_wx 101110 . ..... ..... 100 ..... 1010111 @r_vm
+vnclipu_wi 101110 . ..... ..... 011 ..... 1010111 @r_vm
+vnclip_wv 101111 . ..... ..... 000 ..... 1010111 @r_vm
+vnclip_wx 101111 . ..... ..... 100 ..... 1010111 @r_vm
+vnclip_wi 101111 . ..... ..... 011 ..... 1010111 @r_vm
vfadd_vv 000000 . ..... ..... 001 ..... 1010111 @r_vm
vfadd_vf 000000 . ..... ..... 101 ..... 1010111 @r_vm
vfsub_vv 000010 . ..... ..... 001 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index f46cccc9bb..986f62dabc 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2188,12 +2188,12 @@ GEN_OPIVI_TRANS(vssrl_vi, 1, vssrl_vx, opivx_check)
GEN_OPIVI_TRANS(vssra_vi, 0, vssra_vx, opivx_check)
/* Vector Narrowing Fixed-Point Clip Instructions */
-GEN_OPIVV_NARROW_TRANS(vnclipu_vv)
-GEN_OPIVV_NARROW_TRANS(vnclip_vv)
-GEN_OPIVX_NARROW_TRANS(vnclipu_vx)
-GEN_OPIVX_NARROW_TRANS(vnclip_vx)
-GEN_OPIVI_NARROW_TRANS(vnclipu_vi, 1, vnclipu_vx)
-GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx)
+GEN_OPIWV_NARROW_TRANS(vnclipu_wv)
+GEN_OPIWV_NARROW_TRANS(vnclip_wv)
+GEN_OPIWX_NARROW_TRANS(vnclipu_wx)
+GEN_OPIWX_NARROW_TRANS(vnclip_wx)
+GEN_OPIWI_NARROW_TRANS(vnclipu_wi, 1, vnclipu_wx)
+GEN_OPIWI_NARROW_TRANS(vnclip_wi, 1, vnclip_wx)
/*
*** Vector Float Point Arithmetic Instructions
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index cf245e0145..035ccef9c3 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3310,19 +3310,19 @@ vnclip32(CPURISCVState *env, int vxrm, int64_t a, int32_t b)
}
}
-RVVCALL(OPIVV2_RM, vnclip_vv_b, NOP_SSS_B, H1, H2, H1, vnclip8)
-RVVCALL(OPIVV2_RM, vnclip_vv_h, NOP_SSS_H, H2, H4, H2, vnclip16)
-RVVCALL(OPIVV2_RM, vnclip_vv_w, NOP_SSS_W, H4, H8, H4, vnclip32)
-GEN_VEXT_VV_RM(vnclip_vv_b, 1, 1, clearb)
-GEN_VEXT_VV_RM(vnclip_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_RM(vnclip_vv_w, 4, 4, clearl)
-
-RVVCALL(OPIVX2_RM, vnclip_vx_b, NOP_SSS_B, H1, H2, vnclip8)
-RVVCALL(OPIVX2_RM, vnclip_vx_h, NOP_SSS_H, H2, H4, vnclip16)
-RVVCALL(OPIVX2_RM, vnclip_vx_w, NOP_SSS_W, H4, H8, vnclip32)
-GEN_VEXT_VX_RM(vnclip_vx_b, 1, 1, clearb)
-GEN_VEXT_VX_RM(vnclip_vx_h, 2, 2, clearh)
-GEN_VEXT_VX_RM(vnclip_vx_w, 4, 4, clearl)
+RVVCALL(OPIVV2_RM, vnclip_wv_b, NOP_SSS_B, H1, H2, H1, vnclip8)
+RVVCALL(OPIVV2_RM, vnclip_wv_h, NOP_SSS_H, H2, H4, H2, vnclip16)
+RVVCALL(OPIVV2_RM, vnclip_wv_w, NOP_SSS_W, H4, H8, H4, vnclip32)
+GEN_VEXT_VV_RM(vnclip_wv_b, 1, 1, clearb)
+GEN_VEXT_VV_RM(vnclip_wv_h, 2, 2, clearh)
+GEN_VEXT_VV_RM(vnclip_wv_w, 4, 4, clearl)
+
+RVVCALL(OPIVX2_RM, vnclip_wx_b, NOP_SSS_B, H1, H2, vnclip8)
+RVVCALL(OPIVX2_RM, vnclip_wx_h, NOP_SSS_H, H2, H4, vnclip16)
+RVVCALL(OPIVX2_RM, vnclip_wx_w, NOP_SSS_W, H4, H8, vnclip32)
+GEN_VEXT_VX_RM(vnclip_wx_b, 1, 1, clearb)
+GEN_VEXT_VX_RM(vnclip_wx_h, 2, 2, clearh)
+GEN_VEXT_VX_RM(vnclip_wx_w, 4, 4, clearl)
static inline uint8_t
vnclipu8(CPURISCVState *env, int vxrm, uint16_t a, uint8_t b)
@@ -3360,7 +3360,7 @@ static inline uint32_t
vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b)
{
uint8_t round, shift = b & 0x3f;
- int64_t res;
+ uint64_t res;
round = get_round(vxrm, a, shift);
res = (a >> shift) + round;
@@ -3372,19 +3372,19 @@ vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b)
}
}
-RVVCALL(OPIVV2_RM, vnclipu_vv_b, NOP_UUU_B, H1, H2, H1, vnclipu8)
-RVVCALL(OPIVV2_RM, vnclipu_vv_h, NOP_UUU_H, H2, H4, H2, vnclipu16)
-RVVCALL(OPIVV2_RM, vnclipu_vv_w, NOP_UUU_W, H4, H8, H4, vnclipu32)
-GEN_VEXT_VV_RM(vnclipu_vv_b, 1, 1, clearb)
-GEN_VEXT_VV_RM(vnclipu_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_RM(vnclipu_vv_w, 4, 4, clearl)
+RVVCALL(OPIVV2_RM, vnclipu_wv_b, NOP_UUU_B, H1, H2, H1, vnclipu8)
+RVVCALL(OPIVV2_RM, vnclipu_wv_h, NOP_UUU_H, H2, H4, H2, vnclipu16)
+RVVCALL(OPIVV2_RM, vnclipu_wv_w, NOP_UUU_W, H4, H8, H4, vnclipu32)
+GEN_VEXT_VV_RM(vnclipu_wv_b, 1, 1, clearb)
+GEN_VEXT_VV_RM(vnclipu_wv_h, 2, 2, clearh)
+GEN_VEXT_VV_RM(vnclipu_wv_w, 4, 4, clearl)
-RVVCALL(OPIVX2_RM, vnclipu_vx_b, NOP_UUU_B, H1, H2, vnclipu8)
-RVVCALL(OPIVX2_RM, vnclipu_vx_h, NOP_UUU_H, H2, H4, vnclipu16)
-RVVCALL(OPIVX2_RM, vnclipu_vx_w, NOP_UUU_W, H4, H8, vnclipu32)
-GEN_VEXT_VX_RM(vnclipu_vx_b, 1, 1, clearb)
-GEN_VEXT_VX_RM(vnclipu_vx_h, 2, 2, clearh)
-GEN_VEXT_VX_RM(vnclipu_vx_w, 4, 4, clearl)
+RVVCALL(OPIVX2_RM, vnclipu_wx_b, NOP_UUU_B, H1, H2, vnclipu8)
+RVVCALL(OPIVX2_RM, vnclipu_wx_h, NOP_UUU_H, H2, H4, vnclipu16)
+RVVCALL(OPIVX2_RM, vnclipu_wx_w, NOP_UUU_W, H4, H8, vnclipu32)
+GEN_VEXT_VX_RM(vnclipu_wx_b, 1, 1, clearb)
+GEN_VEXT_VX_RM(vnclipu_wx_h, 2, 2, clearh)
+GEN_VEXT_VX_RM(vnclipu_wx_w, 4, 4, clearl)
/*
*** Vector Float Point Arithmetic Instructions
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 49/65] target/riscv: rvv-0.9: floating-point move instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:49 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 57 ++++++++++++-------------
1 file changed, 28 insertions(+), 29 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 986f62dabc..264cd6509f 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2600,37 +2600,36 @@ GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check)
static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- (s->sew != 0)) {
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ require_align(a->rd, s->flmul);
+ require(s->sew != 0);
- if (s->vl_eq_vlmax) {
- tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
- MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]);
- } else {
- TCGv_ptr dest;
- TCGv_i32 desc;
- uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
- static gen_helper_vmv_vx * const fns[3] = {
- gen_helper_vmv_v_x_h,
- gen_helper_vmv_v_x_w,
- gen_helper_vmv_v_x_d,
- };
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-
- dest = tcg_temp_new_ptr();
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
- fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
-
- tcg_temp_free_ptr(dest);
- tcg_temp_free_i32(desc);
- gen_set_label(over);
- }
- return true;
+ if (s->vl_eq_vlmax) {
+ tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
+ MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]);
+ } else {
+ TCGv_ptr dest;
+ TCGv_i32 desc;
+ uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+ static gen_helper_vmv_vx * const fns[3] = {
+ gen_helper_vmv_v_x_h,
+ gen_helper_vmv_v_x_w,
+ gen_helper_vmv_v_x_d,
+ };
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ dest = tcg_temp_new_ptr();
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+ tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
+ fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
+
+ tcg_temp_free_ptr(dest);
+ tcg_temp_free_i32(desc);
+ gen_set_label(over);
}
- return false;
+ return true;
}
/* Single-Width Floating-Point/Integer Type-Convert Instructions */
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 49/65] target/riscv: rvv-0.9: floating-point move instructions
@ 2020-07-10 10:49 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 57 ++++++++++++-------------
1 file changed, 28 insertions(+), 29 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 986f62dabc..264cd6509f 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2600,37 +2600,36 @@ GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check)
static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- (s->sew != 0)) {
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ require_align(a->rd, s->flmul);
+ require(s->sew != 0);
- if (s->vl_eq_vlmax) {
- tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
- MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]);
- } else {
- TCGv_ptr dest;
- TCGv_i32 desc;
- uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
- static gen_helper_vmv_vx * const fns[3] = {
- gen_helper_vmv_v_x_h,
- gen_helper_vmv_v_x_w,
- gen_helper_vmv_v_x_d,
- };
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-
- dest = tcg_temp_new_ptr();
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
- fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
-
- tcg_temp_free_ptr(dest);
- tcg_temp_free_i32(desc);
- gen_set_label(over);
- }
- return true;
+ if (s->vl_eq_vlmax) {
+ tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
+ MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]);
+ } else {
+ TCGv_ptr dest;
+ TCGv_i32 desc;
+ uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+ static gen_helper_vmv_vx * const fns[3] = {
+ gen_helper_vmv_v_x_h,
+ gen_helper_vmv_v_x_w,
+ gen_helper_vmv_v_x_d,
+ };
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ dest = tcg_temp_new_ptr();
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+ tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
+ fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
+
+ tcg_temp_free_ptr(dest);
+ tcg_temp_free_i32(desc);
+ gen_set_label(over);
}
- return false;
+ return true;
}
/* Single-Width Floating-Point/Integer Type-Convert Instructions */
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 50/65] target/riscv: rvv-0.9: floating-point/integer type-convert instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:49 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 6 ++++
target/riscv/insn32.decode | 11 ++++---
target/riscv/insn_trans/trans_rvv.inc.c | 2 ++
target/riscv/vector_helper.c | 38 +++++++++++++++++++++++++
4 files changed, 53 insertions(+), 4 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 353a1b7868..caf335a703 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -994,6 +994,12 @@ DEF_HELPER_5(vfcvt_f_xu_v_d, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfcvt_f_x_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfcvt_f_x_v_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfcvt_rtz_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfcvt_rtz_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfcvt_rtz_xu_f_v_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfcvt_rtz_x_f_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfcvt_rtz_x_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfcvt_rtz_x_f_v_d, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index dc3965c050..e4b36af89e 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -547,10 +547,13 @@ vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm
vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm
vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
-vfcvt_xu_f_v 100010 . ..... 00000 001 ..... 1010111 @r2_vm
-vfcvt_x_f_v 100010 . ..... 00001 001 ..... 1010111 @r2_vm
-vfcvt_f_xu_v 100010 . ..... 00010 001 ..... 1010111 @r2_vm
-vfcvt_f_x_v 100010 . ..... 00011 001 ..... 1010111 @r2_vm
+
+vfcvt_xu_f_v 010010 . ..... 00000 001 ..... 1010111 @r2_vm
+vfcvt_x_f_v 010010 . ..... 00001 001 ..... 1010111 @r2_vm
+vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm
+vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm
+vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm
+vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm
vfwcvt_xu_f_v 100010 . ..... 01000 001 ..... 1010111 @r2_vm
vfwcvt_x_f_v 100010 . ..... 01001 001 ..... 1010111 @r2_vm
vfwcvt_f_xu_v 100010 . ..... 01010 001 ..... 1010111 @r2_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 264cd6509f..f022c5f5e8 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2637,6 +2637,8 @@ GEN_OPFV_TRANS(vfcvt_xu_f_v, opfv_check)
GEN_OPFV_TRANS(vfcvt_x_f_v, opfv_check)
GEN_OPFV_TRANS(vfcvt_f_xu_v, opfv_check)
GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check)
+GEN_OPFV_TRANS(vfcvt_rtz_xu_f_v, opfv_check)
+GEN_OPFV_TRANS(vfcvt_rtz_x_f_v, opfv_check)
/* Widening Floating-Point/Integer Type-Convert Instructions */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 035ccef9c3..0a8f62b4a9 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4473,6 +4473,44 @@ GEN_VEXT_V_ENV(vfcvt_f_x_v_h, 2, 2, clearh)
GEN_VEXT_V_ENV(vfcvt_f_x_v_w, 4, 4, clearl)
GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8, 8, clearq)
+#define FCVT_RTZ_F_V(STYPE, DTYPE) \
+static DTYPE##_t STYPE##_to_##DTYPE##_rtz(STYPE a, float_status * s) \
+{ \
+ signed char frm = s->float_rounding_mode; \
+ s->float_rounding_mode = float_round_to_zero; \
+ DTYPE##_t result = STYPE##_to_##DTYPE(a, s); \
+ s->float_rounding_mode = frm; \
+ return result; \
+}
+
+/*
+ * vfcvt.rtz.xu.f.v vd, vs2, vm
+ * Convert float to unsigned integer, truncating.
+ */
+FCVT_RTZ_F_V(float16, uint16)
+FCVT_RTZ_F_V(float32, uint32)
+FCVT_RTZ_F_V(float64, uint64)
+RVVCALL(OPFVV1, vfcvt_rtz_xu_f_v_h, OP_UU_H, H2, H2, float16_to_uint16_rtz)
+RVVCALL(OPFVV1, vfcvt_rtz_xu_f_v_w, OP_UU_W, H4, H4, float32_to_uint32_rtz)
+RVVCALL(OPFVV1, vfcvt_rtz_xu_f_v_d, OP_UU_D, H8, H8, float64_to_uint64_rtz)
+GEN_VEXT_V_ENV(vfcvt_rtz_xu_f_v_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfcvt_rtz_xu_f_v_w, 4, 4, clearl)
+GEN_VEXT_V_ENV(vfcvt_rtz_xu_f_v_d, 8, 8, clearq)
+
+/*
+ * vfcvt.rtz.x.f.v vd, vs2, vm
+ * Convert float to signed integer, truncating.
+ */
+FCVT_RTZ_F_V(float16, int16)
+FCVT_RTZ_F_V(float32, int32)
+FCVT_RTZ_F_V(float64, int64)
+RVVCALL(OPFVV1, vfcvt_rtz_x_f_v_h, OP_UU_H, H2, H2, float16_to_int16_rtz)
+RVVCALL(OPFVV1, vfcvt_rtz_x_f_v_w, OP_UU_W, H4, H4, float32_to_int32_rtz)
+RVVCALL(OPFVV1, vfcvt_rtz_x_f_v_d, OP_UU_D, H8, H8, float64_to_int64_rtz)
+GEN_VEXT_V_ENV(vfcvt_rtz_x_f_v_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfcvt_rtz_x_f_v_w, 4, 4, clearl)
+GEN_VEXT_V_ENV(vfcvt_rtz_x_f_v_d, 8, 8, clearq)
+
/* Widening Floating-Point/Integer Type-Convert Instructions */
/* (TD, T2, TX2) */
#define WOP_UU_H uint32_t, uint16_t, uint16_t
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 50/65] target/riscv: rvv-0.9: floating-point/integer type-convert instructions
@ 2020-07-10 10:49 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 6 ++++
target/riscv/insn32.decode | 11 ++++---
target/riscv/insn_trans/trans_rvv.inc.c | 2 ++
target/riscv/vector_helper.c | 38 +++++++++++++++++++++++++
4 files changed, 53 insertions(+), 4 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 353a1b7868..caf335a703 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -994,6 +994,12 @@ DEF_HELPER_5(vfcvt_f_xu_v_d, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfcvt_f_x_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfcvt_f_x_v_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfcvt_rtz_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfcvt_rtz_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfcvt_rtz_xu_f_v_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfcvt_rtz_x_f_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfcvt_rtz_x_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfcvt_rtz_x_f_v_d, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index dc3965c050..e4b36af89e 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -547,10 +547,13 @@ vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm
vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm
vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
-vfcvt_xu_f_v 100010 . ..... 00000 001 ..... 1010111 @r2_vm
-vfcvt_x_f_v 100010 . ..... 00001 001 ..... 1010111 @r2_vm
-vfcvt_f_xu_v 100010 . ..... 00010 001 ..... 1010111 @r2_vm
-vfcvt_f_x_v 100010 . ..... 00011 001 ..... 1010111 @r2_vm
+
+vfcvt_xu_f_v 010010 . ..... 00000 001 ..... 1010111 @r2_vm
+vfcvt_x_f_v 010010 . ..... 00001 001 ..... 1010111 @r2_vm
+vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm
+vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm
+vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm
+vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm
vfwcvt_xu_f_v 100010 . ..... 01000 001 ..... 1010111 @r2_vm
vfwcvt_x_f_v 100010 . ..... 01001 001 ..... 1010111 @r2_vm
vfwcvt_f_xu_v 100010 . ..... 01010 001 ..... 1010111 @r2_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 264cd6509f..f022c5f5e8 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2637,6 +2637,8 @@ GEN_OPFV_TRANS(vfcvt_xu_f_v, opfv_check)
GEN_OPFV_TRANS(vfcvt_x_f_v, opfv_check)
GEN_OPFV_TRANS(vfcvt_f_xu_v, opfv_check)
GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check)
+GEN_OPFV_TRANS(vfcvt_rtz_xu_f_v, opfv_check)
+GEN_OPFV_TRANS(vfcvt_rtz_x_f_v, opfv_check)
/* Widening Floating-Point/Integer Type-Convert Instructions */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 035ccef9c3..0a8f62b4a9 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4473,6 +4473,44 @@ GEN_VEXT_V_ENV(vfcvt_f_x_v_h, 2, 2, clearh)
GEN_VEXT_V_ENV(vfcvt_f_x_v_w, 4, 4, clearl)
GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8, 8, clearq)
+#define FCVT_RTZ_F_V(STYPE, DTYPE) \
+static DTYPE##_t STYPE##_to_##DTYPE##_rtz(STYPE a, float_status * s) \
+{ \
+ signed char frm = s->float_rounding_mode; \
+ s->float_rounding_mode = float_round_to_zero; \
+ DTYPE##_t result = STYPE##_to_##DTYPE(a, s); \
+ s->float_rounding_mode = frm; \
+ return result; \
+}
+
+/*
+ * vfcvt.rtz.xu.f.v vd, vs2, vm
+ * Convert float to unsigned integer, truncating.
+ */
+FCVT_RTZ_F_V(float16, uint16)
+FCVT_RTZ_F_V(float32, uint32)
+FCVT_RTZ_F_V(float64, uint64)
+RVVCALL(OPFVV1, vfcvt_rtz_xu_f_v_h, OP_UU_H, H2, H2, float16_to_uint16_rtz)
+RVVCALL(OPFVV1, vfcvt_rtz_xu_f_v_w, OP_UU_W, H4, H4, float32_to_uint32_rtz)
+RVVCALL(OPFVV1, vfcvt_rtz_xu_f_v_d, OP_UU_D, H8, H8, float64_to_uint64_rtz)
+GEN_VEXT_V_ENV(vfcvt_rtz_xu_f_v_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfcvt_rtz_xu_f_v_w, 4, 4, clearl)
+GEN_VEXT_V_ENV(vfcvt_rtz_xu_f_v_d, 8, 8, clearq)
+
+/*
+ * vfcvt.rtz.x.f.v vd, vs2, vm
+ * Convert float to signed integer, truncating.
+ */
+FCVT_RTZ_F_V(float16, int16)
+FCVT_RTZ_F_V(float32, int32)
+FCVT_RTZ_F_V(float64, int64)
+RVVCALL(OPFVV1, vfcvt_rtz_x_f_v_h, OP_UU_H, H2, H2, float16_to_int16_rtz)
+RVVCALL(OPFVV1, vfcvt_rtz_x_f_v_w, OP_UU_W, H4, H4, float32_to_int32_rtz)
+RVVCALL(OPFVV1, vfcvt_rtz_x_f_v_d, OP_UU_D, H8, H8, float64_to_int64_rtz)
+GEN_VEXT_V_ENV(vfcvt_rtz_x_f_v_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfcvt_rtz_x_f_v_w, 4, 4, clearl)
+GEN_VEXT_V_ENV(vfcvt_rtz_x_f_v_d, 8, 8, clearq)
+
/* Widening Floating-Point/Integer Type-Convert Instructions */
/* (TD, T2, TX2) */
#define WOP_UU_H uint32_t, uint16_t, uint16_t
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 51/65] target/riscv: rvv-0.9: single-width floating-point reduction
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:49 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 3 +
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvv.inc.c | 1 +
target/riscv/vector_helper.c | 144 +++++++++++++++++++-----
4 files changed, 120 insertions(+), 31 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index caf335a703..e1dc1f83d3 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1066,6 +1066,9 @@ DEF_HELPER_6(vwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredsum_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfredosum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfredosum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfredosum_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredmax_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredmax_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredmax_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e4b36af89e..0fe46c10c2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -575,7 +575,8 @@ vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm
vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm
vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm
# Vector ordered and unordered reduction sum
-vfredsum_vs 0000-1 . ..... ..... 001 ..... 1010111 @r_vm
+vfredsum_vs 000001 . ..... ..... 001 ..... 1010111 @r_vm
+vfredosum_vs 000011 . ..... ..... 001 ..... 1010111 @r_vm
vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm
vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm
# Vector widening ordered and unordered float reduction sum
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index f022c5f5e8..f308b2bc3b 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2773,6 +2773,7 @@ GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check)
/* Vector Single-Width Floating-Point Reduction Instructions */
GEN_OPFVV_TRANS(vfredsum_vs, reduction_check)
+GEN_OPFVV_TRANS(vfredosum_vs, reduction_check)
GEN_OPFVV_TRANS(vfredmax_vs, reduction_check)
GEN_OPFVV_TRANS(vfredmin_vs, reduction_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 0a8f62b4a9..76ce3c8e3e 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4675,43 +4675,127 @@ GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD)
GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD)
/* Vector Single-Width Floating-Point Reduction Instructions */
-#define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, OP, CLEAR_FN)\
-void HELPER(NAME)(void *vd, void *v0, void *vs1, \
- void *vs2, CPURISCVState *env, \
- uint32_t desc) \
-{ \
- uint32_t vm = vext_vm(desc); \
- uint32_t vta = vext_vta(desc); \
- uint32_t vl = env->vl; \
- uint32_t i; \
- uint32_t tot = env_archcpu(env)->cfg.vlen / 8; \
- TD s1 = *((TD *)vs1 + HD(0)); \
- \
- for (i = 0; i < vl; i++) { \
- TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
- if (!vm && !vext_elem_mask(v0, i)) { \
- continue; \
- } \
- s1 = OP(s1, (TD)s2, &env->fp_status); \
- } \
- *((TD *)vd + HD(0)) = s1; \
- CLEAR_FN(vd, vta, 1, sizeof(TD), tot); \
+
+/*
+ * If f is NaN, canonicalize NaN f.
+ * Set the invalid exception flag if f is a sNaN.
+ */
+static uint64_t propagate_nan(uint64_t f, uint32_t sew, float_status * s)
+{
+ target_ulong ret;
+
+ switch (sew) {
+ case 16:
+ ret = fclass_h(f);
+ /* check if f is NaN */
+ if (ret & 0x300) {
+ /* check if f is a sNaN */
+ if (ret & 0x100) {
+ s->float_exception_flags |= float_flag_invalid;
+ }
+ /* canonicalize NaN */
+ return float16_default_nan(s);
+ } else {
+ return f;
+ }
+ break;
+ case 32:
+ ret = fclass_s(f);
+ /* check if f is NaN */
+ if (ret & 0x300) {
+ /* check if f is a sNaN */
+ if (ret & 0x100) {
+ s->float_exception_flags |= float_flag_invalid;
+ }
+ /* canonicalize NaN */
+ return float32_default_nan(s);
+ } else {
+ return f;
+ }
+ break;
+ case 64:
+ ret = fclass_d(f);
+ /* check if f is NaN */
+ if (ret & 0x300) {
+ /* check if f is a sNaN */
+ if (ret & 0x100) {
+ s->float_exception_flags |= float_flag_invalid;
+ }
+ /* canonicalize NaN */
+ return float64_default_nan(s);
+ } else {
+ return f;
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
}
+#define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, PROPAGATE_NAN, OP, CLEAR_FN) \
+void HELPER(NAME)(void *vd, void *v0, void *vs1, \
+ void *vs2, CPURISCVState *env, \
+ uint32_t desc) \
+{ \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t i; \
+ uint32_t tot = env_archcpu(env)->cfg.vlen / 8; \
+ bool active = false; \
+ TD s1 = *((TD *)vs1 + HD(0)); \
+ \
+ for (i = 0; i < vl; i++) { \
+ TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ continue; \
+ } \
+ active = true; \
+ s1 = OP(s1, (TD)s2, &env->fp_status); \
+ } \
+ \
+ if (vl > 0) { \
+ if (PROPAGATE_NAN && !active) { \
+ *((TD *)vd + HD(0)) = propagate_nan(s1, sizeof(TD) * 8, \
+ &env->fp_status); \
+ } else { \
+ *((TD *)vd + HD(0)) = s1; \
+ } \
+ } \
+ CLEAR_FN(vd, vta, 1, sizeof(TD), tot); \
+}
+
+/* Ordered sum */
+GEN_VEXT_FRED(vfredosum_vs_h, uint16_t, uint16_t, H2, H2, false,
+ float16_add, clearh)
+GEN_VEXT_FRED(vfredosum_vs_w, uint32_t, uint32_t, H4, H4, false,
+ float32_add, clearl)
+GEN_VEXT_FRED(vfredosum_vs_d, uint64_t, uint64_t, H8, H8, false,
+ float64_add, clearq)
+
/* Unordered sum */
-GEN_VEXT_FRED(vfredsum_vs_h, uint16_t, uint16_t, H2, H2, float16_add, clearh)
-GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, float32_add, clearl)
-GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add, clearq)
+GEN_VEXT_FRED(vfredsum_vs_h, uint16_t, uint16_t, H2, H2, true,
+ float16_add, clearh)
+GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, true,
+ float32_add, clearl)
+GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, true,
+ float64_add, clearq)
/* Maximum value */
-GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maxnum, clearh)
-GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maxnum, clearl)
-GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maxnum, clearq)
+GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, false,
+ float16_maxnum_noprop, clearh)
+GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, false,
+ float32_maxnum_noprop, clearl)
+GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, false,
+ float64_maxnum_noprop, clearq)
/* Minimum value */
-GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum, clearh)
-GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum, clearl)
-GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum, clearq)
+GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, false,
+ float16_minnum_noprop, clearh)
+GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, false,
+ float32_minnum_noprop, clearl)
+GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, false,
+ float64_minnum_noprop, clearq)
/* Vector Widening Floating-Point Reduction Instructions */
/* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 51/65] target/riscv: rvv-0.9: single-width floating-point reduction
@ 2020-07-10 10:49 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 3 +
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvv.inc.c | 1 +
target/riscv/vector_helper.c | 144 +++++++++++++++++++-----
4 files changed, 120 insertions(+), 31 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index caf335a703..e1dc1f83d3 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1066,6 +1066,9 @@ DEF_HELPER_6(vwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredsum_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfredosum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfredosum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfredosum_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredmax_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredmax_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredmax_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e4b36af89e..0fe46c10c2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -575,7 +575,8 @@ vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm
vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm
vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm
# Vector ordered and unordered reduction sum
-vfredsum_vs 0000-1 . ..... ..... 001 ..... 1010111 @r_vm
+vfredsum_vs 000001 . ..... ..... 001 ..... 1010111 @r_vm
+vfredosum_vs 000011 . ..... ..... 001 ..... 1010111 @r_vm
vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm
vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm
# Vector widening ordered and unordered float reduction sum
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index f022c5f5e8..f308b2bc3b 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2773,6 +2773,7 @@ GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check)
/* Vector Single-Width Floating-Point Reduction Instructions */
GEN_OPFVV_TRANS(vfredsum_vs, reduction_check)
+GEN_OPFVV_TRANS(vfredosum_vs, reduction_check)
GEN_OPFVV_TRANS(vfredmax_vs, reduction_check)
GEN_OPFVV_TRANS(vfredmin_vs, reduction_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 0a8f62b4a9..76ce3c8e3e 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4675,43 +4675,127 @@ GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD)
GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD)
/* Vector Single-Width Floating-Point Reduction Instructions */
-#define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, OP, CLEAR_FN)\
-void HELPER(NAME)(void *vd, void *v0, void *vs1, \
- void *vs2, CPURISCVState *env, \
- uint32_t desc) \
-{ \
- uint32_t vm = vext_vm(desc); \
- uint32_t vta = vext_vta(desc); \
- uint32_t vl = env->vl; \
- uint32_t i; \
- uint32_t tot = env_archcpu(env)->cfg.vlen / 8; \
- TD s1 = *((TD *)vs1 + HD(0)); \
- \
- for (i = 0; i < vl; i++) { \
- TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
- if (!vm && !vext_elem_mask(v0, i)) { \
- continue; \
- } \
- s1 = OP(s1, (TD)s2, &env->fp_status); \
- } \
- *((TD *)vd + HD(0)) = s1; \
- CLEAR_FN(vd, vta, 1, sizeof(TD), tot); \
+
+/*
+ * If f is NaN, canonicalize NaN f.
+ * Set the invalid exception flag if f is a sNaN.
+ */
+static uint64_t propagate_nan(uint64_t f, uint32_t sew, float_status * s)
+{
+ target_ulong ret;
+
+ switch (sew) {
+ case 16:
+ ret = fclass_h(f);
+ /* check if f is NaN */
+ if (ret & 0x300) {
+ /* check if f is a sNaN */
+ if (ret & 0x100) {
+ s->float_exception_flags |= float_flag_invalid;
+ }
+ /* canonicalize NaN */
+ return float16_default_nan(s);
+ } else {
+ return f;
+ }
+ break;
+ case 32:
+ ret = fclass_s(f);
+ /* check if f is NaN */
+ if (ret & 0x300) {
+ /* check if f is a sNaN */
+ if (ret & 0x100) {
+ s->float_exception_flags |= float_flag_invalid;
+ }
+ /* canonicalize NaN */
+ return float32_default_nan(s);
+ } else {
+ return f;
+ }
+ break;
+ case 64:
+ ret = fclass_d(f);
+ /* check if f is NaN */
+ if (ret & 0x300) {
+ /* check if f is a sNaN */
+ if (ret & 0x100) {
+ s->float_exception_flags |= float_flag_invalid;
+ }
+ /* canonicalize NaN */
+ return float64_default_nan(s);
+ } else {
+ return f;
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
}
+#define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, PROPAGATE_NAN, OP, CLEAR_FN) \
+void HELPER(NAME)(void *vd, void *v0, void *vs1, \
+ void *vs2, CPURISCVState *env, \
+ uint32_t desc) \
+{ \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t i; \
+ uint32_t tot = env_archcpu(env)->cfg.vlen / 8; \
+ bool active = false; \
+ TD s1 = *((TD *)vs1 + HD(0)); \
+ \
+ for (i = 0; i < vl; i++) { \
+ TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ continue; \
+ } \
+ active = true; \
+ s1 = OP(s1, (TD)s2, &env->fp_status); \
+ } \
+ \
+ if (vl > 0) { \
+ if (PROPAGATE_NAN && !active) { \
+ *((TD *)vd + HD(0)) = propagate_nan(s1, sizeof(TD) * 8, \
+ &env->fp_status); \
+ } else { \
+ *((TD *)vd + HD(0)) = s1; \
+ } \
+ } \
+ CLEAR_FN(vd, vta, 1, sizeof(TD), tot); \
+}
+
+/* Ordered sum */
+GEN_VEXT_FRED(vfredosum_vs_h, uint16_t, uint16_t, H2, H2, false,
+ float16_add, clearh)
+GEN_VEXT_FRED(vfredosum_vs_w, uint32_t, uint32_t, H4, H4, false,
+ float32_add, clearl)
+GEN_VEXT_FRED(vfredosum_vs_d, uint64_t, uint64_t, H8, H8, false,
+ float64_add, clearq)
+
/* Unordered sum */
-GEN_VEXT_FRED(vfredsum_vs_h, uint16_t, uint16_t, H2, H2, float16_add, clearh)
-GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, float32_add, clearl)
-GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add, clearq)
+GEN_VEXT_FRED(vfredsum_vs_h, uint16_t, uint16_t, H2, H2, true,
+ float16_add, clearh)
+GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, true,
+ float32_add, clearl)
+GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, true,
+ float64_add, clearq)
/* Maximum value */
-GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maxnum, clearh)
-GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maxnum, clearl)
-GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maxnum, clearq)
+GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, false,
+ float16_maxnum_noprop, clearh)
+GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, false,
+ float32_maxnum_noprop, clearl)
+GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, false,
+ float64_maxnum_noprop, clearq)
/* Minimum value */
-GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum, clearh)
-GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum, clearl)
-GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum, clearq)
+GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, false,
+ float16_minnum_noprop, clearh)
+GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, false,
+ float32_minnum_noprop, clearl)
+GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, false,
+ float64_minnum_noprop, clearq)
/* Vector Widening Floating-Point Reduction Instructions */
/* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 52/65] target/riscv: rvv-0.9: widening floating-point reduction instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:49 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 2 +
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvv.inc.c | 3 +-
target/riscv/vector_helper.c | 67 ++++++++++++++++++++++++-
4 files changed, 71 insertions(+), 4 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index e1dc1f83d3..1c301c1440 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1078,6 +1078,8 @@ DEF_HELPER_6(vfredmin_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwredosum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwredosum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmand_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmnand_mm, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0fe46c10c2..e32946b1f5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -580,7 +580,8 @@ vfredosum_vs 000011 . ..... ..... 001 ..... 1010111 @r_vm
vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm
vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm
# Vector widening ordered and unordered float reduction sum
-vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm
+vfwredsum_vs 110001 . ..... ..... 001 ..... 1010111 @r_vm
+vfwredosum_vs 110011 . ..... ..... 001 ..... 1010111 @r_vm
vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r
vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r
vmandnot_mm 011000 - ..... ..... 010 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index f308b2bc3b..34b0392625 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2778,7 +2778,8 @@ GEN_OPFVV_TRANS(vfredmax_vs, reduction_check)
GEN_OPFVV_TRANS(vfredmin_vs, reduction_check)
/* Vector Widening Floating-Point Reduction Instructions */
-GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
+GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_widen_check)
+GEN_OPFVV_WIDEN_TRANS(vfwredosum_vs, reduction_widen_check)
/*
*** Vector Mask Operations
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 76ce3c8e3e..67d5fd37aa 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4798,6 +4798,51 @@ GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, false,
float64_minnum_noprop, clearq)
/* Vector Widening Floating-Point Reduction Instructions */
+/* Ordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
+void HELPER(vfwredosum_vs_h)(void *vd, void *v0, void *vs1,
+ void *vs2, CPURISCVState *env, uint32_t desc)
+{
+ uint32_t vm = vext_vm(desc);
+ uint32_t vta = vext_vta(desc);
+ uint32_t vl = env->vl;
+ uint32_t i;
+ uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
+ uint32_t s1 = *((uint32_t *)vs1 + H4(0));
+
+ for (i = 0; i < vl; i++) {
+ uint16_t s2 = *((uint16_t *)vs2 + H2(i));
+ if (!vm && !vext_elem_mask(v0, i)) {
+ continue;
+ }
+ s1 = float32_add(s1, float16_to_float32(s2, true, &env->fp_status),
+ &env->fp_status);
+ }
+ *((uint32_t *)vd + H4(0)) = s1;
+ clearl(vd, vta, 1, sizeof(uint32_t), tot);
+}
+
+void HELPER(vfwredosum_vs_w)(void *vd, void *v0, void *vs1,
+ void *vs2, CPURISCVState *env, uint32_t desc)
+{
+ uint32_t vm = vext_vm(desc);
+ uint32_t vta = vext_vta(desc);
+ uint32_t vl = env->vl;
+ uint32_t i;
+ uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
+ uint64_t s1 = *((uint64_t *)vs1);
+
+ for (i = 0; i < vl; i++) {
+ uint32_t s2 = *((uint32_t *)vs2 + H4(i));
+ if (!vm && !vext_elem_mask(v0, i)) {
+ continue;
+ }
+ s1 = float64_add(s1, float32_to_float64(s2, &env->fp_status),
+ &env->fp_status);
+ }
+ *((uint64_t *)vd) = s1;
+ clearq(vd, vta, 1, sizeof(uint64_t), tot);
+}
+
/* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
void *vs2, CPURISCVState *env, uint32_t desc)
@@ -4808,16 +4853,25 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
uint32_t i;
uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
uint32_t s1 = *((uint32_t *)vs1 + H4(0));
+ bool active = false; \
for (i = 0; i < vl; i++) {
uint16_t s2 = *((uint16_t *)vs2 + H2(i));
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
+ active = true;
s1 = float32_add(s1, float16_to_float32(s2, true, &env->fp_status),
&env->fp_status);
}
- *((uint32_t *)vd + H4(0)) = s1;
+
+ if (vl > 0) {
+ if (!active) {
+ *((uint32_t *)vd + H4(0)) = propagate_nan(s1, 32, &env->fp_status);
+ } else {
+ *((uint32_t *)vd + H4(0)) = s1;
+ }
+ }
clearl(vd, vta, 1, sizeof(uint32_t), tot);
}
@@ -4830,16 +4884,25 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
uint32_t i;
uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
uint64_t s1 = *((uint64_t *)vs1);
+ bool active = false; \
for (i = 0; i < vl; i++) {
uint32_t s2 = *((uint32_t *)vs2 + H4(i));
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
+ active = true;
s1 = float64_add(s1, float32_to_float64(s2, &env->fp_status),
&env->fp_status);
}
- *((uint64_t *)vd) = s1;
+
+ if (vl > 0) {
+ if (!active) {
+ *((uint64_t *)vd) = propagate_nan(s1, 64, &env->fp_status);
+ } else {
+ *((uint64_t *)vd) = s1;
+ }
+ }
clearq(vd, vta, 1, sizeof(uint64_t), tot);
}
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 52/65] target/riscv: rvv-0.9: widening floating-point reduction instructions
@ 2020-07-10 10:49 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 2 +
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvv.inc.c | 3 +-
target/riscv/vector_helper.c | 67 ++++++++++++++++++++++++-
4 files changed, 71 insertions(+), 4 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index e1dc1f83d3..1c301c1440 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1078,6 +1078,8 @@ DEF_HELPER_6(vfredmin_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwredosum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwredosum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmand_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmnand_mm, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0fe46c10c2..e32946b1f5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -580,7 +580,8 @@ vfredosum_vs 000011 . ..... ..... 001 ..... 1010111 @r_vm
vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm
vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm
# Vector widening ordered and unordered float reduction sum
-vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm
+vfwredsum_vs 110001 . ..... ..... 001 ..... 1010111 @r_vm
+vfwredosum_vs 110011 . ..... ..... 001 ..... 1010111 @r_vm
vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r
vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r
vmandnot_mm 011000 - ..... ..... 010 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index f308b2bc3b..34b0392625 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2778,7 +2778,8 @@ GEN_OPFVV_TRANS(vfredmax_vs, reduction_check)
GEN_OPFVV_TRANS(vfredmin_vs, reduction_check)
/* Vector Widening Floating-Point Reduction Instructions */
-GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
+GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_widen_check)
+GEN_OPFVV_WIDEN_TRANS(vfwredosum_vs, reduction_widen_check)
/*
*** Vector Mask Operations
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 76ce3c8e3e..67d5fd37aa 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4798,6 +4798,51 @@ GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, false,
float64_minnum_noprop, clearq)
/* Vector Widening Floating-Point Reduction Instructions */
+/* Ordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
+void HELPER(vfwredosum_vs_h)(void *vd, void *v0, void *vs1,
+ void *vs2, CPURISCVState *env, uint32_t desc)
+{
+ uint32_t vm = vext_vm(desc);
+ uint32_t vta = vext_vta(desc);
+ uint32_t vl = env->vl;
+ uint32_t i;
+ uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
+ uint32_t s1 = *((uint32_t *)vs1 + H4(0));
+
+ for (i = 0; i < vl; i++) {
+ uint16_t s2 = *((uint16_t *)vs2 + H2(i));
+ if (!vm && !vext_elem_mask(v0, i)) {
+ continue;
+ }
+ s1 = float32_add(s1, float16_to_float32(s2, true, &env->fp_status),
+ &env->fp_status);
+ }
+ *((uint32_t *)vd + H4(0)) = s1;
+ clearl(vd, vta, 1, sizeof(uint32_t), tot);
+}
+
+void HELPER(vfwredosum_vs_w)(void *vd, void *v0, void *vs1,
+ void *vs2, CPURISCVState *env, uint32_t desc)
+{
+ uint32_t vm = vext_vm(desc);
+ uint32_t vta = vext_vta(desc);
+ uint32_t vl = env->vl;
+ uint32_t i;
+ uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
+ uint64_t s1 = *((uint64_t *)vs1);
+
+ for (i = 0; i < vl; i++) {
+ uint32_t s2 = *((uint32_t *)vs2 + H4(i));
+ if (!vm && !vext_elem_mask(v0, i)) {
+ continue;
+ }
+ s1 = float64_add(s1, float32_to_float64(s2, &env->fp_status),
+ &env->fp_status);
+ }
+ *((uint64_t *)vd) = s1;
+ clearq(vd, vta, 1, sizeof(uint64_t), tot);
+}
+
/* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
void *vs2, CPURISCVState *env, uint32_t desc)
@@ -4808,16 +4853,25 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
uint32_t i;
uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
uint32_t s1 = *((uint32_t *)vs1 + H4(0));
+ bool active = false; \
for (i = 0; i < vl; i++) {
uint16_t s2 = *((uint16_t *)vs2 + H2(i));
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
+ active = true;
s1 = float32_add(s1, float16_to_float32(s2, true, &env->fp_status),
&env->fp_status);
}
- *((uint32_t *)vd + H4(0)) = s1;
+
+ if (vl > 0) {
+ if (!active) {
+ *((uint32_t *)vd + H4(0)) = propagate_nan(s1, 32, &env->fp_status);
+ } else {
+ *((uint32_t *)vd + H4(0)) = s1;
+ }
+ }
clearl(vd, vta, 1, sizeof(uint32_t), tot);
}
@@ -4830,16 +4884,25 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
uint32_t i;
uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
uint64_t s1 = *((uint64_t *)vs1);
+ bool active = false; \
for (i = 0; i < vl; i++) {
uint32_t s2 = *((uint32_t *)vs2 + H4(i));
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
+ active = true;
s1 = float64_add(s1, float32_to_float64(s2, &env->fp_status),
&env->fp_status);
}
- *((uint64_t *)vd) = s1;
+
+ if (vl > 0) {
+ if (!active) {
+ *((uint64_t *)vd) = propagate_nan(s1, 64, &env->fp_status);
+ } else {
+ *((uint64_t *)vd) = s1;
+ }
+ }
clearq(vd, vta, 1, sizeof(uint64_t), tot);
}
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 53/65] target/riscv: rvv-0.9: single-width scaling shift instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:49 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Zero-extend vssra.vi immediate value.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 34b0392625..5fa1f0c6ed 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2185,7 +2185,7 @@ GEN_OPIVV_TRANS(vssra_vv, opivv_check)
GEN_OPIVX_TRANS(vssrl_vx, opivx_check)
GEN_OPIVX_TRANS(vssra_vx, opivx_check)
GEN_OPIVI_TRANS(vssrl_vi, 1, vssrl_vx, opivx_check)
-GEN_OPIVI_TRANS(vssra_vi, 0, vssra_vx, opivx_check)
+GEN_OPIVI_TRANS(vssra_vi, 1, vssra_vx, opivx_check)
/* Vector Narrowing Fixed-Point Clip Instructions */
GEN_OPIWV_NARROW_TRANS(vnclipu_wv)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 53/65] target/riscv: rvv-0.9: single-width scaling shift instructions
@ 2020-07-10 10:49 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Zero-extend vssra.vi immediate value.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 34b0392625..5fa1f0c6ed 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2185,7 +2185,7 @@ GEN_OPIVV_TRANS(vssra_vv, opivv_check)
GEN_OPIVX_TRANS(vssrl_vx, opivx_check)
GEN_OPIVX_TRANS(vssra_vx, opivx_check)
GEN_OPIVI_TRANS(vssrl_vi, 1, vssrl_vx, opivx_check)
-GEN_OPIVI_TRANS(vssra_vi, 0, vssra_vx, opivx_check)
+GEN_OPIVI_TRANS(vssra_vi, 1, vssra_vx, opivx_check)
/* Vector Narrowing Fixed-Point Clip Instructions */
GEN_OPIWV_NARROW_TRANS(vnclipu_wv)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 54/65] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:49 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 22 ---
target/riscv/insn32.decode | 7 -
target/riscv/insn_trans/trans_rvv.inc.c | 9 --
target/riscv/vector_helper.c | 205 ------------------------
4 files changed, 243 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 1c301c1440..b56342f333 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -729,28 +729,6 @@ DEF_HELPER_6(vsmul_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsmul_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsmul_vx_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmaccu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmaccu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmacc_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmaccsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmaccsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmaccsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmaccu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmacc_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmacc_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmacc_vx_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccsu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccsu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccsu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32)
-
DEF_HELPER_6(vssrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vssrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vssrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e32946b1f5..2be673c2c7 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -456,13 +456,6 @@ vasubu_vv 001010 . ..... ..... 010 ..... 1010111 @r_vm
vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm
vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm
vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm
-vwsmaccu_vv 111100 . ..... ..... 000 ..... 1010111 @r_vm
-vwsmaccu_vx 111100 . ..... ..... 100 ..... 1010111 @r_vm
-vwsmacc_vv 111101 . ..... ..... 000 ..... 1010111 @r_vm
-vwsmacc_vx 111101 . ..... ..... 100 ..... 1010111 @r_vm
-vwsmaccsu_vv 111110 . ..... ..... 000 ..... 1010111 @r_vm
-vwsmaccsu_vx 111110 . ..... ..... 100 ..... 1010111 @r_vm
-vwsmaccus_vx 111111 . ..... ..... 100 ..... 1010111 @r_vm
vssrl_vv 101010 . ..... ..... 000 ..... 1010111 @r_vm
vssrl_vx 101010 . ..... ..... 100 ..... 1010111 @r_vm
vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 5fa1f0c6ed..6481fa7465 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2170,15 +2170,6 @@ GEN_OPIVX_TRANS(vasubu_vx, opivx_check)
GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
GEN_OPIVX_TRANS(vsmul_vx, opivx_check)
-/* Vector Widening Saturating Scaled Multiply-Add */
-GEN_OPIVV_WIDEN_TRANS(vwsmaccu_vv, opivv_widen_check)
-GEN_OPIVV_WIDEN_TRANS(vwsmacc_vv, opivv_widen_check)
-GEN_OPIVV_WIDEN_TRANS(vwsmaccsu_vv, opivv_widen_check)
-GEN_OPIVX_WIDEN_TRANS(vwsmaccu_vx)
-GEN_OPIVX_WIDEN_TRANS(vwsmacc_vx)
-GEN_OPIVX_WIDEN_TRANS(vwsmaccsu_vx)
-GEN_OPIVX_WIDEN_TRANS(vwsmaccus_vx)
-
/* Vector Single-Width Scaling Shift Instructions */
GEN_OPIVV_TRANS(vssrl_vv, opivv_check)
GEN_OPIVV_TRANS(vssra_vv, opivv_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 67d5fd37aa..41faa3592e 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2929,211 +2929,6 @@ GEN_VEXT_VX_RM(vsmul_vx_h, 2, 2, clearh)
GEN_VEXT_VX_RM(vsmul_vx_w, 4, 4, clearl)
GEN_VEXT_VX_RM(vsmul_vx_d, 8, 8, clearq)
-/* Vector Widening Saturating Scaled Multiply-Add */
-static inline uint16_t
-vwsmaccu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b,
- uint16_t c)
-{
- uint8_t round;
- uint16_t res = (uint16_t)a * b;
-
- round = get_round(vxrm, res, 4);
- res = (res >> 4) + round;
- return saddu16(env, vxrm, c, res);
-}
-
-static inline uint32_t
-vwsmaccu16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b,
- uint32_t c)
-{
- uint8_t round;
- uint32_t res = (uint32_t)a * b;
-
- round = get_round(vxrm, res, 8);
- res = (res >> 8) + round;
- return saddu32(env, vxrm, c, res);
-}
-
-static inline uint64_t
-vwsmaccu32(CPURISCVState *env, int vxrm, uint32_t a, uint32_t b,
- uint64_t c)
-{
- uint8_t round;
- uint64_t res = (uint64_t)a * b;
-
- round = get_round(vxrm, res, 16);
- res = (res >> 16) + round;
- return saddu64(env, vxrm, c, res);
-}
-
-#define OPIVV3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
-static inline void \
-do_##NAME(void *vd, void *vs1, void *vs2, int i, \
- CPURISCVState *env, int vxrm) \
-{ \
- TX1 s1 = *((T1 *)vs1 + HS1(i)); \
- TX2 s2 = *((T2 *)vs2 + HS2(i)); \
- TD d = *((TD *)vd + HD(i)); \
- *((TD *)vd + HD(i)) = OP(env, vxrm, s2, s1, d); \
-}
-
-RVVCALL(OPIVV3_RM, vwsmaccu_vv_b, WOP_UUU_B, H2, H1, H1, vwsmaccu8)
-RVVCALL(OPIVV3_RM, vwsmaccu_vv_h, WOP_UUU_H, H4, H2, H2, vwsmaccu16)
-RVVCALL(OPIVV3_RM, vwsmaccu_vv_w, WOP_UUU_W, H8, H4, H4, vwsmaccu32)
-GEN_VEXT_VV_RM(vwsmaccu_vv_b, 1, 2, clearh)
-GEN_VEXT_VV_RM(vwsmaccu_vv_h, 2, 4, clearl)
-GEN_VEXT_VV_RM(vwsmaccu_vv_w, 4, 8, clearq)
-
-#define OPIVX3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
-static inline void \
-do_##NAME(void *vd, target_long s1, void *vs2, int i, \
- CPURISCVState *env, int vxrm) \
-{ \
- TX2 s2 = *((T2 *)vs2 + HS2(i)); \
- TD d = *((TD *)vd + HD(i)); \
- *((TD *)vd + HD(i)) = OP(env, vxrm, s2, (TX1)(T1)s1, d); \
-}
-
-RVVCALL(OPIVX3_RM, vwsmaccu_vx_b, WOP_UUU_B, H2, H1, vwsmaccu8)
-RVVCALL(OPIVX3_RM, vwsmaccu_vx_h, WOP_UUU_H, H4, H2, vwsmaccu16)
-RVVCALL(OPIVX3_RM, vwsmaccu_vx_w, WOP_UUU_W, H8, H4, vwsmaccu32)
-GEN_VEXT_VX_RM(vwsmaccu_vx_b, 1, 2, clearh)
-GEN_VEXT_VX_RM(vwsmaccu_vx_h, 2, 4, clearl)
-GEN_VEXT_VX_RM(vwsmaccu_vx_w, 4, 8, clearq)
-
-static inline int16_t
-vwsmacc8(CPURISCVState *env, int vxrm, int8_t a, int8_t b, int16_t c)
-{
- uint8_t round;
- int16_t res = (int16_t)a * b;
-
- round = get_round(vxrm, res, 4);
- res = (res >> 4) + round;
- return sadd16(env, vxrm, c, res);
-}
-
-static inline int32_t
-vwsmacc16(CPURISCVState *env, int vxrm, int16_t a, int16_t b, int32_t c)
-{
- uint8_t round;
- int32_t res = (int32_t)a * b;
-
- round = get_round(vxrm, res, 8);
- res = (res >> 8) + round;
- return sadd32(env, vxrm, c, res);
-
-}
-
-static inline int64_t
-vwsmacc32(CPURISCVState *env, int vxrm, int32_t a, int32_t b, int64_t c)
-{
- uint8_t round;
- int64_t res = (int64_t)a * b;
-
- round = get_round(vxrm, res, 16);
- res = (res >> 16) + round;
- return sadd64(env, vxrm, c, res);
-}
-
-RVVCALL(OPIVV3_RM, vwsmacc_vv_b, WOP_SSS_B, H2, H1, H1, vwsmacc8)
-RVVCALL(OPIVV3_RM, vwsmacc_vv_h, WOP_SSS_H, H4, H2, H2, vwsmacc16)
-RVVCALL(OPIVV3_RM, vwsmacc_vv_w, WOP_SSS_W, H8, H4, H4, vwsmacc32)
-GEN_VEXT_VV_RM(vwsmacc_vv_b, 1, 2, clearh)
-GEN_VEXT_VV_RM(vwsmacc_vv_h, 2, 4, clearl)
-GEN_VEXT_VV_RM(vwsmacc_vv_w, 4, 8, clearq)
-RVVCALL(OPIVX3_RM, vwsmacc_vx_b, WOP_SSS_B, H2, H1, vwsmacc8)
-RVVCALL(OPIVX3_RM, vwsmacc_vx_h, WOP_SSS_H, H4, H2, vwsmacc16)
-RVVCALL(OPIVX3_RM, vwsmacc_vx_w, WOP_SSS_W, H8, H4, vwsmacc32)
-GEN_VEXT_VX_RM(vwsmacc_vx_b, 1, 2, clearh)
-GEN_VEXT_VX_RM(vwsmacc_vx_h, 2, 4, clearl)
-GEN_VEXT_VX_RM(vwsmacc_vx_w, 4, 8, clearq)
-
-static inline int16_t
-vwsmaccsu8(CPURISCVState *env, int vxrm, uint8_t a, int8_t b, int16_t c)
-{
- uint8_t round;
- int16_t res = a * (int16_t)b;
-
- round = get_round(vxrm, res, 4);
- res = (res >> 4) + round;
- return ssub16(env, vxrm, c, res);
-}
-
-static inline int32_t
-vwsmaccsu16(CPURISCVState *env, int vxrm, uint16_t a, int16_t b, uint32_t c)
-{
- uint8_t round;
- int32_t res = a * (int32_t)b;
-
- round = get_round(vxrm, res, 8);
- res = (res >> 8) + round;
- return ssub32(env, vxrm, c, res);
-}
-
-static inline int64_t
-vwsmaccsu32(CPURISCVState *env, int vxrm, uint32_t a, int32_t b, int64_t c)
-{
- uint8_t round;
- int64_t res = a * (int64_t)b;
-
- round = get_round(vxrm, res, 16);
- res = (res >> 16) + round;
- return ssub64(env, vxrm, c, res);
-}
-
-RVVCALL(OPIVV3_RM, vwsmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, vwsmaccsu8)
-RVVCALL(OPIVV3_RM, vwsmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, vwsmaccsu16)
-RVVCALL(OPIVV3_RM, vwsmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, vwsmaccsu32)
-GEN_VEXT_VV_RM(vwsmaccsu_vv_b, 1, 2, clearh)
-GEN_VEXT_VV_RM(vwsmaccsu_vv_h, 2, 4, clearl)
-GEN_VEXT_VV_RM(vwsmaccsu_vv_w, 4, 8, clearq)
-RVVCALL(OPIVX3_RM, vwsmaccsu_vx_b, WOP_SSU_B, H2, H1, vwsmaccsu8)
-RVVCALL(OPIVX3_RM, vwsmaccsu_vx_h, WOP_SSU_H, H4, H2, vwsmaccsu16)
-RVVCALL(OPIVX3_RM, vwsmaccsu_vx_w, WOP_SSU_W, H8, H4, vwsmaccsu32)
-GEN_VEXT_VX_RM(vwsmaccsu_vx_b, 1, 2, clearh)
-GEN_VEXT_VX_RM(vwsmaccsu_vx_h, 2, 4, clearl)
-GEN_VEXT_VX_RM(vwsmaccsu_vx_w, 4, 8, clearq)
-
-static inline int16_t
-vwsmaccus8(CPURISCVState *env, int vxrm, int8_t a, uint8_t b, int16_t c)
-{
- uint8_t round;
- int16_t res = (int16_t)a * b;
-
- round = get_round(vxrm, res, 4);
- res = (res >> 4) + round;
- return ssub16(env, vxrm, c, res);
-}
-
-static inline int32_t
-vwsmaccus16(CPURISCVState *env, int vxrm, int16_t a, uint16_t b, int32_t c)
-{
- uint8_t round;
- int32_t res = (int32_t)a * b;
-
- round = get_round(vxrm, res, 8);
- res = (res >> 8) + round;
- return ssub32(env, vxrm, c, res);
-}
-
-static inline int64_t
-vwsmaccus32(CPURISCVState *env, int vxrm, int32_t a, uint32_t b, int64_t c)
-{
- uint8_t round;
- int64_t res = (int64_t)a * b;
-
- round = get_round(vxrm, res, 16);
- res = (res >> 16) + round;
- return ssub64(env, vxrm, c, res);
-}
-
-RVVCALL(OPIVX3_RM, vwsmaccus_vx_b, WOP_SUS_B, H2, H1, vwsmaccus8)
-RVVCALL(OPIVX3_RM, vwsmaccus_vx_h, WOP_SUS_H, H4, H2, vwsmaccus16)
-RVVCALL(OPIVX3_RM, vwsmaccus_vx_w, WOP_SUS_W, H8, H4, vwsmaccus32)
-GEN_VEXT_VX_RM(vwsmaccus_vx_b, 1, 2, clearh)
-GEN_VEXT_VX_RM(vwsmaccus_vx_h, 2, 4, clearl)
-GEN_VEXT_VX_RM(vwsmaccus_vx_w, 4, 8, clearq)
-
/* Vector Single-Width Scaling Shift Instructions */
static inline uint8_t
vssrl8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 54/65] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add
@ 2020-07-10 10:49 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 22 ---
target/riscv/insn32.decode | 7 -
target/riscv/insn_trans/trans_rvv.inc.c | 9 --
target/riscv/vector_helper.c | 205 ------------------------
4 files changed, 243 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 1c301c1440..b56342f333 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -729,28 +729,6 @@ DEF_HELPER_6(vsmul_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsmul_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsmul_vx_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmaccu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmaccu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmacc_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmaccsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmaccsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmaccsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmaccu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmacc_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmacc_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmacc_vx_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccsu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccsu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccsu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32)
-
DEF_HELPER_6(vssrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vssrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vssrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e32946b1f5..2be673c2c7 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -456,13 +456,6 @@ vasubu_vv 001010 . ..... ..... 010 ..... 1010111 @r_vm
vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm
vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm
vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm
-vwsmaccu_vv 111100 . ..... ..... 000 ..... 1010111 @r_vm
-vwsmaccu_vx 111100 . ..... ..... 100 ..... 1010111 @r_vm
-vwsmacc_vv 111101 . ..... ..... 000 ..... 1010111 @r_vm
-vwsmacc_vx 111101 . ..... ..... 100 ..... 1010111 @r_vm
-vwsmaccsu_vv 111110 . ..... ..... 000 ..... 1010111 @r_vm
-vwsmaccsu_vx 111110 . ..... ..... 100 ..... 1010111 @r_vm
-vwsmaccus_vx 111111 . ..... ..... 100 ..... 1010111 @r_vm
vssrl_vv 101010 . ..... ..... 000 ..... 1010111 @r_vm
vssrl_vx 101010 . ..... ..... 100 ..... 1010111 @r_vm
vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 5fa1f0c6ed..6481fa7465 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2170,15 +2170,6 @@ GEN_OPIVX_TRANS(vasubu_vx, opivx_check)
GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
GEN_OPIVX_TRANS(vsmul_vx, opivx_check)
-/* Vector Widening Saturating Scaled Multiply-Add */
-GEN_OPIVV_WIDEN_TRANS(vwsmaccu_vv, opivv_widen_check)
-GEN_OPIVV_WIDEN_TRANS(vwsmacc_vv, opivv_widen_check)
-GEN_OPIVV_WIDEN_TRANS(vwsmaccsu_vv, opivv_widen_check)
-GEN_OPIVX_WIDEN_TRANS(vwsmaccu_vx)
-GEN_OPIVX_WIDEN_TRANS(vwsmacc_vx)
-GEN_OPIVX_WIDEN_TRANS(vwsmaccsu_vx)
-GEN_OPIVX_WIDEN_TRANS(vwsmaccus_vx)
-
/* Vector Single-Width Scaling Shift Instructions */
GEN_OPIVV_TRANS(vssrl_vv, opivv_check)
GEN_OPIVV_TRANS(vssra_vv, opivv_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 67d5fd37aa..41faa3592e 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2929,211 +2929,6 @@ GEN_VEXT_VX_RM(vsmul_vx_h, 2, 2, clearh)
GEN_VEXT_VX_RM(vsmul_vx_w, 4, 4, clearl)
GEN_VEXT_VX_RM(vsmul_vx_d, 8, 8, clearq)
-/* Vector Widening Saturating Scaled Multiply-Add */
-static inline uint16_t
-vwsmaccu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b,
- uint16_t c)
-{
- uint8_t round;
- uint16_t res = (uint16_t)a * b;
-
- round = get_round(vxrm, res, 4);
- res = (res >> 4) + round;
- return saddu16(env, vxrm, c, res);
-}
-
-static inline uint32_t
-vwsmaccu16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b,
- uint32_t c)
-{
- uint8_t round;
- uint32_t res = (uint32_t)a * b;
-
- round = get_round(vxrm, res, 8);
- res = (res >> 8) + round;
- return saddu32(env, vxrm, c, res);
-}
-
-static inline uint64_t
-vwsmaccu32(CPURISCVState *env, int vxrm, uint32_t a, uint32_t b,
- uint64_t c)
-{
- uint8_t round;
- uint64_t res = (uint64_t)a * b;
-
- round = get_round(vxrm, res, 16);
- res = (res >> 16) + round;
- return saddu64(env, vxrm, c, res);
-}
-
-#define OPIVV3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
-static inline void \
-do_##NAME(void *vd, void *vs1, void *vs2, int i, \
- CPURISCVState *env, int vxrm) \
-{ \
- TX1 s1 = *((T1 *)vs1 + HS1(i)); \
- TX2 s2 = *((T2 *)vs2 + HS2(i)); \
- TD d = *((TD *)vd + HD(i)); \
- *((TD *)vd + HD(i)) = OP(env, vxrm, s2, s1, d); \
-}
-
-RVVCALL(OPIVV3_RM, vwsmaccu_vv_b, WOP_UUU_B, H2, H1, H1, vwsmaccu8)
-RVVCALL(OPIVV3_RM, vwsmaccu_vv_h, WOP_UUU_H, H4, H2, H2, vwsmaccu16)
-RVVCALL(OPIVV3_RM, vwsmaccu_vv_w, WOP_UUU_W, H8, H4, H4, vwsmaccu32)
-GEN_VEXT_VV_RM(vwsmaccu_vv_b, 1, 2, clearh)
-GEN_VEXT_VV_RM(vwsmaccu_vv_h, 2, 4, clearl)
-GEN_VEXT_VV_RM(vwsmaccu_vv_w, 4, 8, clearq)
-
-#define OPIVX3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
-static inline void \
-do_##NAME(void *vd, target_long s1, void *vs2, int i, \
- CPURISCVState *env, int vxrm) \
-{ \
- TX2 s2 = *((T2 *)vs2 + HS2(i)); \
- TD d = *((TD *)vd + HD(i)); \
- *((TD *)vd + HD(i)) = OP(env, vxrm, s2, (TX1)(T1)s1, d); \
-}
-
-RVVCALL(OPIVX3_RM, vwsmaccu_vx_b, WOP_UUU_B, H2, H1, vwsmaccu8)
-RVVCALL(OPIVX3_RM, vwsmaccu_vx_h, WOP_UUU_H, H4, H2, vwsmaccu16)
-RVVCALL(OPIVX3_RM, vwsmaccu_vx_w, WOP_UUU_W, H8, H4, vwsmaccu32)
-GEN_VEXT_VX_RM(vwsmaccu_vx_b, 1, 2, clearh)
-GEN_VEXT_VX_RM(vwsmaccu_vx_h, 2, 4, clearl)
-GEN_VEXT_VX_RM(vwsmaccu_vx_w, 4, 8, clearq)
-
-static inline int16_t
-vwsmacc8(CPURISCVState *env, int vxrm, int8_t a, int8_t b, int16_t c)
-{
- uint8_t round;
- int16_t res = (int16_t)a * b;
-
- round = get_round(vxrm, res, 4);
- res = (res >> 4) + round;
- return sadd16(env, vxrm, c, res);
-}
-
-static inline int32_t
-vwsmacc16(CPURISCVState *env, int vxrm, int16_t a, int16_t b, int32_t c)
-{
- uint8_t round;
- int32_t res = (int32_t)a * b;
-
- round = get_round(vxrm, res, 8);
- res = (res >> 8) + round;
- return sadd32(env, vxrm, c, res);
-
-}
-
-static inline int64_t
-vwsmacc32(CPURISCVState *env, int vxrm, int32_t a, int32_t b, int64_t c)
-{
- uint8_t round;
- int64_t res = (int64_t)a * b;
-
- round = get_round(vxrm, res, 16);
- res = (res >> 16) + round;
- return sadd64(env, vxrm, c, res);
-}
-
-RVVCALL(OPIVV3_RM, vwsmacc_vv_b, WOP_SSS_B, H2, H1, H1, vwsmacc8)
-RVVCALL(OPIVV3_RM, vwsmacc_vv_h, WOP_SSS_H, H4, H2, H2, vwsmacc16)
-RVVCALL(OPIVV3_RM, vwsmacc_vv_w, WOP_SSS_W, H8, H4, H4, vwsmacc32)
-GEN_VEXT_VV_RM(vwsmacc_vv_b, 1, 2, clearh)
-GEN_VEXT_VV_RM(vwsmacc_vv_h, 2, 4, clearl)
-GEN_VEXT_VV_RM(vwsmacc_vv_w, 4, 8, clearq)
-RVVCALL(OPIVX3_RM, vwsmacc_vx_b, WOP_SSS_B, H2, H1, vwsmacc8)
-RVVCALL(OPIVX3_RM, vwsmacc_vx_h, WOP_SSS_H, H4, H2, vwsmacc16)
-RVVCALL(OPIVX3_RM, vwsmacc_vx_w, WOP_SSS_W, H8, H4, vwsmacc32)
-GEN_VEXT_VX_RM(vwsmacc_vx_b, 1, 2, clearh)
-GEN_VEXT_VX_RM(vwsmacc_vx_h, 2, 4, clearl)
-GEN_VEXT_VX_RM(vwsmacc_vx_w, 4, 8, clearq)
-
-static inline int16_t
-vwsmaccsu8(CPURISCVState *env, int vxrm, uint8_t a, int8_t b, int16_t c)
-{
- uint8_t round;
- int16_t res = a * (int16_t)b;
-
- round = get_round(vxrm, res, 4);
- res = (res >> 4) + round;
- return ssub16(env, vxrm, c, res);
-}
-
-static inline int32_t
-vwsmaccsu16(CPURISCVState *env, int vxrm, uint16_t a, int16_t b, uint32_t c)
-{
- uint8_t round;
- int32_t res = a * (int32_t)b;
-
- round = get_round(vxrm, res, 8);
- res = (res >> 8) + round;
- return ssub32(env, vxrm, c, res);
-}
-
-static inline int64_t
-vwsmaccsu32(CPURISCVState *env, int vxrm, uint32_t a, int32_t b, int64_t c)
-{
- uint8_t round;
- int64_t res = a * (int64_t)b;
-
- round = get_round(vxrm, res, 16);
- res = (res >> 16) + round;
- return ssub64(env, vxrm, c, res);
-}
-
-RVVCALL(OPIVV3_RM, vwsmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, vwsmaccsu8)
-RVVCALL(OPIVV3_RM, vwsmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, vwsmaccsu16)
-RVVCALL(OPIVV3_RM, vwsmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, vwsmaccsu32)
-GEN_VEXT_VV_RM(vwsmaccsu_vv_b, 1, 2, clearh)
-GEN_VEXT_VV_RM(vwsmaccsu_vv_h, 2, 4, clearl)
-GEN_VEXT_VV_RM(vwsmaccsu_vv_w, 4, 8, clearq)
-RVVCALL(OPIVX3_RM, vwsmaccsu_vx_b, WOP_SSU_B, H2, H1, vwsmaccsu8)
-RVVCALL(OPIVX3_RM, vwsmaccsu_vx_h, WOP_SSU_H, H4, H2, vwsmaccsu16)
-RVVCALL(OPIVX3_RM, vwsmaccsu_vx_w, WOP_SSU_W, H8, H4, vwsmaccsu32)
-GEN_VEXT_VX_RM(vwsmaccsu_vx_b, 1, 2, clearh)
-GEN_VEXT_VX_RM(vwsmaccsu_vx_h, 2, 4, clearl)
-GEN_VEXT_VX_RM(vwsmaccsu_vx_w, 4, 8, clearq)
-
-static inline int16_t
-vwsmaccus8(CPURISCVState *env, int vxrm, int8_t a, uint8_t b, int16_t c)
-{
- uint8_t round;
- int16_t res = (int16_t)a * b;
-
- round = get_round(vxrm, res, 4);
- res = (res >> 4) + round;
- return ssub16(env, vxrm, c, res);
-}
-
-static inline int32_t
-vwsmaccus16(CPURISCVState *env, int vxrm, int16_t a, uint16_t b, int32_t c)
-{
- uint8_t round;
- int32_t res = (int32_t)a * b;
-
- round = get_round(vxrm, res, 8);
- res = (res >> 8) + round;
- return ssub32(env, vxrm, c, res);
-}
-
-static inline int64_t
-vwsmaccus32(CPURISCVState *env, int vxrm, int32_t a, uint32_t b, int64_t c)
-{
- uint8_t round;
- int64_t res = (int64_t)a * b;
-
- round = get_round(vxrm, res, 16);
- res = (res >> 16) + round;
- return ssub64(env, vxrm, c, res);
-}
-
-RVVCALL(OPIVX3_RM, vwsmaccus_vx_b, WOP_SUS_B, H2, H1, vwsmaccus8)
-RVVCALL(OPIVX3_RM, vwsmaccus_vx_h, WOP_SUS_H, H4, H2, vwsmaccus16)
-RVVCALL(OPIVX3_RM, vwsmaccus_vx_w, WOP_SUS_W, H8, H4, vwsmaccus32)
-GEN_VEXT_VX_RM(vwsmaccus_vx_b, 1, 2, clearh)
-GEN_VEXT_VX_RM(vwsmaccus_vx_h, 2, 4, clearl)
-GEN_VEXT_VX_RM(vwsmaccus_vx_w, 4, 8, clearq)
-
/* Vector Single-Width Scaling Shift Instructions */
static inline uint8_t
vssrl8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 55/65] target/riscv: rvv-0.9: remove vmford.vv and vmford.vf
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:49 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 6 ------
target/riscv/insn32.decode | 2 --
target/riscv/insn_trans/trans_rvv.inc.c | 2 --
target/riscv/vector_helper.c | 13 -------------
4 files changed, 23 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index b56342f333..e9655453bc 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -945,12 +945,6 @@ DEF_HELPER_6(vmfgt_vf_d, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vmfge_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vmfge_vf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vmfge_vf_d, void, ptr, ptr, i64, ptr, env, i32)
-DEF_HELPER_6(vmford_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vmford_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vmford_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vmford_vf_h, void, ptr, ptr, i64, ptr, env, i32)
-DEF_HELPER_6(vmford_vf_w, void, ptr, ptr, i64, ptr, env, i32)
-DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 2be673c2c7..47337abe52 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -535,8 +535,6 @@ vmfle_vv 011001 . ..... ..... 001 ..... 1010111 @r_vm
vmfle_vf 011001 . ..... ..... 101 ..... 1010111 @r_vm
vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm
vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
-vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm
-vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm
vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm
vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 6481fa7465..2490fc5732 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2564,7 +2564,6 @@ GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check)
GEN_OPFVV_TRANS(vmflt_vv, opfvv_cmp_check)
GEN_OPFVV_TRANS(vmfle_vv, opfvv_cmp_check)
-GEN_OPFVV_TRANS(vmford_vv, opfvv_cmp_check)
static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
{
@@ -2581,7 +2580,6 @@ GEN_OPFVF_TRANS(vmflt_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check)
-GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check)
/* Vector Floating-Point Classify Instruction */
GEN_OPFV_TRANS(vfclass_v, opfv_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 41faa3592e..42a48be5fd 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4107,19 +4107,6 @@ GEN_VEXT_CMP_VF(vmfge_vf_h, uint16_t, H2, vmfge16)
GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32)
GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64)
-static bool float16_unordered_quiet(uint16_t a, uint16_t b, float_status *s)
-{
- FloatRelation compare = float16_compare_quiet(a, b, s);
- return compare == float_relation_unordered;
-}
-
-GEN_VEXT_CMP_VV_ENV(vmford_vv_h, uint16_t, H2, !float16_unordered_quiet)
-GEN_VEXT_CMP_VV_ENV(vmford_vv_w, uint32_t, H4, !float32_unordered_quiet)
-GEN_VEXT_CMP_VV_ENV(vmford_vv_d, uint64_t, H8, !float64_unordered_quiet)
-GEN_VEXT_CMP_VF(vmford_vf_h, uint16_t, H2, !float16_unordered_quiet)
-GEN_VEXT_CMP_VF(vmford_vf_w, uint32_t, H4, !float32_unordered_quiet)
-GEN_VEXT_CMP_VF(vmford_vf_d, uint64_t, H8, !float64_unordered_quiet)
-
/* Vector Floating-Point Classify Instruction */
#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \
static void do_##NAME(void *vd, void *vs2, int i) \
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 55/65] target/riscv: rvv-0.9: remove vmford.vv and vmford.vf
@ 2020-07-10 10:49 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 6 ------
target/riscv/insn32.decode | 2 --
target/riscv/insn_trans/trans_rvv.inc.c | 2 --
target/riscv/vector_helper.c | 13 -------------
4 files changed, 23 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index b56342f333..e9655453bc 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -945,12 +945,6 @@ DEF_HELPER_6(vmfgt_vf_d, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vmfge_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vmfge_vf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vmfge_vf_d, void, ptr, ptr, i64, ptr, env, i32)
-DEF_HELPER_6(vmford_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vmford_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vmford_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vmford_vf_h, void, ptr, ptr, i64, ptr, env, i32)
-DEF_HELPER_6(vmford_vf_w, void, ptr, ptr, i64, ptr, env, i32)
-DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 2be673c2c7..47337abe52 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -535,8 +535,6 @@ vmfle_vv 011001 . ..... ..... 001 ..... 1010111 @r_vm
vmfle_vf 011001 . ..... ..... 101 ..... 1010111 @r_vm
vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm
vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
-vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm
-vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm
vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm
vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 6481fa7465..2490fc5732 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2564,7 +2564,6 @@ GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check)
GEN_OPFVV_TRANS(vmflt_vv, opfvv_cmp_check)
GEN_OPFVV_TRANS(vmfle_vv, opfvv_cmp_check)
-GEN_OPFVV_TRANS(vmford_vv, opfvv_cmp_check)
static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
{
@@ -2581,7 +2580,6 @@ GEN_OPFVF_TRANS(vmflt_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check)
-GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check)
/* Vector Floating-Point Classify Instruction */
GEN_OPFV_TRANS(vfclass_v, opfv_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 41faa3592e..42a48be5fd 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4107,19 +4107,6 @@ GEN_VEXT_CMP_VF(vmfge_vf_h, uint16_t, H2, vmfge16)
GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32)
GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64)
-static bool float16_unordered_quiet(uint16_t a, uint16_t b, float_status *s)
-{
- FloatRelation compare = float16_compare_quiet(a, b, s);
- return compare == float_relation_unordered;
-}
-
-GEN_VEXT_CMP_VV_ENV(vmford_vv_h, uint16_t, H2, !float16_unordered_quiet)
-GEN_VEXT_CMP_VV_ENV(vmford_vv_w, uint32_t, H4, !float32_unordered_quiet)
-GEN_VEXT_CMP_VV_ENV(vmford_vv_d, uint64_t, H8, !float64_unordered_quiet)
-GEN_VEXT_CMP_VF(vmford_vf_h, uint16_t, H2, !float16_unordered_quiet)
-GEN_VEXT_CMP_VF(vmford_vf_w, uint32_t, H4, !float32_unordered_quiet)
-GEN_VEXT_CMP_VF(vmford_vf_d, uint64_t, H8, !float64_unordered_quiet)
-
/* Vector Floating-Point Classify Instruction */
#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \
static void do_##NAME(void *vd, void *vs2, int i) \
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 56/65] target/riscv: rvv-0.9: remove integer extract instruction
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:49 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 1 -
target/riscv/insn_trans/trans_rvv.inc.c | 23 -----------------------
2 files changed, 24 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 47337abe52..bc0e44b8ab 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -590,7 +590,6 @@ viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd
vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2
-vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd
vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2
vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 2490fc5732..fb2c119e13 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2959,8 +2959,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
*** Vector Permutation Instructions
*/
-/* Integer Extract Instruction */
-
static void load_element(TCGv_i64 dest, TCGv_ptr base,
int ofs, int sew, bool sign)
{
@@ -3062,27 +3060,6 @@ static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew, sign);
}
-static bool trans_vext_x_v(DisasContext *s, arg_r *a)
-{
- TCGv_i64 tmp = tcg_temp_new_i64();
- TCGv dest = tcg_temp_new();
-
- if (a->rs1 == 0) {
- /* Special case vmv.x.s rd, vs2. */
- vec_element_loadi(s, tmp, a->rs2, 0);
- } else {
- /* This instruction ignores LMUL and vector register groups */
- int vlmax = s->vlen >> (3 + s->sew);
- vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax);
- }
- tcg_gen_trunc_i64_tl(dest, tmp);
- gen_set_gpr(a->rd, dest);
-
- tcg_temp_free(dest);
- tcg_temp_free_i64(tmp);
- return true;
-}
-
/* Integer Scalar Move Instruction */
static void store_element(TCGv_i64 val, TCGv_ptr base,
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 56/65] target/riscv: rvv-0.9: remove integer extract instruction
@ 2020-07-10 10:49 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 1 -
target/riscv/insn_trans/trans_rvv.inc.c | 23 -----------------------
2 files changed, 24 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 47337abe52..bc0e44b8ab 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -590,7 +590,6 @@ viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd
vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2
-vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd
vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2
vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 2490fc5732..fb2c119e13 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2959,8 +2959,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
*** Vector Permutation Instructions
*/
-/* Integer Extract Instruction */
-
static void load_element(TCGv_i64 dest, TCGv_ptr base,
int ofs, int sew, bool sign)
{
@@ -3062,27 +3060,6 @@ static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew, sign);
}
-static bool trans_vext_x_v(DisasContext *s, arg_r *a)
-{
- TCGv_i64 tmp = tcg_temp_new_i64();
- TCGv dest = tcg_temp_new();
-
- if (a->rs1 == 0) {
- /* Special case vmv.x.s rd, vs2. */
- vec_element_loadi(s, tmp, a->rs2, 0);
- } else {
- /* This instruction ignores LMUL and vector register groups */
- int vlmax = s->vlen >> (3 + s->sew);
- vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax);
- }
- tcg_gen_trunc_i64_tl(dest, tmp);
- gen_set_gpr(a->rd, dest);
-
- tcg_temp_free(dest);
- tcg_temp_free_i64(tmp);
- return true;
-}
-
/* Integer Scalar Move Instruction */
static void store_element(TCGv_i64 val, TCGv_ptr base,
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 57/65] target/riscv: rvv-0.9: floating-point min/max instructions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:49 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/vector_helper.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 42a48be5fd..d617d0dfbd 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3831,28 +3831,28 @@ GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4, clearl)
GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8, clearq)
/* Vector Floating-Point MIN/MAX Instructions */
-RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum)
-RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum)
-RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minnum)
+RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum_noprop)
+RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum_noprop)
+RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minnum_noprop)
GEN_VEXT_VV_ENV(vfmin_vv_h, 2, 2, clearh)
GEN_VEXT_VV_ENV(vfmin_vv_w, 4, 4, clearl)
GEN_VEXT_VV_ENV(vfmin_vv_d, 8, 8, clearq)
-RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum)
-RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum)
-RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum)
+RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum_noprop)
+RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum_noprop)
+RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum_noprop)
GEN_VEXT_VF(vfmin_vf_h, 2, 2, clearh)
GEN_VEXT_VF(vfmin_vf_w, 4, 4, clearl)
GEN_VEXT_VF(vfmin_vf_d, 8, 8, clearq)
-RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum)
-RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum)
-RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum)
+RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum_noprop)
+RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum_noprop)
+RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum_noprop)
GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2, clearh)
GEN_VEXT_VV_ENV(vfmax_vv_w, 4, 4, clearl)
GEN_VEXT_VV_ENV(vfmax_vv_d, 8, 8, clearq)
-RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum)
-RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum)
-RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum)
+RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum_noprop)
+RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum_noprop)
+RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum_noprop)
GEN_VEXT_VF(vfmax_vf_h, 2, 2, clearh)
GEN_VEXT_VF(vfmax_vf_w, 4, 4, clearl)
GEN_VEXT_VF(vfmax_vf_d, 8, 8, clearq)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 57/65] target/riscv: rvv-0.9: floating-point min/max instructions
@ 2020-07-10 10:49 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/vector_helper.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 42a48be5fd..d617d0dfbd 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3831,28 +3831,28 @@ GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4, clearl)
GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8, clearq)
/* Vector Floating-Point MIN/MAX Instructions */
-RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum)
-RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum)
-RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minnum)
+RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum_noprop)
+RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum_noprop)
+RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minnum_noprop)
GEN_VEXT_VV_ENV(vfmin_vv_h, 2, 2, clearh)
GEN_VEXT_VV_ENV(vfmin_vv_w, 4, 4, clearl)
GEN_VEXT_VV_ENV(vfmin_vv_d, 8, 8, clearq)
-RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum)
-RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum)
-RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum)
+RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum_noprop)
+RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum_noprop)
+RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum_noprop)
GEN_VEXT_VF(vfmin_vf_h, 2, 2, clearh)
GEN_VEXT_VF(vfmin_vf_w, 4, 4, clearl)
GEN_VEXT_VF(vfmin_vf_d, 8, 8, clearq)
-RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum)
-RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum)
-RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum)
+RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum_noprop)
+RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum_noprop)
+RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum_noprop)
GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2, clearh)
GEN_VEXT_VV_ENV(vfmax_vv_w, 4, 4, clearl)
GEN_VEXT_VV_ENV(vfmax_vv_d, 8, 8, clearq)
-RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum)
-RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum)
-RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum)
+RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum_noprop)
+RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum_noprop)
+RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum_noprop)
GEN_VEXT_VF(vfmax_vf_h, 2, 2, clearh)
GEN_VEXT_VF(vfmax_vf_w, 4, 4, clearl)
GEN_VEXT_VF(vfmax_vf_d, 8, 8, clearq)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 58/65] target/riscv: rvv-0.9: widening floating-point/integer type-convert
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:49 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 6 ++++
target/riscv/insn32.decode | 13 +++++---
target/riscv/insn_trans/trans_rvv.inc.c | 44 +++++++++++++++++++++++--
target/riscv/vector_helper.c | 29 +++++++++++++++-
4 files changed, 84 insertions(+), 8 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index e9655453bc..0cd5979288 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -977,12 +977,18 @@ DEF_HELPER_5(vfwcvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_x_f_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_x_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvt_f_xu_v_b, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvt_f_x_v_b, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_x_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_f_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvt_rtz_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvt_rtz_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvt_rtz_x_f_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvt_rtz_x_f_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfncvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfncvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index bc0e44b8ab..55d7a6f338 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -545,11 +545,14 @@ vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm
vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm
vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm
vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm
-vfwcvt_xu_f_v 100010 . ..... 01000 001 ..... 1010111 @r2_vm
-vfwcvt_x_f_v 100010 . ..... 01001 001 ..... 1010111 @r2_vm
-vfwcvt_f_xu_v 100010 . ..... 01010 001 ..... 1010111 @r2_vm
-vfwcvt_f_x_v 100010 . ..... 01011 001 ..... 1010111 @r2_vm
-vfwcvt_f_f_v 100010 . ..... 01100 001 ..... 1010111 @r2_vm
+
+vfwcvt_xu_f_v 010010 . ..... 01000 001 ..... 1010111 @r2_vm
+vfwcvt_x_f_v 010010 . ..... 01001 001 ..... 1010111 @r2_vm
+vfwcvt_f_xu_v 010010 . ..... 01010 001 ..... 1010111 @r2_vm
+vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm
+vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm
+vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm
+vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm
vfncvt_xu_f_v 100010 . ..... 10000 001 ..... 1010111 @r2_vm
vfncvt_x_f_v 100010 . ..... 10001 001 ..... 1010111 @r2_vm
vfncvt_f_xu_v 100010 . ..... 10010 001 ..... 1010111 @r2_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index fb2c119e13..4840200f01 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2674,9 +2674,49 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v)
GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v)
-GEN_OPFV_WIDEN_TRANS(vfwcvt_f_xu_v)
-GEN_OPFV_WIDEN_TRANS(vfwcvt_f_x_v)
GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v)
+GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_xu_f_v)
+GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_x_f_v)
+
+static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
+{
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ /* OPFV widening instructions ignore vs1 check */
+ VEXT_CHECK_DSS(s, a->rd, 0, a->rs2, a->vm, false);
+ return true;
+}
+
+#define GEN_OPFXV_WIDEN_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+ if (opfxv_widen_check(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_gvec_3_ptr * const fns[3] = { \
+ gen_helper_##NAME##_b, \
+ gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, \
+ }; \
+ TCGLabel *over = gen_new_label(); \
+ gen_set_rm(s, 7); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs2), cpu_env, 0, \
+ s->vlen / 8, data, fns[s->sew]); \
+ mark_vs_dirty(s); \
+ gen_set_label(over); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_xu_v)
+GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_x_v)
/* Narrowing Floating-Point/Integer Type-Convert Instructions */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index d617d0dfbd..0b6dd4c93f 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4295,6 +4295,7 @@ GEN_VEXT_V_ENV(vfcvt_rtz_x_f_v_d, 8, 8, clearq)
/* Widening Floating-Point/Integer Type-Convert Instructions */
/* (TD, T2, TX2) */
+#define WOP_UU_B uint16_t, uint8_t, uint8_t
#define WOP_UU_H uint32_t, uint16_t, uint16_t
#define WOP_UU_W uint64_t, uint32_t, uint32_t
/* vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer.*/
@@ -4310,19 +4311,45 @@ GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 2, 4, clearl)
GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 4, 8, clearq)
/* vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float */
+RVVCALL(OPFVV1, vfwcvt_f_xu_v_b, WOP_UU_B, H2, H1, uint8_to_float16)
RVVCALL(OPFVV1, vfwcvt_f_xu_v_h, WOP_UU_H, H4, H2, uint16_to_float32)
RVVCALL(OPFVV1, vfwcvt_f_xu_v_w, WOP_UU_W, H8, H4, uint32_to_float64)
+GEN_VEXT_V_ENV(vfwcvt_f_xu_v_b, 1, 2, clearh)
GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h, 2, 4, clearl)
GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w, 4, 8, clearq)
/* vfwcvt.f.x.v vd, vs2, vm # Convert integer to double-width float. */
+RVVCALL(OPFVV1, vfwcvt_f_x_v_b, WOP_UU_B, H2, H1, int8_to_float16)
RVVCALL(OPFVV1, vfwcvt_f_x_v_h, WOP_UU_H, H4, H2, int16_to_float32)
RVVCALL(OPFVV1, vfwcvt_f_x_v_w, WOP_UU_W, H8, H4, int32_to_float64)
+GEN_VEXT_V_ENV(vfwcvt_f_x_v_b, 1, 2, clearh)
GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 2, 4, clearl)
GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 4, 8, clearq)
/*
- * vfwcvt.f.f.v vd, vs2, vm #
+ * vfwcvt.rtz.xu.f.v vd, vs2, vm
+ * Convert float to double-width unsigned integer, truncating
+ */
+FCVT_RTZ_F_V(float16, uint32)
+FCVT_RTZ_F_V(float32, uint64)
+RVVCALL(OPFVV1, vfwcvt_rtz_xu_f_v_h, WOP_UU_H, H4, H2, float16_to_uint32_rtz)
+RVVCALL(OPFVV1, vfwcvt_rtz_xu_f_v_w, WOP_UU_W, H8, H4, float32_to_uint64_rtz)
+GEN_VEXT_V_ENV(vfwcvt_rtz_xu_f_v_h, 2, 4, clearl)
+GEN_VEXT_V_ENV(vfwcvt_rtz_xu_f_v_w, 4, 8, clearq)
+
+/*
+ * vfwcvt.rtz.x.f.v vd, vs2, vm
+ * Convert float to double-width signed integer, truncating.
+ */
+FCVT_RTZ_F_V(float16, int32)
+FCVT_RTZ_F_V(float32, int64)
+RVVCALL(OPFVV1, vfwcvt_rtz_x_f_v_h, WOP_UU_H, H4, H2, float16_to_int32_rtz)
+RVVCALL(OPFVV1, vfwcvt_rtz_x_f_v_w, WOP_UU_W, H8, H4, float32_to_int64_rtz)
+GEN_VEXT_V_ENV(vfwcvt_rtz_x_f_v_h, 2, 4, clearl)
+GEN_VEXT_V_ENV(vfwcvt_rtz_x_f_v_w, 4, 8, clearq)
+
+/*
+ * vfwcvt.f.f.v vd, vs2, vm
* Convert single-width float to double-width float.
*/
static uint32_t vfwcvtffv16(uint16_t a, float_status *s)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 58/65] target/riscv: rvv-0.9: widening floating-point/integer type-convert
@ 2020-07-10 10:49 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 6 ++++
target/riscv/insn32.decode | 13 +++++---
target/riscv/insn_trans/trans_rvv.inc.c | 44 +++++++++++++++++++++++--
target/riscv/vector_helper.c | 29 +++++++++++++++-
4 files changed, 84 insertions(+), 8 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index e9655453bc..0cd5979288 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -977,12 +977,18 @@ DEF_HELPER_5(vfwcvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_x_f_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_x_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvt_f_xu_v_b, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvt_f_x_v_b, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_x_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_f_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvt_rtz_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvt_rtz_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvt_rtz_x_f_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvt_rtz_x_f_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfncvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfncvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index bc0e44b8ab..55d7a6f338 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -545,11 +545,14 @@ vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm
vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm
vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm
vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm
-vfwcvt_xu_f_v 100010 . ..... 01000 001 ..... 1010111 @r2_vm
-vfwcvt_x_f_v 100010 . ..... 01001 001 ..... 1010111 @r2_vm
-vfwcvt_f_xu_v 100010 . ..... 01010 001 ..... 1010111 @r2_vm
-vfwcvt_f_x_v 100010 . ..... 01011 001 ..... 1010111 @r2_vm
-vfwcvt_f_f_v 100010 . ..... 01100 001 ..... 1010111 @r2_vm
+
+vfwcvt_xu_f_v 010010 . ..... 01000 001 ..... 1010111 @r2_vm
+vfwcvt_x_f_v 010010 . ..... 01001 001 ..... 1010111 @r2_vm
+vfwcvt_f_xu_v 010010 . ..... 01010 001 ..... 1010111 @r2_vm
+vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm
+vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm
+vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm
+vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm
vfncvt_xu_f_v 100010 . ..... 10000 001 ..... 1010111 @r2_vm
vfncvt_x_f_v 100010 . ..... 10001 001 ..... 1010111 @r2_vm
vfncvt_f_xu_v 100010 . ..... 10010 001 ..... 1010111 @r2_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index fb2c119e13..4840200f01 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2674,9 +2674,49 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v)
GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v)
-GEN_OPFV_WIDEN_TRANS(vfwcvt_f_xu_v)
-GEN_OPFV_WIDEN_TRANS(vfwcvt_f_x_v)
GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v)
+GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_xu_f_v)
+GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_x_f_v)
+
+static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
+{
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ /* OPFV widening instructions ignore vs1 check */
+ VEXT_CHECK_DSS(s, a->rd, 0, a->rs2, a->vm, false);
+ return true;
+}
+
+#define GEN_OPFXV_WIDEN_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+ if (opfxv_widen_check(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_gvec_3_ptr * const fns[3] = { \
+ gen_helper_##NAME##_b, \
+ gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, \
+ }; \
+ TCGLabel *over = gen_new_label(); \
+ gen_set_rm(s, 7); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs2), cpu_env, 0, \
+ s->vlen / 8, data, fns[s->sew]); \
+ mark_vs_dirty(s); \
+ gen_set_label(over); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_xu_v)
+GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_x_v)
/* Narrowing Floating-Point/Integer Type-Convert Instructions */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index d617d0dfbd..0b6dd4c93f 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4295,6 +4295,7 @@ GEN_VEXT_V_ENV(vfcvt_rtz_x_f_v_d, 8, 8, clearq)
/* Widening Floating-Point/Integer Type-Convert Instructions */
/* (TD, T2, TX2) */
+#define WOP_UU_B uint16_t, uint8_t, uint8_t
#define WOP_UU_H uint32_t, uint16_t, uint16_t
#define WOP_UU_W uint64_t, uint32_t, uint32_t
/* vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer.*/
@@ -4310,19 +4311,45 @@ GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 2, 4, clearl)
GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 4, 8, clearq)
/* vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float */
+RVVCALL(OPFVV1, vfwcvt_f_xu_v_b, WOP_UU_B, H2, H1, uint8_to_float16)
RVVCALL(OPFVV1, vfwcvt_f_xu_v_h, WOP_UU_H, H4, H2, uint16_to_float32)
RVVCALL(OPFVV1, vfwcvt_f_xu_v_w, WOP_UU_W, H8, H4, uint32_to_float64)
+GEN_VEXT_V_ENV(vfwcvt_f_xu_v_b, 1, 2, clearh)
GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h, 2, 4, clearl)
GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w, 4, 8, clearq)
/* vfwcvt.f.x.v vd, vs2, vm # Convert integer to double-width float. */
+RVVCALL(OPFVV1, vfwcvt_f_x_v_b, WOP_UU_B, H2, H1, int8_to_float16)
RVVCALL(OPFVV1, vfwcvt_f_x_v_h, WOP_UU_H, H4, H2, int16_to_float32)
RVVCALL(OPFVV1, vfwcvt_f_x_v_w, WOP_UU_W, H8, H4, int32_to_float64)
+GEN_VEXT_V_ENV(vfwcvt_f_x_v_b, 1, 2, clearh)
GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 2, 4, clearl)
GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 4, 8, clearq)
/*
- * vfwcvt.f.f.v vd, vs2, vm #
+ * vfwcvt.rtz.xu.f.v vd, vs2, vm
+ * Convert float to double-width unsigned integer, truncating
+ */
+FCVT_RTZ_F_V(float16, uint32)
+FCVT_RTZ_F_V(float32, uint64)
+RVVCALL(OPFVV1, vfwcvt_rtz_xu_f_v_h, WOP_UU_H, H4, H2, float16_to_uint32_rtz)
+RVVCALL(OPFVV1, vfwcvt_rtz_xu_f_v_w, WOP_UU_W, H8, H4, float32_to_uint64_rtz)
+GEN_VEXT_V_ENV(vfwcvt_rtz_xu_f_v_h, 2, 4, clearl)
+GEN_VEXT_V_ENV(vfwcvt_rtz_xu_f_v_w, 4, 8, clearq)
+
+/*
+ * vfwcvt.rtz.x.f.v vd, vs2, vm
+ * Convert float to double-width signed integer, truncating.
+ */
+FCVT_RTZ_F_V(float16, int32)
+FCVT_RTZ_F_V(float32, int64)
+RVVCALL(OPFVV1, vfwcvt_rtz_x_f_v_h, WOP_UU_H, H4, H2, float16_to_int32_rtz)
+RVVCALL(OPFVV1, vfwcvt_rtz_x_f_v_w, WOP_UU_W, H8, H4, float32_to_int64_rtz)
+GEN_VEXT_V_ENV(vfwcvt_rtz_x_f_v_h, 2, 4, clearl)
+GEN_VEXT_V_ENV(vfwcvt_rtz_x_f_v_w, 4, 8, clearq)
+
+/*
+ * vfwcvt.f.f.v vd, vs2, vm
* Convert single-width float to double-width float.
*/
static uint32_t vfwcvtffv16(uint16_t a, float_status *s)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 59/65] target/riscv: rvv-0.9: narrowing floating-point/integer type-convert
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:49 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 30 +++++---
target/riscv/insn32.decode | 15 ++--
target/riscv/insn_trans/trans_rvv.inc.c | 50 +++++++++++--
target/riscv/vector_helper.c | 99 ++++++++++++++++++++-----
4 files changed, 154 insertions(+), 40 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 0cd5979288..f8c657737f 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -990,16 +990,26 @@ DEF_HELPER_5(vfwcvt_rtz_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_rtz_x_f_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_rtz_x_f_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_x_f_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_x_f_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_x_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_f_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_xu_f_w_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_xu_f_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_xu_f_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_x_f_w_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_x_f_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_x_f_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_xu_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_xu_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_x_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_x_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_f_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_f_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_rod_f_f_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_rod_f_f_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_rtz_xu_f_w_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_rtz_xu_f_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_rtz_xu_f_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_rtz_x_f_w_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_rtz_x_f_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_rtz_x_f_w_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 55d7a6f338..17350227c6 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -553,11 +553,16 @@ vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm
vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm
vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm
vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm
-vfncvt_xu_f_v 100010 . ..... 10000 001 ..... 1010111 @r2_vm
-vfncvt_x_f_v 100010 . ..... 10001 001 ..... 1010111 @r2_vm
-vfncvt_f_xu_v 100010 . ..... 10010 001 ..... 1010111 @r2_vm
-vfncvt_f_x_v 100010 . ..... 10011 001 ..... 1010111 @r2_vm
-vfncvt_f_f_v 100010 . ..... 10100 001 ..... 1010111 @r2_vm
+
+vfncvt_xu_f_w 010010 . ..... 10000 001 ..... 1010111 @r2_vm
+vfncvt_x_f_w 010010 . ..... 10001 001 ..... 1010111 @r2_vm
+vfncvt_f_xu_w 010010 . ..... 10010 001 ..... 1010111 @r2_vm
+vfncvt_f_x_w 010010 . ..... 10011 001 ..... 1010111 @r2_vm
+vfncvt_f_f_w 010010 . ..... 10100 001 ..... 1010111 @r2_vm
+vfncvt_rod_f_f_w 010010 . ..... 10101 001 ..... 1010111 @r2_vm
+vfncvt_rtz_xu_f_w 010010 . ..... 10110 001 ..... 1010111 @r2_vm
+vfncvt_rtz_x_f_w 010010 . ..... 10111 001 ..... 1010111 @r2_vm
+
vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm
vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm
vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 4840200f01..dffe554966 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2761,11 +2761,51 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
return false; \
}
-GEN_OPFV_NARROW_TRANS(vfncvt_xu_f_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_x_f_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_f_x_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v)
+GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_w)
+GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w)
+GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w)
+GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w)
+
+static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
+{
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ /* OPFV narrowing instructions ignore vs1 check */
+ VEXT_CHECK_SDS(s, a->rd, 0, a->rs2, a->vm, false);
+ return true;
+}
+
+#define GEN_OPXFV_NARROW_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+ if (opxfv_narrow_check(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_gvec_3_ptr * const fns[3] = { \
+ gen_helper_##NAME##_b, \
+ gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, \
+ }; \
+ TCGLabel *over = gen_new_label(); \
+ gen_set_rm(s, 7); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs2), cpu_env, 0, \
+ s->vlen / 8, data, fns[s->sew]); \
+ gen_set_label(over); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_OPXFV_NARROW_TRANS(vfncvt_xu_f_w)
+GEN_OPXFV_NARROW_TRANS(vfncvt_x_f_w)
+GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_xu_f_w)
+GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_x_f_w)
/*
*** Vector Reduction Operations
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 0b6dd4c93f..aac055c6b6 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4265,6 +4265,16 @@ static DTYPE##_t STYPE##_to_##DTYPE##_rtz(STYPE a, float_status * s) \
return result; \
}
+#define FCVT_ROD_F_F(STYPE, DTYPE) \
+static DTYPE STYPE##_to_##DTYPE##_rod(STYPE a, float_status * s) \
+{ \
+ signed char frm = s->float_rounding_mode; \
+ s->float_rounding_mode = float_round_to_odd; \
+ DTYPE result = STYPE##_to_##DTYPE(a, s); \
+ s->float_rounding_mode = frm; \
+ return result; \
+}
+
/*
* vfcvt.rtz.xu.f.v vd, vs2, vm
* Convert float to unsigned integer, truncating.
@@ -4364,31 +4374,36 @@ GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8, clearq)
/* Narrowing Floating-Point/Integer Type-Convert Instructions */
/* (TD, T2, TX2) */
+#define NOP_UU_B uint8_t, uint16_t, uint32_t
#define NOP_UU_H uint16_t, uint32_t, uint32_t
#define NOP_UU_W uint32_t, uint64_t, uint64_t
/* vfncvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */
-RVVCALL(OPFVV1, vfncvt_xu_f_v_h, NOP_UU_H, H2, H4, float32_to_uint16)
-RVVCALL(OPFVV1, vfncvt_xu_f_v_w, NOP_UU_W, H4, H8, float64_to_uint32)
-GEN_VEXT_V_ENV(vfncvt_xu_f_v_h, 2, 2, clearh)
-GEN_VEXT_V_ENV(vfncvt_xu_f_v_w, 4, 4, clearl)
+RVVCALL(OPFVV1, vfncvt_xu_f_w_b, NOP_UU_B, H1, H2, float16_to_uint8)
+RVVCALL(OPFVV1, vfncvt_xu_f_w_h, NOP_UU_H, H2, H4, float32_to_uint16)
+RVVCALL(OPFVV1, vfncvt_xu_f_w_w, NOP_UU_W, H4, H8, float64_to_uint32)
+GEN_VEXT_V_ENV(vfncvt_xu_f_w_b, 1, 1, clearb)
+GEN_VEXT_V_ENV(vfncvt_xu_f_w_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfncvt_xu_f_w_w, 4, 4, clearl)
/* vfncvt.x.f.v vd, vs2, vm # Convert double-width float to signed integer. */
-RVVCALL(OPFVV1, vfncvt_x_f_v_h, NOP_UU_H, H2, H4, float32_to_int16)
-RVVCALL(OPFVV1, vfncvt_x_f_v_w, NOP_UU_W, H4, H8, float64_to_int32)
-GEN_VEXT_V_ENV(vfncvt_x_f_v_h, 2, 2, clearh)
-GEN_VEXT_V_ENV(vfncvt_x_f_v_w, 4, 4, clearl)
+RVVCALL(OPFVV1, vfncvt_x_f_w_b, NOP_UU_B, H1, H2, float16_to_int8)
+RVVCALL(OPFVV1, vfncvt_x_f_w_h, NOP_UU_H, H2, H4, float32_to_int16)
+RVVCALL(OPFVV1, vfncvt_x_f_w_w, NOP_UU_W, H4, H8, float64_to_int32)
+GEN_VEXT_V_ENV(vfncvt_x_f_w_b, 1, 1, clearb)
+GEN_VEXT_V_ENV(vfncvt_x_f_w_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfncvt_x_f_w_w, 4, 4, clearl)
/* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to float */
-RVVCALL(OPFVV1, vfncvt_f_xu_v_h, NOP_UU_H, H2, H4, uint32_to_float16)
-RVVCALL(OPFVV1, vfncvt_f_xu_v_w, NOP_UU_W, H4, H8, uint64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_xu_v_h, 2, 2, clearh)
-GEN_VEXT_V_ENV(vfncvt_f_xu_v_w, 4, 4, clearl)
+RVVCALL(OPFVV1, vfncvt_f_xu_w_h, NOP_UU_H, H2, H4, uint32_to_float16)
+RVVCALL(OPFVV1, vfncvt_f_xu_w_w, NOP_UU_W, H4, H8, uint64_to_float32)
+GEN_VEXT_V_ENV(vfncvt_f_xu_w_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfncvt_f_xu_w_w, 4, 4, clearl)
/* vfncvt.f.x.v vd, vs2, vm # Convert double-width integer to float. */
-RVVCALL(OPFVV1, vfncvt_f_x_v_h, NOP_UU_H, H2, H4, int32_to_float16)
-RVVCALL(OPFVV1, vfncvt_f_x_v_w, NOP_UU_W, H4, H8, int64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_x_v_h, 2, 2, clearh)
-GEN_VEXT_V_ENV(vfncvt_f_x_v_w, 4, 4, clearl)
+RVVCALL(OPFVV1, vfncvt_f_x_w_h, NOP_UU_H, H2, H4, int32_to_float16)
+RVVCALL(OPFVV1, vfncvt_f_x_w_w, NOP_UU_W, H4, H8, int64_to_float32)
+GEN_VEXT_V_ENV(vfncvt_f_x_w_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfncvt_f_x_w_w, 4, 4, clearl)
/* vfncvt.f.f.v vd, vs2, vm # Convert double float to single-width float. */
static uint16_t vfncvtffv16(uint32_t a, float_status *s)
@@ -4396,10 +4411,54 @@ static uint16_t vfncvtffv16(uint32_t a, float_status *s)
return float32_to_float16(a, true, s);
}
-RVVCALL(OPFVV1, vfncvt_f_f_v_h, NOP_UU_H, H2, H4, vfncvtffv16)
-RVVCALL(OPFVV1, vfncvt_f_f_v_w, NOP_UU_W, H4, H8, float64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_f_v_h, 2, 2, clearh)
-GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4, clearl)
+RVVCALL(OPFVV1, vfncvt_f_f_w_h, NOP_UU_H, H2, H4, vfncvtffv16)
+RVVCALL(OPFVV1, vfncvt_f_f_w_w, NOP_UU_W, H4, H8, float64_to_float32)
+GEN_VEXT_V_ENV(vfncvt_f_f_w_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4, 4, clearl)
+
+/*
+ * vfncvt.rod.f.f.w vd, vs2, vm
+ * Convert double-width float to single-width float, rounding towards odd.
+ */
+static uint16_t vfncvtffv16_rod(uint32_t a, float_status * s)
+{
+ s->float_rounding_mode = float_round_to_odd;
+ return float32_to_float16(a, true, s);
+}
+
+FCVT_ROD_F_F(float64, float32)
+RVVCALL(OPFVV1, vfncvt_rod_f_f_w_h, NOP_UU_H, H2, H4, vfncvtffv16_rod)
+RVVCALL(OPFVV1, vfncvt_rod_f_f_w_w, NOP_UU_W, H4, H8, float64_to_float32_rod)
+GEN_VEXT_V_ENV(vfncvt_rod_f_f_w_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfncvt_rod_f_f_w_w, 4, 4, clearl)
+
+/*
+ * vfncvt.rtz.xu.f.w vd, vs2, vm
+ * Convert double-width float to unsigned integer, truncating.
+ */
+FCVT_RTZ_F_V(float16, uint8)
+FCVT_RTZ_F_V(float32, uint16)
+FCVT_RTZ_F_V(float64, uint32)
+RVVCALL(OPFVV1, vfncvt_rtz_xu_f_w_b, NOP_UU_B, H1, H2, float16_to_uint8_rtz)
+RVVCALL(OPFVV1, vfncvt_rtz_xu_f_w_h, NOP_UU_H, H2, H4, float32_to_uint16_rtz)
+RVVCALL(OPFVV1, vfncvt_rtz_xu_f_w_w, NOP_UU_W, H4, H8, float64_to_uint32_rtz)
+GEN_VEXT_V_ENV(vfncvt_rtz_xu_f_w_b, 1, 1, clearb)
+GEN_VEXT_V_ENV(vfncvt_rtz_xu_f_w_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfncvt_rtz_xu_f_w_w, 4, 4, clearl)
+
+/*
+ * vfncvt.rtz.x.f.w vd, vs2, vm
+ * Convert double-width float to signed integer, truncating.
+ */
+FCVT_RTZ_F_V(float16, int8)
+FCVT_RTZ_F_V(float32, int16)
+FCVT_RTZ_F_V(float64, int32)
+RVVCALL(OPFVV1, vfncvt_rtz_x_f_w_b, NOP_UU_B, H1, H2, float16_to_int8_rtz)
+RVVCALL(OPFVV1, vfncvt_rtz_x_f_w_h, NOP_UU_H, H2, H4, float32_to_int16_rtz)
+RVVCALL(OPFVV1, vfncvt_rtz_x_f_w_w, NOP_UU_W, H4, H8, float64_to_int32_rtz)
+GEN_VEXT_V_ENV(vfncvt_rtz_x_f_w_b, 1, 1, clearb)
+GEN_VEXT_V_ENV(vfncvt_rtz_x_f_w_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfncvt_rtz_x_f_w_w, 4, 4, clearl)
/*
*** Vector Reduction Operations
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 59/65] target/riscv: rvv-0.9: narrowing floating-point/integer type-convert
@ 2020-07-10 10:49 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 30 +++++---
target/riscv/insn32.decode | 15 ++--
target/riscv/insn_trans/trans_rvv.inc.c | 50 +++++++++++--
target/riscv/vector_helper.c | 99 ++++++++++++++++++++-----
4 files changed, 154 insertions(+), 40 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 0cd5979288..f8c657737f 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -990,16 +990,26 @@ DEF_HELPER_5(vfwcvt_rtz_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_rtz_x_f_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_rtz_x_f_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_x_f_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_x_f_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_x_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_f_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_xu_f_w_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_xu_f_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_xu_f_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_x_f_w_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_x_f_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_x_f_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_xu_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_xu_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_x_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_x_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_f_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_f_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_rod_f_f_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_rod_f_f_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_rtz_xu_f_w_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_rtz_xu_f_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_rtz_xu_f_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_rtz_x_f_w_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_rtz_x_f_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_rtz_x_f_w_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 55d7a6f338..17350227c6 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -553,11 +553,16 @@ vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm
vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm
vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm
vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm
-vfncvt_xu_f_v 100010 . ..... 10000 001 ..... 1010111 @r2_vm
-vfncvt_x_f_v 100010 . ..... 10001 001 ..... 1010111 @r2_vm
-vfncvt_f_xu_v 100010 . ..... 10010 001 ..... 1010111 @r2_vm
-vfncvt_f_x_v 100010 . ..... 10011 001 ..... 1010111 @r2_vm
-vfncvt_f_f_v 100010 . ..... 10100 001 ..... 1010111 @r2_vm
+
+vfncvt_xu_f_w 010010 . ..... 10000 001 ..... 1010111 @r2_vm
+vfncvt_x_f_w 010010 . ..... 10001 001 ..... 1010111 @r2_vm
+vfncvt_f_xu_w 010010 . ..... 10010 001 ..... 1010111 @r2_vm
+vfncvt_f_x_w 010010 . ..... 10011 001 ..... 1010111 @r2_vm
+vfncvt_f_f_w 010010 . ..... 10100 001 ..... 1010111 @r2_vm
+vfncvt_rod_f_f_w 010010 . ..... 10101 001 ..... 1010111 @r2_vm
+vfncvt_rtz_xu_f_w 010010 . ..... 10110 001 ..... 1010111 @r2_vm
+vfncvt_rtz_x_f_w 010010 . ..... 10111 001 ..... 1010111 @r2_vm
+
vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm
vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm
vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 4840200f01..dffe554966 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2761,11 +2761,51 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
return false; \
}
-GEN_OPFV_NARROW_TRANS(vfncvt_xu_f_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_x_f_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_f_x_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v)
+GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_w)
+GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w)
+GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w)
+GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w)
+
+static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
+{
+ REQUIRE_RVV;
+ VEXT_CHECK_ISA_ILL(s);
+ /* OPFV narrowing instructions ignore vs1 check */
+ VEXT_CHECK_SDS(s, a->rd, 0, a->rs2, a->vm, false);
+ return true;
+}
+
+#define GEN_OPXFV_NARROW_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+ if (opxfv_narrow_check(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_gvec_3_ptr * const fns[3] = { \
+ gen_helper_##NAME##_b, \
+ gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, \
+ }; \
+ TCGLabel *over = gen_new_label(); \
+ gen_set_rm(s, 7); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs2), cpu_env, 0, \
+ s->vlen / 8, data, fns[s->sew]); \
+ gen_set_label(over); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_OPXFV_NARROW_TRANS(vfncvt_xu_f_w)
+GEN_OPXFV_NARROW_TRANS(vfncvt_x_f_w)
+GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_xu_f_w)
+GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_x_f_w)
/*
*** Vector Reduction Operations
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 0b6dd4c93f..aac055c6b6 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4265,6 +4265,16 @@ static DTYPE##_t STYPE##_to_##DTYPE##_rtz(STYPE a, float_status * s) \
return result; \
}
+#define FCVT_ROD_F_F(STYPE, DTYPE) \
+static DTYPE STYPE##_to_##DTYPE##_rod(STYPE a, float_status * s) \
+{ \
+ signed char frm = s->float_rounding_mode; \
+ s->float_rounding_mode = float_round_to_odd; \
+ DTYPE result = STYPE##_to_##DTYPE(a, s); \
+ s->float_rounding_mode = frm; \
+ return result; \
+}
+
/*
* vfcvt.rtz.xu.f.v vd, vs2, vm
* Convert float to unsigned integer, truncating.
@@ -4364,31 +4374,36 @@ GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8, clearq)
/* Narrowing Floating-Point/Integer Type-Convert Instructions */
/* (TD, T2, TX2) */
+#define NOP_UU_B uint8_t, uint16_t, uint32_t
#define NOP_UU_H uint16_t, uint32_t, uint32_t
#define NOP_UU_W uint32_t, uint64_t, uint64_t
/* vfncvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */
-RVVCALL(OPFVV1, vfncvt_xu_f_v_h, NOP_UU_H, H2, H4, float32_to_uint16)
-RVVCALL(OPFVV1, vfncvt_xu_f_v_w, NOP_UU_W, H4, H8, float64_to_uint32)
-GEN_VEXT_V_ENV(vfncvt_xu_f_v_h, 2, 2, clearh)
-GEN_VEXT_V_ENV(vfncvt_xu_f_v_w, 4, 4, clearl)
+RVVCALL(OPFVV1, vfncvt_xu_f_w_b, NOP_UU_B, H1, H2, float16_to_uint8)
+RVVCALL(OPFVV1, vfncvt_xu_f_w_h, NOP_UU_H, H2, H4, float32_to_uint16)
+RVVCALL(OPFVV1, vfncvt_xu_f_w_w, NOP_UU_W, H4, H8, float64_to_uint32)
+GEN_VEXT_V_ENV(vfncvt_xu_f_w_b, 1, 1, clearb)
+GEN_VEXT_V_ENV(vfncvt_xu_f_w_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfncvt_xu_f_w_w, 4, 4, clearl)
/* vfncvt.x.f.v vd, vs2, vm # Convert double-width float to signed integer. */
-RVVCALL(OPFVV1, vfncvt_x_f_v_h, NOP_UU_H, H2, H4, float32_to_int16)
-RVVCALL(OPFVV1, vfncvt_x_f_v_w, NOP_UU_W, H4, H8, float64_to_int32)
-GEN_VEXT_V_ENV(vfncvt_x_f_v_h, 2, 2, clearh)
-GEN_VEXT_V_ENV(vfncvt_x_f_v_w, 4, 4, clearl)
+RVVCALL(OPFVV1, vfncvt_x_f_w_b, NOP_UU_B, H1, H2, float16_to_int8)
+RVVCALL(OPFVV1, vfncvt_x_f_w_h, NOP_UU_H, H2, H4, float32_to_int16)
+RVVCALL(OPFVV1, vfncvt_x_f_w_w, NOP_UU_W, H4, H8, float64_to_int32)
+GEN_VEXT_V_ENV(vfncvt_x_f_w_b, 1, 1, clearb)
+GEN_VEXT_V_ENV(vfncvt_x_f_w_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfncvt_x_f_w_w, 4, 4, clearl)
/* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to float */
-RVVCALL(OPFVV1, vfncvt_f_xu_v_h, NOP_UU_H, H2, H4, uint32_to_float16)
-RVVCALL(OPFVV1, vfncvt_f_xu_v_w, NOP_UU_W, H4, H8, uint64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_xu_v_h, 2, 2, clearh)
-GEN_VEXT_V_ENV(vfncvt_f_xu_v_w, 4, 4, clearl)
+RVVCALL(OPFVV1, vfncvt_f_xu_w_h, NOP_UU_H, H2, H4, uint32_to_float16)
+RVVCALL(OPFVV1, vfncvt_f_xu_w_w, NOP_UU_W, H4, H8, uint64_to_float32)
+GEN_VEXT_V_ENV(vfncvt_f_xu_w_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfncvt_f_xu_w_w, 4, 4, clearl)
/* vfncvt.f.x.v vd, vs2, vm # Convert double-width integer to float. */
-RVVCALL(OPFVV1, vfncvt_f_x_v_h, NOP_UU_H, H2, H4, int32_to_float16)
-RVVCALL(OPFVV1, vfncvt_f_x_v_w, NOP_UU_W, H4, H8, int64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_x_v_h, 2, 2, clearh)
-GEN_VEXT_V_ENV(vfncvt_f_x_v_w, 4, 4, clearl)
+RVVCALL(OPFVV1, vfncvt_f_x_w_h, NOP_UU_H, H2, H4, int32_to_float16)
+RVVCALL(OPFVV1, vfncvt_f_x_w_w, NOP_UU_W, H4, H8, int64_to_float32)
+GEN_VEXT_V_ENV(vfncvt_f_x_w_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfncvt_f_x_w_w, 4, 4, clearl)
/* vfncvt.f.f.v vd, vs2, vm # Convert double float to single-width float. */
static uint16_t vfncvtffv16(uint32_t a, float_status *s)
@@ -4396,10 +4411,54 @@ static uint16_t vfncvtffv16(uint32_t a, float_status *s)
return float32_to_float16(a, true, s);
}
-RVVCALL(OPFVV1, vfncvt_f_f_v_h, NOP_UU_H, H2, H4, vfncvtffv16)
-RVVCALL(OPFVV1, vfncvt_f_f_v_w, NOP_UU_W, H4, H8, float64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_f_v_h, 2, 2, clearh)
-GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4, clearl)
+RVVCALL(OPFVV1, vfncvt_f_f_w_h, NOP_UU_H, H2, H4, vfncvtffv16)
+RVVCALL(OPFVV1, vfncvt_f_f_w_w, NOP_UU_W, H4, H8, float64_to_float32)
+GEN_VEXT_V_ENV(vfncvt_f_f_w_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4, 4, clearl)
+
+/*
+ * vfncvt.rod.f.f.w vd, vs2, vm
+ * Convert double-width float to single-width float, rounding towards odd.
+ */
+static uint16_t vfncvtffv16_rod(uint32_t a, float_status * s)
+{
+ s->float_rounding_mode = float_round_to_odd;
+ return float32_to_float16(a, true, s);
+}
+
+FCVT_ROD_F_F(float64, float32)
+RVVCALL(OPFVV1, vfncvt_rod_f_f_w_h, NOP_UU_H, H2, H4, vfncvtffv16_rod)
+RVVCALL(OPFVV1, vfncvt_rod_f_f_w_w, NOP_UU_W, H4, H8, float64_to_float32_rod)
+GEN_VEXT_V_ENV(vfncvt_rod_f_f_w_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfncvt_rod_f_f_w_w, 4, 4, clearl)
+
+/*
+ * vfncvt.rtz.xu.f.w vd, vs2, vm
+ * Convert double-width float to unsigned integer, truncating.
+ */
+FCVT_RTZ_F_V(float16, uint8)
+FCVT_RTZ_F_V(float32, uint16)
+FCVT_RTZ_F_V(float64, uint32)
+RVVCALL(OPFVV1, vfncvt_rtz_xu_f_w_b, NOP_UU_B, H1, H2, float16_to_uint8_rtz)
+RVVCALL(OPFVV1, vfncvt_rtz_xu_f_w_h, NOP_UU_H, H2, H4, float32_to_uint16_rtz)
+RVVCALL(OPFVV1, vfncvt_rtz_xu_f_w_w, NOP_UU_W, H4, H8, float64_to_uint32_rtz)
+GEN_VEXT_V_ENV(vfncvt_rtz_xu_f_w_b, 1, 1, clearb)
+GEN_VEXT_V_ENV(vfncvt_rtz_xu_f_w_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfncvt_rtz_xu_f_w_w, 4, 4, clearl)
+
+/*
+ * vfncvt.rtz.x.f.w vd, vs2, vm
+ * Convert double-width float to signed integer, truncating.
+ */
+FCVT_RTZ_F_V(float16, int8)
+FCVT_RTZ_F_V(float32, int16)
+FCVT_RTZ_F_V(float64, int32)
+RVVCALL(OPFVV1, vfncvt_rtz_x_f_w_b, NOP_UU_B, H1, H2, float16_to_int8_rtz)
+RVVCALL(OPFVV1, vfncvt_rtz_x_f_w_h, NOP_UU_H, H2, H4, float32_to_int16_rtz)
+RVVCALL(OPFVV1, vfncvt_rtz_x_f_w_w, NOP_UU_W, H4, H8, float64_to_int32_rtz)
+GEN_VEXT_V_ENV(vfncvt_rtz_x_f_w_b, 1, 1, clearb)
+GEN_VEXT_V_ENV(vfncvt_rtz_x_f_w_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfncvt_rtz_x_f_w_w, 4, 4, clearl)
/*
*** Vector Reduction Operations
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:49 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Peter Maydell, Alex Bennée, Aurelien Jarno
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
fpu/softfloat.c | 34 ++++++++++++++++++++++++++++++++++
include/fpu/softfloat.h | 8 ++++++++
2 files changed, 42 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 79be4f5840..fa1c99c03e 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -2109,6 +2109,13 @@ static int64_t round_to_int_and_pack(FloatParts in, FloatRoundMode rmode,
}
}
+int8_t float16_to_int8_scalbn(float16 a, FloatRoundMode rmode, int scale,
+ float_status *s)
+{
+ return round_to_int_and_pack(float16_unpack_canonical(a, s),
+ rmode, scale, INT8_MIN, INT8_MAX, s);
+}
+
int16_t float16_to_int16_scalbn(float16 a, FloatRoundMode rmode, int scale,
float_status *s)
{
@@ -2172,6 +2179,11 @@ int64_t float64_to_int64_scalbn(float64 a, FloatRoundMode rmode, int scale,
rmode, scale, INT64_MIN, INT64_MAX, s);
}
+int8_t float16_to_int8(float16 a, float_status *s)
+{
+ return float16_to_int8_scalbn(a, s->float_rounding_mode, 0, s);
+}
+
int16_t float16_to_int16(float16 a, float_status *s)
{
return float16_to_int16_scalbn(a, s->float_rounding_mode, 0, s);
@@ -2322,6 +2334,13 @@ static uint64_t round_to_uint_and_pack(FloatParts in, FloatRoundMode rmode,
}
}
+uint8_t float16_to_uint8_scalbn(float16 a, FloatRoundMode rmode, int scale,
+ float_status *s)
+{
+ return round_to_uint_and_pack(float16_unpack_canonical(a, s),
+ rmode, scale, UINT8_MAX, s);
+}
+
uint16_t float16_to_uint16_scalbn(float16 a, FloatRoundMode rmode, int scale,
float_status *s)
{
@@ -2385,6 +2404,11 @@ uint64_t float64_to_uint64_scalbn(float64 a, FloatRoundMode rmode, int scale,
rmode, scale, UINT64_MAX, s);
}
+uint8_t float16_to_uint8(float16 a, float_status *s)
+{
+ return float16_to_uint8_scalbn(a, s->float_rounding_mode, 0, s);
+}
+
uint16_t float16_to_uint16(float16 a, float_status *s)
{
return float16_to_uint16_scalbn(a, s->float_rounding_mode, 0, s);
@@ -2539,6 +2563,11 @@ float16 int16_to_float16(int16_t a, float_status *status)
return int64_to_float16_scalbn(a, 0, status);
}
+float16 int8_to_float16(int8_t a, float_status *status)
+{
+ return int64_to_float16_scalbn(a, 0, status);
+}
+
float32 int64_to_float32_scalbn(int64_t a, int scale, float_status *status)
{
FloatParts pa = int_to_float(a, scale, status);
@@ -2664,6 +2693,11 @@ float16 uint16_to_float16(uint16_t a, float_status *status)
return uint64_to_float16_scalbn(a, 0, status);
}
+float16 uint8_to_float16(uint8_t a, float_status *status)
+{
+ return uint64_to_float16_scalbn(a, 0, status);
+}
+
float32 uint64_to_float32_scalbn(uint64_t a, int scale, float_status *status)
{
FloatParts pa = uint_to_float(a, scale, status);
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index ff4e2605b1..b0ae8f6295 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -136,9 +136,11 @@ float16 uint16_to_float16_scalbn(uint16_t a, int, float_status *status);
float16 uint32_to_float16_scalbn(uint32_t a, int, float_status *status);
float16 uint64_to_float16_scalbn(uint64_t a, int, float_status *status);
+float16 int8_to_float16(int8_t a, float_status *status);
float16 int16_to_float16(int16_t a, float_status *status);
float16 int32_to_float16(int32_t a, float_status *status);
float16 int64_to_float16(int64_t a, float_status *status);
+float16 uint8_to_float16(uint8_t a, float_status *status);
float16 uint16_to_float16(uint16_t a, float_status *status);
float16 uint32_to_float16(uint32_t a, float_status *status);
float16 uint64_to_float16(uint64_t a, float_status *status);
@@ -187,10 +189,13 @@ float32 float16_to_float32(float16, bool ieee, float_status *status);
float16 float64_to_float16(float64 a, bool ieee, float_status *status);
float64 float16_to_float64(float16 a, bool ieee, float_status *status);
+int8_t float16_to_int8_scalbn(float16, FloatRoundMode, int,
+ float_status *status);
int16_t float16_to_int16_scalbn(float16, FloatRoundMode, int, float_status *);
int32_t float16_to_int32_scalbn(float16, FloatRoundMode, int, float_status *);
int64_t float16_to_int64_scalbn(float16, FloatRoundMode, int, float_status *);
+int8_t float16_to_int8(float16, float_status *status);
int16_t float16_to_int16(float16, float_status *status);
int32_t float16_to_int32(float16, float_status *status);
int64_t float16_to_int64(float16, float_status *status);
@@ -199,6 +204,8 @@ int16_t float16_to_int16_round_to_zero(float16, float_status *status);
int32_t float16_to_int32_round_to_zero(float16, float_status *status);
int64_t float16_to_int64_round_to_zero(float16, float_status *status);
+uint8_t float16_to_uint8_scalbn(float16 a, FloatRoundMode,
+ int, float_status *status);
uint16_t float16_to_uint16_scalbn(float16 a, FloatRoundMode,
int, float_status *status);
uint32_t float16_to_uint32_scalbn(float16 a, FloatRoundMode,
@@ -206,6 +213,7 @@ uint32_t float16_to_uint32_scalbn(float16 a, FloatRoundMode,
uint64_t float16_to_uint64_scalbn(float16 a, FloatRoundMode,
int, float_status *status);
+uint8_t float16_to_uint8(float16 a, float_status *status);
uint16_t float16_to_uint16(float16 a, float_status *status);
uint32_t float16_to_uint32(float16 a, float_status *status);
uint64_t float16_to_uint64(float16 a, float_status *status);
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions
@ 2020-07-10 10:49 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Aurelien Jarno, Peter Maydell, Alex Bennée
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
fpu/softfloat.c | 34 ++++++++++++++++++++++++++++++++++
include/fpu/softfloat.h | 8 ++++++++
2 files changed, 42 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 79be4f5840..fa1c99c03e 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -2109,6 +2109,13 @@ static int64_t round_to_int_and_pack(FloatParts in, FloatRoundMode rmode,
}
}
+int8_t float16_to_int8_scalbn(float16 a, FloatRoundMode rmode, int scale,
+ float_status *s)
+{
+ return round_to_int_and_pack(float16_unpack_canonical(a, s),
+ rmode, scale, INT8_MIN, INT8_MAX, s);
+}
+
int16_t float16_to_int16_scalbn(float16 a, FloatRoundMode rmode, int scale,
float_status *s)
{
@@ -2172,6 +2179,11 @@ int64_t float64_to_int64_scalbn(float64 a, FloatRoundMode rmode, int scale,
rmode, scale, INT64_MIN, INT64_MAX, s);
}
+int8_t float16_to_int8(float16 a, float_status *s)
+{
+ return float16_to_int8_scalbn(a, s->float_rounding_mode, 0, s);
+}
+
int16_t float16_to_int16(float16 a, float_status *s)
{
return float16_to_int16_scalbn(a, s->float_rounding_mode, 0, s);
@@ -2322,6 +2334,13 @@ static uint64_t round_to_uint_and_pack(FloatParts in, FloatRoundMode rmode,
}
}
+uint8_t float16_to_uint8_scalbn(float16 a, FloatRoundMode rmode, int scale,
+ float_status *s)
+{
+ return round_to_uint_and_pack(float16_unpack_canonical(a, s),
+ rmode, scale, UINT8_MAX, s);
+}
+
uint16_t float16_to_uint16_scalbn(float16 a, FloatRoundMode rmode, int scale,
float_status *s)
{
@@ -2385,6 +2404,11 @@ uint64_t float64_to_uint64_scalbn(float64 a, FloatRoundMode rmode, int scale,
rmode, scale, UINT64_MAX, s);
}
+uint8_t float16_to_uint8(float16 a, float_status *s)
+{
+ return float16_to_uint8_scalbn(a, s->float_rounding_mode, 0, s);
+}
+
uint16_t float16_to_uint16(float16 a, float_status *s)
{
return float16_to_uint16_scalbn(a, s->float_rounding_mode, 0, s);
@@ -2539,6 +2563,11 @@ float16 int16_to_float16(int16_t a, float_status *status)
return int64_to_float16_scalbn(a, 0, status);
}
+float16 int8_to_float16(int8_t a, float_status *status)
+{
+ return int64_to_float16_scalbn(a, 0, status);
+}
+
float32 int64_to_float32_scalbn(int64_t a, int scale, float_status *status)
{
FloatParts pa = int_to_float(a, scale, status);
@@ -2664,6 +2693,11 @@ float16 uint16_to_float16(uint16_t a, float_status *status)
return uint64_to_float16_scalbn(a, 0, status);
}
+float16 uint8_to_float16(uint8_t a, float_status *status)
+{
+ return uint64_to_float16_scalbn(a, 0, status);
+}
+
float32 uint64_to_float32_scalbn(uint64_t a, int scale, float_status *status)
{
FloatParts pa = uint_to_float(a, scale, status);
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index ff4e2605b1..b0ae8f6295 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -136,9 +136,11 @@ float16 uint16_to_float16_scalbn(uint16_t a, int, float_status *status);
float16 uint32_to_float16_scalbn(uint32_t a, int, float_status *status);
float16 uint64_to_float16_scalbn(uint64_t a, int, float_status *status);
+float16 int8_to_float16(int8_t a, float_status *status);
float16 int16_to_float16(int16_t a, float_status *status);
float16 int32_to_float16(int32_t a, float_status *status);
float16 int64_to_float16(int64_t a, float_status *status);
+float16 uint8_to_float16(uint8_t a, float_status *status);
float16 uint16_to_float16(uint16_t a, float_status *status);
float16 uint32_to_float16(uint32_t a, float_status *status);
float16 uint64_to_float16(uint64_t a, float_status *status);
@@ -187,10 +189,13 @@ float32 float16_to_float32(float16, bool ieee, float_status *status);
float16 float64_to_float16(float64 a, bool ieee, float_status *status);
float64 float16_to_float64(float16 a, bool ieee, float_status *status);
+int8_t float16_to_int8_scalbn(float16, FloatRoundMode, int,
+ float_status *status);
int16_t float16_to_int16_scalbn(float16, FloatRoundMode, int, float_status *);
int32_t float16_to_int32_scalbn(float16, FloatRoundMode, int, float_status *);
int64_t float16_to_int64_scalbn(float16, FloatRoundMode, int, float_status *);
+int8_t float16_to_int8(float16, float_status *status);
int16_t float16_to_int16(float16, float_status *status);
int32_t float16_to_int32(float16, float_status *status);
int64_t float16_to_int64(float16, float_status *status);
@@ -199,6 +204,8 @@ int16_t float16_to_int16_round_to_zero(float16, float_status *status);
int32_t float16_to_int32_round_to_zero(float16, float_status *status);
int64_t float16_to_int64_round_to_zero(float16, float_status *status);
+uint8_t float16_to_uint8_scalbn(float16 a, FloatRoundMode,
+ int, float_status *status);
uint16_t float16_to_uint16_scalbn(float16 a, FloatRoundMode,
int, float_status *status);
uint32_t float16_to_uint32_scalbn(float16 a, FloatRoundMode,
@@ -206,6 +213,7 @@ uint32_t float16_to_uint32_scalbn(float16 a, FloatRoundMode,
uint64_t float16_to_uint64_scalbn(float16 a, FloatRoundMode,
int, float_status *status);
+uint8_t float16_to_uint8(float16 a, float_status *status);
uint16_t float16_to_uint16(float16 a, float_status *status);
uint32_t float16_to_uint32(float16 a, float_status *status);
uint64_t float16_to_uint64(float16 a, float_status *status);
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 61/65] fpu: fix float16 nan check
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:49 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Chih-Min Chao, Alex Bennée, Aurelien Jarno,
Peter Maydell
From: Chih-Min Chao <chihmin.chao@sifive.com>
16 15 10 0
|sign | exp | mantissa |
qNaN x 11111 1x_xxxx_xxxx
The mask should check exp + msb of mantissa
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
fpu/softfloat-specialize.inc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/fpu/softfloat-specialize.inc.c b/fpu/softfloat-specialize.inc.c
index 44f5b661f8..fe7a5e79e4 100644
--- a/fpu/softfloat-specialize.inc.c
+++ b/fpu/softfloat-specialize.inc.c
@@ -254,7 +254,7 @@ bool float16_is_quiet_nan(float16 a_, float_status *status)
if (snan_bit_is_one(status)) {
return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
} else {
- return ((a & ~0x8000) >= 0x7C80);
+ return ((a & ~0x8000) >= 0x7E00);
}
#endif
}
@@ -271,7 +271,7 @@ bool float16_is_signaling_nan(float16 a_, float_status *status)
#else
uint16_t a = float16_val(a_);
if (snan_bit_is_one(status)) {
- return ((a & ~0x8000) >= 0x7C80);
+ return ((a & ~0x8000) >= 0x7E00);
} else {
return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
}
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 61/65] fpu: fix float16 nan check
@ 2020-07-10 10:49 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Chih-Min Chao, Frank Chang, Aurelien Jarno, Peter Maydell,
Alex Bennée
From: Chih-Min Chao <chihmin.chao@sifive.com>
16 15 10 0
|sign | exp | mantissa |
qNaN x 11111 1x_xxxx_xxxx
The mask should check exp + msb of mantissa
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
fpu/softfloat-specialize.inc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/fpu/softfloat-specialize.inc.c b/fpu/softfloat-specialize.inc.c
index 44f5b661f8..fe7a5e79e4 100644
--- a/fpu/softfloat-specialize.inc.c
+++ b/fpu/softfloat-specialize.inc.c
@@ -254,7 +254,7 @@ bool float16_is_quiet_nan(float16 a_, float_status *status)
if (snan_bit_is_one(status)) {
return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
} else {
- return ((a & ~0x8000) >= 0x7C80);
+ return ((a & ~0x8000) >= 0x7E00);
}
#endif
}
@@ -271,7 +271,7 @@ bool float16_is_signaling_nan(float16 a_, float_status *status)
#else
uint16_t a = float16_val(a_);
if (snan_bit_is_one(status)) {
- return ((a & ~0x8000) >= 0x7C80);
+ return ((a & ~0x8000) >= 0x7E00);
} else {
return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
}
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 62/65] fpu: add api to handle alternative sNaN propagation
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:49 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Chih-Min Chao, Alex Bennée, Aurelien Jarno,
Peter Maydell
From: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
fpu/softfloat.c | 68 +++++++++++++++++++++++++----------------
include/fpu/softfloat.h | 6 ++++
2 files changed, 48 insertions(+), 26 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index fa1c99c03e..028b857167 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -2777,23 +2777,32 @@ float64 uint16_to_float64(uint16_t a, float_status *status)
* and minNumMag() from the IEEE-754 2008.
*/
static FloatParts minmax_floats(FloatParts a, FloatParts b, bool ismin,
- bool ieee, bool ismag, float_status *s)
+ bool ieee, bool ismag, bool issnan_prop,
+ float_status *s)
{
if (unlikely(is_nan(a.cls) || is_nan(b.cls))) {
if (ieee) {
/* Takes two floating-point values `a' and `b', one of
* which is a NaN, and returns the appropriate NaN
* result. If either `a' or `b' is a signaling NaN,
- * the invalid exception is raised.
+ * the invalid exception is raised but the NaN
+ * propagation is 'shall'.
*/
if (is_snan(a.cls) || is_snan(b.cls)) {
- return pick_nan(a, b, s);
- } else if (is_nan(a.cls) && !is_nan(b.cls)) {
+ if (issnan_prop) {
+ pick_nan(a, b, s);
+ } else {
+ return pick_nan(a, b, s);
+ }
+ }
+
+ if (is_nan(a.cls) && !is_nan(b.cls)) {
return b;
} else if (is_nan(b.cls) && !is_nan(a.cls)) {
return a;
}
}
+
return pick_nan(a, b, s);
} else {
int a_exp, b_exp;
@@ -2847,37 +2856,44 @@ static FloatParts minmax_floats(FloatParts a, FloatParts b, bool ismin,
}
}
-#define MINMAX(sz, name, ismin, isiee, ismag) \
+#define MINMAX(sz, name, ismin, isiee, ismag, issnan_prop) \
float ## sz float ## sz ## _ ## name(float ## sz a, float ## sz b, \
float_status *s) \
{ \
FloatParts pa = float ## sz ## _unpack_canonical(a, s); \
FloatParts pb = float ## sz ## _unpack_canonical(b, s); \
- FloatParts pr = minmax_floats(pa, pb, ismin, isiee, ismag, s); \
+ FloatParts pr = minmax_floats(pa, pb, ismin, isiee, ismag, \
+ issnan_prop, s); \
\
return float ## sz ## _round_pack_canonical(pr, s); \
}
-MINMAX(16, min, true, false, false)
-MINMAX(16, minnum, true, true, false)
-MINMAX(16, minnummag, true, true, true)
-MINMAX(16, max, false, false, false)
-MINMAX(16, maxnum, false, true, false)
-MINMAX(16, maxnummag, false, true, true)
-
-MINMAX(32, min, true, false, false)
-MINMAX(32, minnum, true, true, false)
-MINMAX(32, minnummag, true, true, true)
-MINMAX(32, max, false, false, false)
-MINMAX(32, maxnum, false, true, false)
-MINMAX(32, maxnummag, false, true, true)
-
-MINMAX(64, min, true, false, false)
-MINMAX(64, minnum, true, true, false)
-MINMAX(64, minnummag, true, true, true)
-MINMAX(64, max, false, false, false)
-MINMAX(64, maxnum, false, true, false)
-MINMAX(64, maxnummag, false, true, true)
+MINMAX(16, min, true, false, false, false)
+MINMAX(16, minnum, true, true, false, false)
+MINMAX(16, minnum_noprop, true, true, false, true)
+MINMAX(16, minnummag, true, true, true, false)
+MINMAX(16, max, false, false, false, false)
+MINMAX(16, maxnum, false, true, false, false)
+MINMAX(16, maxnum_noprop, false, true, false, true)
+MINMAX(16, maxnummag, false, true, true, false)
+
+MINMAX(32, min, true, false, false, false)
+MINMAX(32, minnum, true, true, false, false)
+MINMAX(32, minnum_noprop, true, true, false, true)
+MINMAX(32, minnummag, true, true, true, false)
+MINMAX(32, max, false, false, false, false)
+MINMAX(32, maxnum, false, true, false, false)
+MINMAX(32, maxnum_noprop, false, true, false, true)
+MINMAX(32, maxnummag, false, true, true, false)
+
+MINMAX(64, min, true, false, false, false)
+MINMAX(64, minnum, true, true, false, false)
+MINMAX(64, minnum_noprop, true, true, false, true)
+MINMAX(64, minnummag, true, true, true, false)
+MINMAX(64, max, false, false, false, false)
+MINMAX(64, maxnum, false, true, false, false)
+MINMAX(64, maxnum_noprop, false, true, false, true)
+MINMAX(64, maxnummag, false, true, true, false)
#undef MINMAX
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index b0ae8f6295..075c680456 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -239,6 +239,8 @@ float16 float16_minnum(float16, float16, float_status *status);
float16 float16_maxnum(float16, float16, float_status *status);
float16 float16_minnummag(float16, float16, float_status *status);
float16 float16_maxnummag(float16, float16, float_status *status);
+float16 float16_minnum_noprop(float16, float16, float_status *status);
+float16 float16_maxnum_noprop(float16, float16, float_status *status);
float16 float16_sqrt(float16, float_status *status);
FloatRelation float16_compare(float16, float16, float_status *status);
FloatRelation float16_compare_quiet(float16, float16, float_status *status);
@@ -359,6 +361,8 @@ float32 float32_minnum(float32, float32, float_status *status);
float32 float32_maxnum(float32, float32, float_status *status);
float32 float32_minnummag(float32, float32, float_status *status);
float32 float32_maxnummag(float32, float32, float_status *status);
+float32 float32_minnum_noprop(float32, float32, float_status *status);
+float32 float32_maxnum_noprop(float32, float32, float_status *status);
bool float32_is_quiet_nan(float32, float_status *status);
bool float32_is_signaling_nan(float32, float_status *status);
float32 float32_silence_nan(float32, float_status *status);
@@ -548,6 +552,8 @@ float64 float64_minnum(float64, float64, float_status *status);
float64 float64_maxnum(float64, float64, float_status *status);
float64 float64_minnummag(float64, float64, float_status *status);
float64 float64_maxnummag(float64, float64, float_status *status);
+float64 float64_minnum_noprop(float64, float64, float_status *status);
+float64 float64_maxnum_noprop(float64, float64, float_status *status);
bool float64_is_quiet_nan(float64 a, float_status *status);
bool float64_is_signaling_nan(float64, float_status *status);
float64 float64_silence_nan(float64, float_status *status);
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 62/65] fpu: add api to handle alternative sNaN propagation
@ 2020-07-10 10:49 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Chih-Min Chao, Frank Chang, Aurelien Jarno, Peter Maydell,
Alex Bennée
From: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
fpu/softfloat.c | 68 +++++++++++++++++++++++++----------------
include/fpu/softfloat.h | 6 ++++
2 files changed, 48 insertions(+), 26 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index fa1c99c03e..028b857167 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -2777,23 +2777,32 @@ float64 uint16_to_float64(uint16_t a, float_status *status)
* and minNumMag() from the IEEE-754 2008.
*/
static FloatParts minmax_floats(FloatParts a, FloatParts b, bool ismin,
- bool ieee, bool ismag, float_status *s)
+ bool ieee, bool ismag, bool issnan_prop,
+ float_status *s)
{
if (unlikely(is_nan(a.cls) || is_nan(b.cls))) {
if (ieee) {
/* Takes two floating-point values `a' and `b', one of
* which is a NaN, and returns the appropriate NaN
* result. If either `a' or `b' is a signaling NaN,
- * the invalid exception is raised.
+ * the invalid exception is raised but the NaN
+ * propagation is 'shall'.
*/
if (is_snan(a.cls) || is_snan(b.cls)) {
- return pick_nan(a, b, s);
- } else if (is_nan(a.cls) && !is_nan(b.cls)) {
+ if (issnan_prop) {
+ pick_nan(a, b, s);
+ } else {
+ return pick_nan(a, b, s);
+ }
+ }
+
+ if (is_nan(a.cls) && !is_nan(b.cls)) {
return b;
} else if (is_nan(b.cls) && !is_nan(a.cls)) {
return a;
}
}
+
return pick_nan(a, b, s);
} else {
int a_exp, b_exp;
@@ -2847,37 +2856,44 @@ static FloatParts minmax_floats(FloatParts a, FloatParts b, bool ismin,
}
}
-#define MINMAX(sz, name, ismin, isiee, ismag) \
+#define MINMAX(sz, name, ismin, isiee, ismag, issnan_prop) \
float ## sz float ## sz ## _ ## name(float ## sz a, float ## sz b, \
float_status *s) \
{ \
FloatParts pa = float ## sz ## _unpack_canonical(a, s); \
FloatParts pb = float ## sz ## _unpack_canonical(b, s); \
- FloatParts pr = minmax_floats(pa, pb, ismin, isiee, ismag, s); \
+ FloatParts pr = minmax_floats(pa, pb, ismin, isiee, ismag, \
+ issnan_prop, s); \
\
return float ## sz ## _round_pack_canonical(pr, s); \
}
-MINMAX(16, min, true, false, false)
-MINMAX(16, minnum, true, true, false)
-MINMAX(16, minnummag, true, true, true)
-MINMAX(16, max, false, false, false)
-MINMAX(16, maxnum, false, true, false)
-MINMAX(16, maxnummag, false, true, true)
-
-MINMAX(32, min, true, false, false)
-MINMAX(32, minnum, true, true, false)
-MINMAX(32, minnummag, true, true, true)
-MINMAX(32, max, false, false, false)
-MINMAX(32, maxnum, false, true, false)
-MINMAX(32, maxnummag, false, true, true)
-
-MINMAX(64, min, true, false, false)
-MINMAX(64, minnum, true, true, false)
-MINMAX(64, minnummag, true, true, true)
-MINMAX(64, max, false, false, false)
-MINMAX(64, maxnum, false, true, false)
-MINMAX(64, maxnummag, false, true, true)
+MINMAX(16, min, true, false, false, false)
+MINMAX(16, minnum, true, true, false, false)
+MINMAX(16, minnum_noprop, true, true, false, true)
+MINMAX(16, minnummag, true, true, true, false)
+MINMAX(16, max, false, false, false, false)
+MINMAX(16, maxnum, false, true, false, false)
+MINMAX(16, maxnum_noprop, false, true, false, true)
+MINMAX(16, maxnummag, false, true, true, false)
+
+MINMAX(32, min, true, false, false, false)
+MINMAX(32, minnum, true, true, false, false)
+MINMAX(32, minnum_noprop, true, true, false, true)
+MINMAX(32, minnummag, true, true, true, false)
+MINMAX(32, max, false, false, false, false)
+MINMAX(32, maxnum, false, true, false, false)
+MINMAX(32, maxnum_noprop, false, true, false, true)
+MINMAX(32, maxnummag, false, true, true, false)
+
+MINMAX(64, min, true, false, false, false)
+MINMAX(64, minnum, true, true, false, false)
+MINMAX(64, minnum_noprop, true, true, false, true)
+MINMAX(64, minnummag, true, true, true, false)
+MINMAX(64, max, false, false, false, false)
+MINMAX(64, maxnum, false, true, false, false)
+MINMAX(64, maxnum_noprop, false, true, false, true)
+MINMAX(64, maxnummag, false, true, true, false)
#undef MINMAX
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index b0ae8f6295..075c680456 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -239,6 +239,8 @@ float16 float16_minnum(float16, float16, float_status *status);
float16 float16_maxnum(float16, float16, float_status *status);
float16 float16_minnummag(float16, float16, float_status *status);
float16 float16_maxnummag(float16, float16, float_status *status);
+float16 float16_minnum_noprop(float16, float16, float_status *status);
+float16 float16_maxnum_noprop(float16, float16, float_status *status);
float16 float16_sqrt(float16, float_status *status);
FloatRelation float16_compare(float16, float16, float_status *status);
FloatRelation float16_compare_quiet(float16, float16, float_status *status);
@@ -359,6 +361,8 @@ float32 float32_minnum(float32, float32, float_status *status);
float32 float32_maxnum(float32, float32, float_status *status);
float32 float32_minnummag(float32, float32, float_status *status);
float32 float32_maxnummag(float32, float32, float_status *status);
+float32 float32_minnum_noprop(float32, float32, float_status *status);
+float32 float32_maxnum_noprop(float32, float32, float_status *status);
bool float32_is_quiet_nan(float32, float_status *status);
bool float32_is_signaling_nan(float32, float_status *status);
float32 float32_silence_nan(float32, float_status *status);
@@ -548,6 +552,8 @@ float64 float64_minnum(float64, float64, float_status *status);
float64 float64_maxnum(float64, float64, float_status *status);
float64 float64_minnummag(float64, float64, float_status *status);
float64 float64_maxnummag(float64, float64, float_status *status);
+float64 float64_minnum_noprop(float64, float64, float_status *status);
+float64 float64_maxnum_noprop(float64, float64, float_status *status);
bool float64_is_quiet_nan(float64 a, float_status *status);
bool float64_is_signaling_nan(float64, float_status *status);
float64 float64_silence_nan(float64, float_status *status);
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 63/65] fpu: implement full set compare for fp16
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:49 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Peter Maydell, Frank Chang, Chih-Min Chao, Kito Cheng,
Alex Bennée, Aurelien Jarno
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
fpu/softfloat.c | 240 ++++++++++++++++++++++++++++++++++++++++
include/fpu/softfloat.h | 8 ++
2 files changed, 248 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 028b857167..8bebea1142 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -401,6 +401,34 @@ float64_gen2(float64 xa, float64 xb, float_status *s,
return soft(ua.s, ub.s, s);
}
+/*----------------------------------------------------------------------------
+| Returns the fraction bits of the half-precision floating-point value `a'.
+*----------------------------------------------------------------------------*/
+
+static inline uint32_t extractFloat16Frac(float16 a)
+{
+ return float16_val(a) & 0x3ff;
+}
+
+/*----------------------------------------------------------------------------
+| Returns the exponent bits of the half-precision floating-point value `a'.
+*----------------------------------------------------------------------------*/
+
+static inline int extractFloat16Exp(float16 a)
+{
+ return (float16_val(a) >> 10) & 0x1f;
+}
+
+/*----------------------------------------------------------------------------
+| Returns the sign bit of the half-precision floating-point value `a'.
+*----------------------------------------------------------------------------*/
+
+static inline bool extractFloat16Sign(float16 a)
+{
+ return float16_val(a) >> 15;
+}
+
+
/*----------------------------------------------------------------------------
| Returns the fraction bits of the single-precision floating-point value `a'.
*----------------------------------------------------------------------------*/
@@ -5006,6 +5034,218 @@ float64 float64_log2(float64 a, float_status *status)
return normalizeRoundAndPackFloat64(zSign, 0x408, zSig, status);
}
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is equal to
+| the corresponding value `b', and 0 otherwise. The invalid exception is
+| raised if either operand is a NaN. Otherwise, the comparison is performed
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_eq(float16 a, float16 b, float_status *status)
+{
+ uint16_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ float_raise(float_flag_invalid, status);
+ return 0;
+ }
+ av = float16_val(a);
+ bv = float16_val(b);
+ return (av == bv) || ((uint16_t) ((av | bv) << 1) == 0);
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is less than
+| or equal to the corresponding value `b', and 0 otherwise. The invalid
+| exception is raised if either operand is a NaN. The comparison is performed
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_le(float16 a, float16 b, float_status *status)
+{
+ bool aSign, bSign;
+ uint16_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ float_raise(float_flag_invalid, status);
+ return 0;
+ }
+ aSign = extractFloat16Sign(a);
+ bSign = extractFloat16Sign(b);
+ av = float16_val(a);
+ bv = float16_val(b);
+ if (aSign != bSign) {
+ return aSign || ((uint16_t) ((av | bv) << 1) == 0);
+ }
+ return (av == bv) || (aSign ^ (av < bv));
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is less than
+| the corresponding value `b', and 0 otherwise. The invalid exception is
+| raised if either operand is a NaN. The comparison is performed according
+| to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_lt(float16 a, float16 b, float_status *status)
+{
+ bool aSign, bSign;
+ uint16_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ float_raise(float_flag_invalid, status);
+ return 0;
+ }
+ aSign = extractFloat16Sign(a);
+ bSign = extractFloat16Sign(b);
+ av = float16_val(a);
+ bv = float16_val(b);
+ if (aSign != bSign) {
+ return aSign && ((uint16_t) ((av | bv) << 1) != 0);
+ }
+ return (av != bv) && (aSign ^ (av < bv));
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point values `a' and `b' cannot
+| be compared, and 0 otherwise. The invalid exception is raised if either
+| operand is a NaN. The comparison is performed according to the IEC/IEEE
+| Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_unordered(float16 a, float16 b, float_status *status)
+{
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ float_raise(float_flag_invalid, status);
+ return 1;
+ }
+ return 0;
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is equal to
+| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an
+| exception. The comparison is performed according to the IEC/IEEE Standard
+| for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_eq_quiet(float16 a, float16 b, float_status *status)
+{
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ if (float16_is_signaling_nan(a, status)
+ || float16_is_signaling_nan(b, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ return 0;
+ }
+ return (float16_val(a) == float16_val(b)) ||
+ ((uint16_t) ((float16_val(a) | float16_val(b)) << 1) == 0);
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is less than or
+| equal to the corresponding value `b', and 0 otherwise. Quiet NaNs do not
+| cause an exception. Otherwise, the comparison is performed according to the
+| IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_le_quiet(float16 a, float16 b, float_status *status)
+{
+ bool aSign, bSign;
+ uint16_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ if (float16_is_signaling_nan(a, status)
+ || float16_is_signaling_nan(b, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ return 0;
+ }
+ aSign = extractFloat16Sign(a);
+ bSign = extractFloat16Sign(b);
+ av = float16_val(a);
+ bv = float16_val(b);
+ if (aSign != bSign) {
+ return aSign || ((uint16_t) ((av | bv) << 1) == 0);
+ }
+ return (av == bv) || (aSign ^ (av < bv));
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is less than
+| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an
+| exception. Otherwise, the comparison is performed according to the IEC/IEEE
+| Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_lt_quiet(float16 a, float16 b, float_status *status)
+{
+ bool aSign, bSign;
+ uint16_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ if (float16_is_signaling_nan(a, status)
+ || float16_is_signaling_nan(b, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ return 0;
+ }
+ aSign = extractFloat16Sign(a);
+ bSign = extractFloat16Sign(b);
+ av = float16_val(a);
+ bv = float16_val(b);
+ if (aSign != bSign) {
+ return aSign && ((uint16_t) ((av | bv) << 1) != 0);
+ }
+ return (av != bv) && (aSign ^ (av < bv));
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point values `a' and `b' cannot
+| be compared, and 0 otherwise. Quiet NaNs do not cause an exception. The
+| comparison is performed according to the IEC/IEEE Standard for Binary
+| Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_unordered_quiet(float16 a, float16 b, float_status *status)
+{
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ if (float16_is_signaling_nan(a, status)
+ || float16_is_signaling_nan(b, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ return 1;
+ }
+ return 0;
+}
+
/*----------------------------------------------------------------------------
| Returns the result of converting the extended double-precision floating-
| point value `a' to the 32-bit two's complement integer format. The
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 075c680456..d36a54be3e 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -244,6 +244,14 @@ float16 float16_maxnum_noprop(float16, float16, float_status *status);
float16 float16_sqrt(float16, float_status *status);
FloatRelation float16_compare(float16, float16, float_status *status);
FloatRelation float16_compare_quiet(float16, float16, float_status *status);
+int float16_eq(float16, float16, float_status *status);
+int float16_le(float16, float16, float_status *status);
+int float16_lt(float16, float16, float_status *status);
+int float16_unordered(float16, float16, float_status *status);
+int float16_eq_quiet(float16, float16, float_status *status);
+int float16_le_quiet(float16, float16, float_status *status);
+int float16_lt_quiet(float16, float16, float_status *status);
+int float16_unordered_quiet(float16, float16, float_status *status);
bool float16_is_quiet_nan(float16, float_status *status);
bool float16_is_signaling_nan(float16, float_status *status);
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 63/65] fpu: implement full set compare for fp16
@ 2020-07-10 10:49 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Chih-Min Chao, Frank Chang, Aurelien Jarno,
Peter Maydell, Alex Bennée
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
fpu/softfloat.c | 240 ++++++++++++++++++++++++++++++++++++++++
include/fpu/softfloat.h | 8 ++
2 files changed, 248 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 028b857167..8bebea1142 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -401,6 +401,34 @@ float64_gen2(float64 xa, float64 xb, float_status *s,
return soft(ua.s, ub.s, s);
}
+/*----------------------------------------------------------------------------
+| Returns the fraction bits of the half-precision floating-point value `a'.
+*----------------------------------------------------------------------------*/
+
+static inline uint32_t extractFloat16Frac(float16 a)
+{
+ return float16_val(a) & 0x3ff;
+}
+
+/*----------------------------------------------------------------------------
+| Returns the exponent bits of the half-precision floating-point value `a'.
+*----------------------------------------------------------------------------*/
+
+static inline int extractFloat16Exp(float16 a)
+{
+ return (float16_val(a) >> 10) & 0x1f;
+}
+
+/*----------------------------------------------------------------------------
+| Returns the sign bit of the half-precision floating-point value `a'.
+*----------------------------------------------------------------------------*/
+
+static inline bool extractFloat16Sign(float16 a)
+{
+ return float16_val(a) >> 15;
+}
+
+
/*----------------------------------------------------------------------------
| Returns the fraction bits of the single-precision floating-point value `a'.
*----------------------------------------------------------------------------*/
@@ -5006,6 +5034,218 @@ float64 float64_log2(float64 a, float_status *status)
return normalizeRoundAndPackFloat64(zSign, 0x408, zSig, status);
}
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is equal to
+| the corresponding value `b', and 0 otherwise. The invalid exception is
+| raised if either operand is a NaN. Otherwise, the comparison is performed
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_eq(float16 a, float16 b, float_status *status)
+{
+ uint16_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ float_raise(float_flag_invalid, status);
+ return 0;
+ }
+ av = float16_val(a);
+ bv = float16_val(b);
+ return (av == bv) || ((uint16_t) ((av | bv) << 1) == 0);
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is less than
+| or equal to the corresponding value `b', and 0 otherwise. The invalid
+| exception is raised if either operand is a NaN. The comparison is performed
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_le(float16 a, float16 b, float_status *status)
+{
+ bool aSign, bSign;
+ uint16_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ float_raise(float_flag_invalid, status);
+ return 0;
+ }
+ aSign = extractFloat16Sign(a);
+ bSign = extractFloat16Sign(b);
+ av = float16_val(a);
+ bv = float16_val(b);
+ if (aSign != bSign) {
+ return aSign || ((uint16_t) ((av | bv) << 1) == 0);
+ }
+ return (av == bv) || (aSign ^ (av < bv));
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is less than
+| the corresponding value `b', and 0 otherwise. The invalid exception is
+| raised if either operand is a NaN. The comparison is performed according
+| to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_lt(float16 a, float16 b, float_status *status)
+{
+ bool aSign, bSign;
+ uint16_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ float_raise(float_flag_invalid, status);
+ return 0;
+ }
+ aSign = extractFloat16Sign(a);
+ bSign = extractFloat16Sign(b);
+ av = float16_val(a);
+ bv = float16_val(b);
+ if (aSign != bSign) {
+ return aSign && ((uint16_t) ((av | bv) << 1) != 0);
+ }
+ return (av != bv) && (aSign ^ (av < bv));
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point values `a' and `b' cannot
+| be compared, and 0 otherwise. The invalid exception is raised if either
+| operand is a NaN. The comparison is performed according to the IEC/IEEE
+| Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_unordered(float16 a, float16 b, float_status *status)
+{
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ float_raise(float_flag_invalid, status);
+ return 1;
+ }
+ return 0;
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is equal to
+| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an
+| exception. The comparison is performed according to the IEC/IEEE Standard
+| for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_eq_quiet(float16 a, float16 b, float_status *status)
+{
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ if (float16_is_signaling_nan(a, status)
+ || float16_is_signaling_nan(b, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ return 0;
+ }
+ return (float16_val(a) == float16_val(b)) ||
+ ((uint16_t) ((float16_val(a) | float16_val(b)) << 1) == 0);
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is less than or
+| equal to the corresponding value `b', and 0 otherwise. Quiet NaNs do not
+| cause an exception. Otherwise, the comparison is performed according to the
+| IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_le_quiet(float16 a, float16 b, float_status *status)
+{
+ bool aSign, bSign;
+ uint16_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ if (float16_is_signaling_nan(a, status)
+ || float16_is_signaling_nan(b, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ return 0;
+ }
+ aSign = extractFloat16Sign(a);
+ bSign = extractFloat16Sign(b);
+ av = float16_val(a);
+ bv = float16_val(b);
+ if (aSign != bSign) {
+ return aSign || ((uint16_t) ((av | bv) << 1) == 0);
+ }
+ return (av == bv) || (aSign ^ (av < bv));
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is less than
+| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an
+| exception. Otherwise, the comparison is performed according to the IEC/IEEE
+| Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_lt_quiet(float16 a, float16 b, float_status *status)
+{
+ bool aSign, bSign;
+ uint16_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ if (float16_is_signaling_nan(a, status)
+ || float16_is_signaling_nan(b, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ return 0;
+ }
+ aSign = extractFloat16Sign(a);
+ bSign = extractFloat16Sign(b);
+ av = float16_val(a);
+ bv = float16_val(b);
+ if (aSign != bSign) {
+ return aSign && ((uint16_t) ((av | bv) << 1) != 0);
+ }
+ return (av != bv) && (aSign ^ (av < bv));
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point values `a' and `b' cannot
+| be compared, and 0 otherwise. Quiet NaNs do not cause an exception. The
+| comparison is performed according to the IEC/IEEE Standard for Binary
+| Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_unordered_quiet(float16 a, float16 b, float_status *status)
+{
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ if (float16_is_signaling_nan(a, status)
+ || float16_is_signaling_nan(b, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ return 1;
+ }
+ return 0;
+}
+
/*----------------------------------------------------------------------------
| Returns the result of converting the extended double-precision floating-
| point value `a' to the 32-bit two's complement integer format. The
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 075c680456..d36a54be3e 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -244,6 +244,14 @@ float16 float16_maxnum_noprop(float16, float16, float_status *status);
float16 float16_sqrt(float16, float_status *status);
FloatRelation float16_compare(float16, float16, float_status *status);
FloatRelation float16_compare_quiet(float16, float16, float_status *status);
+int float16_eq(float16, float16, float_status *status);
+int float16_le(float16, float16, float_status *status);
+int float16_lt(float16, float16, float_status *status);
+int float16_unordered(float16, float16, float_status *status);
+int float16_eq_quiet(float16, float16, float_status *status);
+int float16_le_quiet(float16, float16, float_status *status);
+int float16_lt_quiet(float16, float16, float_status *status);
+int float16_unordered_quiet(float16, float16, float_status *status);
bool float16_is_quiet_nan(float16, float_status *status);
bool float16_is_signaling_nan(float16, float_status *status);
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 64/65] target/riscv: use softfloat lib float16 comparison functions
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:49 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/vector_helper.c | 19 -------------------
1 file changed, 19 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index aac055c6b6..c206b50182 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3969,12 +3969,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
} \
}
-static bool float16_eq_quiet(uint16_t a, uint16_t b, float_status *s)
-{
- FloatRelation compare = float16_compare_quiet(a, b, s);
- return compare == float_relation_equal;
-}
-
GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h, uint16_t, H2, float16_eq_quiet)
GEN_VEXT_CMP_VV_ENV(vmfeq_vv_w, uint32_t, H4, float32_eq_quiet)
GEN_VEXT_CMP_VV_ENV(vmfeq_vv_d, uint64_t, H8, float64_eq_quiet)
@@ -4033,12 +4027,6 @@ GEN_VEXT_CMP_VF(vmfne_vf_h, uint16_t, H2, vmfne16)
GEN_VEXT_CMP_VF(vmfne_vf_w, uint32_t, H4, vmfne32)
GEN_VEXT_CMP_VF(vmfne_vf_d, uint64_t, H8, vmfne64)
-static bool float16_lt(uint16_t a, uint16_t b, float_status *s)
-{
- FloatRelation compare = float16_compare(a, b, s);
- return compare == float_relation_less;
-}
-
GEN_VEXT_CMP_VV_ENV(vmflt_vv_h, uint16_t, H2, float16_lt)
GEN_VEXT_CMP_VV_ENV(vmflt_vv_w, uint32_t, H4, float32_lt)
GEN_VEXT_CMP_VV_ENV(vmflt_vv_d, uint64_t, H8, float64_lt)
@@ -4046,13 +4034,6 @@ GEN_VEXT_CMP_VF(vmflt_vf_h, uint16_t, H2, float16_lt)
GEN_VEXT_CMP_VF(vmflt_vf_w, uint32_t, H4, float32_lt)
GEN_VEXT_CMP_VF(vmflt_vf_d, uint64_t, H8, float64_lt)
-static bool float16_le(uint16_t a, uint16_t b, float_status *s)
-{
- FloatRelation compare = float16_compare(a, b, s);
- return compare == float_relation_less ||
- compare == float_relation_equal;
-}
-
GEN_VEXT_CMP_VV_ENV(vmfle_vv_h, uint16_t, H2, float16_le)
GEN_VEXT_CMP_VV_ENV(vmfle_vv_w, uint32_t, H4, float32_le)
GEN_VEXT_CMP_VV_ENV(vmfle_vv_d, uint64_t, H8, float64_le)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 64/65] target/riscv: use softfloat lib float16 comparison functions
@ 2020-07-10 10:49 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/vector_helper.c | 19 -------------------
1 file changed, 19 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index aac055c6b6..c206b50182 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3969,12 +3969,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
} \
}
-static bool float16_eq_quiet(uint16_t a, uint16_t b, float_status *s)
-{
- FloatRelation compare = float16_compare_quiet(a, b, s);
- return compare == float_relation_equal;
-}
-
GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h, uint16_t, H2, float16_eq_quiet)
GEN_VEXT_CMP_VV_ENV(vmfeq_vv_w, uint32_t, H4, float32_eq_quiet)
GEN_VEXT_CMP_VV_ENV(vmfeq_vv_d, uint64_t, H8, float64_eq_quiet)
@@ -4033,12 +4027,6 @@ GEN_VEXT_CMP_VF(vmfne_vf_h, uint16_t, H2, vmfne16)
GEN_VEXT_CMP_VF(vmfne_vf_w, uint32_t, H4, vmfne32)
GEN_VEXT_CMP_VF(vmfne_vf_d, uint64_t, H8, vmfne64)
-static bool float16_lt(uint16_t a, uint16_t b, float_status *s)
-{
- FloatRelation compare = float16_compare(a, b, s);
- return compare == float_relation_less;
-}
-
GEN_VEXT_CMP_VV_ENV(vmflt_vv_h, uint16_t, H2, float16_lt)
GEN_VEXT_CMP_VV_ENV(vmflt_vv_w, uint32_t, H4, float32_lt)
GEN_VEXT_CMP_VV_ENV(vmflt_vv_d, uint64_t, H8, float64_lt)
@@ -4046,13 +4034,6 @@ GEN_VEXT_CMP_VF(vmflt_vf_h, uint16_t, H2, float16_lt)
GEN_VEXT_CMP_VF(vmflt_vf_w, uint32_t, H4, float32_lt)
GEN_VEXT_CMP_VF(vmflt_vf_d, uint64_t, H8, float64_lt)
-static bool float16_le(uint16_t a, uint16_t b, float_status *s)
-{
- FloatRelation compare = float16_compare(a, b, s);
- return compare == float_relation_less ||
- compare == float_relation_equal;
-}
-
GEN_VEXT_CMP_VV_ENV(vmfle_vv_h, uint16_t, H2, float16_le)
GEN_VEXT_CMP_VV_ENV(vmfle_vv_w, uint32_t, H4, float32_le)
GEN_VEXT_CMP_VV_ENV(vmfle_vv_d, uint64_t, H8, float64_le)
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 65/65] target/riscv: bump to RVV 0.9
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 10:49 ` frank.chang
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.c | 8 ++++----
target/riscv/cpu.h | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 871c2ddfa1..6168166e64 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -340,7 +340,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
CPURISCVState *env = &cpu->env;
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
int priv_version = PRIV_VERSION_1_11_0;
- int vext_version = VEXT_VERSION_0_07_1;
+ int vext_version = VEXT_VERSION_0_09_0;
target_ulong target_misa = 0;
Error *local_err = NULL;
@@ -456,8 +456,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}
if (cpu->cfg.vext_spec) {
- if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
- vext_version = VEXT_VERSION_0_07_1;
+ if (!g_strcmp0(cpu->cfg.vext_spec, "v0.9")) {
+ vext_version = VEXT_VERSION_0_09_0;
} else {
error_setg(errp,
"Unsupported vector spec version '%s'",
@@ -466,7 +466,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
} else {
qemu_log("vector verison is not specified, "
- "use the default value v0.7.1\n");
+ "use the default value v0.9\n");
}
set_vext_version(env, vext_version);
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 8b4a370572..18015f0bc0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -81,7 +81,7 @@ enum {
#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100
-#define VEXT_VERSION_0_07_1 0x00000701
+#define VEXT_VERSION_0_09_0 0x00000900
#define TRANSLATE_PMP_FAIL 2
#define TRANSLATE_FAIL 1
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* [RFC 65/65] target/riscv: bump to RVV 0.9
@ 2020-07-10 10:49 ` frank.chang
0 siblings, 0 replies; 211+ messages in thread
From: frank.chang @ 2020-07-10 10:49 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.c | 8 ++++----
target/riscv/cpu.h | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 871c2ddfa1..6168166e64 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -340,7 +340,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
CPURISCVState *env = &cpu->env;
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
int priv_version = PRIV_VERSION_1_11_0;
- int vext_version = VEXT_VERSION_0_07_1;
+ int vext_version = VEXT_VERSION_0_09_0;
target_ulong target_misa = 0;
Error *local_err = NULL;
@@ -456,8 +456,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}
if (cpu->cfg.vext_spec) {
- if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
- vext_version = VEXT_VERSION_0_07_1;
+ if (!g_strcmp0(cpu->cfg.vext_spec, "v0.9")) {
+ vext_version = VEXT_VERSION_0_09_0;
} else {
error_setg(errp,
"Unsupported vector spec version '%s'",
@@ -466,7 +466,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
} else {
qemu_log("vector verison is not specified, "
- "use the default value v0.7.1\n");
+ "use the default value v0.9\n");
}
set_vext_version(env, vext_version);
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 8b4a370572..18015f0bc0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -81,7 +81,7 @@ enum {
#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100
-#define VEXT_VERSION_0_07_1 0x00000701
+#define VEXT_VERSION_0_09_0 0x00000900
#define TRANSLATE_PMP_FAIL 2
#define TRANSLATE_FAIL 1
--
2.17.1
^ permalink raw reply related [flat|nested] 211+ messages in thread
* Re: [RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions
2020-07-10 10:49 ` frank.chang
@ 2020-07-10 12:07 ` Alex Bennée
-1 siblings, 0 replies; 211+ messages in thread
From: Alex Bennée @ 2020-07-10 12:07 UTC (permalink / raw)
To: frank.chang; +Cc: Peter Maydell, qemu-riscv, qemu-devel, Aurelien Jarno
frank.chang@sifive.com writes:
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Did I miss the rest of the series somewhere?
Otherwise this looks fine to me:
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions
@ 2020-07-10 12:07 ` Alex Bennée
0 siblings, 0 replies; 211+ messages in thread
From: Alex Bennée @ 2020-07-10 12:07 UTC (permalink / raw)
To: frank.chang; +Cc: qemu-devel, qemu-riscv, Aurelien Jarno, Peter Maydell
frank.chang@sifive.com writes:
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Did I miss the rest of the series somewhere?
Otherwise this looks fine to me:
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 62/65] fpu: add api to handle alternative sNaN propagation
2020-07-10 10:49 ` frank.chang
@ 2020-07-10 12:15 ` Alex Bennée
-1 siblings, 0 replies; 211+ messages in thread
From: Alex Bennée @ 2020-07-10 12:15 UTC (permalink / raw)
To: frank.chang
Cc: Chih-Min Chao, qemu-riscv, qemu-devel, Aurelien Jarno, Peter Maydell
frank.chang@sifive.com writes:
> From: Chih-Min Chao <chihmin.chao@sifive.com>
>
> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> fpu/softfloat.c | 68 +++++++++++++++++++++++++----------------
> include/fpu/softfloat.h | 6 ++++
> 2 files changed, 48 insertions(+), 26 deletions(-)
>
> diff --git a/fpu/softfloat.c b/fpu/softfloat.c
> index fa1c99c03e..028b857167 100644
> --- a/fpu/softfloat.c
> +++ b/fpu/softfloat.c
> @@ -2777,23 +2777,32 @@ float64 uint16_to_float64(uint16_t a, float_status *status)
> * and minNumMag() from the IEEE-754 2008.
> */
> static FloatParts minmax_floats(FloatParts a, FloatParts b, bool ismin,
> - bool ieee, bool ismag, float_status *s)
> + bool ieee, bool ismag, bool issnan_prop,
> + float_status *s)
> {
> if (unlikely(is_nan(a.cls) || is_nan(b.cls))) {
> if (ieee) {
> /* Takes two floating-point values `a' and `b', one of
> * which is a NaN, and returns the appropriate NaN
> * result. If either `a' or `b' is a signaling NaN,
> - * the invalid exception is raised.
> + * the invalid exception is raised but the NaN
> + * propagation is 'shall'.
> */
> if (is_snan(a.cls) || is_snan(b.cls)) {
> - return pick_nan(a, b, s);
> - } else if (is_nan(a.cls) && !is_nan(b.cls)) {
> + if (issnan_prop) {
> + pick_nan(a, b, s);
This looks funky to me because you don't actually pick a nan - are you
just using this for side effects?
I'm also confused by the fact the new helpers have the prototype noprop
which implies no propagation yes the bool flag is true and named
issnan_prop which implies it should propagate.
I think we need a clearer problem statement in the commit of what you
are trying to achieve here. I suspect it might be worth splitting the
flag setting from pick_nan to it's own mini helper if that is all we
want to do in this case.
> + } else {
> + return pick_nan(a, b, s);
> + }
> + }
> +
> + if (is_nan(a.cls) && !is_nan(b.cls)) {
> return b;
> } else if (is_nan(b.cls) && !is_nan(a.cls)) {
> return a;
> }
> }
> +
nit: stray space
> return pick_nan(a, b, s);
> } else {
> int a_exp, b_exp;
> @@ -2847,37 +2856,44 @@ static FloatParts minmax_floats(FloatParts a, FloatParts b, bool ismin,
> }
> }
>
> -#define MINMAX(sz, name, ismin, isiee, ismag) \
> +#define MINMAX(sz, name, ismin, isiee, ismag, issnan_prop) \
> float ## sz float ## sz ## _ ## name(float ## sz a, float ## sz b, \
> float_status *s) \
> { \
> FloatParts pa = float ## sz ## _unpack_canonical(a, s); \
> FloatParts pb = float ## sz ## _unpack_canonical(b, s); \
> - FloatParts pr = minmax_floats(pa, pb, ismin, isiee, ismag, s); \
> + FloatParts pr = minmax_floats(pa, pb, ismin, isiee, ismag, \
> + issnan_prop, s); \
> \
> return float ## sz ## _round_pack_canonical(pr, s); \
> }
>
> -MINMAX(16, min, true, false, false)
> -MINMAX(16, minnum, true, true, false)
> -MINMAX(16, minnummag, true, true, true)
> -MINMAX(16, max, false, false, false)
> -MINMAX(16, maxnum, false, true, false)
> -MINMAX(16, maxnummag, false, true, true)
> -
> -MINMAX(32, min, true, false, false)
> -MINMAX(32, minnum, true, true, false)
> -MINMAX(32, minnummag, true, true, true)
> -MINMAX(32, max, false, false, false)
> -MINMAX(32, maxnum, false, true, false)
> -MINMAX(32, maxnummag, false, true, true)
> -
> -MINMAX(64, min, true, false, false)
> -MINMAX(64, minnum, true, true, false)
> -MINMAX(64, minnummag, true, true, true)
> -MINMAX(64, max, false, false, false)
> -MINMAX(64, maxnum, false, true, false)
> -MINMAX(64, maxnummag, false, true, true)
> +MINMAX(16, min, true, false, false, false)
> +MINMAX(16, minnum, true, true, false, false)
> +MINMAX(16, minnum_noprop, true, true, false, true)
> +MINMAX(16, minnummag, true, true, true, false)
> +MINMAX(16, max, false, false, false, false)
> +MINMAX(16, maxnum, false, true, false, false)
> +MINMAX(16, maxnum_noprop, false, true, false, true)
> +MINMAX(16, maxnummag, false, true, true, false)
> +
> +MINMAX(32, min, true, false, false, false)
> +MINMAX(32, minnum, true, true, false, false)
> +MINMAX(32, minnum_noprop, true, true, false, true)
> +MINMAX(32, minnummag, true, true, true, false)
> +MINMAX(32, max, false, false, false, false)
> +MINMAX(32, maxnum, false, true, false, false)
> +MINMAX(32, maxnum_noprop, false, true, false, true)
> +MINMAX(32, maxnummag, false, true, true, false)
> +
> +MINMAX(64, min, true, false, false, false)
> +MINMAX(64, minnum, true, true, false, false)
> +MINMAX(64, minnum_noprop, true, true, false, true)
> +MINMAX(64, minnummag, true, true, true, false)
> +MINMAX(64, max, false, false, false, false)
> +MINMAX(64, maxnum, false, true, false, false)
> +MINMAX(64, maxnum_noprop, false, true, false, true)
> +MINMAX(64, maxnummag, false, true, true, false)
>
> #undef MINMAX
>
> diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
> index b0ae8f6295..075c680456 100644
> --- a/include/fpu/softfloat.h
> +++ b/include/fpu/softfloat.h
> @@ -239,6 +239,8 @@ float16 float16_minnum(float16, float16, float_status *status);
> float16 float16_maxnum(float16, float16, float_status *status);
> float16 float16_minnummag(float16, float16, float_status *status);
> float16 float16_maxnummag(float16, float16, float_status *status);
> +float16 float16_minnum_noprop(float16, float16, float_status *status);
> +float16 float16_maxnum_noprop(float16, float16, float_status *status);
> float16 float16_sqrt(float16, float_status *status);
> FloatRelation float16_compare(float16, float16, float_status *status);
> FloatRelation float16_compare_quiet(float16, float16, float_status *status);
> @@ -359,6 +361,8 @@ float32 float32_minnum(float32, float32, float_status *status);
> float32 float32_maxnum(float32, float32, float_status *status);
> float32 float32_minnummag(float32, float32, float_status *status);
> float32 float32_maxnummag(float32, float32, float_status *status);
> +float32 float32_minnum_noprop(float32, float32, float_status *status);
> +float32 float32_maxnum_noprop(float32, float32, float_status *status);
> bool float32_is_quiet_nan(float32, float_status *status);
> bool float32_is_signaling_nan(float32, float_status *status);
> float32 float32_silence_nan(float32, float_status *status);
> @@ -548,6 +552,8 @@ float64 float64_minnum(float64, float64, float_status *status);
> float64 float64_maxnum(float64, float64, float_status *status);
> float64 float64_minnummag(float64, float64, float_status *status);
> float64 float64_maxnummag(float64, float64, float_status *status);
> +float64 float64_minnum_noprop(float64, float64, float_status *status);
> +float64 float64_maxnum_noprop(float64, float64, float_status *status);
> bool float64_is_quiet_nan(float64 a, float_status *status);
> bool float64_is_signaling_nan(float64, float_status *status);
> float64 float64_silence_nan(float64, float_status *status);
--
Alex Bennée
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 62/65] fpu: add api to handle alternative sNaN propagation
@ 2020-07-10 12:15 ` Alex Bennée
0 siblings, 0 replies; 211+ messages in thread
From: Alex Bennée @ 2020-07-10 12:15 UTC (permalink / raw)
To: frank.chang
Cc: qemu-devel, qemu-riscv, Chih-Min Chao, Aurelien Jarno, Peter Maydell
frank.chang@sifive.com writes:
> From: Chih-Min Chao <chihmin.chao@sifive.com>
>
> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> fpu/softfloat.c | 68 +++++++++++++++++++++++++----------------
> include/fpu/softfloat.h | 6 ++++
> 2 files changed, 48 insertions(+), 26 deletions(-)
>
> diff --git a/fpu/softfloat.c b/fpu/softfloat.c
> index fa1c99c03e..028b857167 100644
> --- a/fpu/softfloat.c
> +++ b/fpu/softfloat.c
> @@ -2777,23 +2777,32 @@ float64 uint16_to_float64(uint16_t a, float_status *status)
> * and minNumMag() from the IEEE-754 2008.
> */
> static FloatParts minmax_floats(FloatParts a, FloatParts b, bool ismin,
> - bool ieee, bool ismag, float_status *s)
> + bool ieee, bool ismag, bool issnan_prop,
> + float_status *s)
> {
> if (unlikely(is_nan(a.cls) || is_nan(b.cls))) {
> if (ieee) {
> /* Takes two floating-point values `a' and `b', one of
> * which is a NaN, and returns the appropriate NaN
> * result. If either `a' or `b' is a signaling NaN,
> - * the invalid exception is raised.
> + * the invalid exception is raised but the NaN
> + * propagation is 'shall'.
> */
> if (is_snan(a.cls) || is_snan(b.cls)) {
> - return pick_nan(a, b, s);
> - } else if (is_nan(a.cls) && !is_nan(b.cls)) {
> + if (issnan_prop) {
> + pick_nan(a, b, s);
This looks funky to me because you don't actually pick a nan - are you
just using this for side effects?
I'm also confused by the fact the new helpers have the prototype noprop
which implies no propagation yes the bool flag is true and named
issnan_prop which implies it should propagate.
I think we need a clearer problem statement in the commit of what you
are trying to achieve here. I suspect it might be worth splitting the
flag setting from pick_nan to it's own mini helper if that is all we
want to do in this case.
> + } else {
> + return pick_nan(a, b, s);
> + }
> + }
> +
> + if (is_nan(a.cls) && !is_nan(b.cls)) {
> return b;
> } else if (is_nan(b.cls) && !is_nan(a.cls)) {
> return a;
> }
> }
> +
nit: stray space
> return pick_nan(a, b, s);
> } else {
> int a_exp, b_exp;
> @@ -2847,37 +2856,44 @@ static FloatParts minmax_floats(FloatParts a, FloatParts b, bool ismin,
> }
> }
>
> -#define MINMAX(sz, name, ismin, isiee, ismag) \
> +#define MINMAX(sz, name, ismin, isiee, ismag, issnan_prop) \
> float ## sz float ## sz ## _ ## name(float ## sz a, float ## sz b, \
> float_status *s) \
> { \
> FloatParts pa = float ## sz ## _unpack_canonical(a, s); \
> FloatParts pb = float ## sz ## _unpack_canonical(b, s); \
> - FloatParts pr = minmax_floats(pa, pb, ismin, isiee, ismag, s); \
> + FloatParts pr = minmax_floats(pa, pb, ismin, isiee, ismag, \
> + issnan_prop, s); \
> \
> return float ## sz ## _round_pack_canonical(pr, s); \
> }
>
> -MINMAX(16, min, true, false, false)
> -MINMAX(16, minnum, true, true, false)
> -MINMAX(16, minnummag, true, true, true)
> -MINMAX(16, max, false, false, false)
> -MINMAX(16, maxnum, false, true, false)
> -MINMAX(16, maxnummag, false, true, true)
> -
> -MINMAX(32, min, true, false, false)
> -MINMAX(32, minnum, true, true, false)
> -MINMAX(32, minnummag, true, true, true)
> -MINMAX(32, max, false, false, false)
> -MINMAX(32, maxnum, false, true, false)
> -MINMAX(32, maxnummag, false, true, true)
> -
> -MINMAX(64, min, true, false, false)
> -MINMAX(64, minnum, true, true, false)
> -MINMAX(64, minnummag, true, true, true)
> -MINMAX(64, max, false, false, false)
> -MINMAX(64, maxnum, false, true, false)
> -MINMAX(64, maxnummag, false, true, true)
> +MINMAX(16, min, true, false, false, false)
> +MINMAX(16, minnum, true, true, false, false)
> +MINMAX(16, minnum_noprop, true, true, false, true)
> +MINMAX(16, minnummag, true, true, true, false)
> +MINMAX(16, max, false, false, false, false)
> +MINMAX(16, maxnum, false, true, false, false)
> +MINMAX(16, maxnum_noprop, false, true, false, true)
> +MINMAX(16, maxnummag, false, true, true, false)
> +
> +MINMAX(32, min, true, false, false, false)
> +MINMAX(32, minnum, true, true, false, false)
> +MINMAX(32, minnum_noprop, true, true, false, true)
> +MINMAX(32, minnummag, true, true, true, false)
> +MINMAX(32, max, false, false, false, false)
> +MINMAX(32, maxnum, false, true, false, false)
> +MINMAX(32, maxnum_noprop, false, true, false, true)
> +MINMAX(32, maxnummag, false, true, true, false)
> +
> +MINMAX(64, min, true, false, false, false)
> +MINMAX(64, minnum, true, true, false, false)
> +MINMAX(64, minnum_noprop, true, true, false, true)
> +MINMAX(64, minnummag, true, true, true, false)
> +MINMAX(64, max, false, false, false, false)
> +MINMAX(64, maxnum, false, true, false, false)
> +MINMAX(64, maxnum_noprop, false, true, false, true)
> +MINMAX(64, maxnummag, false, true, true, false)
>
> #undef MINMAX
>
> diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
> index b0ae8f6295..075c680456 100644
> --- a/include/fpu/softfloat.h
> +++ b/include/fpu/softfloat.h
> @@ -239,6 +239,8 @@ float16 float16_minnum(float16, float16, float_status *status);
> float16 float16_maxnum(float16, float16, float_status *status);
> float16 float16_minnummag(float16, float16, float_status *status);
> float16 float16_maxnummag(float16, float16, float_status *status);
> +float16 float16_minnum_noprop(float16, float16, float_status *status);
> +float16 float16_maxnum_noprop(float16, float16, float_status *status);
> float16 float16_sqrt(float16, float_status *status);
> FloatRelation float16_compare(float16, float16, float_status *status);
> FloatRelation float16_compare_quiet(float16, float16, float_status *status);
> @@ -359,6 +361,8 @@ float32 float32_minnum(float32, float32, float_status *status);
> float32 float32_maxnum(float32, float32, float_status *status);
> float32 float32_minnummag(float32, float32, float_status *status);
> float32 float32_maxnummag(float32, float32, float_status *status);
> +float32 float32_minnum_noprop(float32, float32, float_status *status);
> +float32 float32_maxnum_noprop(float32, float32, float_status *status);
> bool float32_is_quiet_nan(float32, float_status *status);
> bool float32_is_signaling_nan(float32, float_status *status);
> float32 float32_silence_nan(float32, float_status *status);
> @@ -548,6 +552,8 @@ float64 float64_minnum(float64, float64, float_status *status);
> float64 float64_maxnum(float64, float64, float_status *status);
> float64 float64_minnummag(float64, float64, float_status *status);
> float64 float64_maxnummag(float64, float64, float_status *status);
> +float64 float64_minnum_noprop(float64, float64, float_status *status);
> +float64 float64_maxnum_noprop(float64, float64, float_status *status);
> bool float64_is_quiet_nan(float64 a, float_status *status);
> bool float64_is_signaling_nan(float64, float_status *status);
> float64 float64_silence_nan(float64, float_status *status);
--
Alex Bennée
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions
2020-07-10 12:07 ` Alex Bennée
@ 2020-07-10 12:15 ` Frank Chang
-1 siblings, 0 replies; 211+ messages in thread
From: Frank Chang @ 2020-07-10 12:15 UTC (permalink / raw)
To: Alex Bennée; +Cc: Peter Maydell, qemu-riscv, qemu-devel, Aurelien Jarno
[-- Attachment #1: Type: text/plain, Size: 664 bytes --]
On Fri, Jul 10, 2020 at 8:07 PM Alex Bennée <alex.bennee@linaro.org> wrote:
>
> frank.chang@sifive.com writes:
>
> > From: Frank Chang <frank.chang@sifive.com>
> >
> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
>
> Did I miss the rest of the series somewhere?
>
> Otherwise this looks fine to me:
>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>
> If you mean float16 to uint8 and int8 conversion functions, this commit is
everything.
I think I just cc the mail based on *scripts/get_maintainer.pl
<http://get_maintainer.pl>*, so probably didn't send the whole series to
everyone.
--
Frank Chang
> --
> Alex Bennée
>
[-- Attachment #2: Type: text/html, Size: 1403 bytes --]
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions
@ 2020-07-10 12:15 ` Frank Chang
0 siblings, 0 replies; 211+ messages in thread
From: Frank Chang @ 2020-07-10 12:15 UTC (permalink / raw)
To: Alex Bennée; +Cc: qemu-devel, qemu-riscv, Aurelien Jarno, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 664 bytes --]
On Fri, Jul 10, 2020 at 8:07 PM Alex Bennée <alex.bennee@linaro.org> wrote:
>
> frank.chang@sifive.com writes:
>
> > From: Frank Chang <frank.chang@sifive.com>
> >
> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
>
> Did I miss the rest of the series somewhere?
>
> Otherwise this looks fine to me:
>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>
> If you mean float16 to uint8 and int8 conversion functions, this commit is
everything.
I think I just cc the mail based on *scripts/get_maintainer.pl
<http://get_maintainer.pl>*, so probably didn't send the whole series to
everyone.
--
Frank Chang
> --
> Alex Bennée
>
[-- Attachment #2: Type: text/html, Size: 1403 bytes --]
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 63/65] fpu: implement full set compare for fp16
2020-07-10 10:49 ` frank.chang
@ 2020-07-10 12:24 ` Alex Bennée
-1 siblings, 0 replies; 211+ messages in thread
From: Alex Bennée @ 2020-07-10 12:24 UTC (permalink / raw)
To: frank.chang
Cc: Peter Maydell, qemu-riscv, qemu-devel, Chih-Min Chao, Kito Cheng,
Aurelien Jarno
frank.chang@sifive.com writes:
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
NACK I'm afraid. What's wrong with the exiting float_compare support?
Even if you did want to bring in aliases for these functions within
softfloat itself the correct way would be to use the decomposed
float_compare support for a bunch of stubs and not restore the old style
error prone bit masking code.
> ---
> fpu/softfloat.c | 240 ++++++++++++++++++++++++++++++++++++++++
> include/fpu/softfloat.h | 8 ++
> 2 files changed, 248 insertions(+)
>
> diff --git a/fpu/softfloat.c b/fpu/softfloat.c
> index 028b857167..8bebea1142 100644
> --- a/fpu/softfloat.c
> +++ b/fpu/softfloat.c
> @@ -401,6 +401,34 @@ float64_gen2(float64 xa, float64 xb, float_status *s,
> return soft(ua.s, ub.s, s);
> }
>
> +/*----------------------------------------------------------------------------
> +| Returns the fraction bits of the half-precision floating-point value `a'.
> +*----------------------------------------------------------------------------*/
> +
> +static inline uint32_t extractFloat16Frac(float16 a)
> +{
> + return float16_val(a) & 0x3ff;
> +}
For example you'll notice this function was deleted in e6b405fe00
--
Alex Bennée
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 63/65] fpu: implement full set compare for fp16
@ 2020-07-10 12:24 ` Alex Bennée
0 siblings, 0 replies; 211+ messages in thread
From: Alex Bennée @ 2020-07-10 12:24 UTC (permalink / raw)
To: frank.chang
Cc: qemu-devel, qemu-riscv, Kito Cheng, Chih-Min Chao,
Aurelien Jarno, Peter Maydell
frank.chang@sifive.com writes:
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
NACK I'm afraid. What's wrong with the exiting float_compare support?
Even if you did want to bring in aliases for these functions within
softfloat itself the correct way would be to use the decomposed
float_compare support for a bunch of stubs and not restore the old style
error prone bit masking code.
> ---
> fpu/softfloat.c | 240 ++++++++++++++++++++++++++++++++++++++++
> include/fpu/softfloat.h | 8 ++
> 2 files changed, 248 insertions(+)
>
> diff --git a/fpu/softfloat.c b/fpu/softfloat.c
> index 028b857167..8bebea1142 100644
> --- a/fpu/softfloat.c
> +++ b/fpu/softfloat.c
> @@ -401,6 +401,34 @@ float64_gen2(float64 xa, float64 xb, float_status *s,
> return soft(ua.s, ub.s, s);
> }
>
> +/*----------------------------------------------------------------------------
> +| Returns the fraction bits of the half-precision floating-point value `a'.
> +*----------------------------------------------------------------------------*/
> +
> +static inline uint32_t extractFloat16Frac(float16 a)
> +{
> + return float16_val(a) & 0x3ff;
> +}
For example you'll notice this function was deleted in e6b405fe00
--
Alex Bennée
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 63/65] fpu: implement full set compare for fp16
2020-07-10 12:24 ` Alex Bennée
@ 2020-07-10 12:26 ` Alex Bennée
-1 siblings, 0 replies; 211+ messages in thread
From: Alex Bennée @ 2020-07-10 12:26 UTC (permalink / raw)
To: frank.chang
Cc: Peter Maydell, qemu-riscv, qemu-devel, Chih-Min Chao, Kito Cheng,
Aurelien Jarno
Alex Bennée <alex.bennee@linaro.org> writes:
> frank.chang@sifive.com writes:
>
>> From: Kito Cheng <kito.cheng@sifive.com>
>>
>> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
>> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
>> Signed-off-by: Frank Chang <frank.chang@sifive.com>
>
> NACK I'm afraid. What's wrong with the exiting float_compare support?
>
> Even if you did want to bring in aliases for these functions within
> softfloat itself the correct way would be to use the decomposed
> float_compare support for a bunch of stubs and not restore the old style
> error prone bit masking code.
In fact see the example float32_eq inline function in the softfloat.h header.
--
Alex Bennée
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 63/65] fpu: implement full set compare for fp16
@ 2020-07-10 12:26 ` Alex Bennée
0 siblings, 0 replies; 211+ messages in thread
From: Alex Bennée @ 2020-07-10 12:26 UTC (permalink / raw)
To: frank.chang
Cc: qemu-devel, qemu-riscv, Kito Cheng, Chih-Min Chao,
Aurelien Jarno, Peter Maydell
Alex Bennée <alex.bennee@linaro.org> writes:
> frank.chang@sifive.com writes:
>
>> From: Kito Cheng <kito.cheng@sifive.com>
>>
>> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
>> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
>> Signed-off-by: Frank Chang <frank.chang@sifive.com>
>
> NACK I'm afraid. What's wrong with the exiting float_compare support?
>
> Even if you did want to bring in aliases for these functions within
> softfloat itself the correct way would be to use the decomposed
> float_compare support for a bunch of stubs and not restore the old style
> error prone bit masking code.
In fact see the example float32_eq inline function in the softfloat.h header.
--
Alex Bennée
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions
2020-07-10 12:15 ` Frank Chang
@ 2020-07-10 12:46 ` Alex Bennée
-1 siblings, 0 replies; 211+ messages in thread
From: Alex Bennée @ 2020-07-10 12:46 UTC (permalink / raw)
To: Frank Chang; +Cc: Peter Maydell, qemu-riscv, qemu-devel, Aurelien Jarno
Frank Chang <frank.chang@sifive.com> writes:
> On Fri, Jul 10, 2020 at 8:07 PM Alex Bennée <alex.bennee@linaro.org> wrote:
>
>>
>> frank.chang@sifive.com writes:
>>
>> > From: Frank Chang <frank.chang@sifive.com>
>> >
>> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
>>
>> Did I miss the rest of the series somewhere?
>>
>> Otherwise this looks fine to me:
>>
>> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>>
>> If you mean float16 to uint8 and int8 conversion functions, this commit is
> everything.
> I think I just cc the mail based on *scripts/get_maintainer.pl
> <http://get_maintainer.pl>*, so probably didn't send the whole series to
> everyone.
Usually I see the rest of the thread from the mailing list. I can't see:
In-Reply-To: <20200710104920.13550-1-frank.chang@sifive.com>
References: <20200710104920.13550-1-frank.chang@sifive.com>
on any of the qemu mailing lists.
--
Alex Bennée
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions
@ 2020-07-10 12:46 ` Alex Bennée
0 siblings, 0 replies; 211+ messages in thread
From: Alex Bennée @ 2020-07-10 12:46 UTC (permalink / raw)
To: Frank Chang; +Cc: qemu-devel, qemu-riscv, Aurelien Jarno, Peter Maydell
Frank Chang <frank.chang@sifive.com> writes:
> On Fri, Jul 10, 2020 at 8:07 PM Alex Bennée <alex.bennee@linaro.org> wrote:
>
>>
>> frank.chang@sifive.com writes:
>>
>> > From: Frank Chang <frank.chang@sifive.com>
>> >
>> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
>>
>> Did I miss the rest of the series somewhere?
>>
>> Otherwise this looks fine to me:
>>
>> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>>
>> If you mean float16 to uint8 and int8 conversion functions, this commit is
> everything.
> I think I just cc the mail based on *scripts/get_maintainer.pl
> <http://get_maintainer.pl>*, so probably didn't send the whole series to
> everyone.
Usually I see the rest of the thread from the mailing list. I can't see:
In-Reply-To: <20200710104920.13550-1-frank.chang@sifive.com>
References: <20200710104920.13550-1-frank.chang@sifive.com>
on any of the qemu mailing lists.
--
Alex Bennée
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions
2020-07-10 12:46 ` Alex Bennée
@ 2020-07-10 13:13 ` Frank Chang
-1 siblings, 0 replies; 211+ messages in thread
From: Frank Chang @ 2020-07-10 13:13 UTC (permalink / raw)
To: Alex Bennée; +Cc: Peter Maydell, qemu-riscv, qemu-devel, Aurelien Jarno
[-- Attachment #1: Type: text/plain, Size: 1274 bytes --]
On Fri, Jul 10, 2020 at 8:46 PM Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Frank Chang <frank.chang@sifive.com> writes:
>
> > On Fri, Jul 10, 2020 at 8:07 PM Alex Bennée <alex.bennee@linaro.org>
> wrote:
> >
> >>
> >> frank.chang@sifive.com writes:
> >>
> >> > From: Frank Chang <frank.chang@sifive.com>
> >> >
> >> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
> >>
> >> Did I miss the rest of the series somewhere?
> >>
> >> Otherwise this looks fine to me:
> >>
> >> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> >>
> >> If you mean float16 to uint8 and int8 conversion functions, this commit
> is
> > everything.
> > I think I just cc the mail based on *scripts/get_maintainer.pl
> > <http://get_maintainer.pl>*, so probably didn't send the whole series to
> > everyone.
>
> Usually I see the rest of the thread from the mailing list. I can't see:
>
> In-Reply-To: <20200710104920.13550-1-frank.chang@sifive.com>
> References: <20200710104920.13550-1-frank.chang@sifive.com>
>
> on any of the qemu mailing lists.
>
> --
> Alex Bennée
>
The rest of the patches are coming out:
https://patchew.org/QEMU/20200710104920.13550-1-frank.chang@sifive.com/
Not sure what caused the delay...
--
Frank Chang
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^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions
@ 2020-07-10 13:13 ` Frank Chang
0 siblings, 0 replies; 211+ messages in thread
From: Frank Chang @ 2020-07-10 13:13 UTC (permalink / raw)
To: Alex Bennée; +Cc: qemu-devel, qemu-riscv, Aurelien Jarno, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 1274 bytes --]
On Fri, Jul 10, 2020 at 8:46 PM Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Frank Chang <frank.chang@sifive.com> writes:
>
> > On Fri, Jul 10, 2020 at 8:07 PM Alex Bennée <alex.bennee@linaro.org>
> wrote:
> >
> >>
> >> frank.chang@sifive.com writes:
> >>
> >> > From: Frank Chang <frank.chang@sifive.com>
> >> >
> >> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
> >>
> >> Did I miss the rest of the series somewhere?
> >>
> >> Otherwise this looks fine to me:
> >>
> >> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> >>
> >> If you mean float16 to uint8 and int8 conversion functions, this commit
> is
> > everything.
> > I think I just cc the mail based on *scripts/get_maintainer.pl
> > <http://get_maintainer.pl>*, so probably didn't send the whole series to
> > everyone.
>
> Usually I see the rest of the thread from the mailing list. I can't see:
>
> In-Reply-To: <20200710104920.13550-1-frank.chang@sifive.com>
> References: <20200710104920.13550-1-frank.chang@sifive.com>
>
> on any of the qemu mailing lists.
>
> --
> Alex Bennée
>
The rest of the patches are coming out:
https://patchew.org/QEMU/20200710104920.13550-1-frank.chang@sifive.com/
Not sure what caused the delay...
--
Frank Chang
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^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions
2020-07-10 13:13 ` Frank Chang
@ 2020-07-10 14:59 ` Alex Bennée
-1 siblings, 0 replies; 211+ messages in thread
From: Alex Bennée @ 2020-07-10 14:59 UTC (permalink / raw)
To: Frank Chang; +Cc: Peter Maydell, qemu-riscv, qemu-devel, Aurelien Jarno
Frank Chang <frank.chang@sifive.com> writes:
> On Fri, Jul 10, 2020 at 8:46 PM Alex Bennée <alex.bennee@linaro.org> wrote:
>
>>
>> Frank Chang <frank.chang@sifive.com> writes:
>>
>> > On Fri, Jul 10, 2020 at 8:07 PM Alex Bennée <alex.bennee@linaro.org>
>> wrote:
>> >
>> >>
>> >> frank.chang@sifive.com writes:
>> >>
>> >> > From: Frank Chang <frank.chang@sifive.com>
>> >> >
>> >> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
>> >>
>> >> Did I miss the rest of the series somewhere?
>> >>
>> >> Otherwise this looks fine to me:
>> >>
>> >> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>> >>
>> >> If you mean float16 to uint8 and int8 conversion functions, this commit
>> is
>> > everything.
>> > I think I just cc the mail based on *scripts/get_maintainer.pl
>> > <http://get_maintainer.pl>*, so probably didn't send the whole series to
>> > everyone.
>>
>> Usually I see the rest of the thread from the mailing list. I can't see:
>>
>> In-Reply-To: <20200710104920.13550-1-frank.chang@sifive.com>
>> References: <20200710104920.13550-1-frank.chang@sifive.com>
>>
>> on any of the qemu mailing lists.
>>
>> --
>> Alex Bennée
>>
>
> The rest of the patches are coming out:
> https://patchew.org/QEMU/20200710104920.13550-1-frank.chang@sifive.com/
> Not sure what caused the delay...
Ahh the mailing list is still chugging a bit it seems.
--
Alex Bennée
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions
@ 2020-07-10 14:59 ` Alex Bennée
0 siblings, 0 replies; 211+ messages in thread
From: Alex Bennée @ 2020-07-10 14:59 UTC (permalink / raw)
To: Frank Chang; +Cc: qemu-devel, qemu-riscv, Aurelien Jarno, Peter Maydell
Frank Chang <frank.chang@sifive.com> writes:
> On Fri, Jul 10, 2020 at 8:46 PM Alex Bennée <alex.bennee@linaro.org> wrote:
>
>>
>> Frank Chang <frank.chang@sifive.com> writes:
>>
>> > On Fri, Jul 10, 2020 at 8:07 PM Alex Bennée <alex.bennee@linaro.org>
>> wrote:
>> >
>> >>
>> >> frank.chang@sifive.com writes:
>> >>
>> >> > From: Frank Chang <frank.chang@sifive.com>
>> >> >
>> >> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
>> >>
>> >> Did I miss the rest of the series somewhere?
>> >>
>> >> Otherwise this looks fine to me:
>> >>
>> >> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>> >>
>> >> If you mean float16 to uint8 and int8 conversion functions, this commit
>> is
>> > everything.
>> > I think I just cc the mail based on *scripts/get_maintainer.pl
>> > <http://get_maintainer.pl>*, so probably didn't send the whole series to
>> > everyone.
>>
>> Usually I see the rest of the thread from the mailing list. I can't see:
>>
>> In-Reply-To: <20200710104920.13550-1-frank.chang@sifive.com>
>> References: <20200710104920.13550-1-frank.chang@sifive.com>
>>
>> on any of the qemu mailing lists.
>>
>> --
>> Alex Bennée
>>
>
> The rest of the patches are coming out:
> https://patchew.org/QEMU/20200710104920.13550-1-frank.chang@sifive.com/
> Not sure what caused the delay...
Ahh the mailing list is still chugging a bit it seems.
--
Alex Bennée
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 01/65] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
2020-07-10 10:48 ` frank.chang
@ 2020-07-10 16:12 ` Richard Henderson
-1 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 16:12 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Alistair Francis, Palmer Dabbelt, LIU Zhiwei, Sagar Karandikar,
Bastian Koppelmann
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> gvec should provide vecop_list to avoid:
> "tcg_tcg_assert_listed_vecop: code should not be reached bug" assertion.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.inc.c | 5 +++++
> 1 file changed, 5 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Alistair, this one should be queued for 5.1 as a bug fix.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 01/65] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
@ 2020-07-10 16:12 ` Richard Henderson
0 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 16:12 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> gvec should provide vecop_list to avoid:
> "tcg_tcg_assert_listed_vecop: code should not be reached bug" assertion.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.inc.c | 5 +++++
> 1 file changed, 5 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Alistair, this one should be queued for 5.1 as a bug fix.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 02/65] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
2020-07-10 10:48 ` frank.chang
@ 2020-07-10 16:13 ` Richard Henderson
-1 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 16:13 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Alistair Francis, Palmer Dabbelt, LIU Zhiwei, Sagar Karandikar,
Bastian Koppelmann
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Alistair, this one should be queued for 5.1 as a bug fix.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 02/65] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
@ 2020-07-10 16:13 ` Richard Henderson
0 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 16:13 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Alistair, this one should be queued for 5.1 as a bug fix.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 03/65] target/riscv: fix return value of do_opivx_widen()
2020-07-10 10:48 ` frank.chang
@ 2020-07-10 16:14 ` Richard Henderson
-1 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 16:14 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Alistair Francis, Palmer Dabbelt, LIU Zhiwei, Sagar Karandikar,
Bastian Koppelmann
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> do_opivx_widen() should return false if check function returns false.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Alistair, this one should be queued for 5.1 as a bug fix.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 03/65] target/riscv: fix return value of do_opivx_widen()
@ 2020-07-10 16:14 ` Richard Henderson
0 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 16:14 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> do_opivx_widen() should return false if check function returns false.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Alistair, this one should be queued for 5.1 as a bug fix.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 04/65] target/riscv: fix vill bit index in vtype register
2020-07-10 10:48 ` frank.chang
@ 2020-07-10 16:15 ` Richard Henderson
-1 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 16:15 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar, Bastian Koppelmann
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> vill bit is at vtype[XLEN-1].
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/cpu.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Alistair, this one should be queued for 5.1 as a bug fix.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 04/65] target/riscv: fix vill bit index in vtype register
@ 2020-07-10 16:15 ` Richard Henderson
0 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 16:15 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Alistair Francis, Palmer Dabbelt, Sagar Karandikar, Bastian Koppelmann
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> vill bit is at vtype[XLEN-1].
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/cpu.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Alistair, this one should be queued for 5.1 as a bug fix.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
2020-07-10 10:48 ` frank.chang
@ 2020-07-10 16:27 ` Richard Henderson
-1 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 16:27 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Alistair Francis, Palmer Dabbelt, LIU Zhiwei, Sagar Karandikar,
Bastian Koppelmann
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> vsll.vi, vsrl.vi, vsra.vi cannot use shli gvec as it requires the
> shift immediate value to be within the range: [0.. SEW bits].
> Otherwise, it will hit the assertion:
> tcg_debug_assert(shift >= 0 && shift < (8 << vece));
>
> However, RVV spec does not have such constraint, therefore we have to
> use helper functions instead.
Why do you say that? It does have such a constraint:
# Only the low lg2(SEW) bits are read to obtain the shift amount from a
register value.
While that only talks about the register value, I sincerely doubt that the same
truncation does not actually apply to immediates.
And if the entire immediate value does apply, the manual should certainly
specify what should happen in that case. And at present it doesn't.
It seems to me the bug is the bare use of GEN_OPIVI_GVEC_TRANS and thence
do_opivi_gvec. The ZX parameter should be extended to more than just "zero vs
sign-extend", it should have an option for truncating the immediate to s->sew.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
@ 2020-07-10 16:27 ` Richard Henderson
0 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 16:27 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> vsll.vi, vsrl.vi, vsra.vi cannot use shli gvec as it requires the
> shift immediate value to be within the range: [0.. SEW bits].
> Otherwise, it will hit the assertion:
> tcg_debug_assert(shift >= 0 && shift < (8 << vece));
>
> However, RVV spec does not have such constraint, therefore we have to
> use helper functions instead.
Why do you say that? It does have such a constraint:
# Only the low lg2(SEW) bits are read to obtain the shift amount from a
register value.
While that only talks about the register value, I sincerely doubt that the same
truncation does not actually apply to immediates.
And if the entire immediate value does apply, the manual should certainly
specify what should happen in that case. And at present it doesn't.
It seems to me the bug is the bare use of GEN_OPIVI_GVEC_TRANS and thence
do_opivi_gvec. The ZX parameter should be extended to more than just "zero vs
sign-extend", it should have an option for truncating the immediate to s->sew.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 06/65] target/riscv: rvv-0.9: add vcsr register
2020-07-10 10:48 ` frank.chang
@ 2020-07-10 17:02 ` Richard Henderson
-1 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 17:02 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Bastian Koppelmann, Alistair Francis, Palmer Dabbelt,
Sagar Karandikar, LIU Zhiwei
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> + [CSR_VCSR] = { vs, read_vcsr, write_vcsr },
As long as you have the vext_spec argument, you need a separate vs_0_9
predicate function, so that this csr is not available to VEXT_VERSION_0_07_1.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 06/65] target/riscv: rvv-0.9: add vcsr register
@ 2020-07-10 17:02 ` Richard Henderson
0 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 17:02 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Bastian Koppelmann, Alistair Francis,
Palmer Dabbelt, LIU Zhiwei
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> + [CSR_VCSR] = { vs, read_vcsr, write_vcsr },
As long as you have the vext_spec argument, you need a separate vs_0_9
predicate function, so that this csr is not available to VEXT_VERSION_0_07_1.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 07/65] target/riscv: rvv-0.9: add vector context status
2020-07-10 10:48 ` frank.chang
@ 2020-07-10 17:26 ` Richard Henderson
-1 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 17:26 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Alistair Francis, Palmer Dabbelt, LIU Zhiwei, Sagar Karandikar,
Bastian Koppelmann
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -376,6 +376,7 @@
> #define MSTATUS_SPP 0x00000100
> #define MSTATUS_MPP 0x00001800
> #define MSTATUS_FS 0x00006000
> +#define MSTATUS_VS 0x00000600
> #define MSTATUS_XS 0x00018000
Please sort VS up below SPP, so that the bits are in order.
> @@ -180,6 +180,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
> return -1;
> }
> env->mstatus |= MSTATUS_FS;
> + env->mstatus |= MSTATUS_VS;
> #endif
> env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
> if (vs(env, csrno) >= 0) {
Does rvv 0.9 still have the vector fields in FCSR, or are they only present in
the new VCSR?
> @@ -420,7 +442,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
> mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
> MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
> MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
> - MSTATUS_TW;
> + MSTATUS_TW | MSTATUS_VS;
Since 0.7.1 does not have the VS field, you might want to force VS to dirty in
the written mstatus. Correspondingly, you should remove VS from the returned
mstatus in read_mstatus.
You appear to be missing a change to riscv_cpu_swap_hypervisor_regs.
That makes all of the riscv_cpu_vector_enabled checks return true for 0.7.1,
which afaik is correct.
> @@ -245,7 +250,9 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> - return ldst_us_trans(a->rd, a->rs1, data, fn, s);
> + ret = ldst_us_trans(a->rd, a->rs1, data, fn, s);
> + mark_vs_dirty(s);
> + return ret;
Just push the mark_vs_dirty call into ldst_us_trans.
> @@ -382,7 +390,9 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> - return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
> + ret = ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
> + mark_vs_dirty(s);
> + return ret;
Likewise.
> @@ -510,7 +521,9 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> - return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
> + ret = ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
> + mark_vs_dirty(s);
> + return ret;
Likewise.
> @@ -632,7 +646,9 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> - return ldff_trans(a->rd, a->rs1, data, fn, s);
> + ret = ldff_trans(a->rd, a->rs1, data, fn, s);
> + mark_vs_dirty(s);
Likewise.
> @@ -741,7 +758,9 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, WD, a->wd);
> - return amo_trans(a->rd, a->rs1, a->rs2, data, fn, s);
> + ret = amo_trans(a->rd, a->rs1, a->rs2, data, fn, s);
> + mark_vs_dirty(s);
> + return ret;
Likewise.
> @@ -911,9 +932,12 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
>
> tcg_temp_free_i64(src1);
> tcg_temp_free(tmp);
> + mark_vs_dirty(s);
> return true;
> }
> - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
> + ret = opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
> + mark_vs_dirty(s);
> + return ret;
Likewise. And more.
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 9632e79cf3..a806e33301 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -47,6 +47,7 @@ typedef struct DisasContext {
> bool virt_enabled;
> uint32_t opcode;
> uint32_t mstatus_fs;
> + uint32_t mstatus_vs;
Missing a change to riscv_tr_init_disas_context to initialize this.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 07/65] target/riscv: rvv-0.9: add vector context status
@ 2020-07-10 17:26 ` Richard Henderson
0 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 17:26 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: LIU Zhiwei, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -376,6 +376,7 @@
> #define MSTATUS_SPP 0x00000100
> #define MSTATUS_MPP 0x00001800
> #define MSTATUS_FS 0x00006000
> +#define MSTATUS_VS 0x00000600
> #define MSTATUS_XS 0x00018000
Please sort VS up below SPP, so that the bits are in order.
> @@ -180,6 +180,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
> return -1;
> }
> env->mstatus |= MSTATUS_FS;
> + env->mstatus |= MSTATUS_VS;
> #endif
> env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
> if (vs(env, csrno) >= 0) {
Does rvv 0.9 still have the vector fields in FCSR, or are they only present in
the new VCSR?
> @@ -420,7 +442,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
> mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
> MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
> MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
> - MSTATUS_TW;
> + MSTATUS_TW | MSTATUS_VS;
Since 0.7.1 does not have the VS field, you might want to force VS to dirty in
the written mstatus. Correspondingly, you should remove VS from the returned
mstatus in read_mstatus.
You appear to be missing a change to riscv_cpu_swap_hypervisor_regs.
That makes all of the riscv_cpu_vector_enabled checks return true for 0.7.1,
which afaik is correct.
> @@ -245,7 +250,9 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> - return ldst_us_trans(a->rd, a->rs1, data, fn, s);
> + ret = ldst_us_trans(a->rd, a->rs1, data, fn, s);
> + mark_vs_dirty(s);
> + return ret;
Just push the mark_vs_dirty call into ldst_us_trans.
> @@ -382,7 +390,9 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> - return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
> + ret = ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
> + mark_vs_dirty(s);
> + return ret;
Likewise.
> @@ -510,7 +521,9 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> - return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
> + ret = ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
> + mark_vs_dirty(s);
> + return ret;
Likewise.
> @@ -632,7 +646,9 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> - return ldff_trans(a->rd, a->rs1, data, fn, s);
> + ret = ldff_trans(a->rd, a->rs1, data, fn, s);
> + mark_vs_dirty(s);
Likewise.
> @@ -741,7 +758,9 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, WD, a->wd);
> - return amo_trans(a->rd, a->rs1, a->rs2, data, fn, s);
> + ret = amo_trans(a->rd, a->rs1, a->rs2, data, fn, s);
> + mark_vs_dirty(s);
> + return ret;
Likewise.
> @@ -911,9 +932,12 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
>
> tcg_temp_free_i64(src1);
> tcg_temp_free(tmp);
> + mark_vs_dirty(s);
> return true;
> }
> - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
> + ret = opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
> + mark_vs_dirty(s);
> + return ret;
Likewise. And more.
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 9632e79cf3..a806e33301 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -47,6 +47,7 @@ typedef struct DisasContext {
> bool virt_enabled;
> uint32_t opcode;
> uint32_t mstatus_fs;
> + uint32_t mstatus_vs;
Missing a change to riscv_tr_init_disas_context to initialize this.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 07/65] target/riscv: rvv-0.9: add vector context status
2020-07-10 10:48 ` frank.chang
@ 2020-07-10 17:27 ` Richard Henderson
-1 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 17:27 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Alistair Francis, Palmer Dabbelt, LIU Zhiwei, Sagar Karandikar,
Bastian Koppelmann
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> From: LIU Zhiwei <zhiwei_liu@c-sky.com>
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/cpu.h | 4 ++
> target/riscv/cpu_bits.h | 1 +
> target/riscv/cpu_helper.c | 13 ++++++
> target/riscv/csr.c | 25 ++++++++++-
> target/riscv/insn_trans/trans_rvv.inc.c | 57 +++++++++++++++++++++----
> target/riscv/translate.c | 32 ++++++++++++++
> 6 files changed, 123 insertions(+), 9 deletions(-)
BTW, I think this should be split.
One patch for the csr.c changes, another for the translate changes.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 07/65] target/riscv: rvv-0.9: add vector context status
@ 2020-07-10 17:27 ` Richard Henderson
0 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 17:27 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: LIU Zhiwei, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> From: LIU Zhiwei <zhiwei_liu@c-sky.com>
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/cpu.h | 4 ++
> target/riscv/cpu_bits.h | 1 +
> target/riscv/cpu_helper.c | 13 ++++++
> target/riscv/csr.c | 25 ++++++++++-
> target/riscv/insn_trans/trans_rvv.inc.c | 57 +++++++++++++++++++++----
> target/riscv/translate.c | 32 ++++++++++++++
> 6 files changed, 123 insertions(+), 9 deletions(-)
BTW, I think this should be split.
One patch for the csr.c changes, another for the translate changes.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 08/65] target/riscv: rvv-0.9: update mstatus_vs by tb_flags
2020-07-10 10:48 ` frank.chang
@ 2020-07-10 17:28 ` Richard Henderson
-1 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 17:28 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Bastian Koppelmann, Alistair Francis, Palmer Dabbelt,
Sagar Karandikar, LIU Zhiwei
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> From: LIU Zhiwei <zhiwei_liu@c-sky.com>
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/cpu.h | 2 ++
> target/riscv/translate.c | 1 +
> 2 files changed, 3 insertions(+)
This belongs with the second half of the previous patch, the translate portion.
r~
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 0cf3fe9456..c02690ed0d 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -361,6 +361,7 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
>
> #define TB_FLAGS_MMU_MASK 3
> #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
> +#define TB_FLAGS_MSTATUS_VS MSTATUS_VS
>
> typedef CPURISCVState CPUArchState;
> typedef RISCVCPU ArchCPU;
> @@ -411,6 +412,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
>
> #ifdef CONFIG_USER_ONLY
> flags |= TB_FLAGS_MSTATUS_FS;
> + flags |= TB_FLAGS_MSTATUS_VS;
> #else
> flags |= cpu_mmu_index(env, 0);
> if (riscv_cpu_fp_enabled(env)) {
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index a806e33301..02b4204584 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -796,6 +796,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> ctx->pc_succ_insn = ctx->base.pc_first;
> ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK;
> ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
> + ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS;
> ctx->priv_ver = env->priv_ver;
> #if !defined(CONFIG_USER_ONLY)
> if (riscv_has_ext(env, RVH)) {
>
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 08/65] target/riscv: rvv-0.9: update mstatus_vs by tb_flags
@ 2020-07-10 17:28 ` Richard Henderson
0 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 17:28 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Bastian Koppelmann, Alistair Francis,
Palmer Dabbelt, LIU Zhiwei
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> From: LIU Zhiwei <zhiwei_liu@c-sky.com>
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/cpu.h | 2 ++
> target/riscv/translate.c | 1 +
> 2 files changed, 3 insertions(+)
This belongs with the second half of the previous patch, the translate portion.
r~
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 0cf3fe9456..c02690ed0d 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -361,6 +361,7 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
>
> #define TB_FLAGS_MMU_MASK 3
> #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
> +#define TB_FLAGS_MSTATUS_VS MSTATUS_VS
>
> typedef CPURISCVState CPUArchState;
> typedef RISCVCPU ArchCPU;
> @@ -411,6 +412,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
>
> #ifdef CONFIG_USER_ONLY
> flags |= TB_FLAGS_MSTATUS_FS;
> + flags |= TB_FLAGS_MSTATUS_VS;
> #else
> flags |= cpu_mmu_index(env, 0);
> if (riscv_cpu_fp_enabled(env)) {
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index a806e33301..02b4204584 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -796,6 +796,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> ctx->pc_succ_insn = ctx->base.pc_first;
> ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK;
> ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
> + ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS;
> ctx->priv_ver = env->priv_ver;
> #if !defined(CONFIG_USER_ONLY)
> if (riscv_has_ext(env, RVH)) {
>
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 09/65] target/riscv: rvv-0.9: add vlenb register
2020-07-10 10:48 ` frank.chang
@ 2020-07-10 17:31 ` Richard Henderson
-1 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 17:31 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Bastian Koppelmann, Palmer Dabbelt,
Greentime Hu, Alistair Francis, LIU Zhiwei
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 228b9bdb5d..871c2ddfa1 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -317,6 +317,7 @@ static void riscv_cpu_reset(DeviceState *dev)
> env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
> env->mcause = 0;
> env->pc = env->resetvec;
> + env->vlenb = cpu->cfg.vlen >> 3;
> #endif
> cs->exception_index = EXCP_NONE;
> env->load_res = -1;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index c02690ed0d..81c85bf4c2 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -111,6 +111,7 @@ struct CPURISCVState {
> target_ulong vl;
> target_ulong vstart;
> target_ulong vtype;
> + target_ulong vlenb;
I don't see that you need this. The field is read-only, so the read_vlenb
function can just return
env_archcpu(env)->cfg.vlen >> 3
directly.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 09/65] target/riscv: rvv-0.9: add vlenb register
@ 2020-07-10 17:31 ` Richard Henderson
0 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 17:31 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Bastian Koppelmann, LIU Zhiwei,
Alistair Francis, Greentime Hu, Palmer Dabbelt
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 228b9bdb5d..871c2ddfa1 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -317,6 +317,7 @@ static void riscv_cpu_reset(DeviceState *dev)
> env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
> env->mcause = 0;
> env->pc = env->resetvec;
> + env->vlenb = cpu->cfg.vlen >> 3;
> #endif
> cs->exception_index = EXCP_NONE;
> env->load_res = -1;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index c02690ed0d..81c85bf4c2 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -111,6 +111,7 @@ struct CPURISCVState {
> target_ulong vl;
> target_ulong vstart;
> target_ulong vtype;
> + target_ulong vlenb;
I don't see that you need this. The field is read-only, so the read_vlenb
function can just return
env_archcpu(env)->cfg.vlen >> 3
directly.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 10/65] target/riscv: rvv-0.9: remove MLEN calculations
2020-07-10 10:48 ` frank.chang
@ 2020-07-10 17:32 ` Richard Henderson
-1 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 17:32 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Alistair Francis, Palmer Dabbelt, LIU Zhiwei, Sagar Karandikar,
Bastian Koppelmann
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> As in RVV 0.9 design, MLEN is hardcoded with value 1 (Section 4.5).
> Thus, remove all MLEN related calculations.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.inc.c | 44 +----
> target/riscv/internals.h | 9 +-
> target/riscv/translate.c | 2 -
> target/riscv/vector_helper.c | 252 ++++++++++--------------
> 4 files changed, 116 insertions(+), 191 deletions(-)
You can't do this until you remove 0.7.1 support.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 10/65] target/riscv: rvv-0.9: remove MLEN calculations
@ 2020-07-10 17:32 ` Richard Henderson
0 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 17:32 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> As in RVV 0.9 design, MLEN is hardcoded with value 1 (Section 4.5).
> Thus, remove all MLEN related calculations.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.inc.c | 44 +----
> target/riscv/internals.h | 9 +-
> target/riscv/translate.c | 2 -
> target/riscv/vector_helper.c | 252 ++++++++++--------------
> 4 files changed, 116 insertions(+), 191 deletions(-)
You can't do this until you remove 0.7.1 support.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 11/65] target/riscv: rvv-0.9: add fractional LMUL, VTA and VMA
2020-07-10 10:48 ` frank.chang
@ 2020-07-10 17:45 ` Richard Henderson
-1 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 17:45 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Alistair Francis, Palmer Dabbelt, LIU Zhiwei, Sagar Karandikar,
Bastian Koppelmann
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> -static void vext_clear(void *tail, uint32_t cnt, uint32_t tot)
> +static void vext_clear(void *tail, uint32_t vta, uint32_t cnt, uint32_t tot)
> {
> + /* tail element undisturbed */
> + if (vta == 0) {
> + return;
> + }
> +
> memset(tail, 0, tot - cnt);
> }
First, this patch is doing too much. LMUL should definitely be split from
VTA/VMA; they are not functionally related.
Second, it would be in-spec to simply do nothing for VTA/VMA, except validate
their setting within VTYPE.
Third, the spec talks about setting "agnostic" values to 1s, not 0s as you are
doing here. So there's definitely something wrong.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 11/65] target/riscv: rvv-0.9: add fractional LMUL, VTA and VMA
@ 2020-07-10 17:45 ` Richard Henderson
0 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 17:45 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> -static void vext_clear(void *tail, uint32_t cnt, uint32_t tot)
> +static void vext_clear(void *tail, uint32_t vta, uint32_t cnt, uint32_t tot)
> {
> + /* tail element undisturbed */
> + if (vta == 0) {
> + return;
> + }
> +
> memset(tail, 0, tot - cnt);
> }
First, this patch is doing too much. LMUL should definitely be split from
VTA/VMA; they are not functionally related.
Second, it would be in-spec to simply do nothing for VTA/VMA, except validate
their setting within VTYPE.
Third, the spec talks about setting "agnostic" values to 1s, not 0s as you are
doing here. So there's definitely something wrong.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 12/65] target/riscv: rvv-0.9: update check functions
2020-07-10 10:48 ` frank.chang
@ 2020-07-10 17:51 ` Richard Henderson
-1 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 17:51 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Alistair Francis, Palmer Dabbelt, LIU Zhiwei, Sagar Karandikar,
Bastian Koppelmann
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> +#define REQUIRE_RVV do { \
> + if (s->mstatus_vs == 0) \
> + return false; \
> +} while (0)
You've used this macro already back in patch 7. I guess it should not have
been there? Or this bit belongs there, one or the other.
I think this patch requires a description and justification. I have no idea
why you are replacing
> - return (vext_check_isa_ill(s) &&
> - vext_check_overlap_mask(s, a->rd, a->vm, false) &&
> - vext_check_reg(s, a->rd, false) &&
> - vext_check_reg(s, a->rs2, false) &&
> - vext_check_reg(s, a->rs1, false));
with invisible returns
> + REQUIRE_RVV;
> + VEXT_CHECK_ISA_ILL(s);
> + VEXT_CHECK_SSS(s, a->rd, a->rs1, a->rs2, a->vm, true);
> + return true;
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 12/65] target/riscv: rvv-0.9: update check functions
@ 2020-07-10 17:51 ` Richard Henderson
0 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 17:51 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> +#define REQUIRE_RVV do { \
> + if (s->mstatus_vs == 0) \
> + return false; \
> +} while (0)
You've used this macro already back in patch 7. I guess it should not have
been there? Or this bit belongs there, one or the other.
I think this patch requires a description and justification. I have no idea
why you are replacing
> - return (vext_check_isa_ill(s) &&
> - vext_check_overlap_mask(s, a->rd, a->vm, false) &&
> - vext_check_reg(s, a->rd, false) &&
> - vext_check_reg(s, a->rs2, false) &&
> - vext_check_reg(s, a->rs1, false));
with invisible returns
> + REQUIRE_RVV;
> + VEXT_CHECK_ISA_ILL(s);
> + VEXT_CHECK_SSS(s, a->rd, a->rs1, a->rs2, a->vm, true);
> + return true;
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 13/65] target/riscv: rvv-0.9: configure instructions
2020-07-10 10:48 ` frank.chang
@ 2020-07-10 18:06 ` Richard Henderson
-1 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 18:06 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Alistair Francis, Palmer Dabbelt, LIU Zhiwei, Sagar Karandikar,
Bastian Koppelmann
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> -static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
> +static bool trans_vsetvl(DisasContext *s, arg_vsetvl *a)
Do not mix this change with anything else.
> + rd = tcg_const_i32(a->rd);
> + rs1 = tcg_const_i32(a->rs1);
Any time you put a register number into a tcg const, there's probably a better
way to do things.
> - /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
> - if (a->rs1 == 0) {
> - /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
> - s1 = tcg_const_tl(RV_VLEN_MAX);
> - } else {
> - s1 = tcg_temp_new();
> - gen_get_gpr(s1, a->rs1);
> - }
E.g. this code should be kept, and add
if (a->rd == 0 && a->rs1 == 0) {
s1 = tcg_temp_new();
tcg_gen_mov_tl(s1, cpu_vl);
} else ...
> + if ((sew > cpu->cfg.elen)
> + || vill
> + || vflmul < ((float)sew / cpu->cfg.elen)
> + || (ediv != 0)
> + || (reserved != 0)) {
> /* only set vill bit. */
> env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
> - env->vl = 0;
> - env->vstart = 0;
> return 0;
> }
You do need to check 0.7.1 so long as it's supported.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 13/65] target/riscv: rvv-0.9: configure instructions
@ 2020-07-10 18:06 ` Richard Henderson
0 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 18:06 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> -static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
> +static bool trans_vsetvl(DisasContext *s, arg_vsetvl *a)
Do not mix this change with anything else.
> + rd = tcg_const_i32(a->rd);
> + rs1 = tcg_const_i32(a->rs1);
Any time you put a register number into a tcg const, there's probably a better
way to do things.
> - /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
> - if (a->rs1 == 0) {
> - /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
> - s1 = tcg_const_tl(RV_VLEN_MAX);
> - } else {
> - s1 = tcg_temp_new();
> - gen_get_gpr(s1, a->rs1);
> - }
E.g. this code should be kept, and add
if (a->rd == 0 && a->rs1 == 0) {
s1 = tcg_temp_new();
tcg_gen_mov_tl(s1, cpu_vl);
} else ...
> + if ((sew > cpu->cfg.elen)
> + || vill
> + || vflmul < ((float)sew / cpu->cfg.elen)
> + || (ediv != 0)
> + || (reserved != 0)) {
> /* only set vill bit. */
> env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
> - env->vl = 0;
> - env->vstart = 0;
> return 0;
> }
You do need to check 0.7.1 so long as it's supported.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions
2020-07-10 10:48 ` frank.chang
@ 2020-07-10 18:15 ` Richard Henderson
-1 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 18:15 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Alistair Francis, Palmer Dabbelt, LIU Zhiwei, Sagar Karandikar,
Bastian Koppelmann
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> # *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
> -vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
> -vlh_v ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm
> -vlw_v ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm
Again, something you can't do until 0.7.1 is not supported.
If you don't want to simultaneously support 0.7.1 and 0.9/1.0, then you should
simply remove 0.7.1 in the first patch, so that there's no confusion.
Is the rest of it mostly renaming? You should definitely expand on what you're
doing within each patch description. A description of what has changed in the
spec since 0.7.1 will help the reviewer validate that you've gotten all of the
corner cases.
I am going to stop reviewing this patch series now, as I expect that most of
the remaining patches will have similar comments.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions
@ 2020-07-10 18:15 ` Richard Henderson
0 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-10 18:15 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> # *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
> -vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
> -vlh_v ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm
> -vlw_v ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm
Again, something you can't do until 0.7.1 is not supported.
If you don't want to simultaneously support 0.7.1 and 0.9/1.0, then you should
simply remove 0.7.1 in the first patch, so that there's no confusion.
Is the rest of it mostly renaming? You should definitely expand on what you're
doing within each patch description. A description of what has changed in the
spec since 0.7.1 will help the reviewer validate that you've gotten all of the
corner cases.
I am going to stop reviewing this patch series now, as I expect that most of
the remaining patches will have similar comments.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 57/65] target/riscv: rvv-0.9: floating-point min/max instructions
2020-07-10 10:49 ` frank.chang
@ 2020-07-10 18:19 ` Alex Bennée
-1 siblings, 0 replies; 211+ messages in thread
From: Alex Bennée @ 2020-07-10 18:19 UTC (permalink / raw)
To: frank.chang
Cc: qemu-riscv, Sagar Karandikar, Bastian Koppelmann, qemu-devel,
Alistair Francis, Palmer Dabbelt
frank.chang@sifive.com writes:
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/vector_helper.c | 24 ++++++++++++------------
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 42a48be5fd..d617d0dfbd 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -3831,28 +3831,28 @@ GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4, clearl)
> GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8, clearq)
>
> /* Vector Floating-Point MIN/MAX Instructions */
> -RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum)
> -RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum)
> -RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minnum)
> +RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum_noprop)
> +RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum_noprop)
> +RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8,
> float64_minnum_noprop)
This patch breaks bisection because you don't introduce this into
softfloat until later. You should always ensure each step can build and
run - practically this means the softfloat changes should be at the
beginning of the series.
> GEN_VEXT_VV_ENV(vfmin_vv_h, 2, 2, clearh)
> GEN_VEXT_VV_ENV(vfmin_vv_w, 4, 4, clearl)
> GEN_VEXT_VV_ENV(vfmin_vv_d, 8, 8, clearq)
> -RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum)
> -RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum)
> -RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum)
> +RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum_noprop)
> +RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum_noprop)
> +RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum_noprop)
> GEN_VEXT_VF(vfmin_vf_h, 2, 2, clearh)
> GEN_VEXT_VF(vfmin_vf_w, 4, 4, clearl)
> GEN_VEXT_VF(vfmin_vf_d, 8, 8, clearq)
>
> -RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum)
> -RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum)
> -RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum)
> +RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum_noprop)
> +RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum_noprop)
> +RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum_noprop)
> GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2, clearh)
> GEN_VEXT_VV_ENV(vfmax_vv_w, 4, 4, clearl)
> GEN_VEXT_VV_ENV(vfmax_vv_d, 8, 8, clearq)
> -RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum)
> -RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum)
> -RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum)
> +RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum_noprop)
> +RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum_noprop)
> +RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum_noprop)
> GEN_VEXT_VF(vfmax_vf_h, 2, 2, clearh)
> GEN_VEXT_VF(vfmax_vf_w, 4, 4, clearl)
> GEN_VEXT_VF(vfmax_vf_d, 8, 8, clearq)
--
Alex Bennée
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 57/65] target/riscv: rvv-0.9: floating-point min/max instructions
@ 2020-07-10 18:19 ` Alex Bennée
0 siblings, 0 replies; 211+ messages in thread
From: Alex Bennée @ 2020-07-10 18:19 UTC (permalink / raw)
To: frank.chang
Cc: qemu-riscv, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann, qemu-devel
frank.chang@sifive.com writes:
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/vector_helper.c | 24 ++++++++++++------------
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 42a48be5fd..d617d0dfbd 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -3831,28 +3831,28 @@ GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4, clearl)
> GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8, clearq)
>
> /* Vector Floating-Point MIN/MAX Instructions */
> -RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum)
> -RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum)
> -RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minnum)
> +RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum_noprop)
> +RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum_noprop)
> +RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8,
> float64_minnum_noprop)
This patch breaks bisection because you don't introduce this into
softfloat until later. You should always ensure each step can build and
run - practically this means the softfloat changes should be at the
beginning of the series.
> GEN_VEXT_VV_ENV(vfmin_vv_h, 2, 2, clearh)
> GEN_VEXT_VV_ENV(vfmin_vv_w, 4, 4, clearl)
> GEN_VEXT_VV_ENV(vfmin_vv_d, 8, 8, clearq)
> -RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum)
> -RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum)
> -RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum)
> +RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum_noprop)
> +RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum_noprop)
> +RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum_noprop)
> GEN_VEXT_VF(vfmin_vf_h, 2, 2, clearh)
> GEN_VEXT_VF(vfmin_vf_w, 4, 4, clearl)
> GEN_VEXT_VF(vfmin_vf_d, 8, 8, clearq)
>
> -RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum)
> -RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum)
> -RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum)
> +RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum_noprop)
> +RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum_noprop)
> +RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum_noprop)
> GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2, clearh)
> GEN_VEXT_VV_ENV(vfmax_vv_w, 4, 4, clearl)
> GEN_VEXT_VV_ENV(vfmax_vv_d, 8, 8, clearq)
> -RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum)
> -RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum)
> -RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum)
> +RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum_noprop)
> +RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum_noprop)
> +RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum_noprop)
> GEN_VEXT_VF(vfmax_vf_h, 2, 2, clearh)
> GEN_VEXT_VF(vfmax_vf_w, 4, 4, clearl)
> GEN_VEXT_VF(vfmax_vf_d, 8, 8, clearq)
--
Alex Bennée
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 01/65] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
2020-07-10 16:12 ` Richard Henderson
@ 2020-07-10 18:24 ` Alistair Francis
-1 siblings, 0 replies; 211+ messages in thread
From: Alistair Francis @ 2020-07-10 18:24 UTC (permalink / raw)
To: Richard Henderson
Cc: open list:RISC-V, Sagar Karandikar, frank.chang,
Bastian Koppelmann, qemu-devel@nongnu.org Developers,
Alistair Francis, Palmer Dabbelt, LIU Zhiwei
On Fri, Jul 10, 2020 at 9:13 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> > From: Frank Chang <frank.chang@sifive.com>
> >
> > gvec should provide vecop_list to avoid:
> > "tcg_tcg_assert_listed_vecop: code should not be reached bug" assertion.
> >
> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
> > ---
> > target/riscv/insn_trans/trans_rvv.inc.c | 5 +++++
> > 1 file changed, 5 insertions(+)
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> Alistair, this one should be queued for 5.1 as a bug fix.
Thanks for reviewing these. I have applied the first 4 to my PR for 5.1.
Alistair
>
>
> r~
>
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 01/65] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
@ 2020-07-10 18:24 ` Alistair Francis
0 siblings, 0 replies; 211+ messages in thread
From: Alistair Francis @ 2020-07-10 18:24 UTC (permalink / raw)
To: Richard Henderson
Cc: frank.chang, qemu-devel@nongnu.org Developers, open list:RISC-V,
Alistair Francis, Palmer Dabbelt, LIU Zhiwei, Sagar Karandikar,
Bastian Koppelmann
On Fri, Jul 10, 2020 at 9:13 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> > From: Frank Chang <frank.chang@sifive.com>
> >
> > gvec should provide vecop_list to avoid:
> > "tcg_tcg_assert_listed_vecop: code should not be reached bug" assertion.
> >
> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
> > ---
> > target/riscv/insn_trans/trans_rvv.inc.c | 5 +++++
> > 1 file changed, 5 insertions(+)
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> Alistair, this one should be queued for 5.1 as a bug fix.
Thanks for reviewing these. I have applied the first 4 to my PR for 5.1.
Alistair
>
>
> r~
>
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 00/65] target/riscv: support vector extension v0.9
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
@ 2020-07-10 21:43 ` Alistair Francis
2020-07-10 10:48 ` frank.chang
` (64 subsequent siblings)
65 siblings, 0 replies; 211+ messages in thread
From: Alistair Francis @ 2020-07-10 21:43 UTC (permalink / raw)
To: frank.chang; +Cc: open list:RISC-V, qemu-devel@nongnu.org Developers
On Fri, Jul 10, 2020 at 5:59 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> This patchset implements the vector extension v0.9 for RISC-V on QEMU.
>
> This patchset is sent as RFC because RVV v0.9 is still in draft state.
> However, as RVV v1.0 should be ratified soon and there shouldn't be
> critical changes between RVV v1.0 and RVV v0.9. We would like to have
> the community to review RVV v0.9 implementations. Once RVV v1.0 is
> ratified, we will then upgrade to RVV v1.0.
>
> You can change the cpu argument: vext_spec to v0.9 (i.e. vext_spec=v0.9)
> to run with RVV v0.9 instructions.
Hello,
First off thanks for the patches!
QEMU has a policy of accepting draft specs as experimental. We
currently support the v0.7.1 Vector extension for example, so this
does not need to be an RFC and can be a full patch series that can be
merged into master.
I have applied the first few patches (PR should be out next week) and
they should be in the QEMU 5.1 release. QEMU is currently in a freeze
so I won't be able to merge this series for 5.1. In saying that please
feel free to continue to send patches to the list, they can still be
reviewed.
In general we would need to gracefully handle extension upgrades and
maintain backwards compatibility. This same principle doesn't apply to
experimental features though (such as the vector extension) so you are
free to remove support for the v0.7.1. For users who want v0.7.1
support they can always use the QEMU 5.1. release. Just make sure that
your series does not break bisectability.
Thanks again for the patches!
Alistair
>
> Chih-Min Chao (2):
> fpu: fix float16 nan check
> fpu: add api to handle alternative sNaN propagation
>
> Frank Chang (58):
> target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
> target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
> target/riscv: fix return value of do_opivx_widen()
> target/riscv: fix vill bit index in vtype register
> target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
> target/riscv: rvv-0.9: remove MLEN calculations
> target/riscv: rvv-0.9: add fractional LMUL, VTA and VMA
> target/riscv: rvv-0.9: update check functions
> target/riscv: rvv-0.9: configure instructions
> target/riscv: rvv-0.9: stride load and store instructions
> target/riscv: rvv-0.9: index load and store instructions
> target/riscv: rvv-0.9: fix address index overflow bug of indexed
> load/store insns
> target/riscv: rvv-0.9: fault-only-first unit stride load
> target/riscv: rvv-0.9: amo operations
> target/riscv: rvv-0.9: load/store whole register instructions
> target/riscv: rvv-0.9: update vext_max_elems() for load/store insns
> target/riscv: rvv-0.9: take fractional LMUL into vector max elements
> calculation
> target/riscv: rvv-0.9: floating-point square-root instruction
> target/riscv: rvv-0.9: floating-point classify instructions
> target/riscv: rvv-0.9: mask population count instruction
> target/riscv: rvv-0.9: find-first-set mask bit instruction
> target/riscv: rvv-0.9: set-X-first mask bit instructions
> target/riscv: rvv-0.9: iota instruction
> target/riscv: rvv-0.9: element index instruction
> target/riscv: rvv-0.9: integer scalar move instructions
> target/riscv: rvv-0.9: floating-point scalar move instructions
> target/riscv: rvv-0.9: whole register move instructions
> target/riscv: rvv-0.9: integer extension instructions
> target/riscv: rvv-0.9: single-width averaging add and subtract
> instructions
> target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow
> target/riscv: rvv-0.9: narrowing integer right shift instructions
> target/riscv: rvv-0.9: widening integer multiply-add instructions
> target/riscv: rvv-0.9: quad-widening integer multiply-add instructions
> target/riscv: rvv-0.9: integer merge and move instructions
> target/riscv: rvv-0.9: single-width saturating add and subtract
> instructions
> target/riscv: rvv-0.9: integer comparison instructions
> target/riscv: rvv-0.9: floating-point compare instructions
> target/riscv: rvv-0.9: single-width integer reduction instructions
> target/riscv: rvv-0.9: widening integer reduction instructions
> target/riscv: rvv-0.9: mask-register logical instructions
> target/riscv: rvv-0.9: register gather instructions
> target/riscv: rvv-0.9: slide instructions
> target/riscv: rvv-0.9: floating-point slide instructions
> target/riscv: rvv-0.9: narrowing fixed-point clip instructions
> target/riscv: rvv-0.9: floating-point move instructions
> target/riscv: rvv-0.9: floating-point/integer type-convert
> instructions
> target/riscv: rvv-0.9: single-width floating-point reduction
> target/riscv: rvv-0.9: widening floating-point reduction instructions
> target/riscv: rvv-0.9: single-width scaling shift instructions
> target/riscv: rvv-0.9: remove widening saturating scaled multiply-add
> target/riscv: rvv-0.9: remove vmford.vv and vmford.vf
> target/riscv: rvv-0.9: remove integer extract instruction
> target/riscv: rvv-0.9: floating-point min/max instructions
> target/riscv: rvv-0.9: widening floating-point/integer type-convert
> target/riscv: rvv-0.9: narrowing floating-point/integer type-convert
> softfloat: add fp16 and uint8/int8 interconvert functions
> target/riscv: use softfloat lib float16 comparison functions
> target/riscv: bump to RVV 0.9
>
> Kito Cheng (1):
> fpu: implement full set compare for fp16
>
> LIU Zhiwei (4):
> target/riscv: rvv-0.9: add vcsr register
> target/riscv: rvv-0.9: add vector context status
> target/riscv: rvv-0.9: update mstatus_vs by tb_flags
> target/riscv: rvv-0.9: add vlenb register
>
> fpu/softfloat-specialize.inc.c | 4 +-
> fpu/softfloat.c | 342 +++-
> include/fpu/softfloat.h | 22 +
> target/riscv/cpu.c | 9 +-
> target/riscv/cpu.h | 68 +-
> target/riscv/cpu_bits.h | 9 +
> target/riscv/cpu_helper.c | 13 +
> target/riscv/csr.c | 53 +-
> target/riscv/helper.h | 507 +++--
> target/riscv/insn32-64.decode | 18 +-
> target/riscv/insn32.decode | 282 +--
> target/riscv/insn_trans/trans_rvv.inc.c | 2468 ++++++++++++++---------
> target/riscv/internals.h | 18 +-
> target/riscv/translate.c | 43 +-
> target/riscv/vector_helper.c | 2349 +++++++++++----------
> 15 files changed, 3833 insertions(+), 2372 deletions(-)
>
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 00/65] target/riscv: support vector extension v0.9
@ 2020-07-10 21:43 ` Alistair Francis
0 siblings, 0 replies; 211+ messages in thread
From: Alistair Francis @ 2020-07-10 21:43 UTC (permalink / raw)
To: frank.chang; +Cc: qemu-devel@nongnu.org Developers, open list:RISC-V
On Fri, Jul 10, 2020 at 5:59 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> This patchset implements the vector extension v0.9 for RISC-V on QEMU.
>
> This patchset is sent as RFC because RVV v0.9 is still in draft state.
> However, as RVV v1.0 should be ratified soon and there shouldn't be
> critical changes between RVV v1.0 and RVV v0.9. We would like to have
> the community to review RVV v0.9 implementations. Once RVV v1.0 is
> ratified, we will then upgrade to RVV v1.0.
>
> You can change the cpu argument: vext_spec to v0.9 (i.e. vext_spec=v0.9)
> to run with RVV v0.9 instructions.
Hello,
First off thanks for the patches!
QEMU has a policy of accepting draft specs as experimental. We
currently support the v0.7.1 Vector extension for example, so this
does not need to be an RFC and can be a full patch series that can be
merged into master.
I have applied the first few patches (PR should be out next week) and
they should be in the QEMU 5.1 release. QEMU is currently in a freeze
so I won't be able to merge this series for 5.1. In saying that please
feel free to continue to send patches to the list, they can still be
reviewed.
In general we would need to gracefully handle extension upgrades and
maintain backwards compatibility. This same principle doesn't apply to
experimental features though (such as the vector extension) so you are
free to remove support for the v0.7.1. For users who want v0.7.1
support they can always use the QEMU 5.1. release. Just make sure that
your series does not break bisectability.
Thanks again for the patches!
Alistair
>
> Chih-Min Chao (2):
> fpu: fix float16 nan check
> fpu: add api to handle alternative sNaN propagation
>
> Frank Chang (58):
> target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
> target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
> target/riscv: fix return value of do_opivx_widen()
> target/riscv: fix vill bit index in vtype register
> target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
> target/riscv: rvv-0.9: remove MLEN calculations
> target/riscv: rvv-0.9: add fractional LMUL, VTA and VMA
> target/riscv: rvv-0.9: update check functions
> target/riscv: rvv-0.9: configure instructions
> target/riscv: rvv-0.9: stride load and store instructions
> target/riscv: rvv-0.9: index load and store instructions
> target/riscv: rvv-0.9: fix address index overflow bug of indexed
> load/store insns
> target/riscv: rvv-0.9: fault-only-first unit stride load
> target/riscv: rvv-0.9: amo operations
> target/riscv: rvv-0.9: load/store whole register instructions
> target/riscv: rvv-0.9: update vext_max_elems() for load/store insns
> target/riscv: rvv-0.9: take fractional LMUL into vector max elements
> calculation
> target/riscv: rvv-0.9: floating-point square-root instruction
> target/riscv: rvv-0.9: floating-point classify instructions
> target/riscv: rvv-0.9: mask population count instruction
> target/riscv: rvv-0.9: find-first-set mask bit instruction
> target/riscv: rvv-0.9: set-X-first mask bit instructions
> target/riscv: rvv-0.9: iota instruction
> target/riscv: rvv-0.9: element index instruction
> target/riscv: rvv-0.9: integer scalar move instructions
> target/riscv: rvv-0.9: floating-point scalar move instructions
> target/riscv: rvv-0.9: whole register move instructions
> target/riscv: rvv-0.9: integer extension instructions
> target/riscv: rvv-0.9: single-width averaging add and subtract
> instructions
> target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow
> target/riscv: rvv-0.9: narrowing integer right shift instructions
> target/riscv: rvv-0.9: widening integer multiply-add instructions
> target/riscv: rvv-0.9: quad-widening integer multiply-add instructions
> target/riscv: rvv-0.9: integer merge and move instructions
> target/riscv: rvv-0.9: single-width saturating add and subtract
> instructions
> target/riscv: rvv-0.9: integer comparison instructions
> target/riscv: rvv-0.9: floating-point compare instructions
> target/riscv: rvv-0.9: single-width integer reduction instructions
> target/riscv: rvv-0.9: widening integer reduction instructions
> target/riscv: rvv-0.9: mask-register logical instructions
> target/riscv: rvv-0.9: register gather instructions
> target/riscv: rvv-0.9: slide instructions
> target/riscv: rvv-0.9: floating-point slide instructions
> target/riscv: rvv-0.9: narrowing fixed-point clip instructions
> target/riscv: rvv-0.9: floating-point move instructions
> target/riscv: rvv-0.9: floating-point/integer type-convert
> instructions
> target/riscv: rvv-0.9: single-width floating-point reduction
> target/riscv: rvv-0.9: widening floating-point reduction instructions
> target/riscv: rvv-0.9: single-width scaling shift instructions
> target/riscv: rvv-0.9: remove widening saturating scaled multiply-add
> target/riscv: rvv-0.9: remove vmford.vv and vmford.vf
> target/riscv: rvv-0.9: remove integer extract instruction
> target/riscv: rvv-0.9: floating-point min/max instructions
> target/riscv: rvv-0.9: widening floating-point/integer type-convert
> target/riscv: rvv-0.9: narrowing floating-point/integer type-convert
> softfloat: add fp16 and uint8/int8 interconvert functions
> target/riscv: use softfloat lib float16 comparison functions
> target/riscv: bump to RVV 0.9
>
> Kito Cheng (1):
> fpu: implement full set compare for fp16
>
> LIU Zhiwei (4):
> target/riscv: rvv-0.9: add vcsr register
> target/riscv: rvv-0.9: add vector context status
> target/riscv: rvv-0.9: update mstatus_vs by tb_flags
> target/riscv: rvv-0.9: add vlenb register
>
> fpu/softfloat-specialize.inc.c | 4 +-
> fpu/softfloat.c | 342 +++-
> include/fpu/softfloat.h | 22 +
> target/riscv/cpu.c | 9 +-
> target/riscv/cpu.h | 68 +-
> target/riscv/cpu_bits.h | 9 +
> target/riscv/cpu_helper.c | 13 +
> target/riscv/csr.c | 53 +-
> target/riscv/helper.h | 507 +++--
> target/riscv/insn32-64.decode | 18 +-
> target/riscv/insn32.decode | 282 +--
> target/riscv/insn_trans/trans_rvv.inc.c | 2468 ++++++++++++++---------
> target/riscv/internals.h | 18 +-
> target/riscv/translate.c | 43 +-
> target/riscv/vector_helper.c | 2349 +++++++++++----------
> 15 files changed, 3833 insertions(+), 2372 deletions(-)
>
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 00/65] target/riscv: support vector extension v0.9
2020-07-10 21:43 ` Alistair Francis
@ 2020-07-13 2:02 ` Frank Chang
-1 siblings, 0 replies; 211+ messages in thread
From: Frank Chang @ 2020-07-13 2:02 UTC (permalink / raw)
To: Alistair Francis; +Cc: open list:RISC-V, qemu-devel@nongnu.org Developers
[-- Attachment #1: Type: text/plain, Size: 7870 bytes --]
On Sat, Jul 11, 2020 at 5:53 AM Alistair Francis <alistair23@gmail.com>
wrote:
> On Fri, Jul 10, 2020 at 5:59 AM <frank.chang@sifive.com> wrote:
> >
> > From: Frank Chang <frank.chang@sifive.com>
> >
> > This patchset implements the vector extension v0.9 for RISC-V on QEMU.
> >
> > This patchset is sent as RFC because RVV v0.9 is still in draft state.
> > However, as RVV v1.0 should be ratified soon and there shouldn't be
> > critical changes between RVV v1.0 and RVV v0.9. We would like to have
> > the community to review RVV v0.9 implementations. Once RVV v1.0 is
> > ratified, we will then upgrade to RVV v1.0.
> >
> > You can change the cpu argument: vext_spec to v0.9 (i.e. vext_spec=v0.9)
> > to run with RVV v0.9 instructions.
>
> Hello,
>
> First off thanks for the patches!
>
> QEMU has a policy of accepting draft specs as experimental. We
> currently support the v0.7.1 Vector extension for example, so this
> does not need to be an RFC and can be a full patch series that can be
> merged into master.
>
> I have applied the first few patches (PR should be out next week) and
> they should be in the QEMU 5.1 release. QEMU is currently in a freeze
> so I won't be able to merge this series for 5.1. In saying that please
> feel free to continue to send patches to the list, they can still be
> reviewed.
>
> In general we would need to gracefully handle extension upgrades and
> maintain backwards compatibility. This same principle doesn't apply to
> experimental features though (such as the vector extension) so you are
> free to remove support for the v0.7.1. For users who want v0.7.1
> support they can always use the QEMU 5.1. release. Just make sure that
> your series does not break bisectability.
>
> Thanks again for the patches!
>
> Alistair
>
Hi Alistair,
Thanks for the review.
Currently I would prefer to drop 0.7.1 support because I don't know if
there's
a good way to keep both 0.7.1 and 0.9 opcodes. I'm afraid it would cause the
encoding overlap while compiling with decodetree.
Does decodetree support any feature for multi-version opcodes?
Or if it can use something like C macros to compile with the opcodes by the
vspec
user assigned? If there's any good way to keep both versions, then I can
try to rearrange
my codes to support both vspecs.
Otherwise, I'll keep on my current approach to drop the support of v0.7.1
as the way
Richard has mentioned:
*If you don't want to simultaneously support 0.7.1 and 0.9/1.0, then you
should*
*simply remove 0.7.1 in the first patch, so that there's no confusion.*
Any suggestion would be appreciated.
Thanks
--
Frank Chang
> >
> > Chih-Min Chao (2):
> > fpu: fix float16 nan check
> > fpu: add api to handle alternative sNaN propagation
> >
> > Frank Chang (58):
> > target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
> > target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
> > target/riscv: fix return value of do_opivx_widen()
> > target/riscv: fix vill bit index in vtype register
> > target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
> > target/riscv: rvv-0.9: remove MLEN calculations
> > target/riscv: rvv-0.9: add fractional LMUL, VTA and VMA
> > target/riscv: rvv-0.9: update check functions
> > target/riscv: rvv-0.9: configure instructions
> > target/riscv: rvv-0.9: stride load and store instructions
> > target/riscv: rvv-0.9: index load and store instructions
> > target/riscv: rvv-0.9: fix address index overflow bug of indexed
> > load/store insns
> > target/riscv: rvv-0.9: fault-only-first unit stride load
> > target/riscv: rvv-0.9: amo operations
> > target/riscv: rvv-0.9: load/store whole register instructions
> > target/riscv: rvv-0.9: update vext_max_elems() for load/store insns
> > target/riscv: rvv-0.9: take fractional LMUL into vector max elements
> > calculation
> > target/riscv: rvv-0.9: floating-point square-root instruction
> > target/riscv: rvv-0.9: floating-point classify instructions
> > target/riscv: rvv-0.9: mask population count instruction
> > target/riscv: rvv-0.9: find-first-set mask bit instruction
> > target/riscv: rvv-0.9: set-X-first mask bit instructions
> > target/riscv: rvv-0.9: iota instruction
> > target/riscv: rvv-0.9: element index instruction
> > target/riscv: rvv-0.9: integer scalar move instructions
> > target/riscv: rvv-0.9: floating-point scalar move instructions
> > target/riscv: rvv-0.9: whole register move instructions
> > target/riscv: rvv-0.9: integer extension instructions
> > target/riscv: rvv-0.9: single-width averaging add and subtract
> > instructions
> > target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow
> > target/riscv: rvv-0.9: narrowing integer right shift instructions
> > target/riscv: rvv-0.9: widening integer multiply-add instructions
> > target/riscv: rvv-0.9: quad-widening integer multiply-add instructions
> > target/riscv: rvv-0.9: integer merge and move instructions
> > target/riscv: rvv-0.9: single-width saturating add and subtract
> > instructions
> > target/riscv: rvv-0.9: integer comparison instructions
> > target/riscv: rvv-0.9: floating-point compare instructions
> > target/riscv: rvv-0.9: single-width integer reduction instructions
> > target/riscv: rvv-0.9: widening integer reduction instructions
> > target/riscv: rvv-0.9: mask-register logical instructions
> > target/riscv: rvv-0.9: register gather instructions
> > target/riscv: rvv-0.9: slide instructions
> > target/riscv: rvv-0.9: floating-point slide instructions
> > target/riscv: rvv-0.9: narrowing fixed-point clip instructions
> > target/riscv: rvv-0.9: floating-point move instructions
> > target/riscv: rvv-0.9: floating-point/integer type-convert
> > instructions
> > target/riscv: rvv-0.9: single-width floating-point reduction
> > target/riscv: rvv-0.9: widening floating-point reduction instructions
> > target/riscv: rvv-0.9: single-width scaling shift instructions
> > target/riscv: rvv-0.9: remove widening saturating scaled multiply-add
> > target/riscv: rvv-0.9: remove vmford.vv and vmford.vf
> > target/riscv: rvv-0.9: remove integer extract instruction
> > target/riscv: rvv-0.9: floating-point min/max instructions
> > target/riscv: rvv-0.9: widening floating-point/integer type-convert
> > target/riscv: rvv-0.9: narrowing floating-point/integer type-convert
> > softfloat: add fp16 and uint8/int8 interconvert functions
> > target/riscv: use softfloat lib float16 comparison functions
> > target/riscv: bump to RVV 0.9
> >
> > Kito Cheng (1):
> > fpu: implement full set compare for fp16
> >
> > LIU Zhiwei (4):
> > target/riscv: rvv-0.9: add vcsr register
> > target/riscv: rvv-0.9: add vector context status
> > target/riscv: rvv-0.9: update mstatus_vs by tb_flags
> > target/riscv: rvv-0.9: add vlenb register
> >
> > fpu/softfloat-specialize.inc.c | 4 +-
> > fpu/softfloat.c | 342 +++-
> > include/fpu/softfloat.h | 22 +
> > target/riscv/cpu.c | 9 +-
> > target/riscv/cpu.h | 68 +-
> > target/riscv/cpu_bits.h | 9 +
> > target/riscv/cpu_helper.c | 13 +
> > target/riscv/csr.c | 53 +-
> > target/riscv/helper.h | 507 +++--
> > target/riscv/insn32-64.decode | 18 +-
> > target/riscv/insn32.decode | 282 +--
> > target/riscv/insn_trans/trans_rvv.inc.c | 2468 ++++++++++++++---------
> > target/riscv/internals.h | 18 +-
> > target/riscv/translate.c | 43 +-
> > target/riscv/vector_helper.c | 2349 +++++++++++----------
> > 15 files changed, 3833 insertions(+), 2372 deletions(-)
> >
> > --
> > 2.17.1
> >
> >
>
[-- Attachment #2: Type: text/html, Size: 9994 bytes --]
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 00/65] target/riscv: support vector extension v0.9
@ 2020-07-13 2:02 ` Frank Chang
0 siblings, 0 replies; 211+ messages in thread
From: Frank Chang @ 2020-07-13 2:02 UTC (permalink / raw)
To: Alistair Francis; +Cc: qemu-devel@nongnu.org Developers, open list:RISC-V
[-- Attachment #1: Type: text/plain, Size: 7870 bytes --]
On Sat, Jul 11, 2020 at 5:53 AM Alistair Francis <alistair23@gmail.com>
wrote:
> On Fri, Jul 10, 2020 at 5:59 AM <frank.chang@sifive.com> wrote:
> >
> > From: Frank Chang <frank.chang@sifive.com>
> >
> > This patchset implements the vector extension v0.9 for RISC-V on QEMU.
> >
> > This patchset is sent as RFC because RVV v0.9 is still in draft state.
> > However, as RVV v1.0 should be ratified soon and there shouldn't be
> > critical changes between RVV v1.0 and RVV v0.9. We would like to have
> > the community to review RVV v0.9 implementations. Once RVV v1.0 is
> > ratified, we will then upgrade to RVV v1.0.
> >
> > You can change the cpu argument: vext_spec to v0.9 (i.e. vext_spec=v0.9)
> > to run with RVV v0.9 instructions.
>
> Hello,
>
> First off thanks for the patches!
>
> QEMU has a policy of accepting draft specs as experimental. We
> currently support the v0.7.1 Vector extension for example, so this
> does not need to be an RFC and can be a full patch series that can be
> merged into master.
>
> I have applied the first few patches (PR should be out next week) and
> they should be in the QEMU 5.1 release. QEMU is currently in a freeze
> so I won't be able to merge this series for 5.1. In saying that please
> feel free to continue to send patches to the list, they can still be
> reviewed.
>
> In general we would need to gracefully handle extension upgrades and
> maintain backwards compatibility. This same principle doesn't apply to
> experimental features though (such as the vector extension) so you are
> free to remove support for the v0.7.1. For users who want v0.7.1
> support they can always use the QEMU 5.1. release. Just make sure that
> your series does not break bisectability.
>
> Thanks again for the patches!
>
> Alistair
>
Hi Alistair,
Thanks for the review.
Currently I would prefer to drop 0.7.1 support because I don't know if
there's
a good way to keep both 0.7.1 and 0.9 opcodes. I'm afraid it would cause the
encoding overlap while compiling with decodetree.
Does decodetree support any feature for multi-version opcodes?
Or if it can use something like C macros to compile with the opcodes by the
vspec
user assigned? If there's any good way to keep both versions, then I can
try to rearrange
my codes to support both vspecs.
Otherwise, I'll keep on my current approach to drop the support of v0.7.1
as the way
Richard has mentioned:
*If you don't want to simultaneously support 0.7.1 and 0.9/1.0, then you
should*
*simply remove 0.7.1 in the first patch, so that there's no confusion.*
Any suggestion would be appreciated.
Thanks
--
Frank Chang
> >
> > Chih-Min Chao (2):
> > fpu: fix float16 nan check
> > fpu: add api to handle alternative sNaN propagation
> >
> > Frank Chang (58):
> > target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
> > target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
> > target/riscv: fix return value of do_opivx_widen()
> > target/riscv: fix vill bit index in vtype register
> > target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
> > target/riscv: rvv-0.9: remove MLEN calculations
> > target/riscv: rvv-0.9: add fractional LMUL, VTA and VMA
> > target/riscv: rvv-0.9: update check functions
> > target/riscv: rvv-0.9: configure instructions
> > target/riscv: rvv-0.9: stride load and store instructions
> > target/riscv: rvv-0.9: index load and store instructions
> > target/riscv: rvv-0.9: fix address index overflow bug of indexed
> > load/store insns
> > target/riscv: rvv-0.9: fault-only-first unit stride load
> > target/riscv: rvv-0.9: amo operations
> > target/riscv: rvv-0.9: load/store whole register instructions
> > target/riscv: rvv-0.9: update vext_max_elems() for load/store insns
> > target/riscv: rvv-0.9: take fractional LMUL into vector max elements
> > calculation
> > target/riscv: rvv-0.9: floating-point square-root instruction
> > target/riscv: rvv-0.9: floating-point classify instructions
> > target/riscv: rvv-0.9: mask population count instruction
> > target/riscv: rvv-0.9: find-first-set mask bit instruction
> > target/riscv: rvv-0.9: set-X-first mask bit instructions
> > target/riscv: rvv-0.9: iota instruction
> > target/riscv: rvv-0.9: element index instruction
> > target/riscv: rvv-0.9: integer scalar move instructions
> > target/riscv: rvv-0.9: floating-point scalar move instructions
> > target/riscv: rvv-0.9: whole register move instructions
> > target/riscv: rvv-0.9: integer extension instructions
> > target/riscv: rvv-0.9: single-width averaging add and subtract
> > instructions
> > target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow
> > target/riscv: rvv-0.9: narrowing integer right shift instructions
> > target/riscv: rvv-0.9: widening integer multiply-add instructions
> > target/riscv: rvv-0.9: quad-widening integer multiply-add instructions
> > target/riscv: rvv-0.9: integer merge and move instructions
> > target/riscv: rvv-0.9: single-width saturating add and subtract
> > instructions
> > target/riscv: rvv-0.9: integer comparison instructions
> > target/riscv: rvv-0.9: floating-point compare instructions
> > target/riscv: rvv-0.9: single-width integer reduction instructions
> > target/riscv: rvv-0.9: widening integer reduction instructions
> > target/riscv: rvv-0.9: mask-register logical instructions
> > target/riscv: rvv-0.9: register gather instructions
> > target/riscv: rvv-0.9: slide instructions
> > target/riscv: rvv-0.9: floating-point slide instructions
> > target/riscv: rvv-0.9: narrowing fixed-point clip instructions
> > target/riscv: rvv-0.9: floating-point move instructions
> > target/riscv: rvv-0.9: floating-point/integer type-convert
> > instructions
> > target/riscv: rvv-0.9: single-width floating-point reduction
> > target/riscv: rvv-0.9: widening floating-point reduction instructions
> > target/riscv: rvv-0.9: single-width scaling shift instructions
> > target/riscv: rvv-0.9: remove widening saturating scaled multiply-add
> > target/riscv: rvv-0.9: remove vmford.vv and vmford.vf
> > target/riscv: rvv-0.9: remove integer extract instruction
> > target/riscv: rvv-0.9: floating-point min/max instructions
> > target/riscv: rvv-0.9: widening floating-point/integer type-convert
> > target/riscv: rvv-0.9: narrowing floating-point/integer type-convert
> > softfloat: add fp16 and uint8/int8 interconvert functions
> > target/riscv: use softfloat lib float16 comparison functions
> > target/riscv: bump to RVV 0.9
> >
> > Kito Cheng (1):
> > fpu: implement full set compare for fp16
> >
> > LIU Zhiwei (4):
> > target/riscv: rvv-0.9: add vcsr register
> > target/riscv: rvv-0.9: add vector context status
> > target/riscv: rvv-0.9: update mstatus_vs by tb_flags
> > target/riscv: rvv-0.9: add vlenb register
> >
> > fpu/softfloat-specialize.inc.c | 4 +-
> > fpu/softfloat.c | 342 +++-
> > include/fpu/softfloat.h | 22 +
> > target/riscv/cpu.c | 9 +-
> > target/riscv/cpu.h | 68 +-
> > target/riscv/cpu_bits.h | 9 +
> > target/riscv/cpu_helper.c | 13 +
> > target/riscv/csr.c | 53 +-
> > target/riscv/helper.h | 507 +++--
> > target/riscv/insn32-64.decode | 18 +-
> > target/riscv/insn32.decode | 282 +--
> > target/riscv/insn_trans/trans_rvv.inc.c | 2468 ++++++++++++++---------
> > target/riscv/internals.h | 18 +-
> > target/riscv/translate.c | 43 +-
> > target/riscv/vector_helper.c | 2349 +++++++++++----------
> > 15 files changed, 3833 insertions(+), 2372 deletions(-)
> >
> > --
> > 2.17.1
> >
> >
>
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* Re: [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions
2020-07-10 18:15 ` Richard Henderson
@ 2020-07-13 2:04 ` Frank Chang
-1 siblings, 0 replies; 211+ messages in thread
From: Frank Chang @ 2020-07-13 2:04 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-riscv, Sagar Karandikar, Bastian Koppelmann, qemu-devel,
Palmer Dabbelt, Alistair Francis, LIU Zhiwei
[-- Attachment #1: Type: text/plain, Size: 1179 bytes --]
On Sat, Jul 11, 2020 at 2:15 AM Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> > # *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
> > -vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
> > -vlh_v ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm
> > -vlw_v ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm
>
> Again, something you can't do until 0.7.1 is not supported.
>
> If you don't want to simultaneously support 0.7.1 and 0.9/1.0, then you
> should
> simply remove 0.7.1 in the first patch, so that there's no confusion.
>
> Is the rest of it mostly renaming? You should definitely expand on what
> you're
> doing within each patch description. A description of what has changed in
> the
> spec since 0.7.1 will help the reviewer validate that you've gotten all of
> the
> corner cases.
>
> I am going to stop reviewing this patch series now, as I expect that most
> of
> the remaining patches will have similar comments.
>
>
> r~
>
Thanks for the reviews.
I will rearrange my commits as what you suggest and add more comments in my
next patchset.
--
Frank Chang
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^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions
@ 2020-07-13 2:04 ` Frank Chang
0 siblings, 0 replies; 211+ messages in thread
From: Frank Chang @ 2020-07-13 2:04 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann, LIU Zhiwei
[-- Attachment #1: Type: text/plain, Size: 1179 bytes --]
On Sat, Jul 11, 2020 at 2:15 AM Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> > # *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
> > -vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
> > -vlh_v ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm
> > -vlw_v ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm
>
> Again, something you can't do until 0.7.1 is not supported.
>
> If you don't want to simultaneously support 0.7.1 and 0.9/1.0, then you
> should
> simply remove 0.7.1 in the first patch, so that there's no confusion.
>
> Is the rest of it mostly renaming? You should definitely expand on what
> you're
> doing within each patch description. A description of what has changed in
> the
> spec since 0.7.1 will help the reviewer validate that you've gotten all of
> the
> corner cases.
>
> I am going to stop reviewing this patch series now, as I expect that most
> of
> the remaining patches will have similar comments.
>
>
> r~
>
Thanks for the reviews.
I will rearrange my commits as what you suggest and add more comments in my
next patchset.
--
Frank Chang
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^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 13/65] target/riscv: rvv-0.9: configure instructions
2020-07-10 18:06 ` Richard Henderson
@ 2020-07-13 2:07 ` Frank Chang
-1 siblings, 0 replies; 211+ messages in thread
From: Frank Chang @ 2020-07-13 2:07 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-riscv, Sagar Karandikar, Bastian Koppelmann, qemu-devel,
Palmer Dabbelt, Alistair Francis, LIU Zhiwei
[-- Attachment #1: Type: text/plain, Size: 1539 bytes --]
On Sat, Jul 11, 2020 at 2:07 AM Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> > -static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
> > +static bool trans_vsetvl(DisasContext *s, arg_vsetvl *a)
>
> Do not mix this change with anything else.
OK~
---
Frank Chang
> > + rd = tcg_const_i32(a->rd);
> > + rs1 = tcg_const_i32(a->rs1);
>
> Any time you put a register number into a tcg const, there's probably a
> better
> way to do things.
> > - /* Using x0 as the rs1 register specifier, encodes an infinite AVL
> */
> > - if (a->rs1 == 0) {
> > - /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
> > - s1 = tcg_const_tl(RV_VLEN_MAX);
> > - } else {
> > - s1 = tcg_temp_new();
> > - gen_get_gpr(s1, a->rs1);
> > - }
>
> E.g. this code should be kept, and add
>
> if (a->rd == 0 && a->rs1 == 0) {
> s1 = tcg_temp_new();
> tcg_gen_mov_tl(s1, cpu_vl);
> } else ...
>
OK~
>
> > + if ((sew > cpu->cfg.elen)
> > + || vill
> > + || vflmul < ((float)sew / cpu->cfg.elen)
> > + || (ediv != 0)
> > + || (reserved != 0)) {
> > /* only set vill bit. */
> > env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
> > - env->vl = 0;
> > - env->vstart = 0;
> > return 0;
> > }
>
> You do need to check 0.7.1 so long as it's supported.
>
>
> r~
>
Will drop 0.7.1 support in my first patch to prevent the confusion.
Frank Chang
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^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 13/65] target/riscv: rvv-0.9: configure instructions
@ 2020-07-13 2:07 ` Frank Chang
0 siblings, 0 replies; 211+ messages in thread
From: Frank Chang @ 2020-07-13 2:07 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann, LIU Zhiwei
[-- Attachment #1: Type: text/plain, Size: 1539 bytes --]
On Sat, Jul 11, 2020 at 2:07 AM Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> > -static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
> > +static bool trans_vsetvl(DisasContext *s, arg_vsetvl *a)
>
> Do not mix this change with anything else.
OK~
---
Frank Chang
> > + rd = tcg_const_i32(a->rd);
> > + rs1 = tcg_const_i32(a->rs1);
>
> Any time you put a register number into a tcg const, there's probably a
> better
> way to do things.
> > - /* Using x0 as the rs1 register specifier, encodes an infinite AVL
> */
> > - if (a->rs1 == 0) {
> > - /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
> > - s1 = tcg_const_tl(RV_VLEN_MAX);
> > - } else {
> > - s1 = tcg_temp_new();
> > - gen_get_gpr(s1, a->rs1);
> > - }
>
> E.g. this code should be kept, and add
>
> if (a->rd == 0 && a->rs1 == 0) {
> s1 = tcg_temp_new();
> tcg_gen_mov_tl(s1, cpu_vl);
> } else ...
>
OK~
>
> > + if ((sew > cpu->cfg.elen)
> > + || vill
> > + || vflmul < ((float)sew / cpu->cfg.elen)
> > + || (ediv != 0)
> > + || (reserved != 0)) {
> > /* only set vill bit. */
> > env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
> > - env->vl = 0;
> > - env->vstart = 0;
> > return 0;
> > }
>
> You do need to check 0.7.1 so long as it's supported.
>
>
> r~
>
Will drop 0.7.1 support in my first patch to prevent the confusion.
Frank Chang
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^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 12/65] target/riscv: rvv-0.9: update check functions
2020-07-10 17:51 ` Richard Henderson
@ 2020-07-13 2:10 ` Frank Chang
-1 siblings, 0 replies; 211+ messages in thread
From: Frank Chang @ 2020-07-13 2:10 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-riscv, Sagar Karandikar, Bastian Koppelmann, qemu-devel,
Palmer Dabbelt, Alistair Francis, LIU Zhiwei
[-- Attachment #1: Type: text/plain, Size: 1105 bytes --]
On Sat, Jul 11, 2020 at 1:51 AM Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> > +#define REQUIRE_RVV do { \
> > + if (s->mstatus_vs == 0) \
> > + return false; \
> > +} while (0)
>
> You've used this macro already back in patch 7. I guess it should not have
> been there? Or this bit belongs there, one or the other.
>
> I think this patch requires a description and justification. I have no
> idea
> why you are replacing
>
Yes, this change should be moved to patch 7.
>
> > - return (vext_check_isa_ill(s) &&
> > - vext_check_overlap_mask(s, a->rd, a->vm, false) &&
> > - vext_check_reg(s, a->rd, false) &&
> > - vext_check_reg(s, a->rs2, false) &&
> > - vext_check_reg(s, a->rs1, false));
>
> with invisible returns
>
> > + REQUIRE_RVV;
> > + VEXT_CHECK_ISA_ILL(s);
> > + VEXT_CHECK_SSS(s, a->rd, a->rs1, a->rs2, a->vm, true);
> > + return true;
>
>
> r~
>
You're right, I will resend the patches with more description and
justification.
Frank Chang
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^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 12/65] target/riscv: rvv-0.9: update check functions
@ 2020-07-13 2:10 ` Frank Chang
0 siblings, 0 replies; 211+ messages in thread
From: Frank Chang @ 2020-07-13 2:10 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann, LIU Zhiwei
[-- Attachment #1: Type: text/plain, Size: 1105 bytes --]
On Sat, Jul 11, 2020 at 1:51 AM Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> > +#define REQUIRE_RVV do { \
> > + if (s->mstatus_vs == 0) \
> > + return false; \
> > +} while (0)
>
> You've used this macro already back in patch 7. I guess it should not have
> been there? Or this bit belongs there, one or the other.
>
> I think this patch requires a description and justification. I have no
> idea
> why you are replacing
>
Yes, this change should be moved to patch 7.
>
> > - return (vext_check_isa_ill(s) &&
> > - vext_check_overlap_mask(s, a->rd, a->vm, false) &&
> > - vext_check_reg(s, a->rd, false) &&
> > - vext_check_reg(s, a->rs2, false) &&
> > - vext_check_reg(s, a->rs1, false));
>
> with invisible returns
>
> > + REQUIRE_RVV;
> > + VEXT_CHECK_ISA_ILL(s);
> > + VEXT_CHECK_SSS(s, a->rd, a->rs1, a->rs2, a->vm, true);
> > + return true;
>
>
> r~
>
You're right, I will resend the patches with more description and
justification.
Frank Chang
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^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 00/65] target/riscv: support vector extension v0.9
2020-07-13 2:02 ` Frank Chang
@ 2020-07-13 15:57 ` Alistair Francis
-1 siblings, 0 replies; 211+ messages in thread
From: Alistair Francis @ 2020-07-13 15:57 UTC (permalink / raw)
To: Frank Chang; +Cc: open list:RISC-V, qemu-devel@nongnu.org Developers
On Sun, Jul 12, 2020 at 7:02 PM Frank Chang <frank.chang@sifive.com> wrote:
>
> On Sat, Jul 11, 2020 at 5:53 AM Alistair Francis <alistair23@gmail.com> wrote:
>>
>> On Fri, Jul 10, 2020 at 5:59 AM <frank.chang@sifive.com> wrote:
>> >
>> > From: Frank Chang <frank.chang@sifive.com>
>> >
>> > This patchset implements the vector extension v0.9 for RISC-V on QEMU.
>> >
>> > This patchset is sent as RFC because RVV v0.9 is still in draft state.
>> > However, as RVV v1.0 should be ratified soon and there shouldn't be
>> > critical changes between RVV v1.0 and RVV v0.9. We would like to have
>> > the community to review RVV v0.9 implementations. Once RVV v1.0 is
>> > ratified, we will then upgrade to RVV v1.0.
>> >
>> > You can change the cpu argument: vext_spec to v0.9 (i.e. vext_spec=v0.9)
>> > to run with RVV v0.9 instructions.
>>
>> Hello,
>>
>> First off thanks for the patches!
>>
>> QEMU has a policy of accepting draft specs as experimental. We
>> currently support the v0.7.1 Vector extension for example, so this
>> does not need to be an RFC and can be a full patch series that can be
>> merged into master.
>>
>> I have applied the first few patches (PR should be out next week) and
>> they should be in the QEMU 5.1 release. QEMU is currently in a freeze
>> so I won't be able to merge this series for 5.1. In saying that please
>> feel free to continue to send patches to the list, they can still be
>> reviewed.
>>
>> In general we would need to gracefully handle extension upgrades and
>> maintain backwards compatibility. This same principle doesn't apply to
>> experimental features though (such as the vector extension) so you are
>> free to remove support for the v0.7.1. For users who want v0.7.1
>> support they can always use the QEMU 5.1. release. Just make sure that
>> your series does not break bisectability.
>>
>> Thanks again for the patches!
>>
>> Alistair
>
>
> Hi Alistair,
>
> Thanks for the review.
>
> Currently I would prefer to drop 0.7.1 support because I don't know if there's
> a good way to keep both 0.7.1 and 0.9 opcodes. I'm afraid it would cause the
> encoding overlap while compiling with decodetree.
That's fine. The plan was always to only support one version of a
draft extension (and none when the final spec is frozen).
>
> Does decodetree support any feature for multi-version opcodes?
I'm not sure, but we don't want to deal with the maintenance burden of
two draft extensions anyway.
> Or if it can use something like C macros to compile with the opcodes by the vspec
> user assigned? If there's any good way to keep both versions, then I can try to rearrange
> my codes to support both vspecs.
>
> Otherwise, I'll keep on my current approach to drop the support of v0.7.1 as the way
> Richard has mentioned:
> If you don't want to simultaneously support 0.7.1 and 0.9/1.0, then you should
> simply remove 0.7.1 in the first patch, so that there's no confusion.
That sounds good :)
Alistair
>
> Any suggestion would be appreciated.
>
> Thanks
> --
> Frank Chang
>
>>
>> >
>> > Chih-Min Chao (2):
>> > fpu: fix float16 nan check
>> > fpu: add api to handle alternative sNaN propagation
>> >
>> > Frank Chang (58):
>> > target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
>> > target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
>> > target/riscv: fix return value of do_opivx_widen()
>> > target/riscv: fix vill bit index in vtype register
>> > target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
>> > target/riscv: rvv-0.9: remove MLEN calculations
>> > target/riscv: rvv-0.9: add fractional LMUL, VTA and VMA
>> > target/riscv: rvv-0.9: update check functions
>> > target/riscv: rvv-0.9: configure instructions
>> > target/riscv: rvv-0.9: stride load and store instructions
>> > target/riscv: rvv-0.9: index load and store instructions
>> > target/riscv: rvv-0.9: fix address index overflow bug of indexed
>> > load/store insns
>> > target/riscv: rvv-0.9: fault-only-first unit stride load
>> > target/riscv: rvv-0.9: amo operations
>> > target/riscv: rvv-0.9: load/store whole register instructions
>> > target/riscv: rvv-0.9: update vext_max_elems() for load/store insns
>> > target/riscv: rvv-0.9: take fractional LMUL into vector max elements
>> > calculation
>> > target/riscv: rvv-0.9: floating-point square-root instruction
>> > target/riscv: rvv-0.9: floating-point classify instructions
>> > target/riscv: rvv-0.9: mask population count instruction
>> > target/riscv: rvv-0.9: find-first-set mask bit instruction
>> > target/riscv: rvv-0.9: set-X-first mask bit instructions
>> > target/riscv: rvv-0.9: iota instruction
>> > target/riscv: rvv-0.9: element index instruction
>> > target/riscv: rvv-0.9: integer scalar move instructions
>> > target/riscv: rvv-0.9: floating-point scalar move instructions
>> > target/riscv: rvv-0.9: whole register move instructions
>> > target/riscv: rvv-0.9: integer extension instructions
>> > target/riscv: rvv-0.9: single-width averaging add and subtract
>> > instructions
>> > target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow
>> > target/riscv: rvv-0.9: narrowing integer right shift instructions
>> > target/riscv: rvv-0.9: widening integer multiply-add instructions
>> > target/riscv: rvv-0.9: quad-widening integer multiply-add instructions
>> > target/riscv: rvv-0.9: integer merge and move instructions
>> > target/riscv: rvv-0.9: single-width saturating add and subtract
>> > instructions
>> > target/riscv: rvv-0.9: integer comparison instructions
>> > target/riscv: rvv-0.9: floating-point compare instructions
>> > target/riscv: rvv-0.9: single-width integer reduction instructions
>> > target/riscv: rvv-0.9: widening integer reduction instructions
>> > target/riscv: rvv-0.9: mask-register logical instructions
>> > target/riscv: rvv-0.9: register gather instructions
>> > target/riscv: rvv-0.9: slide instructions
>> > target/riscv: rvv-0.9: floating-point slide instructions
>> > target/riscv: rvv-0.9: narrowing fixed-point clip instructions
>> > target/riscv: rvv-0.9: floating-point move instructions
>> > target/riscv: rvv-0.9: floating-point/integer type-convert
>> > instructions
>> > target/riscv: rvv-0.9: single-width floating-point reduction
>> > target/riscv: rvv-0.9: widening floating-point reduction instructions
>> > target/riscv: rvv-0.9: single-width scaling shift instructions
>> > target/riscv: rvv-0.9: remove widening saturating scaled multiply-add
>> > target/riscv: rvv-0.9: remove vmford.vv and vmford.vf
>> > target/riscv: rvv-0.9: remove integer extract instruction
>> > target/riscv: rvv-0.9: floating-point min/max instructions
>> > target/riscv: rvv-0.9: widening floating-point/integer type-convert
>> > target/riscv: rvv-0.9: narrowing floating-point/integer type-convert
>> > softfloat: add fp16 and uint8/int8 interconvert functions
>> > target/riscv: use softfloat lib float16 comparison functions
>> > target/riscv: bump to RVV 0.9
>> >
>> > Kito Cheng (1):
>> > fpu: implement full set compare for fp16
>> >
>> > LIU Zhiwei (4):
>> > target/riscv: rvv-0.9: add vcsr register
>> > target/riscv: rvv-0.9: add vector context status
>> > target/riscv: rvv-0.9: update mstatus_vs by tb_flags
>> > target/riscv: rvv-0.9: add vlenb register
>> >
>> > fpu/softfloat-specialize.inc.c | 4 +-
>> > fpu/softfloat.c | 342 +++-
>> > include/fpu/softfloat.h | 22 +
>> > target/riscv/cpu.c | 9 +-
>> > target/riscv/cpu.h | 68 +-
>> > target/riscv/cpu_bits.h | 9 +
>> > target/riscv/cpu_helper.c | 13 +
>> > target/riscv/csr.c | 53 +-
>> > target/riscv/helper.h | 507 +++--
>> > target/riscv/insn32-64.decode | 18 +-
>> > target/riscv/insn32.decode | 282 +--
>> > target/riscv/insn_trans/trans_rvv.inc.c | 2468 ++++++++++++++---------
>> > target/riscv/internals.h | 18 +-
>> > target/riscv/translate.c | 43 +-
>> > target/riscv/vector_helper.c | 2349 +++++++++++----------
>> > 15 files changed, 3833 insertions(+), 2372 deletions(-)
>> >
>> > --
>> > 2.17.1
>> >
>> >
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 00/65] target/riscv: support vector extension v0.9
@ 2020-07-13 15:57 ` Alistair Francis
0 siblings, 0 replies; 211+ messages in thread
From: Alistair Francis @ 2020-07-13 15:57 UTC (permalink / raw)
To: Frank Chang; +Cc: qemu-devel@nongnu.org Developers, open list:RISC-V
On Sun, Jul 12, 2020 at 7:02 PM Frank Chang <frank.chang@sifive.com> wrote:
>
> On Sat, Jul 11, 2020 at 5:53 AM Alistair Francis <alistair23@gmail.com> wrote:
>>
>> On Fri, Jul 10, 2020 at 5:59 AM <frank.chang@sifive.com> wrote:
>> >
>> > From: Frank Chang <frank.chang@sifive.com>
>> >
>> > This patchset implements the vector extension v0.9 for RISC-V on QEMU.
>> >
>> > This patchset is sent as RFC because RVV v0.9 is still in draft state.
>> > However, as RVV v1.0 should be ratified soon and there shouldn't be
>> > critical changes between RVV v1.0 and RVV v0.9. We would like to have
>> > the community to review RVV v0.9 implementations. Once RVV v1.0 is
>> > ratified, we will then upgrade to RVV v1.0.
>> >
>> > You can change the cpu argument: vext_spec to v0.9 (i.e. vext_spec=v0.9)
>> > to run with RVV v0.9 instructions.
>>
>> Hello,
>>
>> First off thanks for the patches!
>>
>> QEMU has a policy of accepting draft specs as experimental. We
>> currently support the v0.7.1 Vector extension for example, so this
>> does not need to be an RFC and can be a full patch series that can be
>> merged into master.
>>
>> I have applied the first few patches (PR should be out next week) and
>> they should be in the QEMU 5.1 release. QEMU is currently in a freeze
>> so I won't be able to merge this series for 5.1. In saying that please
>> feel free to continue to send patches to the list, they can still be
>> reviewed.
>>
>> In general we would need to gracefully handle extension upgrades and
>> maintain backwards compatibility. This same principle doesn't apply to
>> experimental features though (such as the vector extension) so you are
>> free to remove support for the v0.7.1. For users who want v0.7.1
>> support they can always use the QEMU 5.1. release. Just make sure that
>> your series does not break bisectability.
>>
>> Thanks again for the patches!
>>
>> Alistair
>
>
> Hi Alistair,
>
> Thanks for the review.
>
> Currently I would prefer to drop 0.7.1 support because I don't know if there's
> a good way to keep both 0.7.1 and 0.9 opcodes. I'm afraid it would cause the
> encoding overlap while compiling with decodetree.
That's fine. The plan was always to only support one version of a
draft extension (and none when the final spec is frozen).
>
> Does decodetree support any feature for multi-version opcodes?
I'm not sure, but we don't want to deal with the maintenance burden of
two draft extensions anyway.
> Or if it can use something like C macros to compile with the opcodes by the vspec
> user assigned? If there's any good way to keep both versions, then I can try to rearrange
> my codes to support both vspecs.
>
> Otherwise, I'll keep on my current approach to drop the support of v0.7.1 as the way
> Richard has mentioned:
> If you don't want to simultaneously support 0.7.1 and 0.9/1.0, then you should
> simply remove 0.7.1 in the first patch, so that there's no confusion.
That sounds good :)
Alistair
>
> Any suggestion would be appreciated.
>
> Thanks
> --
> Frank Chang
>
>>
>> >
>> > Chih-Min Chao (2):
>> > fpu: fix float16 nan check
>> > fpu: add api to handle alternative sNaN propagation
>> >
>> > Frank Chang (58):
>> > target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
>> > target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
>> > target/riscv: fix return value of do_opivx_widen()
>> > target/riscv: fix vill bit index in vtype register
>> > target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
>> > target/riscv: rvv-0.9: remove MLEN calculations
>> > target/riscv: rvv-0.9: add fractional LMUL, VTA and VMA
>> > target/riscv: rvv-0.9: update check functions
>> > target/riscv: rvv-0.9: configure instructions
>> > target/riscv: rvv-0.9: stride load and store instructions
>> > target/riscv: rvv-0.9: index load and store instructions
>> > target/riscv: rvv-0.9: fix address index overflow bug of indexed
>> > load/store insns
>> > target/riscv: rvv-0.9: fault-only-first unit stride load
>> > target/riscv: rvv-0.9: amo operations
>> > target/riscv: rvv-0.9: load/store whole register instructions
>> > target/riscv: rvv-0.9: update vext_max_elems() for load/store insns
>> > target/riscv: rvv-0.9: take fractional LMUL into vector max elements
>> > calculation
>> > target/riscv: rvv-0.9: floating-point square-root instruction
>> > target/riscv: rvv-0.9: floating-point classify instructions
>> > target/riscv: rvv-0.9: mask population count instruction
>> > target/riscv: rvv-0.9: find-first-set mask bit instruction
>> > target/riscv: rvv-0.9: set-X-first mask bit instructions
>> > target/riscv: rvv-0.9: iota instruction
>> > target/riscv: rvv-0.9: element index instruction
>> > target/riscv: rvv-0.9: integer scalar move instructions
>> > target/riscv: rvv-0.9: floating-point scalar move instructions
>> > target/riscv: rvv-0.9: whole register move instructions
>> > target/riscv: rvv-0.9: integer extension instructions
>> > target/riscv: rvv-0.9: single-width averaging add and subtract
>> > instructions
>> > target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow
>> > target/riscv: rvv-0.9: narrowing integer right shift instructions
>> > target/riscv: rvv-0.9: widening integer multiply-add instructions
>> > target/riscv: rvv-0.9: quad-widening integer multiply-add instructions
>> > target/riscv: rvv-0.9: integer merge and move instructions
>> > target/riscv: rvv-0.9: single-width saturating add and subtract
>> > instructions
>> > target/riscv: rvv-0.9: integer comparison instructions
>> > target/riscv: rvv-0.9: floating-point compare instructions
>> > target/riscv: rvv-0.9: single-width integer reduction instructions
>> > target/riscv: rvv-0.9: widening integer reduction instructions
>> > target/riscv: rvv-0.9: mask-register logical instructions
>> > target/riscv: rvv-0.9: register gather instructions
>> > target/riscv: rvv-0.9: slide instructions
>> > target/riscv: rvv-0.9: floating-point slide instructions
>> > target/riscv: rvv-0.9: narrowing fixed-point clip instructions
>> > target/riscv: rvv-0.9: floating-point move instructions
>> > target/riscv: rvv-0.9: floating-point/integer type-convert
>> > instructions
>> > target/riscv: rvv-0.9: single-width floating-point reduction
>> > target/riscv: rvv-0.9: widening floating-point reduction instructions
>> > target/riscv: rvv-0.9: single-width scaling shift instructions
>> > target/riscv: rvv-0.9: remove widening saturating scaled multiply-add
>> > target/riscv: rvv-0.9: remove vmford.vv and vmford.vf
>> > target/riscv: rvv-0.9: remove integer extract instruction
>> > target/riscv: rvv-0.9: floating-point min/max instructions
>> > target/riscv: rvv-0.9: widening floating-point/integer type-convert
>> > target/riscv: rvv-0.9: narrowing floating-point/integer type-convert
>> > softfloat: add fp16 and uint8/int8 interconvert functions
>> > target/riscv: use softfloat lib float16 comparison functions
>> > target/riscv: bump to RVV 0.9
>> >
>> > Kito Cheng (1):
>> > fpu: implement full set compare for fp16
>> >
>> > LIU Zhiwei (4):
>> > target/riscv: rvv-0.9: add vcsr register
>> > target/riscv: rvv-0.9: add vector context status
>> > target/riscv: rvv-0.9: update mstatus_vs by tb_flags
>> > target/riscv: rvv-0.9: add vlenb register
>> >
>> > fpu/softfloat-specialize.inc.c | 4 +-
>> > fpu/softfloat.c | 342 +++-
>> > include/fpu/softfloat.h | 22 +
>> > target/riscv/cpu.c | 9 +-
>> > target/riscv/cpu.h | 68 +-
>> > target/riscv/cpu_bits.h | 9 +
>> > target/riscv/cpu_helper.c | 13 +
>> > target/riscv/csr.c | 53 +-
>> > target/riscv/helper.h | 507 +++--
>> > target/riscv/insn32-64.decode | 18 +-
>> > target/riscv/insn32.decode | 282 +--
>> > target/riscv/insn_trans/trans_rvv.inc.c | 2468 ++++++++++++++---------
>> > target/riscv/internals.h | 18 +-
>> > target/riscv/translate.c | 43 +-
>> > target/riscv/vector_helper.c | 2349 +++++++++++----------
>> > 15 files changed, 3833 insertions(+), 2372 deletions(-)
>> >
>> > --
>> > 2.17.1
>> >
>> >
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 00/65] target/riscv: support vector extension v0.9
2020-07-13 2:02 ` Frank Chang
(?)
(?)
@ 2020-07-13 16:41 ` Richard Henderson
2020-07-13 16:44 ` Frank Chang
-1 siblings, 1 reply; 211+ messages in thread
From: Richard Henderson @ 2020-07-13 16:41 UTC (permalink / raw)
To: Frank Chang, Alistair Francis
Cc: open list:RISC-V, qemu-devel@nongnu.org Developers
On 7/12/20 7:02 PM, Frank Chang wrote:
> Does decodetree support any feature for multi-version opcodes?
> Or if it can use something like C macros to compile with the opcodes by the vspec
> user assigned? If there's any good way to keep both versions, then I can try to
> rearrange
> my codes to support both vspecs.
There is a way, using { } to indicate where overlap is allowed. The trans_*
functions checks the ISA version, and return false. Which causes the next
matching overlapping pattern to be used, etc. Have a look at some of the ARM
decodetree files.
But since Alisair is happy dropping 0.7.1 support, we should do that. It will
be cleaner not to have to retain the backward compatibility.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 00/65] target/riscv: support vector extension v0.9
2020-07-13 16:41 ` Richard Henderson
@ 2020-07-13 16:44 ` Frank Chang
0 siblings, 0 replies; 211+ messages in thread
From: Frank Chang @ 2020-07-13 16:44 UTC (permalink / raw)
To: Richard Henderson
Cc: Alistair Francis, open list:RISC-V, qemu-devel@nongnu.org Developers
[-- Attachment #1: Type: text/plain, Size: 925 bytes --]
On Tue, Jul 14, 2020 at 12:41 AM Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 7/12/20 7:02 PM, Frank Chang wrote:
> > Does decodetree support any feature for multi-version opcodes?
> > Or if it can use something like C macros to compile with the opcodes by
> the vspec
> > user assigned? If there's any good way to keep both versions, then I can
> try to
> > rearrange
> > my codes to support both vspecs.
>
> There is a way, using { } to indicate where overlap is allowed. The
> trans_*
> functions checks the ISA version, and return false. Which causes the next
> matching overlapping pattern to be used, etc. Have a look at some of the
> ARM
> decodetree files.
>
> But since Alisair is happy dropping 0.7.1 support, we should do that. It
> will
> be cleaner not to have to retain the backward compatibility.
>
>
> r~
>
That makes sense to me.
Thanks to Alisair and Richard's feedback.
Frank Chang
[-- Attachment #2: Type: text/html, Size: 1319 bytes --]
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 62/65] fpu: add api to handle alternative sNaN propagation
2020-07-10 12:15 ` Alex Bennée
@ 2020-07-13 17:38 ` Chih-Min Chao
-1 siblings, 0 replies; 211+ messages in thread
From: Chih-Min Chao @ 2020-07-13 17:38 UTC (permalink / raw)
To: Alex Bennée
Cc: frank.chang, Peter Maydell, open list:RISC-V,
qemu-devel@nongnu.org Developers, Aurelien Jarno
[-- Attachment #1: Type: text/plain, Size: 10163 bytes --]
On Fri, Jul 10, 2020 at 8:15 PM Alex Bennée <alex.bennee@linaro.org> wrote:
>
> frank.chang@sifive.com writes:
>
> > From: Chih-Min Chao <chihmin.chao@sifive.com>
> >
> > Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
> > ---
> > fpu/softfloat.c | 68 +++++++++++++++++++++++++----------------
> > include/fpu/softfloat.h | 6 ++++
> > 2 files changed, 48 insertions(+), 26 deletions(-)
> >
> > diff --git a/fpu/softfloat.c b/fpu/softfloat.c
> > index fa1c99c03e..028b857167 100644
> > --- a/fpu/softfloat.c
> > +++ b/fpu/softfloat.c
> > @@ -2777,23 +2777,32 @@ float64 uint16_to_float64(uint16_t a,
> float_status *status)
> > * and minNumMag() from the IEEE-754 2008.
> > */
> > static FloatParts minmax_floats(FloatParts a, FloatParts b, bool ismin,
> > - bool ieee, bool ismag, float_status *s)
> > + bool ieee, bool ismag, bool issnan_prop,
> > + float_status *s)
> > {
> > if (unlikely(is_nan(a.cls) || is_nan(b.cls))) {
> > if (ieee) {
> > /* Takes two floating-point values `a' and `b', one of
> > * which is a NaN, and returns the appropriate NaN
> > * result. If either `a' or `b' is a signaling NaN,
> > - * the invalid exception is raised.
> > + * the invalid exception is raised but the NaN
> > + * propagation is 'shall'.
> > */
> > if (is_snan(a.cls) || is_snan(b.cls)) {
> > - return pick_nan(a, b, s);
> > - } else if (is_nan(a.cls) && !is_nan(b.cls)) {
> > + if (issnan_prop) {
> > + pick_nan(a, b, s);
>
> This looks funky to me because you don't actually pick a nan - are you
> just using this for side effects?
>
> I'm also confused by the fact the new helpers have the prototype noprop
> which implies no propagation yes the bool flag is true and named
> issnan_prop which implies it should propagate.
>
> I think we need a clearer problem statement in the commit of what you
> are trying to achieve here. I suspect it might be worth splitting the
> flag setting from pick_nan to it's own mini helper if that is all we
> want to do in this case.
>
> > + } else {
> > + return pick_nan(a, b, s);
> > + }
> > + }
> > +
> > + if (is_nan(a.cls) && !is_nan(b.cls)) {
> > return b;
> > } else if (is_nan(b.cls) && !is_nan(a.cls)) {
> > return a;
> > }
> > }
> > +
>
> nit: stray space
>
> > return pick_nan(a, b, s);
> > } else {
> > int a_exp, b_exp;
> > @@ -2847,37 +2856,44 @@ static FloatParts minmax_floats(FloatParts a,
> FloatParts b, bool ismin,
> > }
> > }
> >
> > -#define MINMAX(sz, name, ismin, isiee, ismag)
> \
> > +#define MINMAX(sz, name, ismin, isiee, ismag, issnan_prop)
> \
> > float ## sz float ## sz ## _ ## name(float ## sz a, float ## sz b,
> \
> > float_status *s)
> \
> > {
> \
> > FloatParts pa = float ## sz ## _unpack_canonical(a, s);
> \
> > FloatParts pb = float ## sz ## _unpack_canonical(b, s);
> \
> > - FloatParts pr = minmax_floats(pa, pb, ismin, isiee, ismag, s);
> \
> > + FloatParts pr = minmax_floats(pa, pb, ismin, isiee, ismag,
> \
> > + issnan_prop, s);
> \
> >
> \
> > return float ## sz ## _round_pack_canonical(pr, s);
> \
> > }
> >
> > -MINMAX(16, min, true, false, false)
> > -MINMAX(16, minnum, true, true, false)
> > -MINMAX(16, minnummag, true, true, true)
> > -MINMAX(16, max, false, false, false)
> > -MINMAX(16, maxnum, false, true, false)
> > -MINMAX(16, maxnummag, false, true, true)
> > -
> > -MINMAX(32, min, true, false, false)
> > -MINMAX(32, minnum, true, true, false)
> > -MINMAX(32, minnummag, true, true, true)
> > -MINMAX(32, max, false, false, false)
> > -MINMAX(32, maxnum, false, true, false)
> > -MINMAX(32, maxnummag, false, true, true)
> > -
> > -MINMAX(64, min, true, false, false)
> > -MINMAX(64, minnum, true, true, false)
> > -MINMAX(64, minnummag, true, true, true)
> > -MINMAX(64, max, false, false, false)
> > -MINMAX(64, maxnum, false, true, false)
> > -MINMAX(64, maxnummag, false, true, true)
> > +MINMAX(16, min, true, false, false, false)
> > +MINMAX(16, minnum, true, true, false, false)
> > +MINMAX(16, minnum_noprop, true, true, false, true)
> > +MINMAX(16, minnummag, true, true, true, false)
> > +MINMAX(16, max, false, false, false, false)
> > +MINMAX(16, maxnum, false, true, false, false)
> > +MINMAX(16, maxnum_noprop, false, true, false, true)
> > +MINMAX(16, maxnummag, false, true, true, false)
> > +
> > +MINMAX(32, min, true, false, false, false)
> > +MINMAX(32, minnum, true, true, false, false)
> > +MINMAX(32, minnum_noprop, true, true, false, true)
> > +MINMAX(32, minnummag, true, true, true, false)
> > +MINMAX(32, max, false, false, false, false)
> > +MINMAX(32, maxnum, false, true, false, false)
> > +MINMAX(32, maxnum_noprop, false, true, false, true)
> > +MINMAX(32, maxnummag, false, true, true, false)
> > +
> > +MINMAX(64, min, true, false, false, false)
> > +MINMAX(64, minnum, true, true, false, false)
> > +MINMAX(64, minnum_noprop, true, true, false, true)
> > +MINMAX(64, minnummag, true, true, true, false)
> > +MINMAX(64, max, false, false, false, false)
> > +MINMAX(64, maxnum, false, true, false, false)
> > +MINMAX(64, maxnum_noprop, false, true, false, true)
> > +MINMAX(64, maxnummag, false, true, true, false)
> >
> > #undef MINMAX
> >
> > diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
> > index b0ae8f6295..075c680456 100644
> > --- a/include/fpu/softfloat.h
> > +++ b/include/fpu/softfloat.h
> > @@ -239,6 +239,8 @@ float16 float16_minnum(float16, float16,
> float_status *status);
> > float16 float16_maxnum(float16, float16, float_status *status);
> > float16 float16_minnummag(float16, float16, float_status *status);
> > float16 float16_maxnummag(float16, float16, float_status *status);
> > +float16 float16_minnum_noprop(float16, float16, float_status *status);
> > +float16 float16_maxnum_noprop(float16, float16, float_status *status);
> > float16 float16_sqrt(float16, float_status *status);
> > FloatRelation float16_compare(float16, float16, float_status *status);
> > FloatRelation float16_compare_quiet(float16, float16, float_status
> *status);
> > @@ -359,6 +361,8 @@ float32 float32_minnum(float32, float32,
> float_status *status);
> > float32 float32_maxnum(float32, float32, float_status *status);
> > float32 float32_minnummag(float32, float32, float_status *status);
> > float32 float32_maxnummag(float32, float32, float_status *status);
> > +float32 float32_minnum_noprop(float32, float32, float_status *status);
> > +float32 float32_maxnum_noprop(float32, float32, float_status *status);
> > bool float32_is_quiet_nan(float32, float_status *status);
> > bool float32_is_signaling_nan(float32, float_status *status);
> > float32 float32_silence_nan(float32, float_status *status);
> > @@ -548,6 +552,8 @@ float64 float64_minnum(float64, float64,
> float_status *status);
> > float64 float64_maxnum(float64, float64, float_status *status);
> > float64 float64_minnummag(float64, float64, float_status *status);
> > float64 float64_maxnummag(float64, float64, float_status *status);
> > +float64 float64_minnum_noprop(float64, float64, float_status *status);
> > +float64 float64_maxnum_noprop(float64, float64, float_status *status);
> > bool float64_is_quiet_nan(float64 a, float_status *status);
> > bool float64_is_signaling_nan(float64, float_status *status);
> > float64 float64_silence_nan(float64, float_status *status);
>
>
> --
> Alex Bennée
>
Hi Alex,
1.
This patch comes from the change of sNaN propagation implementation of
riscv floating spec.
Take following as example,
fmin.s ft0, ft1, ft2.
For spec 2.2, the sNaN handling for fmin and fmax is
if ft1 is sNaN or ft2 is sNaN
a. set the invalid flag
b. ft0 is canonical NaN
ref:
https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-user-2.2
section 8.3
"For FMIN and FMAX, if at least one input is a signaling
NaN, or if both inputs are quiet NaNs,
the result is the canonical NaN. If one operand is a quiet
NaN and the other is not a NaN, the
result is the non-NaN operand.
For spec 20191213, the behavior is changed to
if ft1 or ft2 is sNaN and the other is non-NaN
a. set the invalid flag
b. ft0 is set to non-NaN source
ref:
https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC
section 11.6
"If both inputs are NaNs, the result is
the canonical NaN. If only one operand is a NaN, the result
is the non-NaN operand. Signaling
NaN inputs set the invalid operation exception flag, even
when the result is not NaN."
2.
As you guess, the patch takes the side effect of pick_nan. The pick_nan
does two works
a. set invalid flag if input is sNaN
b. return correct NaN number by configuration
for one possible case, one operand is sNaN and the other is non-NaN, the
patch does
a. pick_nan to set invalid_flag but doesn't use the return
value)
b. return non-NaN
for the other case, both operands are sNaN, the patch does
a. pick_nan to set_invalid_flag
b pick_nan to return NaN value
Is it better to separate the "set invalid flag" part from pick_nan to make
it concrete ?
3.
The parameter naming is misleading and will be fix in next separated
softfloat patch.
Thanks
Chih-Min Chao
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^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 62/65] fpu: add api to handle alternative sNaN propagation
@ 2020-07-13 17:38 ` Chih-Min Chao
0 siblings, 0 replies; 211+ messages in thread
From: Chih-Min Chao @ 2020-07-13 17:38 UTC (permalink / raw)
To: Alex Bennée
Cc: frank.chang, qemu-devel@nongnu.org Developers, open list:RISC-V,
Aurelien Jarno, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 10163 bytes --]
On Fri, Jul 10, 2020 at 8:15 PM Alex Bennée <alex.bennee@linaro.org> wrote:
>
> frank.chang@sifive.com writes:
>
> > From: Chih-Min Chao <chihmin.chao@sifive.com>
> >
> > Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
> > ---
> > fpu/softfloat.c | 68 +++++++++++++++++++++++++----------------
> > include/fpu/softfloat.h | 6 ++++
> > 2 files changed, 48 insertions(+), 26 deletions(-)
> >
> > diff --git a/fpu/softfloat.c b/fpu/softfloat.c
> > index fa1c99c03e..028b857167 100644
> > --- a/fpu/softfloat.c
> > +++ b/fpu/softfloat.c
> > @@ -2777,23 +2777,32 @@ float64 uint16_to_float64(uint16_t a,
> float_status *status)
> > * and minNumMag() from the IEEE-754 2008.
> > */
> > static FloatParts minmax_floats(FloatParts a, FloatParts b, bool ismin,
> > - bool ieee, bool ismag, float_status *s)
> > + bool ieee, bool ismag, bool issnan_prop,
> > + float_status *s)
> > {
> > if (unlikely(is_nan(a.cls) || is_nan(b.cls))) {
> > if (ieee) {
> > /* Takes two floating-point values `a' and `b', one of
> > * which is a NaN, and returns the appropriate NaN
> > * result. If either `a' or `b' is a signaling NaN,
> > - * the invalid exception is raised.
> > + * the invalid exception is raised but the NaN
> > + * propagation is 'shall'.
> > */
> > if (is_snan(a.cls) || is_snan(b.cls)) {
> > - return pick_nan(a, b, s);
> > - } else if (is_nan(a.cls) && !is_nan(b.cls)) {
> > + if (issnan_prop) {
> > + pick_nan(a, b, s);
>
> This looks funky to me because you don't actually pick a nan - are you
> just using this for side effects?
>
> I'm also confused by the fact the new helpers have the prototype noprop
> which implies no propagation yes the bool flag is true and named
> issnan_prop which implies it should propagate.
>
> I think we need a clearer problem statement in the commit of what you
> are trying to achieve here. I suspect it might be worth splitting the
> flag setting from pick_nan to it's own mini helper if that is all we
> want to do in this case.
>
> > + } else {
> > + return pick_nan(a, b, s);
> > + }
> > + }
> > +
> > + if (is_nan(a.cls) && !is_nan(b.cls)) {
> > return b;
> > } else if (is_nan(b.cls) && !is_nan(a.cls)) {
> > return a;
> > }
> > }
> > +
>
> nit: stray space
>
> > return pick_nan(a, b, s);
> > } else {
> > int a_exp, b_exp;
> > @@ -2847,37 +2856,44 @@ static FloatParts minmax_floats(FloatParts a,
> FloatParts b, bool ismin,
> > }
> > }
> >
> > -#define MINMAX(sz, name, ismin, isiee, ismag)
> \
> > +#define MINMAX(sz, name, ismin, isiee, ismag, issnan_prop)
> \
> > float ## sz float ## sz ## _ ## name(float ## sz a, float ## sz b,
> \
> > float_status *s)
> \
> > {
> \
> > FloatParts pa = float ## sz ## _unpack_canonical(a, s);
> \
> > FloatParts pb = float ## sz ## _unpack_canonical(b, s);
> \
> > - FloatParts pr = minmax_floats(pa, pb, ismin, isiee, ismag, s);
> \
> > + FloatParts pr = minmax_floats(pa, pb, ismin, isiee, ismag,
> \
> > + issnan_prop, s);
> \
> >
> \
> > return float ## sz ## _round_pack_canonical(pr, s);
> \
> > }
> >
> > -MINMAX(16, min, true, false, false)
> > -MINMAX(16, minnum, true, true, false)
> > -MINMAX(16, minnummag, true, true, true)
> > -MINMAX(16, max, false, false, false)
> > -MINMAX(16, maxnum, false, true, false)
> > -MINMAX(16, maxnummag, false, true, true)
> > -
> > -MINMAX(32, min, true, false, false)
> > -MINMAX(32, minnum, true, true, false)
> > -MINMAX(32, minnummag, true, true, true)
> > -MINMAX(32, max, false, false, false)
> > -MINMAX(32, maxnum, false, true, false)
> > -MINMAX(32, maxnummag, false, true, true)
> > -
> > -MINMAX(64, min, true, false, false)
> > -MINMAX(64, minnum, true, true, false)
> > -MINMAX(64, minnummag, true, true, true)
> > -MINMAX(64, max, false, false, false)
> > -MINMAX(64, maxnum, false, true, false)
> > -MINMAX(64, maxnummag, false, true, true)
> > +MINMAX(16, min, true, false, false, false)
> > +MINMAX(16, minnum, true, true, false, false)
> > +MINMAX(16, minnum_noprop, true, true, false, true)
> > +MINMAX(16, minnummag, true, true, true, false)
> > +MINMAX(16, max, false, false, false, false)
> > +MINMAX(16, maxnum, false, true, false, false)
> > +MINMAX(16, maxnum_noprop, false, true, false, true)
> > +MINMAX(16, maxnummag, false, true, true, false)
> > +
> > +MINMAX(32, min, true, false, false, false)
> > +MINMAX(32, minnum, true, true, false, false)
> > +MINMAX(32, minnum_noprop, true, true, false, true)
> > +MINMAX(32, minnummag, true, true, true, false)
> > +MINMAX(32, max, false, false, false, false)
> > +MINMAX(32, maxnum, false, true, false, false)
> > +MINMAX(32, maxnum_noprop, false, true, false, true)
> > +MINMAX(32, maxnummag, false, true, true, false)
> > +
> > +MINMAX(64, min, true, false, false, false)
> > +MINMAX(64, minnum, true, true, false, false)
> > +MINMAX(64, minnum_noprop, true, true, false, true)
> > +MINMAX(64, minnummag, true, true, true, false)
> > +MINMAX(64, max, false, false, false, false)
> > +MINMAX(64, maxnum, false, true, false, false)
> > +MINMAX(64, maxnum_noprop, false, true, false, true)
> > +MINMAX(64, maxnummag, false, true, true, false)
> >
> > #undef MINMAX
> >
> > diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
> > index b0ae8f6295..075c680456 100644
> > --- a/include/fpu/softfloat.h
> > +++ b/include/fpu/softfloat.h
> > @@ -239,6 +239,8 @@ float16 float16_minnum(float16, float16,
> float_status *status);
> > float16 float16_maxnum(float16, float16, float_status *status);
> > float16 float16_minnummag(float16, float16, float_status *status);
> > float16 float16_maxnummag(float16, float16, float_status *status);
> > +float16 float16_minnum_noprop(float16, float16, float_status *status);
> > +float16 float16_maxnum_noprop(float16, float16, float_status *status);
> > float16 float16_sqrt(float16, float_status *status);
> > FloatRelation float16_compare(float16, float16, float_status *status);
> > FloatRelation float16_compare_quiet(float16, float16, float_status
> *status);
> > @@ -359,6 +361,8 @@ float32 float32_minnum(float32, float32,
> float_status *status);
> > float32 float32_maxnum(float32, float32, float_status *status);
> > float32 float32_minnummag(float32, float32, float_status *status);
> > float32 float32_maxnummag(float32, float32, float_status *status);
> > +float32 float32_minnum_noprop(float32, float32, float_status *status);
> > +float32 float32_maxnum_noprop(float32, float32, float_status *status);
> > bool float32_is_quiet_nan(float32, float_status *status);
> > bool float32_is_signaling_nan(float32, float_status *status);
> > float32 float32_silence_nan(float32, float_status *status);
> > @@ -548,6 +552,8 @@ float64 float64_minnum(float64, float64,
> float_status *status);
> > float64 float64_maxnum(float64, float64, float_status *status);
> > float64 float64_minnummag(float64, float64, float_status *status);
> > float64 float64_maxnummag(float64, float64, float_status *status);
> > +float64 float64_minnum_noprop(float64, float64, float_status *status);
> > +float64 float64_maxnum_noprop(float64, float64, float_status *status);
> > bool float64_is_quiet_nan(float64 a, float_status *status);
> > bool float64_is_signaling_nan(float64, float_status *status);
> > float64 float64_silence_nan(float64, float_status *status);
>
>
> --
> Alex Bennée
>
Hi Alex,
1.
This patch comes from the change of sNaN propagation implementation of
riscv floating spec.
Take following as example,
fmin.s ft0, ft1, ft2.
For spec 2.2, the sNaN handling for fmin and fmax is
if ft1 is sNaN or ft2 is sNaN
a. set the invalid flag
b. ft0 is canonical NaN
ref:
https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-user-2.2
section 8.3
"For FMIN and FMAX, if at least one input is a signaling
NaN, or if both inputs are quiet NaNs,
the result is the canonical NaN. If one operand is a quiet
NaN and the other is not a NaN, the
result is the non-NaN operand.
For spec 20191213, the behavior is changed to
if ft1 or ft2 is sNaN and the other is non-NaN
a. set the invalid flag
b. ft0 is set to non-NaN source
ref:
https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC
section 11.6
"If both inputs are NaNs, the result is
the canonical NaN. If only one operand is a NaN, the result
is the non-NaN operand. Signaling
NaN inputs set the invalid operation exception flag, even
when the result is not NaN."
2.
As you guess, the patch takes the side effect of pick_nan. The pick_nan
does two works
a. set invalid flag if input is sNaN
b. return correct NaN number by configuration
for one possible case, one operand is sNaN and the other is non-NaN, the
patch does
a. pick_nan to set invalid_flag but doesn't use the return
value)
b. return non-NaN
for the other case, both operands are sNaN, the patch does
a. pick_nan to set_invalid_flag
b pick_nan to return NaN value
Is it better to separate the "set invalid flag" part from pick_nan to make
it concrete ?
3.
The parameter naming is misleading and will be fix in next separated
softfloat patch.
Thanks
Chih-Min Chao
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^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
2020-07-10 16:27 ` Richard Henderson
@ 2020-07-14 2:59 ` Frank Chang
-1 siblings, 0 replies; 211+ messages in thread
From: Frank Chang @ 2020-07-14 2:59 UTC (permalink / raw)
To: Richard Henderson
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, LIU Zhiwei
[-- Attachment #1: Type: text/plain, Size: 1658 bytes --]
On Sat, Jul 11, 2020 at 12:27 AM Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> > From: Frank Chang <frank.chang@sifive.com>
> >
> > vsll.vi, vsrl.vi, vsra.vi cannot use shli gvec as it requires the
> > shift immediate value to be within the range: [0.. SEW bits].
> > Otherwise, it will hit the assertion:
> > tcg_debug_assert(shift >= 0 && shift < (8 << vece));
> >
> > However, RVV spec does not have such constraint, therefore we have to
> > use helper functions instead.
>
> Why do you say that? It does have such a constraint:
>
> # Only the low lg2(SEW) bits are read to obtain the shift amount from a
> register value.
>
> While that only talks about the register value, I sincerely doubt that the
> same
> truncation does not actually apply to immediates.
>
> And if the entire immediate value does apply, the manual should certainly
> specify what should happen in that case. And at present it doesn't.
>
> It seems to me the bug is the bare use of GEN_OPIVI_GVEC_TRANS and thence
> do_opivi_gvec. The ZX parameter should be extended to more than just
> "zero vs
> sign-extend", it should have an option for truncating the immediate to
> s->sew.
>
>
> r~
>
The latest spec specified:
Only the low *lg2(SEW) bits* are read to obtain the shift amount from
a *register
value*.
The *immediate* is treated as an *unsigned shift amount*, with a *maximum
shift amount of 31*.
Looks like the shift amount in the immediate value is not relevant with SEW
setting.
If so, is it better to just use do_opivi_gvec() and implement the logic by
our own rather than using gvec IR?
Frank Chang
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^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
@ 2020-07-14 2:59 ` Frank Chang
0 siblings, 0 replies; 211+ messages in thread
From: Frank Chang @ 2020-07-14 2:59 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei
[-- Attachment #1: Type: text/plain, Size: 1658 bytes --]
On Sat, Jul 11, 2020 at 12:27 AM Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> > From: Frank Chang <frank.chang@sifive.com>
> >
> > vsll.vi, vsrl.vi, vsra.vi cannot use shli gvec as it requires the
> > shift immediate value to be within the range: [0.. SEW bits].
> > Otherwise, it will hit the assertion:
> > tcg_debug_assert(shift >= 0 && shift < (8 << vece));
> >
> > However, RVV spec does not have such constraint, therefore we have to
> > use helper functions instead.
>
> Why do you say that? It does have such a constraint:
>
> # Only the low lg2(SEW) bits are read to obtain the shift amount from a
> register value.
>
> While that only talks about the register value, I sincerely doubt that the
> same
> truncation does not actually apply to immediates.
>
> And if the entire immediate value does apply, the manual should certainly
> specify what should happen in that case. And at present it doesn't.
>
> It seems to me the bug is the bare use of GEN_OPIVI_GVEC_TRANS and thence
> do_opivi_gvec. The ZX parameter should be extended to more than just
> "zero vs
> sign-extend", it should have an option for truncating the immediate to
> s->sew.
>
>
> r~
>
The latest spec specified:
Only the low *lg2(SEW) bits* are read to obtain the shift amount from
a *register
value*.
The *immediate* is treated as an *unsigned shift amount*, with a *maximum
shift amount of 31*.
Looks like the shift amount in the immediate value is not relevant with SEW
setting.
If so, is it better to just use do_opivi_gvec() and implement the logic by
our own rather than using gvec IR?
Frank Chang
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^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
2020-07-14 2:59 ` Frank Chang
@ 2020-07-14 3:35 ` LIU Zhiwei
-1 siblings, 0 replies; 211+ messages in thread
From: LIU Zhiwei @ 2020-07-14 3:35 UTC (permalink / raw)
To: Frank Chang, Richard Henderson
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis
[-- Attachment #1: Type: text/plain, Size: 2187 bytes --]
On 2020/7/14 10:59, Frank Chang wrote:
> On Sat, Jul 11, 2020 at 12:27 AM Richard Henderson
> <richard.henderson@linaro.org <mailto:richard.henderson@linaro.org>>
> wrote:
>
> On 7/10/20 3:48 AM, frank.chang@sifive.com
> <mailto:frank.chang@sifive.com> wrote:
> > From: Frank Chang <frank.chang@sifive.com
> <mailto:frank.chang@sifive.com>>
> >
> > vsll.vi <http://vsll.vi>, vsrl.vi <http://vsrl.vi>, vsra.vi
> <http://vsra.vi> cannot use shli gvec as it requires the
> > shift immediate value to be within the range: [0.. SEW bits].
> > Otherwise, it will hit the assertion:
> > tcg_debug_assert(shift >= 0 && shift < (8 << vece));
> >
> > However, RVV spec does not have such constraint, therefore we
> have to
> > use helper functions instead.
>
> Why do you say that? It does have such a constraint:
>
> # Only the low lg2(SEW) bits are read to obtain the shift amount
> from a
> register value.
>
> While that only talks about the register value, I sincerely doubt
> that the same
> truncation does not actually apply to immediates.
>
> And if the entire immediate value does apply, the manual should
> certainly
> specify what should happen in that case. And at present it doesn't.
>
> It seems to me the bug is the bare use of GEN_OPIVI_GVEC_TRANS and
> thence
> do_opivi_gvec. The ZX parameter should be extended to more than
> just "zero vs
> sign-extend", it should have an option for truncating the
> immediate to s->sew.
>
>
> r~
>
>
> The latest spec specified:
>
> Only the low *lg2(SEW) bits* are read to obtain the shift amount from
> a *register value*.
> The *immediate* is treated as an *unsigned shift amount*, with a
> *maximum shift amount of 31*.
>
> Looks like the shift amount in the immediate value is not relevant
> with SEW setting.
> If so, is it better to just use do_opivi_gvec() and implement the
> logic by our own rather than using gvec IR?
In my opinion, it doesn't matter to truncate the immediate to s->sew
before calling the gvec IR,
whether the constraint of immediate exits or not.
Zhiwei
>
> Frank Chang
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^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
@ 2020-07-14 3:35 ` LIU Zhiwei
0 siblings, 0 replies; 211+ messages in thread
From: LIU Zhiwei @ 2020-07-14 3:35 UTC (permalink / raw)
To: Frank Chang, Richard Henderson
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann
[-- Attachment #1: Type: text/plain, Size: 2187 bytes --]
On 2020/7/14 10:59, Frank Chang wrote:
> On Sat, Jul 11, 2020 at 12:27 AM Richard Henderson
> <richard.henderson@linaro.org <mailto:richard.henderson@linaro.org>>
> wrote:
>
> On 7/10/20 3:48 AM, frank.chang@sifive.com
> <mailto:frank.chang@sifive.com> wrote:
> > From: Frank Chang <frank.chang@sifive.com
> <mailto:frank.chang@sifive.com>>
> >
> > vsll.vi <http://vsll.vi>, vsrl.vi <http://vsrl.vi>, vsra.vi
> <http://vsra.vi> cannot use shli gvec as it requires the
> > shift immediate value to be within the range: [0.. SEW bits].
> > Otherwise, it will hit the assertion:
> > tcg_debug_assert(shift >= 0 && shift < (8 << vece));
> >
> > However, RVV spec does not have such constraint, therefore we
> have to
> > use helper functions instead.
>
> Why do you say that? It does have such a constraint:
>
> # Only the low lg2(SEW) bits are read to obtain the shift amount
> from a
> register value.
>
> While that only talks about the register value, I sincerely doubt
> that the same
> truncation does not actually apply to immediates.
>
> And if the entire immediate value does apply, the manual should
> certainly
> specify what should happen in that case. And at present it doesn't.
>
> It seems to me the bug is the bare use of GEN_OPIVI_GVEC_TRANS and
> thence
> do_opivi_gvec. The ZX parameter should be extended to more than
> just "zero vs
> sign-extend", it should have an option for truncating the
> immediate to s->sew.
>
>
> r~
>
>
> The latest spec specified:
>
> Only the low *lg2(SEW) bits* are read to obtain the shift amount from
> a *register value*.
> The *immediate* is treated as an *unsigned shift amount*, with a
> *maximum shift amount of 31*.
>
> Looks like the shift amount in the immediate value is not relevant
> with SEW setting.
> If so, is it better to just use do_opivi_gvec() and implement the
> logic by our own rather than using gvec IR?
In my opinion, it doesn't matter to truncate the immediate to s->sew
before calling the gvec IR,
whether the constraint of immediate exits or not.
Zhiwei
>
> Frank Chang
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^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
2020-07-14 3:35 ` LIU Zhiwei
@ 2020-07-14 4:39 ` Frank Chang
-1 siblings, 0 replies; 211+ messages in thread
From: Frank Chang @ 2020-07-14 4:39 UTC (permalink / raw)
To: LIU Zhiwei
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Richard Henderson, qemu-devel@nongnu.org Developers,
Alistair Francis, Palmer Dabbelt
[-- Attachment #1: Type: text/plain, Size: 2439 bytes --]
On Tue, Jul 14, 2020 at 11:35 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
>
> On 2020/7/14 10:59, Frank Chang wrote:
>
> On Sat, Jul 11, 2020 at 12:27 AM Richard Henderson <
> richard.henderson@linaro.org> wrote:
>
>> On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
>> > From: Frank Chang <frank.chang@sifive.com>
>> >
>> > vsll.vi, vsrl.vi, vsra.vi cannot use shli gvec as it requires the
>> > shift immediate value to be within the range: [0.. SEW bits].
>> > Otherwise, it will hit the assertion:
>> > tcg_debug_assert(shift >= 0 && shift < (8 << vece));
>> >
>> > However, RVV spec does not have such constraint, therefore we have to
>> > use helper functions instead.
>>
>> Why do you say that? It does have such a constraint:
>>
>> # Only the low lg2(SEW) bits are read to obtain the shift amount from a
>> register value.
>>
>> While that only talks about the register value, I sincerely doubt that
>> the same
>> truncation does not actually apply to immediates.
>>
>> And if the entire immediate value does apply, the manual should certainly
>> specify what should happen in that case. And at present it doesn't.
>>
>> It seems to me the bug is the bare use of GEN_OPIVI_GVEC_TRANS and thence
>> do_opivi_gvec. The ZX parameter should be extended to more than just
>> "zero vs
>> sign-extend", it should have an option for truncating the immediate to
>> s->sew.
>>
>>
>> r~
>>
>
> The latest spec specified:
>
> Only the low *lg2(SEW) bits* are read to obtain the shift amount from a *register
> value*.
> The *immediate* is treated as an *unsigned shift amount*, with a *maximum
> shift amount of 31*.
>
> Looks like the shift amount in the immediate value is not relevant with
> SEW setting.
> If so, is it better to just use do_opivi_gvec() and implement the logic by
> our own rather than using gvec IR?
>
>
> In my opinion, it doesn't matter to truncate the immediate to s->sew
> before calling the gvec IR,
> whether the constraint of immediate exits or not.
>
> Zhiwei
>
>
> Frank Chang
>
>
>
The current issue I've encountered is the test like:
*vsetvli t0,t0,e8,m1,tu,mu,d1*
*vsll.vi <http://vsll.vi> v30, v30, 27*
where the SEW is 8 (i.e. vece = 0), but the immediate value is: 27.
The instruction doesn't violate the requirement specified in spec as its
value is less then 31.
However, it can't pass *tcg_debug_assert(shift >= 0 && shift < (8 <<
vece));* assertion if tcg debug option is enabled.
Frank Chang
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^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
@ 2020-07-14 4:39 ` Frank Chang
0 siblings, 0 replies; 211+ messages in thread
From: Frank Chang @ 2020-07-14 4:39 UTC (permalink / raw)
To: LIU Zhiwei
Cc: Richard Henderson, qemu-devel@nongnu.org Developers,
open list:RISC-V, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann
[-- Attachment #1: Type: text/plain, Size: 2439 bytes --]
On Tue, Jul 14, 2020 at 11:35 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
>
> On 2020/7/14 10:59, Frank Chang wrote:
>
> On Sat, Jul 11, 2020 at 12:27 AM Richard Henderson <
> richard.henderson@linaro.org> wrote:
>
>> On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
>> > From: Frank Chang <frank.chang@sifive.com>
>> >
>> > vsll.vi, vsrl.vi, vsra.vi cannot use shli gvec as it requires the
>> > shift immediate value to be within the range: [0.. SEW bits].
>> > Otherwise, it will hit the assertion:
>> > tcg_debug_assert(shift >= 0 && shift < (8 << vece));
>> >
>> > However, RVV spec does not have such constraint, therefore we have to
>> > use helper functions instead.
>>
>> Why do you say that? It does have such a constraint:
>>
>> # Only the low lg2(SEW) bits are read to obtain the shift amount from a
>> register value.
>>
>> While that only talks about the register value, I sincerely doubt that
>> the same
>> truncation does not actually apply to immediates.
>>
>> And if the entire immediate value does apply, the manual should certainly
>> specify what should happen in that case. And at present it doesn't.
>>
>> It seems to me the bug is the bare use of GEN_OPIVI_GVEC_TRANS and thence
>> do_opivi_gvec. The ZX parameter should be extended to more than just
>> "zero vs
>> sign-extend", it should have an option for truncating the immediate to
>> s->sew.
>>
>>
>> r~
>>
>
> The latest spec specified:
>
> Only the low *lg2(SEW) bits* are read to obtain the shift amount from a *register
> value*.
> The *immediate* is treated as an *unsigned shift amount*, with a *maximum
> shift amount of 31*.
>
> Looks like the shift amount in the immediate value is not relevant with
> SEW setting.
> If so, is it better to just use do_opivi_gvec() and implement the logic by
> our own rather than using gvec IR?
>
>
> In my opinion, it doesn't matter to truncate the immediate to s->sew
> before calling the gvec IR,
> whether the constraint of immediate exits or not.
>
> Zhiwei
>
>
> Frank Chang
>
>
>
The current issue I've encountered is the test like:
*vsetvli t0,t0,e8,m1,tu,mu,d1*
*vsll.vi <http://vsll.vi> v30, v30, 27*
where the SEW is 8 (i.e. vece = 0), but the immediate value is: 27.
The instruction doesn't violate the requirement specified in spec as its
value is less then 31.
However, it can't pass *tcg_debug_assert(shift >= 0 && shift < (8 <<
vece));* assertion if tcg debug option is enabled.
Frank Chang
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^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 63/65] fpu: implement full set compare for fp16
2020-07-10 12:26 ` Alex Bennée
@ 2020-07-14 9:29 ` Chih-Min Chao
-1 siblings, 0 replies; 211+ messages in thread
From: Chih-Min Chao @ 2020-07-14 9:29 UTC (permalink / raw)
To: Alex Bennée
Cc: Peter Maydell, open list:RISC-V, Frank Chang,
qemu-devel@nongnu.org Developers, Kito Cheng, Aurelien Jarno
[-- Attachment #1: Type: text/plain, Size: 1026 bytes --]
On Fri, Jul 10, 2020 at 8:26 PM Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Alex Bennée <alex.bennee@linaro.org> writes:
>
> > frank.chang@sifive.com writes:
> >
> >> From: Kito Cheng <kito.cheng@sifive.com>
> >>
> >> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> >> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
> >> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> >
> > NACK I'm afraid. What's wrong with the exiting float_compare support?
> >
> > Even if you did want to bring in aliases for these functions within
> > softfloat itself the correct way would be to use the decomposed
> > float_compare support for a bunch of stubs and not restore the old style
> > error prone bit masking code.
>
> In fact see the example float32_eq inline function in the softfloat.h
> header.
>
> --
> Alex Bennée
>
Hi Alex,
Thanks for the suggestion of using wrong and old implementation and this
part will be refined in next separated softfloat PR.
Thanks
Chih-Min Chao
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^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 63/65] fpu: implement full set compare for fp16
@ 2020-07-14 9:29 ` Chih-Min Chao
0 siblings, 0 replies; 211+ messages in thread
From: Chih-Min Chao @ 2020-07-14 9:29 UTC (permalink / raw)
To: Alex Bennée
Cc: Frank Chang, qemu-devel@nongnu.org Developers, open list:RISC-V,
Kito Cheng, Aurelien Jarno, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 1026 bytes --]
On Fri, Jul 10, 2020 at 8:26 PM Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Alex Bennée <alex.bennee@linaro.org> writes:
>
> > frank.chang@sifive.com writes:
> >
> >> From: Kito Cheng <kito.cheng@sifive.com>
> >>
> >> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> >> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
> >> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> >
> > NACK I'm afraid. What's wrong with the exiting float_compare support?
> >
> > Even if you did want to bring in aliases for these functions within
> > softfloat itself the correct way would be to use the decomposed
> > float_compare support for a bunch of stubs and not restore the old style
> > error prone bit masking code.
>
> In fact see the example float32_eq inline function in the softfloat.h
> header.
>
> --
> Alex Bennée
>
Hi Alex,
Thanks for the suggestion of using wrong and old implementation and this
part will be refined in next separated softfloat PR.
Thanks
Chih-Min Chao
[-- Attachment #2: Type: text/html, Size: 2028 bytes --]
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
2020-07-14 2:59 ` Frank Chang
@ 2020-07-14 13:21 ` Richard Henderson
-1 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-14 13:21 UTC (permalink / raw)
To: Frank Chang
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, LIU Zhiwei
On 7/13/20 7:59 PM, Frank Chang wrote:
> The latest spec specified:
>
> Only the low *lg2(SEW) bits* are read to obtain the shift amount from a
> *register value*.
> The *immediate* is treated as an *unsigned shift amount*, with a *maximum shift
> amount of 31*.
Which, I hope you will agree is underspecified, and should be reported as a bug
in the manual.
> Looks like the shift amount in the immediate value is not relevant with SEW
> setting.
How can it not be? It is when the value comes from a register...
> If so, is it better to just use do_opivi_gvec() and implement the logic by our
> own rather than using gvec IR?
No, it is not. What is the logic you would apply on your own? There should be
a right answer.
If the answer is that out-of-range shift produces zero, which some
architectures use, then you can look at the immediate value, see that you must
supply zero, and then fill the vector with zeros from translate. You need not
call a helper to perform N shifts when you know the result a-priori.
If the answer is that shift values are truncated, which riscv uses *everywhere
else*, then you should truncate the immediate value during translate.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
@ 2020-07-14 13:21 ` Richard Henderson
0 siblings, 0 replies; 211+ messages in thread
From: Richard Henderson @ 2020-07-14 13:21 UTC (permalink / raw)
To: Frank Chang
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei
On 7/13/20 7:59 PM, Frank Chang wrote:
> The latest spec specified:
>
> Only the low *lg2(SEW) bits* are read to obtain the shift amount from a
> *register value*.
> The *immediate* is treated as an *unsigned shift amount*, with a *maximum shift
> amount of 31*.
Which, I hope you will agree is underspecified, and should be reported as a bug
in the manual.
> Looks like the shift amount in the immediate value is not relevant with SEW
> setting.
How can it not be? It is when the value comes from a register...
> If so, is it better to just use do_opivi_gvec() and implement the logic by our
> own rather than using gvec IR?
No, it is not. What is the logic you would apply on your own? There should be
a right answer.
If the answer is that out-of-range shift produces zero, which some
architectures use, then you can look at the immediate value, see that you must
supply zero, and then fill the vector with zeros from translate. You need not
call a helper to perform N shifts when you know the result a-priori.
If the answer is that shift values are truncated, which riscv uses *everywhere
else*, then you should truncate the immediate value during translate.
r~
^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
2020-07-14 13:21 ` Richard Henderson
@ 2020-07-14 13:59 ` Frank Chang
-1 siblings, 0 replies; 211+ messages in thread
From: Frank Chang @ 2020-07-14 13:59 UTC (permalink / raw)
To: Richard Henderson
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, LIU Zhiwei
[-- Attachment #1: Type: text/plain, Size: 2250 bytes --]
On Tue, Jul 14, 2020 at 9:21 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 7/13/20 7:59 PM, Frank Chang wrote:
> > The latest spec specified:
> >
> > Only the low *lg2(SEW) bits* are read to obtain the shift amount from a
> > *register value*.
> > The *immediate* is treated as an *unsigned shift amount*, with a
> *maximum shift
> > amount of 31*.
>
> Which, I hope you will agree is underspecified, and should be reported as
> a bug
> in the manual.
>
Yes, you're correct.
I found out I missed the MASK part in GEN_VEXT_SHIFT_VV() macro,
which this macro is shared between OPIVV and OPIVI format of instructions.
So the same masking methodology should be applied to shift amounts coming
from both register and immediate value.
Spike also does something like:
*vs2 >> (zimm5 & (sew - 1) & 0x1f);* for SEW = 8.
I think spec is kind of misleading to the reader by the way it expresses.
>
> > Looks like the shift amount in the immediate value is not relevant with
> SEW
> > setting.
>
> How can it not be? It is when the value comes from a register...
>
> > If so, is it better to just use do_opivi_gvec() and implement the logic
> by our
> > own rather than using gvec IR?
>
> No, it is not. What is the logic you would apply on your own? There
> should be
> a right answer.
>
I was talking about just calling GEN_OPIVI_TRANS() to generate the helper
functions
defined in vector_helper.c as what I'm doing in the original patch.
But as long as the immediate value should also apply *lg2(SEW) bits*
truncating,
I think I should update GEN_OPIVI_GVEC_TRANS() to utilize gvec IR.
>
> If the answer is that out-of-range shift produces zero, which some
> architectures use, then you can look at the immediate value, see that you
> must
> supply zero, and then fill the vector with zeros from translate. You need
> not
> call a helper to perform N shifts when you know the result a-priori.
>
> If the answer is that shift values are truncated, which riscv uses
> *everywhere
> else*, then you should truncate the immediate value during translate.
>
I think vsll.vi, vsrl.vi and vsra.vi truncate the out-of-range shift as
other riscv instructions.
I will double confirm that, thanks for the advice.
Frank Chang
>
>
> r~
>
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^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
@ 2020-07-14 13:59 ` Frank Chang
0 siblings, 0 replies; 211+ messages in thread
From: Frank Chang @ 2020-07-14 13:59 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, LIU Zhiwei
[-- Attachment #1: Type: text/plain, Size: 2250 bytes --]
On Tue, Jul 14, 2020 at 9:21 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 7/13/20 7:59 PM, Frank Chang wrote:
> > The latest spec specified:
> >
> > Only the low *lg2(SEW) bits* are read to obtain the shift amount from a
> > *register value*.
> > The *immediate* is treated as an *unsigned shift amount*, with a
> *maximum shift
> > amount of 31*.
>
> Which, I hope you will agree is underspecified, and should be reported as
> a bug
> in the manual.
>
Yes, you're correct.
I found out I missed the MASK part in GEN_VEXT_SHIFT_VV() macro,
which this macro is shared between OPIVV and OPIVI format of instructions.
So the same masking methodology should be applied to shift amounts coming
from both register and immediate value.
Spike also does something like:
*vs2 >> (zimm5 & (sew - 1) & 0x1f);* for SEW = 8.
I think spec is kind of misleading to the reader by the way it expresses.
>
> > Looks like the shift amount in the immediate value is not relevant with
> SEW
> > setting.
>
> How can it not be? It is when the value comes from a register...
>
> > If so, is it better to just use do_opivi_gvec() and implement the logic
> by our
> > own rather than using gvec IR?
>
> No, it is not. What is the logic you would apply on your own? There
> should be
> a right answer.
>
I was talking about just calling GEN_OPIVI_TRANS() to generate the helper
functions
defined in vector_helper.c as what I'm doing in the original patch.
But as long as the immediate value should also apply *lg2(SEW) bits*
truncating,
I think I should update GEN_OPIVI_GVEC_TRANS() to utilize gvec IR.
>
> If the answer is that out-of-range shift produces zero, which some
> architectures use, then you can look at the immediate value, see that you
> must
> supply zero, and then fill the vector with zeros from translate. You need
> not
> call a helper to perform N shifts when you know the result a-priori.
>
> If the answer is that shift values are truncated, which riscv uses
> *everywhere
> else*, then you should truncate the immediate value during translate.
>
I think vsll.vi, vsrl.vi and vsra.vi truncate the out-of-range shift as
other riscv instructions.
I will double confirm that, thanks for the advice.
Frank Chang
>
>
> r~
>
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^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
2020-07-14 13:59 ` Frank Chang
@ 2020-07-15 2:52 ` LIU Zhiwei
-1 siblings, 0 replies; 211+ messages in thread
From: LIU Zhiwei @ 2020-07-15 2:52 UTC (permalink / raw)
To: Frank Chang, Richard Henderson
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis
[-- Attachment #1: Type: text/plain, Size: 2879 bytes --]
On 2020/7/14 21:59, Frank Chang wrote:
> On Tue, Jul 14, 2020 at 9:21 PM Richard Henderson
> <richard.henderson@linaro.org <mailto:richard.henderson@linaro.org>>
> wrote:
>
> On 7/13/20 7:59 PM, Frank Chang wrote:
> > The latest spec specified:
> >
> > Only the low *lg2(SEW) bits* are read to obtain the shift amount
> from a
> > *register value*.
> > The *immediate* is treated as an *unsigned shift amount*, with a
> *maximum shift
> > amount of 31*.
>
> Which, I hope you will agree is underspecified, and should be
> reported as a bug
> in the manual.
>
>
> Yes, you're correct.
> I found out I missed the MASK part in GEN_VEXT_SHIFT_VV() macro,
> which this macro is shared between OPIVV and OPIVI format of instructions.
> So the same masking methodology should be applied to shift amounts
> coming from both register and immediate value.
> Spike also does something like:
> /vs2 >> (zimm5 & (sew - 1) & 0x1f);/ for SEW = 8.
>
> I think spec is kind of misleading to the reader by the way it expresses.
>
>
> > Looks like the shift amount in the immediate value is not
> relevant with SEW
> > setting.
>
> How can it not be? It is when the value comes from a register...
>
> > If so, is it better to just use do_opivi_gvec() and implement
> the logic by our
> > own rather than using gvec IR?
>
> No, it is not. What is the logic you would apply on your own?
> There should be
> a right answer.
>
>
> I was talking about just calling GEN_OPIVI_TRANS() to generate the
> helper functions
> defined in vector_helper.c as what I'm doing in the original patch.
> But as long as the immediate value should also apply *lg2(SEW) bits*
> truncating,
> I think I should update GEN_OPIVI_GVEC_TRANS() to utilize gvec IR.
>
>
> If the answer is that out-of-range shift produces zero, which some
> architectures use, then you can look at the immediate value, see
> that you must
> supply zero, and then fill the vector with zeros from translate.
> You need not
> call a helper to perform N shifts when you know the result a-priori.
>
> If the answer is that shift values are truncated, which riscv uses
> *everywhere
> else*, then you should truncate the immediate value during translate.
>
>
> I think vsll.vi <http://vsll.vi>, vsrl.vi <http://vsrl.vi> and vsra.vi
> <http://vsra.vi> truncate the out-of-range shift as other riscv
> instructions.
> I will double confirm that, thanks for the advice.
>
Perhaps the reason is that the assembler can't identify if an imm is
legal according to log(SEW),
because the assembler can't get the SEW.
To make more compliance with assembler directly users' intuition, just
let the imm encoding to insn as itself(truncate to 31)
and work as itself.
Zhiwei
> Frank Chang
>
>
>
> r~
>
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^ permalink raw reply [flat|nested] 211+ messages in thread
* Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
@ 2020-07-15 2:52 ` LIU Zhiwei
0 siblings, 0 replies; 211+ messages in thread
From: LIU Zhiwei @ 2020-07-15 2:52 UTC (permalink / raw)
To: Frank Chang, Richard Henderson
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann
[-- Attachment #1: Type: text/plain, Size: 2879 bytes --]
On 2020/7/14 21:59, Frank Chang wrote:
> On Tue, Jul 14, 2020 at 9:21 PM Richard Henderson
> <richard.henderson@linaro.org <mailto:richard.henderson@linaro.org>>
> wrote:
>
> On 7/13/20 7:59 PM, Frank Chang wrote:
> > The latest spec specified:
> >
> > Only the low *lg2(SEW) bits* are read to obtain the shift amount
> from a
> > *register value*.
> > The *immediate* is treated as an *unsigned shift amount*, with a
> *maximum shift
> > amount of 31*.
>
> Which, I hope you will agree is underspecified, and should be
> reported as a bug
> in the manual.
>
>
> Yes, you're correct.
> I found out I missed the MASK part in GEN_VEXT_SHIFT_VV() macro,
> which this macro is shared between OPIVV and OPIVI format of instructions.
> So the same masking methodology should be applied to shift amounts
> coming from both register and immediate value.
> Spike also does something like:
> /vs2 >> (zimm5 & (sew - 1) & 0x1f);/ for SEW = 8.
>
> I think spec is kind of misleading to the reader by the way it expresses.
>
>
> > Looks like the shift amount in the immediate value is not
> relevant with SEW
> > setting.
>
> How can it not be? It is when the value comes from a register...
>
> > If so, is it better to just use do_opivi_gvec() and implement
> the logic by our
> > own rather than using gvec IR?
>
> No, it is not. What is the logic you would apply on your own?
> There should be
> a right answer.
>
>
> I was talking about just calling GEN_OPIVI_TRANS() to generate the
> helper functions
> defined in vector_helper.c as what I'm doing in the original patch.
> But as long as the immediate value should also apply *lg2(SEW) bits*
> truncating,
> I think I should update GEN_OPIVI_GVEC_TRANS() to utilize gvec IR.
>
>
> If the answer is that out-of-range shift produces zero, which some
> architectures use, then you can look at the immediate value, see
> that you must
> supply zero, and then fill the vector with zeros from translate.
> You need not
> call a helper to perform N shifts when you know the result a-priori.
>
> If the answer is that shift values are truncated, which riscv uses
> *everywhere
> else*, then you should truncate the immediate value during translate.
>
>
> I think vsll.vi <http://vsll.vi>, vsrl.vi <http://vsrl.vi> and vsra.vi
> <http://vsra.vi> truncate the out-of-range shift as other riscv
> instructions.
> I will double confirm that, thanks for the advice.
>
Perhaps the reason is that the assembler can't identify if an imm is
legal according to log(SEW),
because the assembler can't get the SEW.
To make more compliance with assembler directly users' intuition, just
let the imm encoding to insn as itself(truncate to 31)
and work as itself.
Zhiwei
> Frank Chang
>
>
>
> r~
>
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^ permalink raw reply [flat|nested] 211+ messages in thread
end of thread, other threads:[~2020-07-15 2:54 UTC | newest]
Thread overview: 211+ messages (download: mbox.gz / follow: Atom feed)
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2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
2020-07-10 10:48 ` [RFC 01/65] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 16:12 ` Richard Henderson
2020-07-10 16:12 ` Richard Henderson
2020-07-10 18:24 ` Alistair Francis
2020-07-10 18:24 ` Alistair Francis
2020-07-10 10:48 ` [RFC 02/65] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 16:13 ` Richard Henderson
2020-07-10 16:13 ` Richard Henderson
2020-07-10 10:48 ` [RFC 03/65] target/riscv: fix return value of do_opivx_widen() frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 16:14 ` Richard Henderson
2020-07-10 16:14 ` Richard Henderson
2020-07-10 10:48 ` [RFC 04/65] target/riscv: fix vill bit index in vtype register frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 16:15 ` Richard Henderson
2020-07-10 16:15 ` Richard Henderson
2020-07-10 10:48 ` [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 16:27 ` Richard Henderson
2020-07-10 16:27 ` Richard Henderson
2020-07-14 2:59 ` Frank Chang
2020-07-14 2:59 ` Frank Chang
2020-07-14 3:35 ` LIU Zhiwei
2020-07-14 3:35 ` LIU Zhiwei
2020-07-14 4:39 ` Frank Chang
2020-07-14 4:39 ` Frank Chang
2020-07-14 13:21 ` Richard Henderson
2020-07-14 13:21 ` Richard Henderson
2020-07-14 13:59 ` Frank Chang
2020-07-14 13:59 ` Frank Chang
2020-07-15 2:52 ` LIU Zhiwei
2020-07-15 2:52 ` LIU Zhiwei
2020-07-10 10:48 ` [RFC 06/65] target/riscv: rvv-0.9: add vcsr register frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 17:02 ` Richard Henderson
2020-07-10 17:02 ` Richard Henderson
2020-07-10 10:48 ` [RFC 07/65] target/riscv: rvv-0.9: add vector context status frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 17:26 ` Richard Henderson
2020-07-10 17:26 ` Richard Henderson
2020-07-10 17:27 ` Richard Henderson
2020-07-10 17:27 ` Richard Henderson
2020-07-10 10:48 ` [RFC 08/65] target/riscv: rvv-0.9: update mstatus_vs by tb_flags frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 17:28 ` Richard Henderson
2020-07-10 17:28 ` Richard Henderson
2020-07-10 10:48 ` [RFC 09/65] target/riscv: rvv-0.9: add vlenb register frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 17:31 ` Richard Henderson
2020-07-10 17:31 ` Richard Henderson
2020-07-10 10:48 ` [RFC 10/65] target/riscv: rvv-0.9: remove MLEN calculations frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 17:32 ` Richard Henderson
2020-07-10 17:32 ` Richard Henderson
2020-07-10 10:48 ` [RFC 11/65] target/riscv: rvv-0.9: add fractional LMUL, VTA and VMA frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 17:45 ` Richard Henderson
2020-07-10 17:45 ` Richard Henderson
2020-07-10 10:48 ` [RFC 12/65] target/riscv: rvv-0.9: update check functions frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 17:51 ` Richard Henderson
2020-07-10 17:51 ` Richard Henderson
2020-07-13 2:10 ` Frank Chang
2020-07-13 2:10 ` Frank Chang
2020-07-10 10:48 ` [RFC 13/65] target/riscv: rvv-0.9: configure instructions frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 18:06 ` Richard Henderson
2020-07-10 18:06 ` Richard Henderson
2020-07-13 2:07 ` Frank Chang
2020-07-13 2:07 ` Frank Chang
2020-07-10 10:48 ` [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 18:15 ` Richard Henderson
2020-07-10 18:15 ` Richard Henderson
2020-07-13 2:04 ` Frank Chang
2020-07-13 2:04 ` Frank Chang
2020-07-10 10:48 ` [RFC 15/65] target/riscv: rvv-0.9: index " frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 16/65] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 17/65] target/riscv: rvv-0.9: fault-only-first unit stride load frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 18/65] target/riscv: rvv-0.9: amo operations frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 19/65] target/riscv: rvv-0.9: load/store whole register instructions frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 20/65] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 21/65] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 22/65] target/riscv: rvv-0.9: floating-point square-root instruction frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 23/65] target/riscv: rvv-0.9: floating-point classify instructions frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 24/65] target/riscv: rvv-0.9: mask population count instruction frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 25/65] target/riscv: rvv-0.9: find-first-set mask bit instruction frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 26/65] target/riscv: rvv-0.9: set-X-first mask bit instructions frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 27/65] target/riscv: rvv-0.9: iota instruction frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 28/65] target/riscv: rvv-0.9: element index instruction frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 29/65] target/riscv: rvv-0.9: integer scalar move instructions frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 30/65] target/riscv: rvv-0.9: floating-point " frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 31/65] target/riscv: rvv-0.9: whole register " frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 32/65] target/riscv: rvv-0.9: integer extension instructions frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 33/65] target/riscv: rvv-0.9: single-width averaging add and subtract instructions frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 34/65] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 35/65] target/riscv: rvv-0.9: narrowing integer right shift instructions frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 36/65] target/riscv: rvv-0.9: widening integer multiply-add instructions frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 37/65] target/riscv: rvv-0.9: quad-widening " frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 38/65] target/riscv: rvv-0.9: integer merge and move instructions frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 39/65] target/riscv: rvv-0.9: single-width saturating add and subtract instructions frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 40/65] target/riscv: rvv-0.9: integer comparison instructions frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 41/65] target/riscv: rvv-0.9: floating-point compare instructions frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 42/65] target/riscv: rvv-0.9: single-width integer reduction instructions frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 43/65] target/riscv: rvv-0.9: widening " frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 44/65] target/riscv: rvv-0.9: mask-register logical instructions frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:48 ` [RFC 45/65] target/riscv: rvv-0.9: register gather instructions frank.chang
2020-07-10 10:48 ` frank.chang
2020-07-10 10:49 ` [RFC 46/65] target/riscv: rvv-0.9: slide instructions frank.chang
2020-07-10 10:49 ` frank.chang
2020-07-10 10:49 ` [RFC 47/65] target/riscv: rvv-0.9: floating-point " frank.chang
2020-07-10 10:49 ` frank.chang
2020-07-10 10:49 ` [RFC 48/65] target/riscv: rvv-0.9: narrowing fixed-point clip instructions frank.chang
2020-07-10 10:49 ` frank.chang
2020-07-10 10:49 ` [RFC 49/65] target/riscv: rvv-0.9: floating-point move instructions frank.chang
2020-07-10 10:49 ` frank.chang
2020-07-10 10:49 ` [RFC 50/65] target/riscv: rvv-0.9: floating-point/integer type-convert instructions frank.chang
2020-07-10 10:49 ` frank.chang
2020-07-10 10:49 ` [RFC 51/65] target/riscv: rvv-0.9: single-width floating-point reduction frank.chang
2020-07-10 10:49 ` frank.chang
2020-07-10 10:49 ` [RFC 52/65] target/riscv: rvv-0.9: widening floating-point reduction instructions frank.chang
2020-07-10 10:49 ` frank.chang
2020-07-10 10:49 ` [RFC 53/65] target/riscv: rvv-0.9: single-width scaling shift instructions frank.chang
2020-07-10 10:49 ` frank.chang
2020-07-10 10:49 ` [RFC 54/65] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add frank.chang
2020-07-10 10:49 ` frank.chang
2020-07-10 10:49 ` [RFC 55/65] target/riscv: rvv-0.9: remove vmford.vv and vmford.vf frank.chang
2020-07-10 10:49 ` frank.chang
2020-07-10 10:49 ` [RFC 56/65] target/riscv: rvv-0.9: remove integer extract instruction frank.chang
2020-07-10 10:49 ` frank.chang
2020-07-10 10:49 ` [RFC 57/65] target/riscv: rvv-0.9: floating-point min/max instructions frank.chang
2020-07-10 10:49 ` frank.chang
2020-07-10 18:19 ` Alex Bennée
2020-07-10 18:19 ` Alex Bennée
2020-07-10 10:49 ` [RFC 58/65] target/riscv: rvv-0.9: widening floating-point/integer type-convert frank.chang
2020-07-10 10:49 ` frank.chang
2020-07-10 10:49 ` [RFC 59/65] target/riscv: rvv-0.9: narrowing " frank.chang
2020-07-10 10:49 ` frank.chang
2020-07-10 10:49 ` [RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions frank.chang
2020-07-10 10:49 ` frank.chang
2020-07-10 12:07 ` Alex Bennée
2020-07-10 12:07 ` Alex Bennée
2020-07-10 12:15 ` Frank Chang
2020-07-10 12:15 ` Frank Chang
2020-07-10 12:46 ` Alex Bennée
2020-07-10 12:46 ` Alex Bennée
2020-07-10 13:13 ` Frank Chang
2020-07-10 13:13 ` Frank Chang
2020-07-10 14:59 ` Alex Bennée
2020-07-10 14:59 ` Alex Bennée
2020-07-10 10:49 ` [RFC 61/65] fpu: fix float16 nan check frank.chang
2020-07-10 10:49 ` frank.chang
2020-07-10 10:49 ` [RFC 62/65] fpu: add api to handle alternative sNaN propagation frank.chang
2020-07-10 10:49 ` frank.chang
2020-07-10 12:15 ` Alex Bennée
2020-07-10 12:15 ` Alex Bennée
2020-07-13 17:38 ` Chih-Min Chao
2020-07-13 17:38 ` Chih-Min Chao
2020-07-10 10:49 ` [RFC 63/65] fpu: implement full set compare for fp16 frank.chang
2020-07-10 10:49 ` frank.chang
2020-07-10 12:24 ` Alex Bennée
2020-07-10 12:24 ` Alex Bennée
2020-07-10 12:26 ` Alex Bennée
2020-07-10 12:26 ` Alex Bennée
2020-07-14 9:29 ` Chih-Min Chao
2020-07-14 9:29 ` Chih-Min Chao
2020-07-10 10:49 ` [RFC 64/65] target/riscv: use softfloat lib float16 comparison functions frank.chang
2020-07-10 10:49 ` frank.chang
2020-07-10 10:49 ` [RFC 65/65] target/riscv: bump to RVV 0.9 frank.chang
2020-07-10 10:49 ` frank.chang
2020-07-10 21:43 ` [RFC 00/65] target/riscv: support vector extension v0.9 Alistair Francis
2020-07-10 21:43 ` Alistair Francis
2020-07-13 2:02 ` Frank Chang
2020-07-13 2:02 ` Frank Chang
2020-07-13 15:57 ` Alistair Francis
2020-07-13 15:57 ` Alistair Francis
2020-07-13 16:41 ` Richard Henderson
2020-07-13 16:44 ` Frank Chang
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