* [PATCH v5 0/6] ARM: arbitrary virtual-physical mappings for RPi4 XHCI support
[not found] <CGME20200603124402eucas1p16e3f9864e02f863656b8640f14255fb9@eucas1p1.samsung.com>
@ 2020-06-03 12:43 ` Marek Szyprowski
[not found] ` <CGME20200603124404eucas1p1aef17d34805c41ba3fc8ac7d7adbd9c7@eucas1p1.samsung.com>
` (6 more replies)
0 siblings, 7 replies; 20+ messages in thread
From: Marek Szyprowski @ 2020-06-03 12:43 UTC (permalink / raw)
To: u-boot
Hi All,
This patchset adds support for creating a mapping for the arbitrary
physical address at the given virtual address. This is needed to enable
support for XHCI USB controller on PCIe bridge on Raspberry Pi 4 board,
on which the USB controller's MMIO area 0x600000000 has to be remapped
somewhere to fit in 4GiB virtual address space when running in ARM 32bit
mode.
This patchset is a continuation of the Raspberry Pi 4 XHCI/PCIe patchset:
https://patchwork.ozlabs.org/project/uboot/list/?series=179078
and the following discussion:
https://lists.denx.de/pipermail/u-boot/2020-May/411086.html
Best regards
Marek Szyprowski
Samsung R&D Institute Poland
Changelog:
v5:
- fixed issues pointed by Tom Rini (comments style, ifdefs, spdx)
v4: https://lists.denx.de/pipermail/u-boot/2020-June/414531.html
- added a patch, which moves ADDR_MAP config entry to Kconfig system
as requested by Simon Glass
- rebased onto v4 of the "USB host support for Raspberry Pi 4 board
(64-bit)" patchset
v3: https://lists.denx.de/pipermail/u-boot/2020-May/412427.html
- fixed broken RPi3 and lack of the identity mapping for map_physmem
(for example for the itest command was broken)
- added a patch fixing a new build warning
v2: https://lists.denx.de/pipermail/u-boot/2020-May/411765.html
- fixed ARM64 build
v1: https://lists.denx.de/pipermail/u-boot/2020-May/411765.html
- initial RFC
Patch summary:
Marek Szyprowski (5):
powerpc: move ADDR_MAP to Kconfig
arm: update comments to the common style
arm: provide a function for boards init code to modify MMU
virtual-physical map
rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM
32bit)
config: Enable support for the XHCI controller on RPI4 board
Seung-Woo Kim (1):
mmc: bcm283x: fix int to pointer cast
arch/arm/include/asm/mmu.h | 8 +++++
arch/arm/include/asm/system.h | 36 ++++++++++++++++------
arch/arm/lib/cache-cp15.c | 24 +++++++++++----
arch/arm/mach-bcm283x/Kconfig | 1 +
arch/arm/mach-bcm283x/include/mach/base.h | 8 +++++
arch/arm/mach-bcm283x/init.c | 21 +++++++++++++
configs/B4420QDS_NAND_defconfig | 2 ++
configs/B4420QDS_SPIFLASH_defconfig | 2 ++
configs/B4420QDS_defconfig | 2 ++
configs/B4860QDS_NAND_defconfig | 2 ++
configs/B4860QDS_SECURE_BOOT_defconfig | 2 ++
configs/B4860QDS_SPIFLASH_defconfig | 2 ++
configs/B4860QDS_SRIO_PCIE_BOOT_defconfig | 2 ++
configs/B4860QDS_defconfig | 2 ++
configs/C29XPCIE_NAND_defconfig | 1 +
configs/C29XPCIE_NOR_SECBOOT_defconfig | 1 +
configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig | 1 +
configs/C29XPCIE_SPIFLASH_defconfig | 1 +
configs/C29XPCIE_defconfig | 1 +
configs/Cyrus_P5020_defconfig | 2 ++
configs/Cyrus_P5040_defconfig | 2 ++
configs/MPC8536DS_36BIT_defconfig | 1 +
configs/MPC8548CDS_36BIT_defconfig | 1 +
configs/MPC8572DS_36BIT_defconfig | 1 +
configs/MPC8641HPCN_36BIT_defconfig | 2 ++
configs/MPC8641HPCN_defconfig | 2 ++
configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig | 1 +
configs/P1010RDB-PA_36BIT_NAND_defconfig | 1 +
configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig | 1 +
configs/P1010RDB-PA_36BIT_NOR_defconfig | 1 +
configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 1 +
.../P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig | 1 +
configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 1 +
configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig | 1 +
configs/P1010RDB-PB_36BIT_NAND_defconfig | 1 +
configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig | 1 +
configs/P1010RDB-PB_36BIT_NOR_defconfig | 1 +
configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 1 +
.../P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig | 1 +
configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 1 +
configs/P1020MBG-PC_36BIT_SDCARD_defconfig | 1 +
configs/P1020MBG-PC_36BIT_defconfig | 1 +
configs/P1020RDB-PC_36BIT_NAND_defconfig | 1 +
configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 1 +
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 +
configs/P1020RDB-PC_36BIT_defconfig | 1 +
configs/P1020UTM-PC_36BIT_SDCARD_defconfig | 1 +
configs/P1020UTM-PC_36BIT_defconfig | 1 +
configs/P1021RDB-PC_36BIT_NAND_defconfig | 1 +
configs/P1021RDB-PC_36BIT_SDCARD_defconfig | 1 +
configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig | 1 +
configs/P1021RDB-PC_36BIT_defconfig | 1 +
configs/P1022DS_36BIT_NAND_defconfig | 1 +
configs/P1022DS_36BIT_SDCARD_defconfig | 1 +
configs/P1022DS_36BIT_SPIFLASH_defconfig | 1 +
configs/P1022DS_36BIT_defconfig | 1 +
configs/P1024RDB_36BIT_defconfig | 1 +
configs/P1025RDB_36BIT_defconfig | 1 +
configs/P2020RDB-PC_36BIT_NAND_defconfig | 1 +
configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 1 +
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 1 +
configs/P2020RDB-PC_36BIT_defconfig | 1 +
configs/P2041RDB_NAND_defconfig | 2 ++
configs/P2041RDB_SDCARD_defconfig | 2 ++
configs/P2041RDB_SECURE_BOOT_defconfig | 2 ++
configs/P2041RDB_SPIFLASH_defconfig | 2 ++
configs/P2041RDB_SRIO_PCIE_BOOT_defconfig | 2 ++
configs/P2041RDB_defconfig | 2 ++
configs/P3041DS_NAND_SECURE_BOOT_defconfig | 2 ++
configs/P3041DS_NAND_defconfig | 2 ++
configs/P3041DS_SDCARD_defconfig | 2 ++
configs/P3041DS_SECURE_BOOT_defconfig | 2 ++
configs/P3041DS_SPIFLASH_defconfig | 2 ++
configs/P3041DS_SRIO_PCIE_BOOT_defconfig | 2 ++
configs/P3041DS_defconfig | 2 ++
configs/P4080DS_SDCARD_defconfig | 2 ++
configs/P4080DS_SECURE_BOOT_defconfig | 2 ++
configs/P4080DS_SPIFLASH_defconfig | 2 ++
configs/P4080DS_SRIO_PCIE_BOOT_defconfig | 2 ++
configs/P4080DS_defconfig | 2 ++
configs/P5020DS_NAND_SECURE_BOOT_defconfig | 2 ++
configs/P5020DS_NAND_defconfig | 2 ++
configs/P5020DS_SDCARD_defconfig | 2 ++
configs/P5020DS_SECURE_BOOT_defconfig | 2 ++
configs/P5020DS_SPIFLASH_defconfig | 2 ++
configs/P5020DS_SRIO_PCIE_BOOT_defconfig | 2 ++
configs/P5020DS_defconfig | 2 ++
configs/P5040DS_NAND_SECURE_BOOT_defconfig | 2 ++
configs/P5040DS_NAND_defconfig | 2 ++
configs/P5040DS_SDCARD_defconfig | 2 ++
configs/P5040DS_SECURE_BOOT_defconfig | 2 ++
configs/P5040DS_SPIFLASH_defconfig | 2 ++
configs/P5040DS_defconfig | 2 ++
configs/T1023RDB_NAND_defconfig | 2 ++
configs/T1023RDB_SDCARD_defconfig | 2 ++
configs/T1023RDB_SECURE_BOOT_defconfig | 2 ++
configs/T1023RDB_SPIFLASH_defconfig | 2 ++
configs/T1023RDB_defconfig | 2 ++
configs/T1024QDS_DDR4_SECURE_BOOT_defconfig | 2 ++
configs/T1024QDS_DDR4_defconfig | 2 ++
configs/T1024QDS_NAND_defconfig | 2 ++
configs/T1024QDS_SDCARD_defconfig | 2 ++
configs/T1024QDS_SECURE_BOOT_defconfig | 2 ++
configs/T1024QDS_SPIFLASH_defconfig | 2 ++
configs/T1024QDS_defconfig | 2 ++
configs/T1024RDB_NAND_defconfig | 2 ++
configs/T1024RDB_SDCARD_defconfig | 2 ++
configs/T1024RDB_SECURE_BOOT_defconfig | 2 ++
configs/T1024RDB_SPIFLASH_defconfig | 2 ++
configs/T1024RDB_defconfig | 2 ++
configs/T1040D4RDB_NAND_defconfig | 2 ++
configs/T1040D4RDB_SDCARD_defconfig | 2 ++
configs/T1040D4RDB_SECURE_BOOT_defconfig | 2 ++
configs/T1040D4RDB_SPIFLASH_defconfig | 2 ++
configs/T1040D4RDB_defconfig | 2 ++
configs/T1040QDS_DDR4_defconfig | 2 ++
configs/T1040QDS_SECURE_BOOT_defconfig | 2 ++
configs/T1040QDS_defconfig | 2 ++
configs/T1040RDB_NAND_defconfig | 2 ++
configs/T1040RDB_SDCARD_defconfig | 2 ++
configs/T1040RDB_SECURE_BOOT_defconfig | 2 ++
configs/T1040RDB_SPIFLASH_defconfig | 2 ++
configs/T1040RDB_defconfig | 2 ++
configs/T1042D4RDB_NAND_defconfig | 2 ++
configs/T1042D4RDB_SDCARD_defconfig | 2 ++
configs/T1042D4RDB_SECURE_BOOT_defconfig | 2 ++
configs/T1042D4RDB_SPIFLASH_defconfig | 2 ++
configs/T1042D4RDB_defconfig | 2 ++
configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig | 2 ++
configs/T1042RDB_PI_NAND_defconfig | 2 ++
configs/T1042RDB_PI_SDCARD_defconfig | 2 ++
configs/T1042RDB_PI_SPIFLASH_defconfig | 2 ++
configs/T1042RDB_PI_defconfig | 2 ++
configs/T1042RDB_SECURE_BOOT_defconfig | 2 ++
configs/T1042RDB_defconfig | 2 ++
configs/T2080QDS_NAND_defconfig | 2 ++
configs/T2080QDS_SDCARD_defconfig | 2 ++
configs/T2080QDS_SECURE_BOOT_defconfig | 2 ++
configs/T2080QDS_SPIFLASH_defconfig | 2 ++
configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 2 ++
configs/T2080QDS_defconfig | 2 ++
configs/T2080RDB_NAND_defconfig | 2 ++
configs/T2080RDB_SDCARD_defconfig | 2 ++
configs/T2080RDB_SECURE_BOOT_defconfig | 2 ++
configs/T2080RDB_SPIFLASH_defconfig | 2 ++
configs/T2080RDB_SRIO_PCIE_BOOT_defconfig | 2 ++
configs/T2080RDB_defconfig | 2 ++
configs/T2081QDS_NAND_defconfig | 2 ++
configs/T2081QDS_SDCARD_defconfig | 2 ++
configs/T2081QDS_SPIFLASH_defconfig | 2 ++
configs/T2081QDS_SRIO_PCIE_BOOT_defconfig | 2 ++
configs/T2081QDS_defconfig | 2 ++
configs/T4160QDS_NAND_defconfig | 2 ++
configs/T4160QDS_SDCARD_defconfig | 2 ++
configs/T4160QDS_SECURE_BOOT_defconfig | 2 ++
configs/T4160QDS_defconfig | 2 ++
configs/T4160RDB_defconfig | 2 ++
configs/T4240QDS_NAND_defconfig | 2 ++
configs/T4240QDS_SDCARD_defconfig | 2 ++
configs/T4240QDS_SECURE_BOOT_defconfig | 2 ++
configs/T4240QDS_SRIO_PCIE_BOOT_defconfig | 2 ++
configs/T4240QDS_defconfig | 2 ++
configs/T4240RDB_SDCARD_defconfig | 2 ++
configs/T4240RDB_defconfig | 2 ++
.../controlcenterd_36BIT_SDCARD_DEVELOP_defconfig | 1 +
configs/controlcenterd_36BIT_SDCARD_defconfig | 1 +
configs/kmcoge4_defconfig | 2 ++
configs/qemu-ppce500_defconfig | 1 +
configs/rpi_4_32b_defconfig | 11 +++++++
drivers/mmc/bcm2835_sdhci.c | 2 +-
include/configs/B4860QDS.h | 5 ---
include/configs/C29XPCIE.h | 3 --
include/configs/MPC8536DS.h | 5 ---
include/configs/MPC8548CDS.h | 5 ---
include/configs/MPC8572DS.h | 5 ---
include/configs/MPC8641HPCN.h | 2 --
include/configs/P1010RDB.h | 5 ---
include/configs/P1022DS.h | 5 ---
include/configs/P2041RDB.h | 5 ---
include/configs/T102xQDS.h | 5 ---
include/configs/T102xRDB.h | 5 ---
include/configs/T1040QDS.h | 3 --
include/configs/T104xRDB.h | 3 --
include/configs/T208xQDS.h | 5 ---
include/configs/T208xRDB.h | 5 ---
include/configs/T4240RDB.h | 3 --
include/configs/controlcenterd.h | 5 ---
include/configs/corenet_ds.h | 5 ---
include/configs/cyrus.h | 5 ---
include/configs/kmp204x.h | 3 --
include/configs/p1_p2_rdb_pc.h | 5 ---
include/configs/qemu-ppce500.h | 3 --
include/configs/t4qds.h | 3 --
lib/Kconfig | 13 ++++++++
scripts/config_whitelist.txt | 2 --
195 files changed, 385 insertions(+), 116 deletions(-)
create mode 100644 arch/arm/include/asm/mmu.h
--
1.9.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v5 1/6] powerpc: move ADDR_MAP to Kconfig
[not found] ` <CGME20200603124404eucas1p1aef17d34805c41ba3fc8ac7d7adbd9c7@eucas1p1.samsung.com>
@ 2020-06-03 12:43 ` Marek Szyprowski
2020-07-10 20:21 ` Tom Rini
0 siblings, 1 reply; 20+ messages in thread
From: Marek Szyprowski @ 2020-06-03 12:43 UTC (permalink / raw)
To: u-boot
Move ADDR_MAP related config options from include/configs/*.h to the
proper place in lib/Kconfig. This has been done using
./tools/moveconfig.py and manual inspection of the generated changes.
This is a preparation to use ADDR_MAP helper on ARM 32bit Raspberry Pi4
board for mapping the PCIe XHCI MMIO, which is above the 4GiB identity
mapping limit.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
configs/B4420QDS_NAND_defconfig | 2 ++
configs/B4420QDS_SPIFLASH_defconfig | 2 ++
configs/B4420QDS_defconfig | 2 ++
configs/B4860QDS_NAND_defconfig | 2 ++
configs/B4860QDS_SECURE_BOOT_defconfig | 2 ++
configs/B4860QDS_SPIFLASH_defconfig | 2 ++
configs/B4860QDS_SRIO_PCIE_BOOT_defconfig | 2 ++
configs/B4860QDS_defconfig | 2 ++
configs/C29XPCIE_NAND_defconfig | 1 +
configs/C29XPCIE_NOR_SECBOOT_defconfig | 1 +
configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig | 1 +
configs/C29XPCIE_SPIFLASH_defconfig | 1 +
configs/C29XPCIE_defconfig | 1 +
configs/Cyrus_P5020_defconfig | 2 ++
configs/Cyrus_P5040_defconfig | 2 ++
configs/MPC8536DS_36BIT_defconfig | 1 +
configs/MPC8548CDS_36BIT_defconfig | 1 +
configs/MPC8572DS_36BIT_defconfig | 1 +
configs/MPC8641HPCN_36BIT_defconfig | 2 ++
configs/MPC8641HPCN_defconfig | 2 ++
configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig | 1 +
configs/P1010RDB-PA_36BIT_NAND_defconfig | 1 +
configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig | 1 +
configs/P1010RDB-PA_36BIT_NOR_defconfig | 1 +
configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 1 +
configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig | 1 +
configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 1 +
configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig | 1 +
configs/P1010RDB-PB_36BIT_NAND_defconfig | 1 +
configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig | 1 +
configs/P1010RDB-PB_36BIT_NOR_defconfig | 1 +
configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 1 +
configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig | 1 +
configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 1 +
configs/P1020MBG-PC_36BIT_SDCARD_defconfig | 1 +
configs/P1020MBG-PC_36BIT_defconfig | 1 +
configs/P1020RDB-PC_36BIT_NAND_defconfig | 1 +
configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 1 +
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 +
configs/P1020RDB-PC_36BIT_defconfig | 1 +
configs/P1020UTM-PC_36BIT_SDCARD_defconfig | 1 +
configs/P1020UTM-PC_36BIT_defconfig | 1 +
configs/P1021RDB-PC_36BIT_NAND_defconfig | 1 +
configs/P1021RDB-PC_36BIT_SDCARD_defconfig | 1 +
configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig | 1 +
configs/P1021RDB-PC_36BIT_defconfig | 1 +
configs/P1022DS_36BIT_NAND_defconfig | 1 +
configs/P1022DS_36BIT_SDCARD_defconfig | 1 +
configs/P1022DS_36BIT_SPIFLASH_defconfig | 1 +
configs/P1022DS_36BIT_defconfig | 1 +
configs/P1024RDB_36BIT_defconfig | 1 +
configs/P1025RDB_36BIT_defconfig | 1 +
configs/P2020RDB-PC_36BIT_NAND_defconfig | 1 +
configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 1 +
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 1 +
configs/P2020RDB-PC_36BIT_defconfig | 1 +
configs/P2041RDB_NAND_defconfig | 2 ++
configs/P2041RDB_SDCARD_defconfig | 2 ++
configs/P2041RDB_SECURE_BOOT_defconfig | 2 ++
configs/P2041RDB_SPIFLASH_defconfig | 2 ++
configs/P2041RDB_SRIO_PCIE_BOOT_defconfig | 2 ++
configs/P2041RDB_defconfig | 2 ++
configs/P3041DS_NAND_SECURE_BOOT_defconfig | 2 ++
configs/P3041DS_NAND_defconfig | 2 ++
configs/P3041DS_SDCARD_defconfig | 2 ++
configs/P3041DS_SECURE_BOOT_defconfig | 2 ++
configs/P3041DS_SPIFLASH_defconfig | 2 ++
configs/P3041DS_SRIO_PCIE_BOOT_defconfig | 2 ++
configs/P3041DS_defconfig | 2 ++
configs/P4080DS_SDCARD_defconfig | 2 ++
configs/P4080DS_SECURE_BOOT_defconfig | 2 ++
configs/P4080DS_SPIFLASH_defconfig | 2 ++
configs/P4080DS_SRIO_PCIE_BOOT_defconfig | 2 ++
configs/P4080DS_defconfig | 2 ++
configs/P5020DS_NAND_SECURE_BOOT_defconfig | 2 ++
configs/P5020DS_NAND_defconfig | 2 ++
configs/P5020DS_SDCARD_defconfig | 2 ++
configs/P5020DS_SECURE_BOOT_defconfig | 2 ++
configs/P5020DS_SPIFLASH_defconfig | 2 ++
configs/P5020DS_SRIO_PCIE_BOOT_defconfig | 2 ++
configs/P5020DS_defconfig | 2 ++
configs/P5040DS_NAND_SECURE_BOOT_defconfig | 2 ++
configs/P5040DS_NAND_defconfig | 2 ++
configs/P5040DS_SDCARD_defconfig | 2 ++
configs/P5040DS_SECURE_BOOT_defconfig | 2 ++
configs/P5040DS_SPIFLASH_defconfig | 2 ++
configs/P5040DS_defconfig | 2 ++
configs/T1023RDB_NAND_defconfig | 2 ++
configs/T1023RDB_SDCARD_defconfig | 2 ++
configs/T1023RDB_SECURE_BOOT_defconfig | 2 ++
configs/T1023RDB_SPIFLASH_defconfig | 2 ++
configs/T1023RDB_defconfig | 2 ++
configs/T1024QDS_DDR4_SECURE_BOOT_defconfig | 2 ++
configs/T1024QDS_DDR4_defconfig | 2 ++
configs/T1024QDS_NAND_defconfig | 2 ++
configs/T1024QDS_SDCARD_defconfig | 2 ++
configs/T1024QDS_SECURE_BOOT_defconfig | 2 ++
configs/T1024QDS_SPIFLASH_defconfig | 2 ++
configs/T1024QDS_defconfig | 2 ++
configs/T1024RDB_NAND_defconfig | 2 ++
configs/T1024RDB_SDCARD_defconfig | 2 ++
configs/T1024RDB_SECURE_BOOT_defconfig | 2 ++
configs/T1024RDB_SPIFLASH_defconfig | 2 ++
configs/T1024RDB_defconfig | 2 ++
configs/T1040D4RDB_NAND_defconfig | 2 ++
configs/T1040D4RDB_SDCARD_defconfig | 2 ++
configs/T1040D4RDB_SECURE_BOOT_defconfig | 2 ++
configs/T1040D4RDB_SPIFLASH_defconfig | 2 ++
configs/T1040D4RDB_defconfig | 2 ++
configs/T1040QDS_DDR4_defconfig | 2 ++
configs/T1040QDS_SECURE_BOOT_defconfig | 2 ++
configs/T1040QDS_defconfig | 2 ++
configs/T1040RDB_NAND_defconfig | 2 ++
configs/T1040RDB_SDCARD_defconfig | 2 ++
configs/T1040RDB_SECURE_BOOT_defconfig | 2 ++
configs/T1040RDB_SPIFLASH_defconfig | 2 ++
configs/T1040RDB_defconfig | 2 ++
configs/T1042D4RDB_NAND_defconfig | 2 ++
configs/T1042D4RDB_SDCARD_defconfig | 2 ++
configs/T1042D4RDB_SECURE_BOOT_defconfig | 2 ++
configs/T1042D4RDB_SPIFLASH_defconfig | 2 ++
configs/T1042D4RDB_defconfig | 2 ++
configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig | 2 ++
configs/T1042RDB_PI_NAND_defconfig | 2 ++
configs/T1042RDB_PI_SDCARD_defconfig | 2 ++
configs/T1042RDB_PI_SPIFLASH_defconfig | 2 ++
configs/T1042RDB_PI_defconfig | 2 ++
configs/T1042RDB_SECURE_BOOT_defconfig | 2 ++
configs/T1042RDB_defconfig | 2 ++
configs/T2080QDS_NAND_defconfig | 2 ++
configs/T2080QDS_SDCARD_defconfig | 2 ++
configs/T2080QDS_SECURE_BOOT_defconfig | 2 ++
configs/T2080QDS_SPIFLASH_defconfig | 2 ++
configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 2 ++
configs/T2080QDS_defconfig | 2 ++
configs/T2080RDB_NAND_defconfig | 2 ++
configs/T2080RDB_SDCARD_defconfig | 2 ++
configs/T2080RDB_SECURE_BOOT_defconfig | 2 ++
configs/T2080RDB_SPIFLASH_defconfig | 2 ++
configs/T2080RDB_SRIO_PCIE_BOOT_defconfig | 2 ++
configs/T2080RDB_defconfig | 2 ++
configs/T2081QDS_NAND_defconfig | 2 ++
configs/T2081QDS_SDCARD_defconfig | 2 ++
configs/T2081QDS_SPIFLASH_defconfig | 2 ++
configs/T2081QDS_SRIO_PCIE_BOOT_defconfig | 2 ++
configs/T2081QDS_defconfig | 2 ++
configs/T4160QDS_NAND_defconfig | 2 ++
configs/T4160QDS_SDCARD_defconfig | 2 ++
configs/T4160QDS_SECURE_BOOT_defconfig | 2 ++
configs/T4160QDS_defconfig | 2 ++
configs/T4160RDB_defconfig | 2 ++
configs/T4240QDS_NAND_defconfig | 2 ++
configs/T4240QDS_SDCARD_defconfig | 2 ++
configs/T4240QDS_SECURE_BOOT_defconfig | 2 ++
configs/T4240QDS_SRIO_PCIE_BOOT_defconfig | 2 ++
configs/T4240QDS_defconfig | 2 ++
configs/T4240RDB_SDCARD_defconfig | 2 ++
configs/T4240RDB_defconfig | 2 ++
configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig | 1 +
configs/controlcenterd_36BIT_SDCARD_defconfig | 1 +
configs/kmcoge4_defconfig | 2 ++
configs/qemu-ppce500_defconfig | 1 +
include/configs/B4860QDS.h | 5 -----
include/configs/C29XPCIE.h | 3 ---
include/configs/MPC8536DS.h | 5 -----
include/configs/MPC8548CDS.h | 5 -----
include/configs/MPC8572DS.h | 5 -----
include/configs/MPC8641HPCN.h | 2 --
include/configs/P1010RDB.h | 5 -----
include/configs/P1022DS.h | 5 -----
include/configs/P2041RDB.h | 5 -----
include/configs/T102xQDS.h | 5 -----
include/configs/T102xRDB.h | 5 -----
include/configs/T1040QDS.h | 3 ---
include/configs/T104xRDB.h | 3 ---
include/configs/T208xQDS.h | 5 -----
include/configs/T208xRDB.h | 5 -----
include/configs/T4240RDB.h | 3 ---
include/configs/controlcenterd.h | 5 -----
include/configs/corenet_ds.h | 5 -----
include/configs/cyrus.h | 5 -----
include/configs/kmp204x.h | 3 ---
include/configs/p1_p2_rdb_pc.h | 5 -----
include/configs/qemu-ppce500.h | 3 ---
include/configs/t4qds.h | 3 ---
lib/Kconfig | 13 +++++++++++++
scripts/config_whitelist.txt | 2 --
187 files changed, 290 insertions(+), 100 deletions(-)
diff --git a/configs/B4420QDS_NAND_defconfig b/configs/B4420QDS_NAND_defconfig
index 6fcb51a..59b4c74 100644
--- a/configs/B4420QDS_NAND_defconfig
+++ b/configs/B4420QDS_NAND_defconfig
@@ -66,4 +66,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/B4420QDS_SPIFLASH_defconfig b/configs/B4420QDS_SPIFLASH_defconfig
index 5dc72cb..626b556 100644
--- a/configs/B4420QDS_SPIFLASH_defconfig
+++ b/configs/B4420QDS_SPIFLASH_defconfig
@@ -52,4 +52,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/B4420QDS_defconfig b/configs/B4420QDS_defconfig
index 5f9a88a..f166549 100644
--- a/configs/B4420QDS_defconfig
+++ b/configs/B4420QDS_defconfig
@@ -50,4 +50,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/B4860QDS_NAND_defconfig b/configs/B4860QDS_NAND_defconfig
index 0874acd..c5d894e 100644
--- a/configs/B4860QDS_NAND_defconfig
+++ b/configs/B4860QDS_NAND_defconfig
@@ -66,4 +66,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/B4860QDS_SECURE_BOOT_defconfig b/configs/B4860QDS_SECURE_BOOT_defconfig
index 4d7bf5d..448dc70 100644
--- a/configs/B4860QDS_SECURE_BOOT_defconfig
+++ b/configs/B4860QDS_SECURE_BOOT_defconfig
@@ -50,6 +50,8 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/B4860QDS_SPIFLASH_defconfig b/configs/B4860QDS_SPIFLASH_defconfig
index 5660765..45c3b7d 100644
--- a/configs/B4860QDS_SPIFLASH_defconfig
+++ b/configs/B4860QDS_SPIFLASH_defconfig
@@ -52,4 +52,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
index 58195ad..d3eb91a 100644
--- a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
@@ -46,4 +46,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/B4860QDS_defconfig b/configs/B4860QDS_defconfig
index 68ff6ed..257f627 100644
--- a/configs/B4860QDS_defconfig
+++ b/configs/B4860QDS_defconfig
@@ -50,4 +50,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/C29XPCIE_NAND_defconfig b/configs/C29XPCIE_NAND_defconfig
index cdcf50e..d2ec14d 100644
--- a/configs/C29XPCIE_NAND_defconfig
+++ b/configs/C29XPCIE_NAND_defconfig
@@ -67,4 +67,5 @@ CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
+CONFIG_ADDR_MAP=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/C29XPCIE_NOR_SECBOOT_defconfig b/configs/C29XPCIE_NOR_SECBOOT_defconfig
index e43c728..1b838f0 100644
--- a/configs/C29XPCIE_NOR_SECBOOT_defconfig
+++ b/configs/C29XPCIE_NOR_SECBOOT_defconfig
@@ -49,6 +49,7 @@ CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
+CONFIG_ADDR_MAP=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
index b7eb77e..502a399 100644
--- a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
+++ b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
@@ -51,6 +51,7 @@ CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
+CONFIG_ADDR_MAP=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/C29XPCIE_SPIFLASH_defconfig b/configs/C29XPCIE_SPIFLASH_defconfig
index 9bfdcd0..5427a24 100644
--- a/configs/C29XPCIE_SPIFLASH_defconfig
+++ b/configs/C29XPCIE_SPIFLASH_defconfig
@@ -52,4 +52,5 @@ CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
+CONFIG_ADDR_MAP=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/C29XPCIE_defconfig b/configs/C29XPCIE_defconfig
index 3e7f196..431796e 100644
--- a/configs/C29XPCIE_defconfig
+++ b/configs/C29XPCIE_defconfig
@@ -50,4 +50,5 @@ CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
+CONFIG_ADDR_MAP=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/Cyrus_P5020_defconfig b/configs/Cyrus_P5020_defconfig
index 19fc741..d7798ef 100644
--- a/configs/Cyrus_P5020_defconfig
+++ b/configs/Cyrus_P5020_defconfig
@@ -42,4 +42,6 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/Cyrus_P5040_defconfig b/configs/Cyrus_P5040_defconfig
index 9c6919f..39191de 100644
--- a/configs/Cyrus_P5040_defconfig
+++ b/configs/Cyrus_P5040_defconfig
@@ -42,4 +42,6 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8536DS_36BIT_defconfig b/configs/MPC8536DS_36BIT_defconfig
index e60890e..016215f 100644
--- a/configs/MPC8536DS_36BIT_defconfig
+++ b/configs/MPC8536DS_36BIT_defconfig
@@ -58,4 +58,5 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
+CONFIG_ADDR_MAP=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig
index 010e375..6884754 100644
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ b/configs/MPC8548CDS_36BIT_defconfig
@@ -46,3 +46,4 @@ CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
+CONFIG_ADDR_MAP=y
diff --git a/configs/MPC8572DS_36BIT_defconfig b/configs/MPC8572DS_36BIT_defconfig
index 50912bf..4053cb7 100644
--- a/configs/MPC8572DS_36BIT_defconfig
+++ b/configs/MPC8572DS_36BIT_defconfig
@@ -51,4 +51,5 @@ CONFIG_USB=y
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
+CONFIG_ADDR_MAP=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8641HPCN_36BIT_defconfig b/configs/MPC8641HPCN_36BIT_defconfig
index 1e64367..c75e665 100644
--- a/configs/MPC8641HPCN_36BIT_defconfig
+++ b/configs/MPC8641HPCN_36BIT_defconfig
@@ -42,4 +42,6 @@ CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_KEYBOARD=y
CONFIG_VIDEO=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=8
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8641HPCN_defconfig b/configs/MPC8641HPCN_defconfig
index 7ce7891..b60813d 100644
--- a/configs/MPC8641HPCN_defconfig
+++ b/configs/MPC8641HPCN_defconfig
@@ -42,4 +42,6 @@ CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_KEYBOARD=y
CONFIG_VIDEO=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=8
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
index c104452..c406667 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
@@ -57,6 +57,7 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index da04cab0..f4c61af 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -83,3 +83,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
index 723f6ca..c3cfaf1 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
@@ -56,6 +56,7 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index e6edd39..5a2dcae 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -65,3 +65,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index dcd606b..b55afcf 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -77,3 +77,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
index 9987cde..8a13e3a 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
@@ -58,6 +58,7 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index c0800c8..a839a7c 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -79,3 +79,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
index 66bdebb..1f2e969 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
@@ -57,6 +57,7 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index 9f4876d..d19a037 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -83,3 +83,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
index f2e4066..bbaec2b 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
@@ -56,6 +56,7 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index e85af32..58f4430 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -65,3 +65,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index 45feab4..0eb37da 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -77,3 +77,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
index 50b5c5f..63ac2f2 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
@@ -58,6 +58,7 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index 3cd94f8..883da41 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -79,3 +79,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
diff --git a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
index 91d46e4..63dc6f4 100644
--- a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
@@ -64,4 +64,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020MBG-PC_36BIT_defconfig b/configs/P1020MBG-PC_36BIT_defconfig
index 7930af3..2385da4 100644
--- a/configs/P1020MBG-PC_36BIT_defconfig
+++ b/configs/P1020MBG-PC_36BIT_defconfig
@@ -52,4 +52,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index 6ee52fe..4fa5e5e 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -83,3 +83,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index 489b91d..b45af8a 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -78,3 +78,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index 4a8e4e3..21059d6 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -80,3 +80,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index f9a4b73..850a152 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -67,3 +67,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
diff --git a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
index 4b00005..5343914 100644
--- a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
@@ -64,4 +64,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020UTM-PC_36BIT_defconfig b/configs/P1020UTM-PC_36BIT_defconfig
index 968d3ed..47232d9 100644
--- a/configs/P1020UTM-PC_36BIT_defconfig
+++ b/configs/P1020UTM-PC_36BIT_defconfig
@@ -52,4 +52,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1021RDB-PC_36BIT_NAND_defconfig b/configs/P1021RDB-PC_36BIT_NAND_defconfig
index ba1d836..1c4cb86 100644
--- a/configs/P1021RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1021RDB-PC_36BIT_NAND_defconfig
@@ -81,4 +81,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
index 30b8372..8f58aa4 100644
--- a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
@@ -76,4 +76,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
index 37bc209..121b658 100644
--- a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
@@ -78,4 +78,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1021RDB-PC_36BIT_defconfig b/configs/P1021RDB-PC_36BIT_defconfig
index ca1be9c..608a6d1 100644
--- a/configs/P1021RDB-PC_36BIT_defconfig
+++ b/configs/P1021RDB-PC_36BIT_defconfig
@@ -64,4 +64,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1022DS_36BIT_NAND_defconfig b/configs/P1022DS_36BIT_NAND_defconfig
index 2bfda3e..b698530 100644
--- a/configs/P1022DS_36BIT_NAND_defconfig
+++ b/configs/P1022DS_36BIT_NAND_defconfig
@@ -77,4 +77,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1022DS_36BIT_SDCARD_defconfig b/configs/P1022DS_36BIT_SDCARD_defconfig
index 9cc2140..ea1199f 100644
--- a/configs/P1022DS_36BIT_SDCARD_defconfig
+++ b/configs/P1022DS_36BIT_SDCARD_defconfig
@@ -71,4 +71,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1022DS_36BIT_SPIFLASH_defconfig b/configs/P1022DS_36BIT_SPIFLASH_defconfig
index 80d3a88..a2a432f 100644
--- a/configs/P1022DS_36BIT_SPIFLASH_defconfig
+++ b/configs/P1022DS_36BIT_SPIFLASH_defconfig
@@ -73,4 +73,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1022DS_36BIT_defconfig b/configs/P1022DS_36BIT_defconfig
index 1048b53..36d60a3 100644
--- a/configs/P1022DS_36BIT_defconfig
+++ b/configs/P1022DS_36BIT_defconfig
@@ -59,4 +59,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1024RDB_36BIT_defconfig b/configs/P1024RDB_36BIT_defconfig
index 5116fac..bb016af 100644
--- a/configs/P1024RDB_36BIT_defconfig
+++ b/configs/P1024RDB_36BIT_defconfig
@@ -58,4 +58,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1025RDB_36BIT_defconfig b/configs/P1025RDB_36BIT_defconfig
index 8eaddb1..c096593 100644
--- a/configs/P1025RDB_36BIT_defconfig
+++ b/configs/P1025RDB_36BIT_defconfig
@@ -60,4 +60,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index 3e6ea64..6f6576b 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -88,3 +88,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index 187cbee..1ffbe45 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -83,3 +83,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index 88c9224..7b09786 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -85,3 +85,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index 88e24c3..1140177 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -72,3 +72,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index 13b20dd..2f5634e 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -62,3 +62,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index d99c153..0a0a8be 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -61,3 +61,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/P2041RDB_SECURE_BOOT_defconfig b/configs/P2041RDB_SECURE_BOOT_defconfig
index af33f9d..3b4e0d9 100644
--- a/configs/P2041RDB_SECURE_BOOT_defconfig
+++ b/configs/P2041RDB_SECURE_BOOT_defconfig
@@ -51,6 +51,8 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index 78a2a97..ed583cf 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -62,3 +62,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
index dd5f2a4..2832a86 100644
--- a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
@@ -47,4 +47,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 0b9625e..8a9c3a4 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -60,3 +60,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
index 8ab2537..c14a05b 100644
--- a/configs/P3041DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
@@ -53,6 +53,8 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index 55613cc..f774e1f 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -62,3 +62,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index b52068d..89678ea 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -61,3 +61,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/P3041DS_SECURE_BOOT_defconfig b/configs/P3041DS_SECURE_BOOT_defconfig
index d6cabeb..afb1aec 100644
--- a/configs/P3041DS_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_SECURE_BOOT_defconfig
@@ -51,6 +51,8 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
index 3af52b9..a5d881a 100644
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig
@@ -62,3 +62,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
index c34311b..6c7b951 100644
--- a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
@@ -47,4 +47,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index cc3234c..0a766c8 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -60,3 +60,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index 18ad56a..c0d184e 100644
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig
@@ -60,3 +60,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/P4080DS_SECURE_BOOT_defconfig b/configs/P4080DS_SECURE_BOOT_defconfig
index 22a6ebe..e4d494b 100644
--- a/configs/P4080DS_SECURE_BOOT_defconfig
+++ b/configs/P4080DS_SECURE_BOOT_defconfig
@@ -50,6 +50,8 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
index 81a513b..f171d7c 100644
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig
@@ -61,3 +61,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
index a740bc4..46aee4d 100644
--- a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
@@ -45,4 +45,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index 52db2e0..2980020 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -59,3 +59,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
index 52efa92..5f0c597 100644
--- a/configs/P5020DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
@@ -54,6 +54,8 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/P5020DS_NAND_defconfig b/configs/P5020DS_NAND_defconfig
index baf7d83..b711f3b 100644
--- a/configs/P5020DS_NAND_defconfig
+++ b/configs/P5020DS_NAND_defconfig
@@ -54,4 +54,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/P5020DS_SDCARD_defconfig b/configs/P5020DS_SDCARD_defconfig
index c5b4241..b459047 100644
--- a/configs/P5020DS_SDCARD_defconfig
+++ b/configs/P5020DS_SDCARD_defconfig
@@ -52,4 +52,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/P5020DS_SECURE_BOOT_defconfig b/configs/P5020DS_SECURE_BOOT_defconfig
index c08f9ff..79e8cc9 100644
--- a/configs/P5020DS_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_SECURE_BOOT_defconfig
@@ -51,6 +51,8 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/P5020DS_SPIFLASH_defconfig b/configs/P5020DS_SPIFLASH_defconfig
index 03d7a16..3777c1d 100644
--- a/configs/P5020DS_SPIFLASH_defconfig
+++ b/configs/P5020DS_SPIFLASH_defconfig
@@ -53,4 +53,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
index 7569364..9b7cb68 100644
--- a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
@@ -47,4 +47,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/P5020DS_defconfig b/configs/P5020DS_defconfig
index a1b410c..77fcf26 100644
--- a/configs/P5020DS_defconfig
+++ b/configs/P5020DS_defconfig
@@ -51,4 +51,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
index beab855..782b027 100644
--- a/configs/P5040DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
@@ -54,6 +54,8 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index efffb70..35584e2 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -63,3 +63,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index fdd39ac..91c0285 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -61,3 +61,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/P5040DS_SECURE_BOOT_defconfig b/configs/P5040DS_SECURE_BOOT_defconfig
index 5d48206..34e024a 100644
--- a/configs/P5040DS_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_SECURE_BOOT_defconfig
@@ -51,6 +51,8 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
index 3f4642f..49a2b93 100644
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig
@@ -62,3 +62,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index d2a2e02..a797088 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -60,3 +60,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig
index 7560438..7dfa238 100644
--- a/configs/T1023RDB_NAND_defconfig
+++ b/configs/T1023RDB_NAND_defconfig
@@ -74,4 +74,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig
index 4471c83..aeb540d 100644
--- a/configs/T1023RDB_SDCARD_defconfig
+++ b/configs/T1023RDB_SDCARD_defconfig
@@ -71,4 +71,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig
index 34fe6e5..a9c9794 100644
--- a/configs/T1023RDB_SECURE_BOOT_defconfig
+++ b/configs/T1023RDB_SECURE_BOOT_defconfig
@@ -58,6 +58,8 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig
index 599aeec..be66193 100644
--- a/configs/T1023RDB_SPIFLASH_defconfig
+++ b/configs/T1023RDB_SPIFLASH_defconfig
@@ -74,4 +74,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig
index 62cc129..3366ff0 100644
--- a/configs/T1023RDB_defconfig
+++ b/configs/T1023RDB_defconfig
@@ -58,4 +58,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
index 2199abc..b3477ae 100644
--- a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
@@ -63,6 +63,8 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/T1024QDS_DDR4_defconfig b/configs/T1024QDS_DDR4_defconfig
index 0a52af4..96024f7 100644
--- a/configs/T1024QDS_DDR4_defconfig
+++ b/configs/T1024QDS_DDR4_defconfig
@@ -61,4 +61,6 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig
index 9db39b1..e39f513 100644
--- a/configs/T1024QDS_NAND_defconfig
+++ b/configs/T1024QDS_NAND_defconfig
@@ -80,4 +80,6 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig
index 679f2ad..00daf85 100644
--- a/configs/T1024QDS_SDCARD_defconfig
+++ b/configs/T1024QDS_SDCARD_defconfig
@@ -77,4 +77,6 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig
index cc080c7..fcb3cdf 100644
--- a/configs/T1024QDS_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_SECURE_BOOT_defconfig
@@ -64,6 +64,8 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig
index 01bc511..e763838 100644
--- a/configs/T1024QDS_SPIFLASH_defconfig
+++ b/configs/T1024QDS_SPIFLASH_defconfig
@@ -80,4 +80,6 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024QDS_defconfig b/configs/T1024QDS_defconfig
index 6ebffb8..c76d80e 100644
--- a/configs/T1024QDS_defconfig
+++ b/configs/T1024QDS_defconfig
@@ -64,4 +64,6 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index 9b11654..832c06b 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -84,3 +84,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index 5e087fe..8334e4e 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -81,3 +81,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig
index f23f021..9cbf87d 100644
--- a/configs/T1024RDB_SECURE_BOOT_defconfig
+++ b/configs/T1024RDB_SECURE_BOOT_defconfig
@@ -60,6 +60,8 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index 39b4537..7c30639 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -84,3 +84,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index 8ff2fe3..b359f16 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -69,3 +69,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig
index 87b2a76..79cc58f 100644
--- a/configs/T1040D4RDB_NAND_defconfig
+++ b/configs/T1040D4RDB_NAND_defconfig
@@ -72,4 +72,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig
index 4b9e428..492a3e4 100644
--- a/configs/T1040D4RDB_SDCARD_defconfig
+++ b/configs/T1040D4RDB_SDCARD_defconfig
@@ -69,4 +69,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig
index 7adffb7..01fa29c 100644
--- a/configs/T1040D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040D4RDB_SECURE_BOOT_defconfig
@@ -55,6 +55,8 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig
index 2320b72..eb7c778 100644
--- a/configs/T1040D4RDB_SPIFLASH_defconfig
+++ b/configs/T1040D4RDB_SPIFLASH_defconfig
@@ -72,4 +72,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig
index eb25930..dcf3dce 100644
--- a/configs/T1040D4RDB_defconfig
+++ b/configs/T1040D4RDB_defconfig
@@ -56,4 +56,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040QDS_DDR4_defconfig b/configs/T1040QDS_DDR4_defconfig
index a575b6f..38f3ef7 100644
--- a/configs/T1040QDS_DDR4_defconfig
+++ b/configs/T1040QDS_DDR4_defconfig
@@ -64,4 +64,6 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040QDS_SECURE_BOOT_defconfig b/configs/T1040QDS_SECURE_BOOT_defconfig
index e616f0d..d0747ba 100644
--- a/configs/T1040QDS_SECURE_BOOT_defconfig
+++ b/configs/T1040QDS_SECURE_BOOT_defconfig
@@ -64,6 +64,8 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/T1040QDS_defconfig b/configs/T1040QDS_defconfig
index 0b1c7cd..705b775 100644
--- a/configs/T1040QDS_defconfig
+++ b/configs/T1040QDS_defconfig
@@ -65,4 +65,6 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040RDB_NAND_defconfig b/configs/T1040RDB_NAND_defconfig
index 7cf9847..e4b9932 100644
--- a/configs/T1040RDB_NAND_defconfig
+++ b/configs/T1040RDB_NAND_defconfig
@@ -73,4 +73,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040RDB_SDCARD_defconfig b/configs/T1040RDB_SDCARD_defconfig
index 321260f..4f6126d 100644
--- a/configs/T1040RDB_SDCARD_defconfig
+++ b/configs/T1040RDB_SDCARD_defconfig
@@ -70,4 +70,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig
index 910b984..aa22883 100644
--- a/configs/T1040RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040RDB_SECURE_BOOT_defconfig
@@ -56,6 +56,8 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/T1040RDB_SPIFLASH_defconfig b/configs/T1040RDB_SPIFLASH_defconfig
index 65ab4e0..d69d817 100644
--- a/configs/T1040RDB_SPIFLASH_defconfig
+++ b/configs/T1040RDB_SPIFLASH_defconfig
@@ -73,4 +73,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040RDB_defconfig b/configs/T1040RDB_defconfig
index e8c5393..56d61ae 100644
--- a/configs/T1040RDB_defconfig
+++ b/configs/T1040RDB_defconfig
@@ -57,4 +57,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index 1602fb8..1b5b39d 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -84,3 +84,5 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index a4a31bf..bf598e8 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -81,3 +81,5 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig
index f460b17..b9adcc0 100644
--- a/configs/T1042D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig
@@ -58,6 +58,8 @@ CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index 697c08d..06021e8 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -84,3 +84,5 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 70ddffb..2c6e8d0 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -69,3 +69,5 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
index 167325f..fde3599 100644
--- a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
+++ b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
@@ -79,6 +79,8 @@ CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig
index 90bbee2..6969526 100644
--- a/configs/T1042RDB_PI_NAND_defconfig
+++ b/configs/T1042RDB_PI_NAND_defconfig
@@ -77,4 +77,6 @@ CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig
index ae664df..f772d57 100644
--- a/configs/T1042RDB_PI_SDCARD_defconfig
+++ b/configs/T1042RDB_PI_SDCARD_defconfig
@@ -74,4 +74,6 @@ CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig
index ef65465..05335f8 100644
--- a/configs/T1042RDB_PI_SPIFLASH_defconfig
+++ b/configs/T1042RDB_PI_SPIFLASH_defconfig
@@ -77,4 +77,6 @@ CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig
index 07ad865..4a9e534 100644
--- a/configs/T1042RDB_PI_defconfig
+++ b/configs/T1042RDB_PI_defconfig
@@ -61,4 +61,6 @@ CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig
index c5f39e8..2633b83 100644
--- a/configs/T1042RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042RDB_SECURE_BOOT_defconfig
@@ -55,6 +55,8 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/T1042RDB_defconfig b/configs/T1042RDB_defconfig
index c94730d..0755a95 100644
--- a/configs/T1042RDB_defconfig
+++ b/configs/T1042RDB_defconfig
@@ -56,4 +56,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index 52255ed..1cdce6d 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -81,3 +81,5 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index ba57ea3..a6843b5 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -78,3 +78,5 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index 9b3f709..35891cc 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -65,6 +65,8 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index 5aa45f5..7f053ff 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -81,3 +81,5 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index 4958435..38d947c 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -58,3 +58,5 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index 602bf57..a5bd06c 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -66,3 +66,5 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index 81baa5d..9770476 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -82,3 +82,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index a1d7d87..3ea5c60 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -79,3 +79,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig
index 7d04a94..1a89cd8 100644
--- a/configs/T2080RDB_SECURE_BOOT_defconfig
+++ b/configs/T2080RDB_SECURE_BOOT_defconfig
@@ -57,6 +57,8 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index c433a92..d7ce9c1 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -82,3 +82,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
index a8f0a96..729edaa 100644
--- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
@@ -50,4 +50,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index 85e3b64..d957e40 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -66,3 +66,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T2081QDS_NAND_defconfig b/configs/T2081QDS_NAND_defconfig
index 85381c6..8837087 100644
--- a/configs/T2081QDS_NAND_defconfig
+++ b/configs/T2081QDS_NAND_defconfig
@@ -72,4 +72,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T2081QDS_SDCARD_defconfig b/configs/T2081QDS_SDCARD_defconfig
index bbc8b76..dadc692 100644
--- a/configs/T2081QDS_SDCARD_defconfig
+++ b/configs/T2081QDS_SDCARD_defconfig
@@ -69,4 +69,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T2081QDS_SPIFLASH_defconfig b/configs/T2081QDS_SPIFLASH_defconfig
index b02505b..fd5e79b 100644
--- a/configs/T2081QDS_SPIFLASH_defconfig
+++ b/configs/T2081QDS_SPIFLASH_defconfig
@@ -72,4 +72,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
index a10f39b..87cfb5f 100644
--- a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
@@ -48,4 +48,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T2081QDS_defconfig b/configs/T2081QDS_defconfig
index 22ca083..c7ff58a 100644
--- a/configs/T2081QDS_defconfig
+++ b/configs/T2081QDS_defconfig
@@ -56,4 +56,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T4160QDS_NAND_defconfig b/configs/T4160QDS_NAND_defconfig
index ddff896..e9b6ea3 100644
--- a/configs/T4160QDS_NAND_defconfig
+++ b/configs/T4160QDS_NAND_defconfig
@@ -66,4 +66,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T4160QDS_SDCARD_defconfig b/configs/T4160QDS_SDCARD_defconfig
index 5d25353..1e11665 100644
--- a/configs/T4160QDS_SDCARD_defconfig
+++ b/configs/T4160QDS_SDCARD_defconfig
@@ -63,4 +63,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T4160QDS_SECURE_BOOT_defconfig b/configs/T4160QDS_SECURE_BOOT_defconfig
index 8934c3e..47f4362 100644
--- a/configs/T4160QDS_SECURE_BOOT_defconfig
+++ b/configs/T4160QDS_SECURE_BOOT_defconfig
@@ -50,6 +50,8 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/T4160QDS_defconfig b/configs/T4160QDS_defconfig
index d0d1290..0a055dd 100644
--- a/configs/T4160QDS_defconfig
+++ b/configs/T4160QDS_defconfig
@@ -50,4 +50,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig
index f3c7e1e..70e6d92 100644
--- a/configs/T4160RDB_defconfig
+++ b/configs/T4160RDB_defconfig
@@ -51,4 +51,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T4240QDS_NAND_defconfig b/configs/T4240QDS_NAND_defconfig
index f971cee..9b9bf46 100644
--- a/configs/T4240QDS_NAND_defconfig
+++ b/configs/T4240QDS_NAND_defconfig
@@ -66,4 +66,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T4240QDS_SDCARD_defconfig b/configs/T4240QDS_SDCARD_defconfig
index 5e662be..87343ef 100644
--- a/configs/T4240QDS_SDCARD_defconfig
+++ b/configs/T4240QDS_SDCARD_defconfig
@@ -63,4 +63,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T4240QDS_SECURE_BOOT_defconfig b/configs/T4240QDS_SECURE_BOOT_defconfig
index 807d5b58..4937c59 100644
--- a/configs/T4240QDS_SECURE_BOOT_defconfig
+++ b/configs/T4240QDS_SECURE_BOOT_defconfig
@@ -50,6 +50,8 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
index 2bc30bb..adf31ee 100644
--- a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
@@ -46,4 +46,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T4240QDS_defconfig b/configs/T4240QDS_defconfig
index 84341f7..4f6d818 100644
--- a/configs/T4240QDS_defconfig
+++ b/configs/T4240QDS_defconfig
@@ -50,4 +50,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index 14e3663..d3bea76 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -72,3 +72,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index dfe8953..2d8ab6f 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -60,3 +60,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
index 90fe803..41785d0 100644
--- a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
+++ b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
@@ -64,5 +64,6 @@ CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_ADDR_MAP=y
CONFIG_TPM=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/controlcenterd_36BIT_SDCARD_defconfig b/configs/controlcenterd_36BIT_SDCARD_defconfig
index 55a46c3..777f5ae 100644
--- a/configs/controlcenterd_36BIT_SDCARD_defconfig
+++ b/configs/controlcenterd_36BIT_SDCARD_defconfig
@@ -64,5 +64,6 @@ CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_ADDR_MAP=y
CONFIG_TPM=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/kmcoge4_defconfig b/configs/kmcoge4_defconfig
index a0d2c1a..cf54e9f 100644
--- a/configs/kmcoge4_defconfig
+++ b/configs/kmcoge4_defconfig
@@ -64,5 +64,7 @@ CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig
index ab4bc5d..ba2ee27 100644
--- a/configs/qemu-ppce500_defconfig
+++ b/configs/qemu-ppce500_defconfig
@@ -27,5 +27,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_MMC is not set
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_ADDR_MAP=y
CONFIG_PANIC_HANG=y
CONFIG_OF_LIBFDT=y
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index a515bf9..742420c 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -122,11 +122,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
#if 0
#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
#endif
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 9a8cba6..16e1855 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -104,9 +104,6 @@
#define CONFIG_ENABLE_36BIT_PHYS
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-
/* DDR Setup */
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 0
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 340574a..dec17c7 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -55,11 +55,6 @@
#define CONFIG_ENABLE_36BIT_PHYS 1
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
/*
* Config the L2 Cache as L2 SRAM
*/
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index de2bfd8..7ef8eab 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -43,11 +43,6 @@ extern unsigned long get_clock_freq(void);
*/
#define CONFIG_ENABLE_36BIT_PHYS 1
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
#define CONFIG_SYS_CCSRBAR 0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 3243f39..f6a1939 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -45,11 +45,6 @@
#define CONFIG_ENABLE_36BIT_PHYS 1
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
/*
* Config the L2 Cache as L2 SRAM
*/
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index edbeeef..206f684 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -19,7 +19,6 @@
/* High Level Configuration Options */
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
-#define CONFIG_ADDR_MAP 1 /* Use addr map */
/*
* default CCSRBAR is at 0xff700000
@@ -47,7 +46,6 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
-#define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */
#define CONFIG_ALTIVEC 1
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 8f709a6..fc74d57 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -196,11 +196,6 @@
#define CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
/* DDR Setup */
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_DDR_SPD
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 2b76107..3420c44 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -87,11 +87,6 @@
#define CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 59404cb..3687350 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -70,11 +70,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
/*
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index 53ae961..f781597 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -17,11 +17,6 @@
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index f5d9657..efd9b6b 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -17,11 +17,6 @@
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 7ad018b..a17b8f7 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -90,9 +90,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_ENABLE_36BIT_PHYS
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-
/*
* Config the L3 Cache as L3 SRAM
*/
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 4237dfc..8f9de56 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -186,9 +186,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
#define CONFIG_ENABLE_36BIT_PHYS
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-
/*
* Config the L3 Cache as L3 SRAM
*/
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index c54f7f5..f32e668 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -26,11 +26,6 @@
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 70eafc3..e666e4f 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -20,11 +20,6 @@
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index fcfd3b0..7e39e8c 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -80,9 +80,6 @@
#define CONFIG_ENABLE_36BIT_PHYS
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-
/*
* Config the L3 Cache as L3 SRAM
*/
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index 34d268e..9b02aec 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -41,11 +41,6 @@
#define CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
#define CONFIG_L2_CACHE
#define CONFIG_BTB
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index a49f905..d7812bd 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -84,11 +84,6 @@
#define CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
/*
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index 052e601..b587cb8 100644
--- a/include/configs/cyrus.h
+++ b/include/configs/cyrus.h
@@ -70,11 +70,6 @@
#define CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
/* test POST memory test */
#undef CONFIG_POST
diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h
index e43b2f7..6cd77ed 100644
--- a/include/configs/kmp204x.h
+++ b/include/configs/kmp204x.h
@@ -64,9 +64,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_ENABLE_36BIT_PHYS
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-
#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */
/*
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 219e5d2..1e6c8ae 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -233,11 +233,6 @@
#define CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
#define CONFIG_SYS_CCSRBAR 0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h
index cfbd472..a43f8f0 100644
--- a/include/configs/qemu-ppce500.h
+++ b/include/configs/qemu-ppce500.h
@@ -21,9 +21,6 @@
#define CONFIG_ENABLE_36BIT_PHYS
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-
/* Needed to fill the ccsrbar pointer */
/* Virtual address to CCSRBAR */
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index 976d527..ee6f5af 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -42,9 +42,6 @@
#define CONFIG_ENABLE_36BIT_PHYS
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-
/*
* Config the L3 Cache as L3 SRAM
*/
diff --git a/lib/Kconfig b/lib/Kconfig
index f18bf37..bab7486 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -1,5 +1,18 @@
menu "Library routines"
+config ADDR_MAP
+ bool "Enable support for non-identity virtual-physical mappings"
+ help
+ Enables helper code for implementing non-identity virtual-physical
+ memory mappings for 32bit CPUs.
+
+config SYS_NUM_ADDR_MAP
+ int "Size of the address-map table"
+ depends on ADDR_MAP
+ default 16
+ help
+ Sets the number of entries in the virtual-physical mapping table.
+
config BCH
bool "Enable Software based BCH ECC"
help
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 61d025f..554f31b 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -15,7 +15,6 @@ CONFIG_ACX517AKN
CONFIG_ACX544AKN
CONFIG_ADDRESS
CONFIG_ADDR_AUTO_INCR_BIT
-CONFIG_ADDR_MAP
CONFIG_ADNPESC1
CONFIG_AEABI
CONFIG_AEMIF_CNTRL_BASE
@@ -3281,7 +3280,6 @@ CONFIG_SYS_NS16550_MEM32
CONFIG_SYS_NS16550_PORT_MAPPED
CONFIG_SYS_NS16550_REG_SIZE
CONFIG_SYS_NS16550_SERIAL
-CONFIG_SYS_NUM_ADDR_MAP
CONFIG_SYS_NUM_CPC
CONFIG_SYS_NUM_FM1_10GEC
CONFIG_SYS_NUM_FM1_DTSEC
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v5 2/6] arm: update comments to the common style
[not found] ` <CGME20200603124405eucas1p22471280b162f8d0e1a863b2c48f122f4@eucas1p2.samsung.com>
@ 2020-06-03 12:43 ` Marek Szyprowski
2020-06-03 13:55 ` Tom Rini
2020-07-10 20:21 ` Tom Rini
0 siblings, 2 replies; 20+ messages in thread
From: Marek Szyprowski @ 2020-06-03 12:43 UTC (permalink / raw)
To: u-boot
Update the comments in include/asm/system.h to the common style.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
arch/arm/include/asm/system.h | 23 ++++++++++++++---------
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 1e3f574..63649ed 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -205,7 +205,7 @@ int __asm_invalidate_l3_icache(void);
void __asm_switch_ttbr(u64 new_ttbr);
/*
- * Switch from EL3 to EL2 for ARMv8
+ * armv8_switch_to_el2() - switch from EL3 to EL2 for ARMv8
*
* @args: For loading 64-bit OS, fdt address.
* For loading 32-bit OS, zero.
@@ -220,7 +220,7 @@ void __asm_switch_ttbr(u64 new_ttbr);
void __noreturn armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr,
u64 arg4, u64 entry_point, u64 es_flag);
/*
- * Switch from EL2 to EL1 for ARMv8
+ * armv8_switch_to_el1() - switch from EL2 to EL1 for ARMv8
*
* @args: For loading 64-bit OS, fdt address.
* For loading 32-bit OS, zero.
@@ -246,11 +246,12 @@ void flush_l3_cache(void);
void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs);
/*
- *Issue a secure monitor call in accordance with ARM "SMC Calling convention",
+ * smc_call() - issue a secure monitor call
+ *
+ * Issue a secure monitor call in accordance with ARM "SMC Calling convention",
* DEN0028A
*
* @args: input and output arguments
- *
*/
void smc_call(struct pt_regs *args);
@@ -519,10 +520,12 @@ enum {
#endif
/**
+ * mmu_page_table_flush() - register an update to page tables
+ *
* Register an update to the page tables, and flush the TLB
*
- * \param start start address of update in page table
- * \param stop stop address of update in page table
+ * @start: start address of update in page table
+ * @stop: stop address of update in page table
*/
void mmu_page_table_flush(unsigned long start, unsigned long stop);
@@ -582,11 +585,13 @@ s32 psci_features(u32 function_id, u32 psci_fid);
void save_boot_params_ret(void);
/**
+ * mmu_set_region_dcache_behaviour() - set cache settings
+ *
* Change the cache settings for a region.
*
- * \param start start address of memory region to change
- * \param size size of memory region to change
- * \param option dcache option to select
+ * @start: start address of memory region to change
+ * @size: size of memory region to change
+ * @option: dcache option to select
*/
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
enum dcache_option option);
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v5 3/6] arm: provide a function for boards init code to modify MMU virtual-physical map
[not found] ` <CGME20200603124405eucas1p18b8d5eb55cac3bf2b17b0309304947c1@eucas1p1.samsung.com>
@ 2020-06-03 12:43 ` Marek Szyprowski
2020-06-03 13:55 ` Tom Rini
2020-07-10 20:22 ` Tom Rini
0 siblings, 2 replies; 20+ messages in thread
From: Marek Szyprowski @ 2020-06-03 12:43 UTC (permalink / raw)
To: u-boot
Provide function for setting arbitrary virtual-physical MMU mapping
and cache settings for the given region.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
arch/arm/include/asm/mmu.h | 8 ++++++++
arch/arm/include/asm/system.h | 13 +++++++++++++
arch/arm/lib/cache-cp15.c | 24 ++++++++++++++++++------
3 files changed, 39 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/include/asm/mmu.h
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
new file mode 100644
index 0000000..9ac16f5
--- /dev/null
+++ b/arch/arm/include/asm/mmu.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __ASM_ARM_MMU_H
+#define __ASM_ARM_MMU_H
+
+void init_addr_map(void);
+
+#endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 63649ed..5d3b6d0 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -585,6 +585,19 @@ s32 psci_features(u32 function_id, u32 psci_fid);
void save_boot_params_ret(void);
/**
+ * mmu_set_region_dcache_behaviour_phys() - set virt/phys mapping
+ *
+ * Change the virt/phys mapping and cache settings for a region.
+ *
+ * @virt: virtual start address of memory region to change
+ * @phys: physical address for the memory region to set
+ * @size: size of memory region to change
+ * @option: dcache option to select
+ */
+void mmu_set_region_dcache_behaviour_phys(phys_addr_t virt, phys_addr_t phys,
+ size_t size, enum dcache_option option);
+
+/**
* mmu_set_region_dcache_behaviour() - set cache settings
*
* Change the cache settings for a region.
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 1da2e92..3971761 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -25,7 +25,8 @@ __weak void arm_init_domains(void)
{
}
-void set_section_dcache(int section, enum dcache_option option)
+static void set_section_phys(int section, phys_addr_t phys,
+ enum dcache_option option)
{
#ifdef CONFIG_ARMV7_LPAE
u64 *page_table = (u64 *)gd->arch.tlb_addr;
@@ -37,7 +38,7 @@ void set_section_dcache(int section, enum dcache_option option)
#endif
/* Add the page offset */
- value |= ((u32)section << MMU_SECTION_SHIFT);
+ value |= phys;
/* Add caching bits */
value |= option;
@@ -46,13 +47,18 @@ void set_section_dcache(int section, enum dcache_option option)
page_table[section] = value;
}
+void set_section_dcache(int section, enum dcache_option option)
+{
+ set_section_phys(section, (u32)section << MMU_SECTION_SHIFT, option);
+}
+
__weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
{
debug("%s: Warning: not implemented\n", __func__);
}
-void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
- enum dcache_option option)
+void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys,
+ size_t size, enum dcache_option option)
{
#ifdef CONFIG_ARMV7_LPAE
u64 *page_table = (u64 *)gd->arch.tlb_addr;
@@ -74,8 +80,8 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
option);
#endif
- for (upto = start; upto < end; upto++)
- set_section_dcache(upto, option);
+ for (upto = start; upto < end; upto++, phys += MMU_SECTION_SIZE)
+ set_section_phys(upto, phys, option);
/*
* Make sure range is cache line aligned
@@ -90,6 +96,12 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
mmu_page_table_flush(startpt, stoppt);
}
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+ enum dcache_option option)
+{
+ mmu_set_region_dcache_behaviour_phys(start, start, size, option);
+}
+
__weak void dram_bank_mmu_setup(int bank)
{
bd_t *bd = gd->bd;
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v5 4/6] mmc: bcm283x: fix int to pointer cast
[not found] ` <CGME20200603124406eucas1p1b628068324987ed59576fae97bf2833a@eucas1p1.samsung.com>
@ 2020-06-03 12:43 ` Marek Szyprowski
2020-07-10 20:22 ` Tom Rini
0 siblings, 1 reply; 20+ messages in thread
From: Marek Szyprowski @ 2020-06-03 12:43 UTC (permalink / raw)
To: u-boot
From: Seung-Woo Kim <sw0312.kim@samsung.com>
On build with 32 bit, there is a warning for int-to-pointer-cast.
Fix the int to pointer cast by using uintptr_t.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
drivers/mmc/bcm2835_sdhci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c
index dc3dffb..5cdf3c5 100644
--- a/drivers/mmc/bcm2835_sdhci.c
+++ b/drivers/mmc/bcm2835_sdhci.c
@@ -210,7 +210,7 @@ static int bcm2835_sdhci_probe(struct udevice *dev)
priv->last_write = 0;
host->name = dev->name;
- host->ioaddr = (void *)base;
+ host->ioaddr = (void *)(uintptr_t)base;
host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B |
SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_NO_HISPD_BIT;
host->max_clk = emmc_freq;
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v5 5/6] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)
[not found] ` <CGME20200603124407eucas1p1a343fda06c124089af99d1bfdbfcf657@eucas1p1.samsung.com>
@ 2020-06-03 12:43 ` Marek Szyprowski
2020-07-10 20:22 ` Tom Rini
0 siblings, 1 reply; 20+ messages in thread
From: Marek Szyprowski @ 2020-06-03 12:43 UTC (permalink / raw)
To: u-boot
Create a non-cacheable mapping for the 0x600000000 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
32bit mode, this region is mapped at 0xff800000 CPU virtual address.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
arch/arm/mach-bcm283x/Kconfig | 1 +
arch/arm/mach-bcm283x/include/mach/base.h | 8 ++++++++
arch/arm/mach-bcm283x/init.c | 21 +++++++++++++++++++++
3 files changed, 30 insertions(+)
diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index e6eb904..b3287ce 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -36,6 +36,7 @@ config BCM2711_32B
select BCM2711
select ARMV7_LPAE
select CPU_V7A
+ select PHYS_64BIT
config BCM2711_64B
bool "Broadcom BCM2711 SoC 64-bit support"
diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h
index c4ae398..4ccaf69 100644
--- a/arch/arm/mach-bcm283x/include/mach/base.h
+++ b/arch/arm/mach-bcm283x/include/mach/base.h
@@ -8,4 +8,12 @@
extern unsigned long rpi_bcm283x_base;
+#ifdef CONFIG_ARMV7_LPAE
+#ifdef CONFIG_TARGET_RPI_4_32B
+#include <addr_map.h>
+#define phys_to_virt addrmap_phys_to_virt
+#define virt_to_phys addrmap_virt_to_phys
+#endif
+#endif
+
#endif
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index cf4c5b2..f2a5411 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -146,6 +146,27 @@ int mach_cpu_init(void)
}
#ifdef CONFIG_ARMV7_LPAE
+#ifdef CONFIG_TARGET_RPI_4_32B
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL
+#include <addr_map.h>
+#include <asm/system.h>
+
+void init_addr_map(void)
+{
+ mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
+ BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+ BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
+ DCACHE_OFF);
+
+ /* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
+ addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0);
+ /* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
+ addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
+ BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+ BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1);
+}
+#endif
+
void enable_caches(void)
{
dcache_enable();
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v5 6/6] config: Enable support for the XHCI controller on RPI4 board
[not found] ` <CGME20200603124407eucas1p29bd0c3b02952deb6c58037c0b10f57b7@eucas1p2.samsung.com>
@ 2020-06-03 12:43 ` Marek Szyprowski
2020-07-10 20:22 ` Tom Rini
0 siblings, 1 reply; 20+ messages in thread
From: Marek Szyprowski @ 2020-06-03 12:43 UTC (permalink / raw)
To: u-boot
This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI
and USB commands. To get it working one has to call the following commands:
"pci enum; usb start;", thus such commands have been added to the default
"preboot" environment variable. One has to update their environment if it
is already configured to get this feature working out of the box.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
configs/rpi_4_32b_defconfig | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
index 52bdd0a..3317ef9 100644
--- a/configs/rpi_4_32b_defconfig
+++ b/configs/rpi_4_32b_defconfig
@@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="pci enum; usb start;"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
@@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
CONFIG_CMD_FS_UUID=y
CONFIG_OF_BOARD=y
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
@@ -28,12 +32,17 @@ CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_BCM2835=y
CONFIG_DM_ETH=y
CONFIG_BCMGENET=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_BRCMSTB=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
@@ -46,4 +55,6 @@ CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_PHYS_TO_BUS=y
+CONFIG_ADDR_MAP=y
+CONFIG_SYS_NUM_ADDR_MAP=2
CONFIG_OF_LIBFDT_OVERLAY=y
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v5 2/6] arm: update comments to the common style
2020-06-03 12:43 ` [PATCH v5 2/6] arm: update comments to the common style Marek Szyprowski
@ 2020-06-03 13:55 ` Tom Rini
2020-07-10 20:21 ` Tom Rini
1 sibling, 0 replies; 20+ messages in thread
From: Tom Rini @ 2020-06-03 13:55 UTC (permalink / raw)
To: u-boot
On Wed, Jun 03, 2020 at 02:43:41PM +0200, Marek Szyprowski wrote:
> Update the comments in include/asm/system.h to the common style.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Thanks!
Reviewed-by: Tom Rini <trini@konsulko.com>
--
Tom
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v5 3/6] arm: provide a function for boards init code to modify MMU virtual-physical map
2020-06-03 12:43 ` [PATCH v5 3/6] arm: provide a function for boards init code to modify MMU virtual-physical map Marek Szyprowski
@ 2020-06-03 13:55 ` Tom Rini
2020-07-10 20:22 ` Tom Rini
1 sibling, 0 replies; 20+ messages in thread
From: Tom Rini @ 2020-06-03 13:55 UTC (permalink / raw)
To: u-boot
On Wed, Jun 03, 2020 at 02:43:42PM +0200, Marek Szyprowski wrote:
> Provide function for setting arbitrary virtual-physical MMU mapping
> and cache settings for the given region.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
--
Tom
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* [PATCH v5 0/6] ARM: arbitrary virtual-physical mappings for RPi4 XHCI support
2020-06-03 12:43 ` [PATCH v5 0/6] ARM: arbitrary virtual-physical mappings for RPi4 XHCI support Marek Szyprowski
` (5 preceding siblings ...)
[not found] ` <CGME20200603124407eucas1p29bd0c3b02952deb6c58037c0b10f57b7@eucas1p2.samsung.com>
@ 2020-06-11 8:39 ` Matthias Brugger
2020-07-09 6:33 ` Marek Szyprowski
6 siblings, 1 reply; 20+ messages in thread
From: Matthias Brugger @ 2020-06-11 8:39 UTC (permalink / raw)
To: u-boot
On 03/06/2020 14:43, Marek Szyprowski wrote:
> Hi All,
>
> This patchset adds support for creating a mapping for the arbitrary
> physical address at the given virtual address. This is needed to enable
> support for XHCI USB controller on PCIe bridge on Raspberry Pi 4 board,
> on which the USB controller's MMIO area 0x600000000 has to be remapped
> somewhere to fit in 4GiB virtual address space when running in ARM 32bit
> mode.
>
> This patchset is a continuation of the Raspberry Pi 4 XHCI/PCIe patchset:
> https://patchwork.ozlabs.org/project/uboot/list/?series=179078
> and the following discussion:
> https://lists.denx.de/pipermail/u-boot/2020-May/411086.html
>
> Best regards
> Marek Szyprowski
> Samsung R&D Institute Poland
>
>
> Changelog:
>
> v5:
> - fixed issues pointed by Tom Rini (comments style, ifdefs, spdx)
>
> v4: https://lists.denx.de/pipermail/u-boot/2020-June/414531.html
> - added a patch, which moves ADDR_MAP config entry to Kconfig system
> as requested by Simon Glass
> - rebased onto v4 of the "USB host support for Raspberry Pi 4 board
> (64-bit)" patchset
>
> v3: https://lists.denx.de/pipermail/u-boot/2020-May/412427.html
> - fixed broken RPi3 and lack of the identity mapping for map_physmem
> (for example for the itest command was broken)
> - added a patch fixing a new build warning
>
> v2: https://lists.denx.de/pipermail/u-boot/2020-May/411765.html
> - fixed ARM64 build
>
> v1: https://lists.denx.de/pipermail/u-boot/2020-May/411765.html
> - initial RFC
>
>
> Patch summary:
>
> Marek Szyprowski (5):
> powerpc: move ADDR_MAP to Kconfig
> arm: update comments to the common style
> arm: provide a function for boards init code to modify MMU
> virtual-physical map
> rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM
> 32bit)
> config: Enable support for the XHCI controller on RPI4 board
>
> Seung-Woo Kim (1):
> mmc: bcm283x: fix int to pointer cast
>
Series looks good to me. The problem is that on RPi4 with 8 GB the USB FW get's
loaded via the RPi FW. Nicolas provided a series which is under review right
now. Without this series the 8 GB RPi4 won't boot. As soon as the series is
ready I'll take all the RPi4 PCI/USB related patches into the next branch.
Regards,
Matthias
> arch/arm/include/asm/mmu.h | 8 +++++
> arch/arm/include/asm/system.h | 36 ++++++++++++++++------
> arch/arm/lib/cache-cp15.c | 24 +++++++++++----
> arch/arm/mach-bcm283x/Kconfig | 1 +
> arch/arm/mach-bcm283x/include/mach/base.h | 8 +++++
> arch/arm/mach-bcm283x/init.c | 21 +++++++++++++
> configs/B4420QDS_NAND_defconfig | 2 ++
> configs/B4420QDS_SPIFLASH_defconfig | 2 ++
> configs/B4420QDS_defconfig | 2 ++
> configs/B4860QDS_NAND_defconfig | 2 ++
> configs/B4860QDS_SECURE_BOOT_defconfig | 2 ++
> configs/B4860QDS_SPIFLASH_defconfig | 2 ++
> configs/B4860QDS_SRIO_PCIE_BOOT_defconfig | 2 ++
> configs/B4860QDS_defconfig | 2 ++
> configs/C29XPCIE_NAND_defconfig | 1 +
> configs/C29XPCIE_NOR_SECBOOT_defconfig | 1 +
> configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig | 1 +
> configs/C29XPCIE_SPIFLASH_defconfig | 1 +
> configs/C29XPCIE_defconfig | 1 +
> configs/Cyrus_P5020_defconfig | 2 ++
> configs/Cyrus_P5040_defconfig | 2 ++
> configs/MPC8536DS_36BIT_defconfig | 1 +
> configs/MPC8548CDS_36BIT_defconfig | 1 +
> configs/MPC8572DS_36BIT_defconfig | 1 +
> configs/MPC8641HPCN_36BIT_defconfig | 2 ++
> configs/MPC8641HPCN_defconfig | 2 ++
> configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig | 1 +
> configs/P1010RDB-PA_36BIT_NAND_defconfig | 1 +
> configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig | 1 +
> configs/P1010RDB-PA_36BIT_NOR_defconfig | 1 +
> configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 1 +
> .../P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig | 1 +
> configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 1 +
> configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig | 1 +
> configs/P1010RDB-PB_36BIT_NAND_defconfig | 1 +
> configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig | 1 +
> configs/P1010RDB-PB_36BIT_NOR_defconfig | 1 +
> configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 1 +
> .../P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig | 1 +
> configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 1 +
> configs/P1020MBG-PC_36BIT_SDCARD_defconfig | 1 +
> configs/P1020MBG-PC_36BIT_defconfig | 1 +
> configs/P1020RDB-PC_36BIT_NAND_defconfig | 1 +
> configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 1 +
> configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 +
> configs/P1020RDB-PC_36BIT_defconfig | 1 +
> configs/P1020UTM-PC_36BIT_SDCARD_defconfig | 1 +
> configs/P1020UTM-PC_36BIT_defconfig | 1 +
> configs/P1021RDB-PC_36BIT_NAND_defconfig | 1 +
> configs/P1021RDB-PC_36BIT_SDCARD_defconfig | 1 +
> configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig | 1 +
> configs/P1021RDB-PC_36BIT_defconfig | 1 +
> configs/P1022DS_36BIT_NAND_defconfig | 1 +
> configs/P1022DS_36BIT_SDCARD_defconfig | 1 +
> configs/P1022DS_36BIT_SPIFLASH_defconfig | 1 +
> configs/P1022DS_36BIT_defconfig | 1 +
> configs/P1024RDB_36BIT_defconfig | 1 +
> configs/P1025RDB_36BIT_defconfig | 1 +
> configs/P2020RDB-PC_36BIT_NAND_defconfig | 1 +
> configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 1 +
> configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 1 +
> configs/P2020RDB-PC_36BIT_defconfig | 1 +
> configs/P2041RDB_NAND_defconfig | 2 ++
> configs/P2041RDB_SDCARD_defconfig | 2 ++
> configs/P2041RDB_SECURE_BOOT_defconfig | 2 ++
> configs/P2041RDB_SPIFLASH_defconfig | 2 ++
> configs/P2041RDB_SRIO_PCIE_BOOT_defconfig | 2 ++
> configs/P2041RDB_defconfig | 2 ++
> configs/P3041DS_NAND_SECURE_BOOT_defconfig | 2 ++
> configs/P3041DS_NAND_defconfig | 2 ++
> configs/P3041DS_SDCARD_defconfig | 2 ++
> configs/P3041DS_SECURE_BOOT_defconfig | 2 ++
> configs/P3041DS_SPIFLASH_defconfig | 2 ++
> configs/P3041DS_SRIO_PCIE_BOOT_defconfig | 2 ++
> configs/P3041DS_defconfig | 2 ++
> configs/P4080DS_SDCARD_defconfig | 2 ++
> configs/P4080DS_SECURE_BOOT_defconfig | 2 ++
> configs/P4080DS_SPIFLASH_defconfig | 2 ++
> configs/P4080DS_SRIO_PCIE_BOOT_defconfig | 2 ++
> configs/P4080DS_defconfig | 2 ++
> configs/P5020DS_NAND_SECURE_BOOT_defconfig | 2 ++
> configs/P5020DS_NAND_defconfig | 2 ++
> configs/P5020DS_SDCARD_defconfig | 2 ++
> configs/P5020DS_SECURE_BOOT_defconfig | 2 ++
> configs/P5020DS_SPIFLASH_defconfig | 2 ++
> configs/P5020DS_SRIO_PCIE_BOOT_defconfig | 2 ++
> configs/P5020DS_defconfig | 2 ++
> configs/P5040DS_NAND_SECURE_BOOT_defconfig | 2 ++
> configs/P5040DS_NAND_defconfig | 2 ++
> configs/P5040DS_SDCARD_defconfig | 2 ++
> configs/P5040DS_SECURE_BOOT_defconfig | 2 ++
> configs/P5040DS_SPIFLASH_defconfig | 2 ++
> configs/P5040DS_defconfig | 2 ++
> configs/T1023RDB_NAND_defconfig | 2 ++
> configs/T1023RDB_SDCARD_defconfig | 2 ++
> configs/T1023RDB_SECURE_BOOT_defconfig | 2 ++
> configs/T1023RDB_SPIFLASH_defconfig | 2 ++
> configs/T1023RDB_defconfig | 2 ++
> configs/T1024QDS_DDR4_SECURE_BOOT_defconfig | 2 ++
> configs/T1024QDS_DDR4_defconfig | 2 ++
> configs/T1024QDS_NAND_defconfig | 2 ++
> configs/T1024QDS_SDCARD_defconfig | 2 ++
> configs/T1024QDS_SECURE_BOOT_defconfig | 2 ++
> configs/T1024QDS_SPIFLASH_defconfig | 2 ++
> configs/T1024QDS_defconfig | 2 ++
> configs/T1024RDB_NAND_defconfig | 2 ++
> configs/T1024RDB_SDCARD_defconfig | 2 ++
> configs/T1024RDB_SECURE_BOOT_defconfig | 2 ++
> configs/T1024RDB_SPIFLASH_defconfig | 2 ++
> configs/T1024RDB_defconfig | 2 ++
> configs/T1040D4RDB_NAND_defconfig | 2 ++
> configs/T1040D4RDB_SDCARD_defconfig | 2 ++
> configs/T1040D4RDB_SECURE_BOOT_defconfig | 2 ++
> configs/T1040D4RDB_SPIFLASH_defconfig | 2 ++
> configs/T1040D4RDB_defconfig | 2 ++
> configs/T1040QDS_DDR4_defconfig | 2 ++
> configs/T1040QDS_SECURE_BOOT_defconfig | 2 ++
> configs/T1040QDS_defconfig | 2 ++
> configs/T1040RDB_NAND_defconfig | 2 ++
> configs/T1040RDB_SDCARD_defconfig | 2 ++
> configs/T1040RDB_SECURE_BOOT_defconfig | 2 ++
> configs/T1040RDB_SPIFLASH_defconfig | 2 ++
> configs/T1040RDB_defconfig | 2 ++
> configs/T1042D4RDB_NAND_defconfig | 2 ++
> configs/T1042D4RDB_SDCARD_defconfig | 2 ++
> configs/T1042D4RDB_SECURE_BOOT_defconfig | 2 ++
> configs/T1042D4RDB_SPIFLASH_defconfig | 2 ++
> configs/T1042D4RDB_defconfig | 2 ++
> configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig | 2 ++
> configs/T1042RDB_PI_NAND_defconfig | 2 ++
> configs/T1042RDB_PI_SDCARD_defconfig | 2 ++
> configs/T1042RDB_PI_SPIFLASH_defconfig | 2 ++
> configs/T1042RDB_PI_defconfig | 2 ++
> configs/T1042RDB_SECURE_BOOT_defconfig | 2 ++
> configs/T1042RDB_defconfig | 2 ++
> configs/T2080QDS_NAND_defconfig | 2 ++
> configs/T2080QDS_SDCARD_defconfig | 2 ++
> configs/T2080QDS_SECURE_BOOT_defconfig | 2 ++
> configs/T2080QDS_SPIFLASH_defconfig | 2 ++
> configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 2 ++
> configs/T2080QDS_defconfig | 2 ++
> configs/T2080RDB_NAND_defconfig | 2 ++
> configs/T2080RDB_SDCARD_defconfig | 2 ++
> configs/T2080RDB_SECURE_BOOT_defconfig | 2 ++
> configs/T2080RDB_SPIFLASH_defconfig | 2 ++
> configs/T2080RDB_SRIO_PCIE_BOOT_defconfig | 2 ++
> configs/T2080RDB_defconfig | 2 ++
> configs/T2081QDS_NAND_defconfig | 2 ++
> configs/T2081QDS_SDCARD_defconfig | 2 ++
> configs/T2081QDS_SPIFLASH_defconfig | 2 ++
> configs/T2081QDS_SRIO_PCIE_BOOT_defconfig | 2 ++
> configs/T2081QDS_defconfig | 2 ++
> configs/T4160QDS_NAND_defconfig | 2 ++
> configs/T4160QDS_SDCARD_defconfig | 2 ++
> configs/T4160QDS_SECURE_BOOT_defconfig | 2 ++
> configs/T4160QDS_defconfig | 2 ++
> configs/T4160RDB_defconfig | 2 ++
> configs/T4240QDS_NAND_defconfig | 2 ++
> configs/T4240QDS_SDCARD_defconfig | 2 ++
> configs/T4240QDS_SECURE_BOOT_defconfig | 2 ++
> configs/T4240QDS_SRIO_PCIE_BOOT_defconfig | 2 ++
> configs/T4240QDS_defconfig | 2 ++
> configs/T4240RDB_SDCARD_defconfig | 2 ++
> configs/T4240RDB_defconfig | 2 ++
> .../controlcenterd_36BIT_SDCARD_DEVELOP_defconfig | 1 +
> configs/controlcenterd_36BIT_SDCARD_defconfig | 1 +
> configs/kmcoge4_defconfig | 2 ++
> configs/qemu-ppce500_defconfig | 1 +
> configs/rpi_4_32b_defconfig | 11 +++++++
> drivers/mmc/bcm2835_sdhci.c | 2 +-
> include/configs/B4860QDS.h | 5 ---
> include/configs/C29XPCIE.h | 3 --
> include/configs/MPC8536DS.h | 5 ---
> include/configs/MPC8548CDS.h | 5 ---
> include/configs/MPC8572DS.h | 5 ---
> include/configs/MPC8641HPCN.h | 2 --
> include/configs/P1010RDB.h | 5 ---
> include/configs/P1022DS.h | 5 ---
> include/configs/P2041RDB.h | 5 ---
> include/configs/T102xQDS.h | 5 ---
> include/configs/T102xRDB.h | 5 ---
> include/configs/T1040QDS.h | 3 --
> include/configs/T104xRDB.h | 3 --
> include/configs/T208xQDS.h | 5 ---
> include/configs/T208xRDB.h | 5 ---
> include/configs/T4240RDB.h | 3 --
> include/configs/controlcenterd.h | 5 ---
> include/configs/corenet_ds.h | 5 ---
> include/configs/cyrus.h | 5 ---
> include/configs/kmp204x.h | 3 --
> include/configs/p1_p2_rdb_pc.h | 5 ---
> include/configs/qemu-ppce500.h | 3 --
> include/configs/t4qds.h | 3 --
> lib/Kconfig | 13 ++++++++
> scripts/config_whitelist.txt | 2 --
> 195 files changed, 385 insertions(+), 116 deletions(-)
> create mode 100644 arch/arm/include/asm/mmu.h
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v5 0/6] ARM: arbitrary virtual-physical mappings for RPi4 XHCI support
2020-06-11 8:39 ` [PATCH v5 0/6] ARM: arbitrary virtual-physical mappings for RPi4 XHCI support Matthias Brugger
@ 2020-07-09 6:33 ` Marek Szyprowski
2020-07-09 7:14 ` Matthias Brugger
0 siblings, 1 reply; 20+ messages in thread
From: Marek Szyprowski @ 2020-07-09 6:33 UTC (permalink / raw)
To: u-boot
Hi Matthias,
On 11.06.2020 10:39, Matthias Brugger wrote:
> ...
> Series looks good to me. The problem is that on RPi4 with 8 GB the USB FW get's
> loaded via the RPi FW. Nicolas provided a series which is under review right
> now. Without this series the 8 GB RPi4 won't boot. As soon as the series is
> ready I'll take all the RPi4 PCI/USB related patches into the next branch.
I've noticed that You took both required patchsets to rpi-next branch.
May I ask for taking this one too?
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v5 0/6] ARM: arbitrary virtual-physical mappings for RPi4 XHCI support
2020-07-09 6:33 ` Marek Szyprowski
@ 2020-07-09 7:14 ` Matthias Brugger
0 siblings, 0 replies; 20+ messages in thread
From: Matthias Brugger @ 2020-07-09 7:14 UTC (permalink / raw)
To: u-boot
Hi Marek,
On 09/07/2020 08:33, Marek Szyprowski wrote:
> Hi Matthias,
>
> On 11.06.2020 10:39, Matthias Brugger wrote:
>> ...
>> Series looks good to me. The problem is that on RPi4 with 8 GB the USB FW get's
>> loaded via the RPi FW. Nicolas provided a series which is under review right
>> now. Without this series the 8 GB RPi4 won't boot. As soon as the series is
>> ready I'll take all the RPi4 PCI/USB related patches into the next branch.
>
> I've noticed that You took both required patchsets to rpi-next branch.
> May I ask for taking this one too?
>
I didn't forgot that series. The thing is, that it is assigned to Tom in
patchwork, so I wanted to sync with him, if he is OK that I take the series. He
provided already his Reviewed-by tags for the parts that I was concerned about.
@Tom, is it OK if I take this series through my rpi-next branch?
Regards,
Matthias
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v5 1/6] powerpc: move ADDR_MAP to Kconfig
2020-06-03 12:43 ` [PATCH v5 1/6] powerpc: move ADDR_MAP to Kconfig Marek Szyprowski
@ 2020-07-10 20:21 ` Tom Rini
0 siblings, 0 replies; 20+ messages in thread
From: Tom Rini @ 2020-07-10 20:21 UTC (permalink / raw)
To: u-boot
On Wed, Jun 03, 2020 at 02:43:40PM +0200, Marek Szyprowski wrote:
> Move ADDR_MAP related config options from include/configs/*.h to the
> proper place in lib/Kconfig. This has been done using
> ./tools/moveconfig.py and manual inspection of the generated changes.
> This is a preparation to use ADDR_MAP helper on ARM 32bit Raspberry Pi4
> board for mapping the PCIe XHCI MMIO, which is above the 4GiB identity
> mapping limit.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
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* [PATCH v5 2/6] arm: update comments to the common style
2020-06-03 12:43 ` [PATCH v5 2/6] arm: update comments to the common style Marek Szyprowski
2020-06-03 13:55 ` Tom Rini
@ 2020-07-10 20:21 ` Tom Rini
1 sibling, 0 replies; 20+ messages in thread
From: Tom Rini @ 2020-07-10 20:21 UTC (permalink / raw)
To: u-boot
On Wed, Jun 03, 2020 at 02:43:41PM +0200, Marek Szyprowski wrote:
> Update the comments in include/asm/system.h to the common style.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v5 3/6] arm: provide a function for boards init code to modify MMU virtual-physical map
2020-06-03 12:43 ` [PATCH v5 3/6] arm: provide a function for boards init code to modify MMU virtual-physical map Marek Szyprowski
2020-06-03 13:55 ` Tom Rini
@ 2020-07-10 20:22 ` Tom Rini
2020-07-23 16:32 ` Patrick DELAUNAY
1 sibling, 1 reply; 20+ messages in thread
From: Tom Rini @ 2020-07-10 20:22 UTC (permalink / raw)
To: u-boot
On Wed, Jun 03, 2020 at 02:43:42PM +0200, Marek Szyprowski wrote:
> Provide function for setting arbitrary virtual-physical MMU mapping
> and cache settings for the given region.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v5 4/6] mmc: bcm283x: fix int to pointer cast
2020-06-03 12:43 ` [PATCH v5 4/6] mmc: bcm283x: fix int to pointer cast Marek Szyprowski
@ 2020-07-10 20:22 ` Tom Rini
0 siblings, 0 replies; 20+ messages in thread
From: Tom Rini @ 2020-07-10 20:22 UTC (permalink / raw)
To: u-boot
On Wed, Jun 03, 2020 at 02:43:43PM +0200, Marek Szyprowski wrote:
> From: Seung-Woo Kim <sw0312.kim@samsung.com>
>
> On build with 32 bit, there is a warning for int-to-pointer-cast.
> Fix the int to pointer cast by using uintptr_t.
>
> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Applied to u-boot/master, thanks!
--
Tom
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* [PATCH v5 5/6] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)
2020-06-03 12:43 ` [PATCH v5 5/6] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit) Marek Szyprowski
@ 2020-07-10 20:22 ` Tom Rini
0 siblings, 0 replies; 20+ messages in thread
From: Tom Rini @ 2020-07-10 20:22 UTC (permalink / raw)
To: u-boot
On Wed, Jun 03, 2020 at 02:43:44PM +0200, Marek Szyprowski wrote:
> Create a non-cacheable mapping for the 0x600000000 physical memory region,
> where MMIO registers for the PCIe XHCI controller are instantiated by the
> PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
> 32bit mode, this region is mapped at 0xff800000 CPU virtual address.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Applied to u-boot/master, thanks!
--
Tom
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* [PATCH v5 6/6] config: Enable support for the XHCI controller on RPI4 board
2020-06-03 12:43 ` [PATCH v5 6/6] config: Enable support for the XHCI controller on RPI4 board Marek Szyprowski
@ 2020-07-10 20:22 ` Tom Rini
0 siblings, 0 replies; 20+ messages in thread
From: Tom Rini @ 2020-07-10 20:22 UTC (permalink / raw)
To: u-boot
On Wed, Jun 03, 2020 at 02:43:45PM +0200, Marek Szyprowski wrote:
> This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI
> and USB commands. To get it working one has to call the following commands:
> "pci enum; usb start;", thus such commands have been added to the default
> "preboot" environment variable. One has to update their environment if it
> is already configured to get this feature working out of the box.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v5 3/6] arm: provide a function for boards init code to modify MMU virtual-physical map
2020-07-10 20:22 ` Tom Rini
@ 2020-07-23 16:32 ` Patrick DELAUNAY
2020-08-03 12:32 ` Marek Szyprowski
0 siblings, 1 reply; 20+ messages in thread
From: Patrick DELAUNAY @ 2020-07-23 16:32 UTC (permalink / raw)
To: u-boot
Hi Marek,
> From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Tom Rini
> Sent: vendredi 10 juillet 2020 22:22
>
> On Wed, Jun 03, 2020 at 02:43:42PM +0200, Marek Szyprowski wrote:
>
> > Provide function for setting arbitrary virtual-physical MMU mapping
> > and cache settings for the given region.
> >
> > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> > Reviewed-by: Tom Rini <trini@konsulko.com>
>
> Applied to u-boot/master, thanks!
For information, this patch break the SPL boot on stm32mp1 platform in master branch.
It is linked to commit 7e8471cae5c6614c54b9cfae2746d7299bd47a0c
("arm: stm32mp: activate data cache in SPL and before relocation")
For the lines:
+ mmu_set_region_dcache_behaviour(STM32_SYSRAM_BASE,
+ STM32_SYSRAM_SIZE,
+ DCACHE_DEFAULT_OPTION);
In this patch, the STM32MP15x activate the DACACHE on SYSRAM with:
#define STM32_SYSRAM_BASE 0x2FFC0000
#define STM32_SYSRAM_SIZE SZ_256K
Even is this address is not MMU_SECTION_SIZE aligned, the configuration of the MMU
section was correctly aligned in set_section_dcache
- value |= ((u32)section << MMU_SECTION_SHIFT);
With caller :
void mmu_set_region_dcache_behaviour (
.....
/* div by 2 before start + size to avoid phys_addr_t overflow */
end = ALIGN((start / 2) + (size / 2), MMU_SECTION_SIZE / 2)
>> (MMU_SECTION_SHIFT - 1);
start = start >> MMU_SECTION_SHIFT;
....
- for (upto = start; upto < end; upto++)
- set_section_dcache(upto, option);
But today it it no more the case when the start address is not MMU_SIZE aligned.
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
enum dcache_option option)
{
mmu_set_region_dcache_behaviour_phys(start, start, size, option);
}
'start' parameter is directly used in 'phys' address in the next function:
void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys,
size_t size, enum dcache_option option)
{
.....
for (upto = start; upto < end; upto++, phys += MMU_SECTION_SIZE)
set_section_phys(upto, phys, option);
and then
static void set_section_phys(int section, phys_addr_t phys,
enum dcache_option option)
{
....
/* Add the page offset */
value |= phys;
So today I can solve my issue, if I align the section in my code:
if (IS_ENABLED(CONFIG_SPL_BUILD))
- mmu_set_region_dcache_behaviour(STM32_SYSRAM_BASE,
- STM32_SYSRAM_SIZE,
- DCACHE_DEFAULT_OPTION);
+ mmu_set_region_dcache_behaviour(
+ ALIGN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE),
+ round_up(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE),
+ DCACHE_DEFAULT_OPTION);
else
But I just concerned that this lib behavior is really unexpected: need to provided MMU_SIZE aligned
start address when mmu_set_region_dcache_behaviour is called.
Do you think we need to restore the previous behavior of the cp15 function mmu_set_region_dcache_behaviour() ?
=> internally aligned DACHE region on MMU_SECTION_SIZE when parameters, start or size, are not aligned.
See also explanation for other use case, and start / end / size usage
http://patchwork.ozlabs.org/project/uboot/patch/20200424201957.v2.3.Ic2c7c6923035711a4c653d52ae7c0f57ca6f9210 at changeid/
> --
> Tom
Regards
Patrick
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v5 3/6] arm: provide a function for boards init code to modify MMU virtual-physical map
2020-07-23 16:32 ` Patrick DELAUNAY
@ 2020-08-03 12:32 ` Marek Szyprowski
0 siblings, 0 replies; 20+ messages in thread
From: Marek Szyprowski @ 2020-08-03 12:32 UTC (permalink / raw)
To: u-boot
Hi Patrick,
On 23.07.2020 18:32, Patrick DELAUNAY wrote:
> Hi Marek,
>
>> From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Tom Rini
>> Sent: vendredi 10 juillet 2020 22:22
>>
>> On Wed, Jun 03, 2020 at 02:43:42PM +0200, Marek Szyprowski wrote:
>>
>>> Provide function for setting arbitrary virtual-physical MMU mapping
>>> and cache settings for the given region.
>>>
>>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>>> Reviewed-by: Tom Rini <trini@konsulko.com>
>> Applied to u-boot/master, thanks!
> For information, this patch break the SPL boot on stm32mp1 platform in master branch.
>
> It is linked to commit 7e8471cae5c6614c54b9cfae2746d7299bd47a0c
> ("arm: stm32mp: activate data cache in SPL and before relocation")
>
> For the lines:
>
> + mmu_set_region_dcache_behaviour(STM32_SYSRAM_BASE,
> + STM32_SYSRAM_SIZE,
> + DCACHE_DEFAULT_OPTION);
>
> In this patch, the STM32MP15x activate the DACACHE on SYSRAM with:
>
> #define STM32_SYSRAM_BASE 0x2FFC0000
> #define STM32_SYSRAM_SIZE SZ_256K
>
> Even is this address is not MMU_SECTION_SIZE aligned, the configuration of the MMU
> section was correctly aligned in set_section_dcache
>
> - value |= ((u32)section << MMU_SECTION_SHIFT);
>
> With caller :
>
> void mmu_set_region_dcache_behaviour (
> .....
> /* div by 2 before start + size to avoid phys_addr_t overflow */
> end = ALIGN((start / 2) + (size / 2), MMU_SECTION_SIZE / 2)
> >> (MMU_SECTION_SHIFT - 1);
> start = start >> MMU_SECTION_SHIFT;
> ....
> - for (upto = start; upto < end; upto++)
> - set_section_dcache(upto, option);
>
>
> But today it it no more the case when the start address is not MMU_SIZE aligned.
>
> void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
> enum dcache_option option)
> {
> mmu_set_region_dcache_behaviour_phys(start, start, size, option);
> }
>
> 'start' parameter is directly used in 'phys' address in the next function:
>
> void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys,
> size_t size, enum dcache_option option)
> {
> .....
> for (upto = start; upto < end; upto++, phys += MMU_SECTION_SIZE)
> set_section_phys(upto, phys, option);
>
>
> and then
>
> static void set_section_phys(int section, phys_addr_t phys,
> enum dcache_option option)
> {
> ....
>
> /* Add the page offset */
> value |= phys;
>
>
> So today I can solve my issue, if I align the section in my code:
>
> if (IS_ENABLED(CONFIG_SPL_BUILD))
> - mmu_set_region_dcache_behaviour(STM32_SYSRAM_BASE,
> - STM32_SYSRAM_SIZE,
> - DCACHE_DEFAULT_OPTION);
> + mmu_set_region_dcache_behaviour(
> + ALIGN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE),
> + round_up(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE),
> + DCACHE_DEFAULT_OPTION);
> else
>
> But I just concerned that this lib behavior is really unexpected: need to provided MMU_SIZE aligned
> start address when mmu_set_region_dcache_behaviour is called.
>
> Do you think we need to restore the previous behavior of the cp15 function mmu_set_region_dcache_behaviour() ?
> => internally aligned DACHE region on MMU_SECTION_SIZE when parameters, start or size, are not aligned.
>
> See also explanation for other use case, and start / end / size usage
> http://patchwork.ozlabs.org/project/uboot/patch/20200424201957.v2.3.Ic2c7c6923035711a4c653d52ae7c0f57ca6f9210 at changeid/
I'm sorry for breaking your setup. However IMHO the caller should ensure
that the parameters are correctly aligned. The old behavior modified
cache parameters on the larger area of the memory than the called
wanted, what might lead to some side-effects. I would prefer aligning
parameters in the callers and maybe add some comment to the function
description that it assumes that the parameters are properly aligned.
Adding a check for the proper alignment is a bit useless, because
usually this function is called so early, that no message can be printed.
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2020-08-03 12:32 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <CGME20200603124402eucas1p16e3f9864e02f863656b8640f14255fb9@eucas1p1.samsung.com>
2020-06-03 12:43 ` [PATCH v5 0/6] ARM: arbitrary virtual-physical mappings for RPi4 XHCI support Marek Szyprowski
[not found] ` <CGME20200603124404eucas1p1aef17d34805c41ba3fc8ac7d7adbd9c7@eucas1p1.samsung.com>
2020-06-03 12:43 ` [PATCH v5 1/6] powerpc: move ADDR_MAP to Kconfig Marek Szyprowski
2020-07-10 20:21 ` Tom Rini
[not found] ` <CGME20200603124405eucas1p22471280b162f8d0e1a863b2c48f122f4@eucas1p2.samsung.com>
2020-06-03 12:43 ` [PATCH v5 2/6] arm: update comments to the common style Marek Szyprowski
2020-06-03 13:55 ` Tom Rini
2020-07-10 20:21 ` Tom Rini
[not found] ` <CGME20200603124405eucas1p18b8d5eb55cac3bf2b17b0309304947c1@eucas1p1.samsung.com>
2020-06-03 12:43 ` [PATCH v5 3/6] arm: provide a function for boards init code to modify MMU virtual-physical map Marek Szyprowski
2020-06-03 13:55 ` Tom Rini
2020-07-10 20:22 ` Tom Rini
2020-07-23 16:32 ` Patrick DELAUNAY
2020-08-03 12:32 ` Marek Szyprowski
[not found] ` <CGME20200603124406eucas1p1b628068324987ed59576fae97bf2833a@eucas1p1.samsung.com>
2020-06-03 12:43 ` [PATCH v5 4/6] mmc: bcm283x: fix int to pointer cast Marek Szyprowski
2020-07-10 20:22 ` Tom Rini
[not found] ` <CGME20200603124407eucas1p1a343fda06c124089af99d1bfdbfcf657@eucas1p1.samsung.com>
2020-06-03 12:43 ` [PATCH v5 5/6] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit) Marek Szyprowski
2020-07-10 20:22 ` Tom Rini
[not found] ` <CGME20200603124407eucas1p29bd0c3b02952deb6c58037c0b10f57b7@eucas1p2.samsung.com>
2020-06-03 12:43 ` [PATCH v5 6/6] config: Enable support for the XHCI controller on RPI4 board Marek Szyprowski
2020-07-10 20:22 ` Tom Rini
2020-06-11 8:39 ` [PATCH v5 0/6] ARM: arbitrary virtual-physical mappings for RPi4 XHCI support Matthias Brugger
2020-07-09 6:33 ` Marek Szyprowski
2020-07-09 7:14 ` Matthias Brugger
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