From: Joerg Roedel <joro@8bytes.org> To: x86@kernel.org Cc: Joerg Roedel <joro@8bytes.org>, Joerg Roedel <jroedel@suse.de>, hpa@zytor.com, Andy Lutomirski <luto@kernel.org>, Dave Hansen <dave.hansen@linux.intel.com>, Peter Zijlstra <peterz@infradead.org>, Jiri Slaby <jslaby@suse.cz>, Dan Williams <dan.j.williams@intel.com>, Tom Lendacky <thomas.lendacky@amd.com>, Juergen Gross <jgross@suse.com>, Kees Cook <keescook@chromium.org>, David Rientjes <rientjes@google.com>, Cfir Cohen <cfir@google.com>, Erdem Aktas <erdemaktas@google.com>, Masami Hiramatsu <mhiramat@kernel.org>, Mike Stunes <mstunes@vmware.com>, Sean Christopherson <sean.j.christopherson@intel.com>, Martin Radev <martin.b.radev@gmail.com>, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, virtualization@lists.linux-foundation.org Subject: [PATCH v4 12/75] x86/boot/compressed/64: Add IDT Infrastructure Date: Tue, 14 Jul 2020 14:08:14 +0200 [thread overview] Message-ID: <20200714120917.11253-13-joro@8bytes.org> (raw) In-Reply-To: <20200714120917.11253-1-joro@8bytes.org> From: Joerg Roedel <jroedel@suse.de> Add code needed to setup an IDT in the early pre-decompression boot-code. The IDT is loaded first in startup_64, which is after EfiExitBootServices() has been called, and later reloaded when the kernel image has been relocated to the end of the decompression area. This allows to setup different IDT handlers before and after the relocation. Signed-off-by: Joerg Roedel <jroedel@suse.de> --- arch/x86/boot/compressed/Makefile | 1 + arch/x86/boot/compressed/head_64.S | 25 +++++++- arch/x86/boot/compressed/idt_64.c | 44 ++++++++++++++ arch/x86/boot/compressed/idt_handlers_64.S | 70 ++++++++++++++++++++++ arch/x86/boot/compressed/misc.h | 5 ++ arch/x86/include/asm/desc_defs.h | 3 + 6 files changed, 147 insertions(+), 1 deletion(-) create mode 100644 arch/x86/boot/compressed/idt_64.c create mode 100644 arch/x86/boot/compressed/idt_handlers_64.S diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/Makefile index 95ac85b8ef27..46928cb90d19 100644 --- a/arch/x86/boot/compressed/Makefile +++ b/arch/x86/boot/compressed/Makefile @@ -84,6 +84,7 @@ vmlinux-objs-$(CONFIG_EARLY_PRINTK) += $(obj)/early_serial_console.o vmlinux-objs-$(CONFIG_RANDOMIZE_BASE) += $(obj)/kaslr.o ifdef CONFIG_X86_64 vmlinux-objs-$(CONFIG_RANDOMIZE_BASE) += $(obj)/kaslr_64.o + vmlinux-objs-y += $(obj)/idt_64.o $(obj)/idt_handlers_64.o vmlinux-objs-y += $(obj)/mem_encrypt.o vmlinux-objs-y += $(obj)/pgtable_64.o endif diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S index 97d37f0a34f5..4174d2f97b29 100644 --- a/arch/x86/boot/compressed/head_64.S +++ b/arch/x86/boot/compressed/head_64.S @@ -33,6 +33,7 @@ #include <asm/processor-flags.h> #include <asm/asm-offsets.h> #include <asm/bootparam.h> +#include <asm/desc_defs.h> #include "pgtable.h" /* @@ -410,6 +411,10 @@ SYM_CODE_START(startup_64) .Lon_kernel_cs: + pushq %rsi + call load_stage1_idt + popq %rsi + /* * paging_prepare() sets up the trampoline and checks if we need to * enable 5-level paging. @@ -537,6 +542,13 @@ SYM_FUNC_START_LOCAL_NOALIGN(.Lrelocated) shrq $3, %rcx rep stosq +/* + * Load stage2 IDT + */ + pushq %rsi + call load_stage2_idt + popq %rsi + /* * Do the extraction, and jump to the new kernel.. */ @@ -690,10 +702,21 @@ SYM_DATA_START_LOCAL(gdt) .quad 0x0000000000000000 /* TS continued */ SYM_DATA_END_LABEL(gdt, SYM_L_LOCAL, gdt_end) +SYM_DATA_START(boot_idt_desc) + .word boot_idt_end - boot_idt + .quad 0 +SYM_DATA_END(boot_idt_desc) + .balign 8 +SYM_DATA_START(boot_idt) + .rept BOOT_IDT_ENTRIES + .quad 0 + .quad 0 + .endr +SYM_DATA_END_LABEL(boot_idt, SYM_L_GLOBAL, boot_idt_end) + #ifdef CONFIG_EFI_STUB SYM_DATA(image_offset, .long 0) #endif - #ifdef CONFIG_EFI_MIXED SYM_DATA_LOCAL(efi32_boot_args, .long 0, 0, 0) SYM_DATA(efi_is64, .byte 1) diff --git a/arch/x86/boot/compressed/idt_64.c b/arch/x86/boot/compressed/idt_64.c new file mode 100644 index 000000000000..082cd6bca033 --- /dev/null +++ b/arch/x86/boot/compressed/idt_64.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include <asm/trap_pf.h> +#include <asm/segment.h> +#include <asm/trapnr.h> +#include "misc.h" + +static void set_idt_entry(int vector, void (*handler)(void)) +{ + unsigned long address = (unsigned long)handler; + gate_desc entry; + + memset(&entry, 0, sizeof(entry)); + + entry.offset_low = (u16)(address & 0xffff); + entry.segment = __KERNEL_CS; + entry.bits.type = GATE_TRAP; + entry.bits.p = 1; + entry.offset_middle = (u16)((address >> 16) & 0xffff); + entry.offset_high = (u32)(address >> 32); + + memcpy(&boot_idt[vector], &entry, sizeof(entry)); +} + +/* Have this here so we don't need to include <asm/desc.h> */ +static void load_boot_idt(const struct desc_ptr *dtr) +{ + asm volatile("lidt %0"::"m" (*dtr)); +} + +/* Setup IDT before kernel jumping to .Lrelocated */ +void load_stage1_idt(void) +{ + boot_idt_desc.address = (unsigned long)boot_idt; + + load_boot_idt(&boot_idt_desc); +} + +/* Setup IDT after kernel jumping to .Lrelocated */ +void load_stage2_idt(void) +{ + boot_idt_desc.address = (unsigned long)boot_idt; + + load_boot_idt(&boot_idt_desc); +} diff --git a/arch/x86/boot/compressed/idt_handlers_64.S b/arch/x86/boot/compressed/idt_handlers_64.S new file mode 100644 index 000000000000..36dee2f40a8b --- /dev/null +++ b/arch/x86/boot/compressed/idt_handlers_64.S @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Early IDT handler entry points + * + * Copyright (C) 2019 SUSE + * + * Author: Joerg Roedel <jroedel@suse.de> + */ + +#include <asm/segment.h> + +/* For ORIG_RAX */ +#include "../../entry/calling.h" + +.macro EXCEPTION_HANDLER name function error_code=0 +SYM_FUNC_START(\name) + + /* Build pt_regs */ + .if \error_code == 0 + pushq $0 + .endif + + pushq %rdi + pushq %rsi + pushq %rdx + pushq %rcx + pushq %rax + pushq %r8 + pushq %r9 + pushq %r10 + pushq %r11 + pushq %rbx + pushq %rbp + pushq %r12 + pushq %r13 + pushq %r14 + pushq %r15 + + /* Call handler with pt_regs */ + movq %rsp, %rdi + /* Error code is second parameter */ + movq ORIG_RAX(%rsp), %rsi + call \function + + /* Restore regs */ + popq %r15 + popq %r14 + popq %r13 + popq %r12 + popq %rbp + popq %rbx + popq %r11 + popq %r10 + popq %r9 + popq %r8 + popq %rax + popq %rcx + popq %rdx + popq %rsi + popq %rdi + + /* Remove error code and return */ + addq $8, %rsp + + iretq +SYM_FUNC_END(\name) + .endm + + .text + .code64 diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/misc.h index 726e264410ff..062ae3ae6930 100644 --- a/arch/x86/boot/compressed/misc.h +++ b/arch/x86/boot/compressed/misc.h @@ -23,6 +23,7 @@ #include <asm/page.h> #include <asm/boot.h> #include <asm/bootparam.h> +#include <asm/desc_defs.h> #define BOOT_CTYPE_H #include <linux/acpi.h> @@ -133,4 +134,8 @@ int count_immovable_mem_regions(void); static inline int count_immovable_mem_regions(void) { return 0; } #endif +/* idt_64.c */ +extern gate_desc boot_idt[BOOT_IDT_ENTRIES]; +extern struct desc_ptr boot_idt_desc; + #endif /* BOOT_COMPRESSED_MISC_H */ diff --git a/arch/x86/include/asm/desc_defs.h b/arch/x86/include/asm/desc_defs.h index a91f3b6e4f2a..5621fb3f2d1a 100644 --- a/arch/x86/include/asm/desc_defs.h +++ b/arch/x86/include/asm/desc_defs.h @@ -109,6 +109,9 @@ struct desc_ptr { #endif /* !__ASSEMBLY__ */ +/* Boot IDT definitions */ +#define BOOT_IDT_ENTRIES 32 + /* Access rights as returned by LAR */ #define AR_TYPE_RODATA (0 * (1 << 9)) #define AR_TYPE_RWDATA (1 * (1 << 9)) -- 2.27.0
WARNING: multiple messages have this Message-ID (diff)
From: Joerg Roedel <joro@8bytes.org> To: x86@kernel.org Cc: Juergen Gross <jgross@suse.com>, Tom Lendacky <thomas.lendacky@amd.com>, Joerg Roedel <jroedel@suse.de>, Mike Stunes <mstunes@vmware.com>, Kees Cook <keescook@chromium.org>, kvm@vger.kernel.org, Peter Zijlstra <peterz@infradead.org>, Cfir Cohen <cfir@google.com>, Joerg Roedel <joro@8bytes.org>, Dave Hansen <dave.hansen@linux.intel.com>, linux-kernel@vger.kernel.org, Sean Christopherson <sean.j.christopherson@intel.com>, virtualization@lists.linux-foundation.org, Martin Radev <martin.b.radev@gmail.com>, Masami Hiramatsu <mhiramat@kernel.org>, Andy Lutomirski <luto@kernel.org>, hpa@zytor.com, Erdem Aktas <erdemaktas@google.com>, David Rientjes <rientjes@google.com>, Dan Williams <dan.j.williams@intel.com>, Jiri Slaby <jslaby@suse.cz> Subject: [PATCH v4 12/75] x86/boot/compressed/64: Add IDT Infrastructure Date: Tue, 14 Jul 2020 14:08:14 +0200 [thread overview] Message-ID: <20200714120917.11253-13-joro@8bytes.org> (raw) In-Reply-To: <20200714120917.11253-1-joro@8bytes.org> From: Joerg Roedel <jroedel@suse.de> Add code needed to setup an IDT in the early pre-decompression boot-code. The IDT is loaded first in startup_64, which is after EfiExitBootServices() has been called, and later reloaded when the kernel image has been relocated to the end of the decompression area. This allows to setup different IDT handlers before and after the relocation. Signed-off-by: Joerg Roedel <jroedel@suse.de> --- arch/x86/boot/compressed/Makefile | 1 + arch/x86/boot/compressed/head_64.S | 25 +++++++- arch/x86/boot/compressed/idt_64.c | 44 ++++++++++++++ arch/x86/boot/compressed/idt_handlers_64.S | 70 ++++++++++++++++++++++ arch/x86/boot/compressed/misc.h | 5 ++ arch/x86/include/asm/desc_defs.h | 3 + 6 files changed, 147 insertions(+), 1 deletion(-) create mode 100644 arch/x86/boot/compressed/idt_64.c create mode 100644 arch/x86/boot/compressed/idt_handlers_64.S diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/Makefile index 95ac85b8ef27..46928cb90d19 100644 --- a/arch/x86/boot/compressed/Makefile +++ b/arch/x86/boot/compressed/Makefile @@ -84,6 +84,7 @@ vmlinux-objs-$(CONFIG_EARLY_PRINTK) += $(obj)/early_serial_console.o vmlinux-objs-$(CONFIG_RANDOMIZE_BASE) += $(obj)/kaslr.o ifdef CONFIG_X86_64 vmlinux-objs-$(CONFIG_RANDOMIZE_BASE) += $(obj)/kaslr_64.o + vmlinux-objs-y += $(obj)/idt_64.o $(obj)/idt_handlers_64.o vmlinux-objs-y += $(obj)/mem_encrypt.o vmlinux-objs-y += $(obj)/pgtable_64.o endif diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S index 97d37f0a34f5..4174d2f97b29 100644 --- a/arch/x86/boot/compressed/head_64.S +++ b/arch/x86/boot/compressed/head_64.S @@ -33,6 +33,7 @@ #include <asm/processor-flags.h> #include <asm/asm-offsets.h> #include <asm/bootparam.h> +#include <asm/desc_defs.h> #include "pgtable.h" /* @@ -410,6 +411,10 @@ SYM_CODE_START(startup_64) .Lon_kernel_cs: + pushq %rsi + call load_stage1_idt + popq %rsi + /* * paging_prepare() sets up the trampoline and checks if we need to * enable 5-level paging. @@ -537,6 +542,13 @@ SYM_FUNC_START_LOCAL_NOALIGN(.Lrelocated) shrq $3, %rcx rep stosq +/* + * Load stage2 IDT + */ + pushq %rsi + call load_stage2_idt + popq %rsi + /* * Do the extraction, and jump to the new kernel.. */ @@ -690,10 +702,21 @@ SYM_DATA_START_LOCAL(gdt) .quad 0x0000000000000000 /* TS continued */ SYM_DATA_END_LABEL(gdt, SYM_L_LOCAL, gdt_end) +SYM_DATA_START(boot_idt_desc) + .word boot_idt_end - boot_idt + .quad 0 +SYM_DATA_END(boot_idt_desc) + .balign 8 +SYM_DATA_START(boot_idt) + .rept BOOT_IDT_ENTRIES + .quad 0 + .quad 0 + .endr +SYM_DATA_END_LABEL(boot_idt, SYM_L_GLOBAL, boot_idt_end) + #ifdef CONFIG_EFI_STUB SYM_DATA(image_offset, .long 0) #endif - #ifdef CONFIG_EFI_MIXED SYM_DATA_LOCAL(efi32_boot_args, .long 0, 0, 0) SYM_DATA(efi_is64, .byte 1) diff --git a/arch/x86/boot/compressed/idt_64.c b/arch/x86/boot/compressed/idt_64.c new file mode 100644 index 000000000000..082cd6bca033 --- /dev/null +++ b/arch/x86/boot/compressed/idt_64.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include <asm/trap_pf.h> +#include <asm/segment.h> +#include <asm/trapnr.h> +#include "misc.h" + +static void set_idt_entry(int vector, void (*handler)(void)) +{ + unsigned long address = (unsigned long)handler; + gate_desc entry; + + memset(&entry, 0, sizeof(entry)); + + entry.offset_low = (u16)(address & 0xffff); + entry.segment = __KERNEL_CS; + entry.bits.type = GATE_TRAP; + entry.bits.p = 1; + entry.offset_middle = (u16)((address >> 16) & 0xffff); + entry.offset_high = (u32)(address >> 32); + + memcpy(&boot_idt[vector], &entry, sizeof(entry)); +} + +/* Have this here so we don't need to include <asm/desc.h> */ +static void load_boot_idt(const struct desc_ptr *dtr) +{ + asm volatile("lidt %0"::"m" (*dtr)); +} + +/* Setup IDT before kernel jumping to .Lrelocated */ +void load_stage1_idt(void) +{ + boot_idt_desc.address = (unsigned long)boot_idt; + + load_boot_idt(&boot_idt_desc); +} + +/* Setup IDT after kernel jumping to .Lrelocated */ +void load_stage2_idt(void) +{ + boot_idt_desc.address = (unsigned long)boot_idt; + + load_boot_idt(&boot_idt_desc); +} diff --git a/arch/x86/boot/compressed/idt_handlers_64.S b/arch/x86/boot/compressed/idt_handlers_64.S new file mode 100644 index 000000000000..36dee2f40a8b --- /dev/null +++ b/arch/x86/boot/compressed/idt_handlers_64.S @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Early IDT handler entry points + * + * Copyright (C) 2019 SUSE + * + * Author: Joerg Roedel <jroedel@suse.de> + */ + +#include <asm/segment.h> + +/* For ORIG_RAX */ +#include "../../entry/calling.h" + +.macro EXCEPTION_HANDLER name function error_code=0 +SYM_FUNC_START(\name) + + /* Build pt_regs */ + .if \error_code == 0 + pushq $0 + .endif + + pushq %rdi + pushq %rsi + pushq %rdx + pushq %rcx + pushq %rax + pushq %r8 + pushq %r9 + pushq %r10 + pushq %r11 + pushq %rbx + pushq %rbp + pushq %r12 + pushq %r13 + pushq %r14 + pushq %r15 + + /* Call handler with pt_regs */ + movq %rsp, %rdi + /* Error code is second parameter */ + movq ORIG_RAX(%rsp), %rsi + call \function + + /* Restore regs */ + popq %r15 + popq %r14 + popq %r13 + popq %r12 + popq %rbp + popq %rbx + popq %r11 + popq %r10 + popq %r9 + popq %r8 + popq %rax + popq %rcx + popq %rdx + popq %rsi + popq %rdi + + /* Remove error code and return */ + addq $8, %rsp + + iretq +SYM_FUNC_END(\name) + .endm + + .text + .code64 diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/misc.h index 726e264410ff..062ae3ae6930 100644 --- a/arch/x86/boot/compressed/misc.h +++ b/arch/x86/boot/compressed/misc.h @@ -23,6 +23,7 @@ #include <asm/page.h> #include <asm/boot.h> #include <asm/bootparam.h> +#include <asm/desc_defs.h> #define BOOT_CTYPE_H #include <linux/acpi.h> @@ -133,4 +134,8 @@ int count_immovable_mem_regions(void); static inline int count_immovable_mem_regions(void) { return 0; } #endif +/* idt_64.c */ +extern gate_desc boot_idt[BOOT_IDT_ENTRIES]; +extern struct desc_ptr boot_idt_desc; + #endif /* BOOT_COMPRESSED_MISC_H */ diff --git a/arch/x86/include/asm/desc_defs.h b/arch/x86/include/asm/desc_defs.h index a91f3b6e4f2a..5621fb3f2d1a 100644 --- a/arch/x86/include/asm/desc_defs.h +++ b/arch/x86/include/asm/desc_defs.h @@ -109,6 +109,9 @@ struct desc_ptr { #endif /* !__ASSEMBLY__ */ +/* Boot IDT definitions */ +#define BOOT_IDT_ENTRIES 32 + /* Access rights as returned by LAR */ #define AR_TYPE_RODATA (0 * (1 << 9)) #define AR_TYPE_RWDATA (1 * (1 << 9)) -- 2.27.0
next prev parent reply other threads:[~2020-07-14 12:17 UTC|newest] Thread overview: 165+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-07-14 12:08 [PATCH v4 00/75] x86: SEV-ES Guest Support Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 01/75] KVM: SVM: Add GHCB definitions Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 02/75] KVM: SVM: Add GHCB Accessor functions Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 03/75] KVM: SVM: Use __packed shorthand Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 04/75] x86/cpufeatures: Add SEV-ES CPU feature Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 05/75] x86/traps: Move pf error codes to <asm/trap_pf.h> Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 06/75] x86/insn: Make inat-tables.c suitable for pre-decompression code Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-17 13:58 ` Masami Hiramatsu 2020-07-14 12:08 ` [PATCH v4 07/75] x86/umip: Factor out instruction fetch Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 08/75] x86/umip: Factor out instruction decoding Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 09/75] x86/insn: Add insn_get_modrm_reg_off() Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 10/75] x86/insn: Add insn_has_rep_prefix() helper Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-17 14:06 ` Masami Hiramatsu 2020-07-14 12:08 ` [PATCH v4 11/75] x86/boot/compressed/64: Disable red-zone usage Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel [this message] 2020-07-14 12:08 ` [PATCH v4 12/75] x86/boot/compressed/64: Add IDT Infrastructure Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 13/75] x86/boot/compressed/64: Rename kaslr_64.c to ident_map_64.c Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-15 1:23 ` Kees Cook 2020-07-15 1:23 ` Kees Cook 2020-07-14 12:08 ` [PATCH v4 14/75] x86/boot/compressed/64: Add page-fault handler Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-15 1:24 ` Kees Cook 2020-07-14 12:08 ` [PATCH v4 15/75] x86/boot/compressed/64: Always switch to own page-table Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-15 1:23 ` Kees Cook 2020-07-14 12:08 ` [PATCH v4 16/75] x86/boot/compressed/64: Don't pre-map memory in KASLR code Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-15 1:24 ` Kees Cook 2020-07-14 12:08 ` [PATCH v4 17/75] x86/boot/compressed/64: Change add_identity_map() to take start and end Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-15 1:24 ` Kees Cook 2020-07-14 12:08 ` [PATCH v4 18/75] x86/boot/compressed/64: Add stage1 #VC handler Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 19/75] x86/boot/compressed/64: Call set_sev_encryption_mask earlier Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 20/75] x86/boot/compressed/64: Check return value of kernel_ident_mapping_init() Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 21/75] x86/boot/compressed/64: Add set_page_en/decrypted() helpers Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 22/75] x86/boot/compressed/64: Setup GHCB Based VC Exception handler Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 23/75] x86/boot/compressed/64: Unmap GHCB page before booting the kernel Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 24/75] x86/sev-es: Add support for handling IOIO exceptions Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 25/75] x86/fpu: Move xgetbv()/xsetbv() into separate header Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 26/75] x86/sev-es: Add CPUID handling to #VC handler Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 27/75] x86/idt: Move IDT to data segment Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-15 1:25 ` Kees Cook 2020-07-14 12:08 ` [PATCH v4 28/75] x86/idt: Split idt_data setup out of set_intr_gate() Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-15 1:26 ` Kees Cook 2020-07-14 12:08 ` [PATCH v4 29/75] x86/idt: Move two function from k/idt.c to i/a/desc.h Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-15 1:29 ` Kees Cook 2020-07-14 12:08 ` [PATCH v4 30/75] x86/head/64: Install boot GDT Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 31/75] x86/head/64: Reload GDT after switch to virtual addresses Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 32/75] x86/head/64: Load segment registers earlier Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 33/75] x86/head/64: Switch to initial stack earlier Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 34/75] x86/head/64: Build k/head64.c with -fno-stack-protector Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-15 1:34 ` Kees Cook 2020-07-15 1:34 ` Kees Cook 2020-07-15 16:34 ` Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 35/75] x86/head/64: Load IDT earlier Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 36/75] x86/head/64: Move early exception dispatch to C code Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 37/75] x86/sev-es: Add SEV-ES Feature Detection Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 38/75] x86/sev-es: Print SEV-ES info into kernel log Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 39/75] x86/sev-es: Compile early handler code into kernel image Joerg Roedel 2020-07-14 12:08 ` Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 40/75] x86/sev-es: Setup early #VC handler Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 41/75] x86/sev-es: Setup GHCB based boot " Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 42/75] x86/sev-es: Setup per-cpu GHCBs for the runtime handler Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 43/75] x86/sev-es: Allocate and Map stacks for #VC handler Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 44/75] x86/sev-es: Allocate and setup IST entry for #VC Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 45/75] x86/sev-es: Adjust #VC IST Stack on entering NMI handler Joerg Roedel 2020-07-15 9:47 ` Peter Zijlstra 2020-07-15 10:26 ` Joerg Roedel 2020-07-15 10:56 ` Peter Zijlstra 2020-07-15 10:56 ` Peter Zijlstra 2020-07-14 12:08 ` [PATCH v4 46/75] x86/dumpstack/64: Add noinstr version of get_stack_info() Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 47/75] x86/entry/64: Add entry code for #VC handler Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 48/75] x86/sev-es: Add Runtime #VC Exception Handler Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 49/75] x86/sev-es: Wire up existing #VC exit-code handlers Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 50/75] x86/sev-es: Handle instruction fetches from user-space Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 51/75] x86/sev-es: Handle MMIO events Joerg Roedel 2020-07-21 21:01 ` Mike Stunes 2020-07-21 21:01 ` Mike Stunes 2020-07-22 7:55 ` Joerg Roedel 2020-07-22 7:55 ` Joerg Roedel 2020-07-22 8:05 ` Joerg Roedel 2020-07-22 8:05 ` Joerg Roedel 2020-07-22 22:53 ` Mike Stunes 2020-07-22 22:53 ` Mike Stunes 2020-07-23 7:21 ` Joerg Roedel 2020-07-23 7:21 ` Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 52/75] x86/sev-es: Handle MMIO String Instructions Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 53/75] x86/sev-es: Handle MSR events Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 54/75] x86/sev-es: Handle DR7 read/write events Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 55/75] x86/sev-es: Handle WBINVD Events Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 56/75] x86/sev-es: Handle RDTSC(P) Events Joerg Roedel 2020-07-14 12:08 ` [PATCH v4 57/75] x86/sev-es: Handle RDPMC Events Joerg Roedel 2020-07-14 12:09 ` [PATCH v4 58/75] x86/sev-es: Handle INVD Events Joerg Roedel 2020-07-14 12:09 ` [PATCH v4 59/75] x86/sev-es: Handle MONITOR/MONITORX Events Joerg Roedel 2020-07-14 12:09 ` [PATCH v4 60/75] x86/sev-es: Handle MWAIT/MWAITX Events Joerg Roedel 2020-07-14 12:09 ` [PATCH v4 61/75] x86/sev-es: Handle VMMCALL Events Joerg Roedel 2020-07-14 12:09 ` [PATCH v4 62/75] x86/sev-es: Handle #AC Events Joerg Roedel 2020-07-14 12:09 ` [PATCH v4 63/75] x86/sev-es: Handle #DB Events Joerg Roedel 2020-07-15 8:47 ` Peter Zijlstra 2020-07-15 8:47 ` Peter Zijlstra 2020-07-15 9:13 ` Joerg Roedel 2020-07-15 9:51 ` Peter Zijlstra 2020-07-15 9:51 ` Peter Zijlstra 2020-07-15 10:08 ` Joerg Roedel 2020-07-15 10:13 ` Peter Zijlstra 2020-07-15 10:13 ` Peter Zijlstra 2020-07-15 10:31 ` Joerg Roedel 2020-07-14 12:09 ` [PATCH v4 64/75] x86/paravirt: Allow hypervisor specific VMMCALL handling under SEV-ES Joerg Roedel 2020-07-14 12:09 ` [PATCH v4 65/75] x86/kvm: Add KVM " Joerg Roedel 2020-07-14 12:09 ` [PATCH v4 66/75] x86/vmware: Add VMware specific handling for VMMCALL " Joerg Roedel 2020-07-14 12:09 ` Joerg Roedel 2020-07-14 12:09 ` [PATCH v4 67/75] x86/realmode: Add SEV-ES specific trampoline entry point Joerg Roedel 2020-07-14 12:09 ` [PATCH v4 68/75] x86/realmode: Setup AP jump table Joerg Roedel 2020-07-14 12:09 ` [PATCH v4 69/75] x86/head/64: Setup TSS early for secondary CPUs Joerg Roedel 2020-07-14 12:09 ` [PATCH v4 70/75] x86/head/64: Don't call verify_cpu() on starting APs Joerg Roedel 2020-07-15 1:40 ` Kees Cook 2020-07-15 9:26 ` Joerg Roedel 2020-07-15 15:26 ` Kees Cook 2020-07-15 15:48 ` Joerg Roedel 2020-07-15 19:49 ` Kees Cook 2020-07-20 15:29 ` Joerg Roedel 2020-07-14 12:09 ` [PATCH v4 71/75] x86/head/64: Rename start_cpu0 Joerg Roedel 2020-07-14 12:09 ` [PATCH v4 72/75] x86/sev-es: Support CPU offline/online Joerg Roedel 2020-07-14 12:09 ` [PATCH v4 73/75] x86/sev-es: Handle NMI State Joerg Roedel 2020-07-14 12:09 ` [PATCH v4 74/75] x86/efi: Add GHCB mappings when SEV-ES is active Joerg Roedel 2020-07-14 12:09 ` [PATCH v4 75/75] x86/sev-es: Check required CPU features for SEV-ES Joerg Roedel 2020-07-14 18:53 ` kernel test robot 2020-07-15 9:24 ` [PATCH v4 00/75] x86: SEV-ES Guest Support Peter Zijlstra 2020-07-15 9:34 ` Joerg Roedel 2020-07-15 9:55 ` Peter Zijlstra 2020-07-15 9:55 ` Peter Zijlstra 2020-07-15 10:10 ` Joerg Roedel 2020-07-21 1:09 ` Erdem Aktas 2020-07-21 12:49 ` Joerg Roedel 2020-07-21 12:49 ` Joerg Roedel 2020-07-21 16:48 ` Erdem Aktas 2020-07-22 9:04 ` Joerg Roedel 2020-07-22 16:54 ` Erdem Aktas 2020-07-22 17:45 ` Joerg Roedel
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