* [PATCH v2 1/2] dt-bindings: Add documentation for GV11B GPU
@ 2020-07-16 14:33 ` Thierry Reding
0 siblings, 0 replies; 9+ messages in thread
From: Thierry Reding @ 2020-07-16 14:33 UTC (permalink / raw)
To: Thierry Reding
Cc: Rob Herring, Jon Hunter, Terje Bergstrom, Debarshi Dutta,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
The GV11B's device tree bindings are the same as for GP10B, though the
GPU is not completely compatible, so all that is needed is a different
compatible string.
Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
.../devicetree/bindings/gpu/nvidia,gk20a.txt | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
index f32bbba4d3bc..533edb4c3eec 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
+++ b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
@@ -6,6 +6,7 @@ Required properties:
- nvidia,gk20a
- nvidia,gm20b
- nvidia,gp10b
+ - nvidia,gv11b
- reg: Physical base address and length of the controller's registers.
Must contain two entries:
- first entry for bar0
@@ -88,3 +89,21 @@ Example for GP10B:
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
iommus = <&smmu TEGRA186_SID_GPU>;
};
+
+Example for GV11B:
+
+ gpu@17000000 {
+ compatible = "nvidia,gv11b";
+ reg = <0x17000000 0x10000000>,
+ <0x18000000 0x10000000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "stall", "nonstall";
+ clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
+ <&bpmp TEGRA194_CLK_GPU_PWR>;
+ clock-names = "gpu", "pwr";
+ resets = <&bpmp TEGRA194_RESET_GPU>;
+ reset-names = "gpu";
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
+ iommus = <&smmu TEGRA194_SID_GPU>;
+ };
--
2.27.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 1/2] dt-bindings: Add documentation for GV11B GPU
@ 2020-07-16 14:33 ` Thierry Reding
0 siblings, 0 replies; 9+ messages in thread
From: Thierry Reding @ 2020-07-16 14:33 UTC (permalink / raw)
To: Thierry Reding
Cc: devicetree, Debarshi Dutta, Terje Bergstrom, Jon Hunter,
Rob Herring, linux-tegra, linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
The GV11B's device tree bindings are the same as for GP10B, though the
GPU is not completely compatible, so all that is needed is a different
compatible string.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../devicetree/bindings/gpu/nvidia,gk20a.txt | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
index f32bbba4d3bc..533edb4c3eec 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
+++ b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
@@ -6,6 +6,7 @@ Required properties:
- nvidia,gk20a
- nvidia,gm20b
- nvidia,gp10b
+ - nvidia,gv11b
- reg: Physical base address and length of the controller's registers.
Must contain two entries:
- first entry for bar0
@@ -88,3 +89,21 @@ Example for GP10B:
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
iommus = <&smmu TEGRA186_SID_GPU>;
};
+
+Example for GV11B:
+
+ gpu@17000000 {
+ compatible = "nvidia,gv11b";
+ reg = <0x17000000 0x10000000>,
+ <0x18000000 0x10000000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "stall", "nonstall";
+ clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
+ <&bpmp TEGRA194_CLK_GPU_PWR>;
+ clock-names = "gpu", "pwr";
+ resets = <&bpmp TEGRA194_RESET_GPU>;
+ reset-names = "gpu";
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
+ iommus = <&smmu TEGRA194_SID_GPU>;
+ };
--
2.27.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 1/2] dt-bindings: Add documentation for GV11B GPU
@ 2020-07-16 14:33 ` Thierry Reding
0 siblings, 0 replies; 9+ messages in thread
From: Thierry Reding @ 2020-07-16 14:33 UTC (permalink / raw)
To: Thierry Reding
Cc: Rob Herring, Jon Hunter, Terje Bergstrom, Debarshi Dutta,
linux-tegra, devicetree, linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
The GV11B's device tree bindings are the same as for GP10B, though the
GPU is not completely compatible, so all that is needed is a different
compatible string.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../devicetree/bindings/gpu/nvidia,gk20a.txt | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
index f32bbba4d3bc..533edb4c3eec 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
+++ b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
@@ -6,6 +6,7 @@ Required properties:
- nvidia,gk20a
- nvidia,gm20b
- nvidia,gp10b
+ - nvidia,gv11b
- reg: Physical base address and length of the controller's registers.
Must contain two entries:
- first entry for bar0
@@ -88,3 +89,21 @@ Example for GP10B:
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
iommus = <&smmu TEGRA186_SID_GPU>;
};
+
+Example for GV11B:
+
+ gpu@17000000 {
+ compatible = "nvidia,gv11b";
+ reg = <0x17000000 0x10000000>,
+ <0x18000000 0x10000000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "stall", "nonstall";
+ clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
+ <&bpmp TEGRA194_CLK_GPU_PWR>;
+ clock-names = "gpu", "pwr";
+ resets = <&bpmp TEGRA194_RESET_GPU>;
+ reset-names = "gpu";
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
+ iommus = <&smmu TEGRA194_SID_GPU>;
+ };
--
2.27.0
^ permalink raw reply related [flat|nested] 9+ messages in thread[parent not found: <20200716143341.545804-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* [PATCH v2 2/2] arm64: tegra: Add the GPU on Tegra194
2020-07-16 14:33 ` Thierry Reding
(?)
@ 2020-07-16 14:33 ` Thierry Reding
-1 siblings, 0 replies; 9+ messages in thread
From: Thierry Reding @ 2020-07-16 14:33 UTC (permalink / raw)
To: Thierry Reding
Cc: Rob Herring, Jon Hunter, Terje Bergstrom, Debarshi Dutta,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
The GPU found on NVIDIA Tegra194 SoCs is a Volta generation GPU called
GV11B.
Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 33 ++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 98c366ab4aab..14da0793be69 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1395,6 +1395,39 @@ sor3: sor@15bc0000 {
nvidia,interface = <3>;
};
};
+
+ gpu@17000000 {
+ compatible = "nvidia,gv11b";
+ reg = <0x17000000 0x10000000>,
+ <0x18000000 0x10000000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "stall", "nonstall";
+ clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
+ <&bpmp TEGRA194_CLK_GPU_PWR>;
+ clock-names = "gpu", "pwr";
+ resets = <&bpmp TEGRA194_RESET_GPU>;
+ reset-names = "gpu";
+ status = "disabled";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>;
+ interconnect-names = "dma-mem", "read-0-hp", "write-0",
+ "read-1", "read-1-hp", "write-1",
+ "read-2", "read-2-hp", "write-2",
+ "read-3", "read-3-hp", "write-3";
+ };
};
pcie@14100000 {
--
2.27.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 2/2] arm64: tegra: Add the GPU on Tegra194
@ 2020-07-16 14:33 ` Thierry Reding
0 siblings, 0 replies; 9+ messages in thread
From: Thierry Reding @ 2020-07-16 14:33 UTC (permalink / raw)
To: Thierry Reding
Cc: devicetree, Debarshi Dutta, Terje Bergstrom, Jon Hunter,
Rob Herring, linux-tegra, linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
The GPU found on NVIDIA Tegra194 SoCs is a Volta generation GPU called
GV11B.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 33 ++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 98c366ab4aab..14da0793be69 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1395,6 +1395,39 @@ sor3: sor@15bc0000 {
nvidia,interface = <3>;
};
};
+
+ gpu@17000000 {
+ compatible = "nvidia,gv11b";
+ reg = <0x17000000 0x10000000>,
+ <0x18000000 0x10000000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "stall", "nonstall";
+ clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
+ <&bpmp TEGRA194_CLK_GPU_PWR>;
+ clock-names = "gpu", "pwr";
+ resets = <&bpmp TEGRA194_RESET_GPU>;
+ reset-names = "gpu";
+ status = "disabled";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>;
+ interconnect-names = "dma-mem", "read-0-hp", "write-0",
+ "read-1", "read-1-hp", "write-1",
+ "read-2", "read-2-hp", "write-2",
+ "read-3", "read-3-hp", "write-3";
+ };
};
pcie@14100000 {
--
2.27.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 2/2] arm64: tegra: Add the GPU on Tegra194
@ 2020-07-16 14:33 ` Thierry Reding
0 siblings, 0 replies; 9+ messages in thread
From: Thierry Reding @ 2020-07-16 14:33 UTC (permalink / raw)
To: Thierry Reding
Cc: Rob Herring, Jon Hunter, Terje Bergstrom, Debarshi Dutta,
linux-tegra, devicetree, linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
The GPU found on NVIDIA Tegra194 SoCs is a Volta generation GPU called
GV11B.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 33 ++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 98c366ab4aab..14da0793be69 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1395,6 +1395,39 @@ sor3: sor@15bc0000 {
nvidia,interface = <3>;
};
};
+
+ gpu@17000000 {
+ compatible = "nvidia,gv11b";
+ reg = <0x17000000 0x10000000>,
+ <0x18000000 0x10000000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "stall", "nonstall";
+ clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
+ <&bpmp TEGRA194_CLK_GPU_PWR>;
+ clock-names = "gpu", "pwr";
+ resets = <&bpmp TEGRA194_RESET_GPU>;
+ reset-names = "gpu";
+ status = "disabled";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>;
+ interconnect-names = "dma-mem", "read-0-hp", "write-0",
+ "read-1", "read-1-hp", "write-1",
+ "read-2", "read-2-hp", "write-2",
+ "read-3", "read-3-hp", "write-3";
+ };
};
pcie@14100000 {
--
2.27.0
^ permalink raw reply related [flat|nested] 9+ messages in thread[parent not found: <20200716143341.545804-2-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH v2 2/2] arm64: tegra: Add the GPU on Tegra194
2020-07-16 14:33 ` Thierry Reding
(?)
@ 2020-07-20 17:29 ` Terje Bergstrom
-1 siblings, 0 replies; 9+ messages in thread
From: Terje Bergstrom @ 2020-07-20 17:29 UTC (permalink / raw)
To: Thierry Reding
Cc: Rob Herring, Jon Hunter, Debarshi Dutta,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 7/16/2020 7:33 AM, Thierry Reding wrote:
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index 98c366ab4aab..14da0793be69 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -1395,6 +1395,39 @@ sor3: sor@15bc0000 {
> nvidia,interface = <3>;
> };
> };
> +
> + gpu@17000000 {
> + compatible = "nvidia,gv11b";
> + reg = <0x17000000 0x10000000>,
> + <0x18000000 0x10000000>;
Hi,
I noticed a typo here. The sizes of the resources have one zero too
many. Should be 0x1000000.
Terje
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v2 2/2] arm64: tegra: Add the GPU on Tegra194
@ 2020-07-20 17:29 ` Terje Bergstrom
0 siblings, 0 replies; 9+ messages in thread
From: Terje Bergstrom @ 2020-07-20 17:29 UTC (permalink / raw)
To: Thierry Reding
Cc: devicetree, Debarshi Dutta, Jon Hunter, Rob Herring, linux-tegra,
linux-arm-kernel
On 7/16/2020 7:33 AM, Thierry Reding wrote:
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index 98c366ab4aab..14da0793be69 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -1395,6 +1395,39 @@ sor3: sor@15bc0000 {
> nvidia,interface = <3>;
> };
> };
> +
> + gpu@17000000 {
> + compatible = "nvidia,gv11b";
> + reg = <0x17000000 0x10000000>,
> + <0x18000000 0x10000000>;
Hi,
I noticed a typo here. The sizes of the resources have one zero too
many. Should be 0x1000000.
Terje
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v2 2/2] arm64: tegra: Add the GPU on Tegra194
@ 2020-07-20 17:29 ` Terje Bergstrom
0 siblings, 0 replies; 9+ messages in thread
From: Terje Bergstrom @ 2020-07-20 17:29 UTC (permalink / raw)
To: Thierry Reding
Cc: Rob Herring, Jon Hunter, Debarshi Dutta, linux-tegra, devicetree,
linux-arm-kernel
On 7/16/2020 7:33 AM, Thierry Reding wrote:
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index 98c366ab4aab..14da0793be69 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -1395,6 +1395,39 @@ sor3: sor@15bc0000 {
> nvidia,interface = <3>;
> };
> };
> +
> + gpu@17000000 {
> + compatible = "nvidia,gv11b";
> + reg = <0x17000000 0x10000000>,
> + <0x18000000 0x10000000>;
Hi,
I noticed a typo here. The sizes of the resources have one zero too
many. Should be 0x1000000.
Terje
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-07-20 17:30 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-16 14:33 [PATCH v2 1/2] dt-bindings: Add documentation for GV11B GPU Thierry Reding
2020-07-16 14:33 ` Thierry Reding
2020-07-16 14:33 ` Thierry Reding
[not found] ` <20200716143341.545804-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-07-16 14:33 ` [PATCH v2 2/2] arm64: tegra: Add the GPU on Tegra194 Thierry Reding
2020-07-16 14:33 ` Thierry Reding
2020-07-16 14:33 ` Thierry Reding
[not found] ` <20200716143341.545804-2-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-07-20 17:29 ` Terje Bergstrom
2020-07-20 17:29 ` Terje Bergstrom
2020-07-20 17:29 ` Terje Bergstrom
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