* [PATCH 01/17] coresight: replicator: Use CS_AMBA_ID macro for id table
2020-07-16 17:57 [PATCH 00/17] coresight: next v5.8-rc5 Mathieu Poirier
@ 2020-07-16 17:57 ` Mathieu Poirier
2020-07-16 17:57 ` [PATCH 02/17] coresight: catu: " Mathieu Poirier
` (15 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mathieu Poirier @ 2020-07-16 17:57 UTC (permalink / raw)
To: gregkh
Cc: saiprakash.ranjan, suzuki.poulose, vulab, tingwei,
andriy.shevchenko, linux-arm-kernel, mike.leach
From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Use CS_AMBA_ID macro for dynamic replicator AMBA id table
instead of open coding.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-replicator.c | 13 +++----------
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c
index e7dc1c31d20d..c619b456f55a 100644
--- a/drivers/hwtracing/coresight/coresight-replicator.c
+++ b/drivers/hwtracing/coresight/coresight-replicator.c
@@ -348,16 +348,9 @@ static int dynamic_replicator_probe(struct amba_device *adev,
}
static const struct amba_id dynamic_replicator_ids[] = {
- {
- .id = 0x000bb909,
- .mask = 0x000fffff,
- },
- {
- /* Coresight SoC-600 */
- .id = 0x000bb9ec,
- .mask = 0x000fffff,
- },
- { 0, 0 },
+ CS_AMBA_ID(0x000bb909),
+ CS_AMBA_ID(0x000bb9ec), /* Coresight SoC-600 */
+ {},
};
static struct amba_driver dynamic_replicator_driver = {
--
2.25.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 02/17] coresight: catu: Use CS_AMBA_ID macro for id table
2020-07-16 17:57 [PATCH 00/17] coresight: next v5.8-rc5 Mathieu Poirier
2020-07-16 17:57 ` [PATCH 01/17] coresight: replicator: Use CS_AMBA_ID macro for id table Mathieu Poirier
@ 2020-07-16 17:57 ` Mathieu Poirier
2020-07-16 17:57 ` [PATCH 03/17] coresight: etm4x: Add support to skip trace unit power up Mathieu Poirier
` (14 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mathieu Poirier @ 2020-07-16 17:57 UTC (permalink / raw)
To: gregkh
Cc: saiprakash.ranjan, suzuki.poulose, vulab, tingwei,
andriy.shevchenko, linux-arm-kernel, mike.leach
From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Use CS_AMBA_ID macro for coresight catu AMBA id table
instead of open coding.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-catu.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c
index 16ebf38a9f66..1801804a7762 100644
--- a/drivers/hwtracing/coresight/coresight-catu.c
+++ b/drivers/hwtracing/coresight/coresight-catu.c
@@ -568,10 +568,7 @@ static int catu_probe(struct amba_device *adev, const struct amba_id *id)
}
static struct amba_id catu_ids[] = {
- {
- .id = 0x000bb9ee,
- .mask = 0x000fffff,
- },
+ CS_AMBA_ID(0x000bb9ee),
{},
};
--
2.25.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 03/17] coresight: etm4x: Add support to skip trace unit power up
2020-07-16 17:57 [PATCH 00/17] coresight: next v5.8-rc5 Mathieu Poirier
2020-07-16 17:57 ` [PATCH 01/17] coresight: replicator: Use CS_AMBA_ID macro for id table Mathieu Poirier
2020-07-16 17:57 ` [PATCH 02/17] coresight: catu: " Mathieu Poirier
@ 2020-07-16 17:57 ` Mathieu Poirier
2020-07-16 17:57 ` [PATCH 04/17] dt-bindings: arm: coresight: " Mathieu Poirier
` (13 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mathieu Poirier @ 2020-07-16 17:57 UTC (permalink / raw)
To: gregkh
Cc: saiprakash.ranjan, suzuki.poulose, vulab, tingwei,
andriy.shevchenko, linux-arm-kernel, mike.leach
From: Tingwei Zhang <tingwei@codeaurora.org>
On some Qualcomm Technologies Inc. SoCs like SC7180, there
exists a hardware errata where the APSS (Application Processor
SubSystem)/CPU watchdog counter is stopped when the trace unit
power up ETM register is set (TRCPDCR.PU = 1). Since the ETMs
share the same power domain as that of respective CPU cores,
they are powered on when the CPU core is powered on. So we can
skip powering up of trace unit after checking for this errata
via new property called "qcom,skip-power-up".
Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
Co-developed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etm4x.c | 27 ++++++++++++-------
drivers/hwtracing/coresight/coresight-etm4x.h | 3 +++
2 files changed, 20 insertions(+), 10 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index 0c35cd5e0d1d..2290f41f0074 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -196,12 +196,14 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0);
writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1);
- /*
- * Request to keep the trace unit powered and also
- * emulation of powerdown
- */
- writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU,
- drvdata->base + TRCPDCR);
+ if (!drvdata->skip_power_up) {
+ /*
+ * Request to keep the trace unit powered and also
+ * emulation of powerdown
+ */
+ writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) |
+ TRCPDCR_PU, drvdata->base + TRCPDCR);
+ }
/* Enable the trace unit */
writel_relaxed(1, drvdata->base + TRCPRGCTLR);
@@ -476,10 +478,12 @@ static void etm4_disable_hw(void *info)
CS_UNLOCK(drvdata->base);
- /* power can be removed from the trace unit now */
- control = readl_relaxed(drvdata->base + TRCPDCR);
- control &= ~TRCPDCR_PU;
- writel_relaxed(control, drvdata->base + TRCPDCR);
+ if (!drvdata->skip_power_up) {
+ /* power can be removed from the trace unit now */
+ control = readl_relaxed(drvdata->base + TRCPDCR);
+ control &= ~TRCPDCR_PU;
+ writel_relaxed(control, drvdata->base + TRCPDCR);
+ }
control = readl_relaxed(drvdata->base + TRCPRGCTLR);
@@ -1468,6 +1472,9 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
return -ENOMEM;
}
+ if (fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
+ drvdata->skip_power_up = true;
+
/* Validity for the resource is already checked by the AMBA core */
base = devm_ioremap_resource(dev, res);
if (IS_ERR(base))
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 4a695bf90582..72c9a55e67df 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -407,6 +407,8 @@ struct etmv4_save_state {
* @config: structure holding configuration parameters.
* @save_state: State to be preserved across power loss
* @state_needs_restore: True when there is context to restore after PM exit
+ * @skip_power_up: Indicates if an implementation can skip powering up
+ * the trace unit.
*/
struct etmv4_drvdata {
void __iomem *base;
@@ -454,6 +456,7 @@ struct etmv4_drvdata {
struct etmv4_config config;
struct etmv4_save_state *save_state;
bool state_needs_restore;
+ bool skip_power_up;
};
/* Address comparator access types */
--
2.25.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 04/17] dt-bindings: arm: coresight: Add support to skip trace unit power up
2020-07-16 17:57 [PATCH 00/17] coresight: next v5.8-rc5 Mathieu Poirier
` (2 preceding siblings ...)
2020-07-16 17:57 ` [PATCH 03/17] coresight: etm4x: Add support to skip trace unit power up Mathieu Poirier
@ 2020-07-16 17:57 ` Mathieu Poirier
2020-07-16 17:57 ` [PATCH 05/17] coresight: replicator: Reset replicator if context is lost Mathieu Poirier
` (12 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mathieu Poirier @ 2020-07-16 17:57 UTC (permalink / raw)
To: gregkh
Cc: saiprakash.ranjan, suzuki.poulose, vulab, tingwei,
andriy.shevchenko, linux-arm-kernel, mike.leach
From: Tingwei Zhang <tingwei@codeaurora.org>
Add "qcom,skip-power-up" property to identify systems which can
skip powering up of trace unit since they share the same power
domain as their CPU core. This is required to identify such
systems with hardware errata which stops the CPU watchdog counter
when the power up bit is set (TRCPDCR.PU).
Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
Co-developed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
Documentation/devicetree/bindings/arm/coresight.txt | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
index 846f6daae71b..e4b2eda0b53b 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -108,6 +108,13 @@ its hardware characteristcs.
* arm,cp14: must be present if the system accesses ETM/PTM management
registers via co-processor 14.
+ * qcom,skip-power-up: boolean. Indicates that an implementation can
+ skip powering up the trace unit. TRCPDCR.PU does not have to be set
+ on Qualcomm Technologies Inc. systems since ETMs are in the same power
+ domain as their CPU cores. This property is required to identify such
+ systems with hardware errata where the CPU watchdog counter is stopped
+ when TRCPDCR.PU is set.
+
* Optional property for TMC:
* arm,buffer-size: size of contiguous buffer space for TMC ETR
--
2.25.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 05/17] coresight: replicator: Reset replicator if context is lost
2020-07-16 17:57 [PATCH 00/17] coresight: next v5.8-rc5 Mathieu Poirier
` (3 preceding siblings ...)
2020-07-16 17:57 ` [PATCH 04/17] dt-bindings: arm: coresight: " Mathieu Poirier
@ 2020-07-16 17:57 ` Mathieu Poirier
2020-07-16 17:57 ` [PATCH 06/17] dt-bindings: arm: coresight: Add optional property to replicators Mathieu Poirier
` (11 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mathieu Poirier @ 2020-07-16 17:57 UTC (permalink / raw)
To: gregkh
Cc: saiprakash.ranjan, suzuki.poulose, vulab, tingwei,
andriy.shevchenko, linux-arm-kernel, mike.leach
From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
On some QCOM SoCs, replicators in Always-On domain loses its
context as soon as the clock is disabled. Currently as a part
of pm_runtime workqueue, clock is disabled after the replicator
is initialized by amba_pm_runtime_suspend assuming that context
is not lost which is not true for replicators with such
limitations. So add a new property "qcom,replicator-loses-context"
to identify such replicators and reset them.
Suggested-by: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
.../coresight/coresight-replicator.c | 55 +++++++++++++------
1 file changed, 38 insertions(+), 17 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c
index c619b456f55a..78acf29c49ca 100644
--- a/drivers/hwtracing/coresight/coresight-replicator.c
+++ b/drivers/hwtracing/coresight/coresight-replicator.c
@@ -14,6 +14,7 @@
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
+#include <linux/property.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/coresight.h>
@@ -32,12 +33,14 @@ DEFINE_CORESIGHT_DEVLIST(replicator_devs, "replicator");
* @atclk: optional clock for the core parts of the replicator.
* @csdev: component vitals needed by the framework
* @spinlock: serialize enable/disable operations.
+ * @check_idfilter_val: check if the context is lost upon clock removal.
*/
struct replicator_drvdata {
void __iomem *base;
struct clk *atclk;
struct coresight_device *csdev;
spinlock_t spinlock;
+ bool check_idfilter_val;
};
static void dynamic_replicator_reset(struct replicator_drvdata *drvdata)
@@ -66,29 +69,43 @@ static int dynamic_replicator_enable(struct replicator_drvdata *drvdata,
int inport, int outport)
{
int rc = 0;
- u32 reg;
-
- switch (outport) {
- case 0:
- reg = REPLICATOR_IDFILTER0;
- break;
- case 1:
- reg = REPLICATOR_IDFILTER1;
- break;
- default:
- WARN_ON(1);
- return -EINVAL;
- }
+ u32 id0val, id1val;
CS_UNLOCK(drvdata->base);
- if ((readl_relaxed(drvdata->base + REPLICATOR_IDFILTER0) == 0xff) &&
- (readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1) == 0xff))
+ id0val = readl_relaxed(drvdata->base + REPLICATOR_IDFILTER0);
+ id1val = readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1);
+
+ /*
+ * Some replicator designs lose context when AMBA clocks are removed,
+ * so have a check for this.
+ */
+ if (drvdata->check_idfilter_val && id0val == 0x0 && id1val == 0x0)
+ id0val = id1val = 0xff;
+
+ if (id0val == 0xff && id1val == 0xff)
rc = coresight_claim_device_unlocked(drvdata->base);
+ if (!rc) {
+ switch (outport) {
+ case 0:
+ id0val = 0x0;
+ break;
+ case 1:
+ id1val = 0x0;
+ break;
+ default:
+ WARN_ON(1);
+ rc = -EINVAL;
+ }
+ }
+
/* Ensure that the outport is enabled. */
- if (!rc)
- writel_relaxed(0x00, drvdata->base + reg);
+ if (!rc) {
+ writel_relaxed(id0val, drvdata->base + REPLICATOR_IDFILTER0);
+ writel_relaxed(id1val, drvdata->base + REPLICATOR_IDFILTER1);
+ }
+
CS_LOCK(drvdata->base);
return rc;
@@ -239,6 +256,10 @@ static int replicator_probe(struct device *dev, struct resource *res)
desc.groups = replicator_groups;
}
+ if (fwnode_property_present(dev_fwnode(dev),
+ "qcom,replicator-loses-context"))
+ drvdata->check_idfilter_val = true;
+
dev_set_drvdata(dev, drvdata);
pdata = coresight_get_platform_data(dev);
--
2.25.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 06/17] dt-bindings: arm: coresight: Add optional property to replicators
2020-07-16 17:57 [PATCH 00/17] coresight: next v5.8-rc5 Mathieu Poirier
` (4 preceding siblings ...)
2020-07-16 17:57 ` [PATCH 05/17] coresight: replicator: Reset replicator if context is lost Mathieu Poirier
@ 2020-07-16 17:57 ` Mathieu Poirier
2020-07-16 17:57 ` [PATCH 07/17] coresight: Use devm_kcalloc() in coresight_alloc_conns() Mathieu Poirier
` (10 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mathieu Poirier @ 2020-07-16 17:57 UTC (permalink / raw)
To: gregkh
Cc: saiprakash.ranjan, suzuki.poulose, vulab, tingwei,
andriy.shevchenko, linux-arm-kernel, mike.leach
From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Add an optional boolean property "qcom,replicator-loses-context" to
identify replicators which loses context when AMBA clocks are removed
in certain configurable replicator designs.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
Documentation/devicetree/bindings/arm/coresight.txt | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
index e4b2eda0b53b..d711676b4a51 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -128,6 +128,12 @@ its hardware characteristcs.
* interrupts : Exactly one SPI may be listed for reporting the address
error
+* Optional property for configurable replicators:
+
+ * qcom,replicator-loses-context: boolean. Indicates that the replicator
+ will lose register context when AMBA clock is removed which is observed
+ in some replicator designs.
+
Graph bindings for Coresight
-------------------------------
--
2.25.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 07/17] coresight: Use devm_kcalloc() in coresight_alloc_conns()
2020-07-16 17:57 [PATCH 00/17] coresight: next v5.8-rc5 Mathieu Poirier
` (5 preceding siblings ...)
2020-07-16 17:57 ` [PATCH 06/17] dt-bindings: arm: coresight: Add optional property to replicators Mathieu Poirier
@ 2020-07-16 17:57 ` Mathieu Poirier
2020-07-16 17:57 ` [PATCH 08/17] coresight: Drop double check for ACPI companion device Mathieu Poirier
` (9 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mathieu Poirier @ 2020-07-16 17:57 UTC (permalink / raw)
To: gregkh
Cc: saiprakash.ranjan, suzuki.poulose, vulab, tingwei,
andriy.shevchenko, linux-arm-kernel, mike.leach
From: Xu Wang <vulab@iscas.ac.cn>
A multiplication for the size determination of a memory allocation
indicated that an array data structure should be processed.
Thus use the corresponding function "devm_kcalloc".
Signed-off-by: Xu Wang <vulab@iscas.ac.cn>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-platform.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-platform.c b/drivers/hwtracing/coresight/coresight-platform.c
index e4912abda3aa..bfd44231d7ad 100644
--- a/drivers/hwtracing/coresight/coresight-platform.c
+++ b/drivers/hwtracing/coresight/coresight-platform.c
@@ -27,9 +27,8 @@ static int coresight_alloc_conns(struct device *dev,
struct coresight_platform_data *pdata)
{
if (pdata->nr_outport) {
- pdata->conns = devm_kzalloc(dev, pdata->nr_outport *
- sizeof(*pdata->conns),
- GFP_KERNEL);
+ pdata->conns = devm_kcalloc(dev, pdata->nr_outport,
+ sizeof(*pdata->conns), GFP_KERNEL);
if (!pdata->conns)
return -ENOMEM;
}
--
2.25.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 08/17] coresight: Drop double check for ACPI companion device
2020-07-16 17:57 [PATCH 00/17] coresight: next v5.8-rc5 Mathieu Poirier
` (6 preceding siblings ...)
2020-07-16 17:57 ` [PATCH 07/17] coresight: Use devm_kcalloc() in coresight_alloc_conns() Mathieu Poirier
@ 2020-07-16 17:57 ` Mathieu Poirier
2020-07-16 17:57 ` [PATCH 09/17] coresight: etmv4: Fix resource selector constant Mathieu Poirier
` (8 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mathieu Poirier @ 2020-07-16 17:57 UTC (permalink / raw)
To: gregkh
Cc: saiprakash.ranjan, suzuki.poulose, vulab, tingwei,
andriy.shevchenko, linux-arm-kernel, mike.leach
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
acpi_dev_get_resources() does perform the NULL pointer check against
ACPI companion device which is given as function parameter. Thus,
there is no need to duplicate this check in the caller.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-stm.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c
index b908ca104645..673d2f56ed1e 100644
--- a/drivers/hwtracing/coresight/coresight-stm.c
+++ b/drivers/hwtracing/coresight/coresight-stm.c
@@ -727,8 +727,6 @@ static int acpi_stm_get_stimulus_area(struct device *dev, struct resource *res)
struct acpi_device *adev = ACPI_COMPANION(dev);
- if (!adev)
- return -ENODEV;
rc = acpi_dev_get_resources(adev, &res_list, NULL, NULL);
if (rc < 0)
return rc;
--
2.25.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 09/17] coresight: etmv4: Fix resource selector constant
2020-07-16 17:57 [PATCH 00/17] coresight: next v5.8-rc5 Mathieu Poirier
` (7 preceding siblings ...)
2020-07-16 17:57 ` [PATCH 08/17] coresight: Drop double check for ACPI companion device Mathieu Poirier
@ 2020-07-16 17:57 ` Mathieu Poirier
2020-07-16 17:57 ` [PATCH 10/17] coresight: etmv4: Counter values not saved on disable Mathieu Poirier
` (7 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mathieu Poirier @ 2020-07-16 17:57 UTC (permalink / raw)
To: gregkh
Cc: saiprakash.ranjan, suzuki.poulose, vulab, tingwei,
andriy.shevchenko, linux-arm-kernel, mike.leach
From: Mike Leach <mike.leach@linaro.org>
ETMv4 max resource selector constant incorrectly set to 16. Updated to the
correct 32 value, and adjustments made to limited code using it.
Signed-off-by: Mike Leach <mike.leach@linaro.org>
Fixes: 2e1cdfe184b52 ("coresight-etm4x: Adding CoreSight ETM4x driver")
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etm4x.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 72c9a55e67df..7da022e87218 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -133,7 +133,7 @@
#define ETMv4_MAX_CTXID_CMP 8
#define ETM_MAX_VMID_CMP 8
#define ETM_MAX_PE_CMP 8
-#define ETM_MAX_RES_SEL 16
+#define ETM_MAX_RES_SEL 32
#define ETM_MAX_SS_CMP 8
#define ETM_ARCH_V4 0x40
@@ -325,7 +325,7 @@ struct etmv4_save_state {
u32 trccntctlr[ETMv4_MAX_CNTR];
u32 trccntvr[ETMv4_MAX_CNTR];
- u32 trcrsctlr[ETM_MAX_RES_SEL * 2];
+ u32 trcrsctlr[ETM_MAX_RES_SEL];
u32 trcssccr[ETM_MAX_SS_CMP];
u32 trcsscsr[ETM_MAX_SS_CMP];
--
2.25.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 10/17] coresight: etmv4: Counter values not saved on disable
2020-07-16 17:57 [PATCH 00/17] coresight: next v5.8-rc5 Mathieu Poirier
` (8 preceding siblings ...)
2020-07-16 17:57 ` [PATCH 09/17] coresight: etmv4: Fix resource selector constant Mathieu Poirier
@ 2020-07-16 17:57 ` Mathieu Poirier
2020-07-16 17:57 ` [PATCH 11/17] coresight: Fix comment in main header file Mathieu Poirier
` (6 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mathieu Poirier @ 2020-07-16 17:57 UTC (permalink / raw)
To: gregkh
Cc: saiprakash.ranjan, suzuki.poulose, vulab, tingwei,
andriy.shevchenko, linux-arm-kernel, mike.leach
From: Mike Leach <mike.leach@linaro.org>
The counter value registers change during operation, however this change
is not reflected in the values seen by the user in sysfs.
This fixes the issue by reading back the values on disable.
Signed-off-by: Mike Leach <mike.leach@linaro.org>
Fixes: 2e1cdfe184b52 ("coresight-etm4x: Adding CoreSight ETM4x driver")
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etm4x.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index 2290f41f0074..2d732af8b3e7 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -511,6 +511,12 @@ static void etm4_disable_hw(void *info)
readl_relaxed(drvdata->base + TRCSSCSRn(i));
}
+ /* read back the current counter values */
+ for (i = 0; i < drvdata->nr_cntr; i++) {
+ config->cntr_val[i] =
+ readl_relaxed(drvdata->base + TRCCNTVRn(i));
+ }
+
coresight_disclaim_device_unlocked(drvdata->base);
CS_LOCK(drvdata->base);
--
2.25.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 11/17] coresight: Fix comment in main header file
2020-07-16 17:57 [PATCH 00/17] coresight: next v5.8-rc5 Mathieu Poirier
` (9 preceding siblings ...)
2020-07-16 17:57 ` [PATCH 10/17] coresight: etmv4: Counter values not saved on disable Mathieu Poirier
@ 2020-07-16 17:57 ` Mathieu Poirier
2020-07-16 17:57 ` [PATCH 12/17] coresight: tmc: Add shutdown callback for TMC ETR Mathieu Poirier
` (5 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mathieu Poirier @ 2020-07-16 17:57 UTC (permalink / raw)
To: gregkh
Cc: saiprakash.ranjan, suzuki.poulose, vulab, tingwei,
andriy.shevchenko, linux-arm-kernel, mike.leach
From: Mike Leach <mike.leach@linaro.org>
Comment for an elemnt in the coresight_device structure appears to have
been corrupted and makes no sense. Fix this before making further changes.
Signed-off-by: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
include/linux/coresight.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index e3e9f0e3a878..84dc695e87d4 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -179,7 +179,8 @@ struct coresight_sysfs_link {
* @enable: 'true' if component is currently part of an active path.
* @activated: 'true' only if a _sink_ has been activated. A sink can be
* activated but not yet enabled. Enabling for a _sink_
- * appens when a source has been selected for that it.
+ * happens when a source has been selected and a path is enabled
+ * from source to that sink.
* @ea: Device attribute for sink representation under PMU directory.
* @ect_dev: Associated cross trigger device. Not part of the trace data
* path or connections.
--
2.25.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 12/17] coresight: tmc: Add shutdown callback for TMC ETR
2020-07-16 17:57 [PATCH 00/17] coresight: next v5.8-rc5 Mathieu Poirier
` (10 preceding siblings ...)
2020-07-16 17:57 ` [PATCH 11/17] coresight: Fix comment in main header file Mathieu Poirier
@ 2020-07-16 17:57 ` Mathieu Poirier
2020-07-16 17:57 ` [PATCH 13/17] coresight: tmc: Fix TMC mode read in tmc_read_unprepare_etb() Mathieu Poirier
` (4 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mathieu Poirier @ 2020-07-16 17:57 UTC (permalink / raw)
To: gregkh
Cc: saiprakash.ranjan, suzuki.poulose, vulab, tingwei,
andriy.shevchenko, linux-arm-kernel, mike.leach
From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Implement a shutdown callback to ensure ETR hardware is
properly shutdown in reboot/shutdown path. This is required
for ETR which has SMMU address translation enabled like on
SC7180 SoC and few others. If the hardware is still accessing
memory after SMMU translation is disabled as part of SMMU
shutdown callback in system reboot or shutdown path, then
IOVAs(I/O virtual address) which it was using will go on the
bus as the physical addresses which might result in unknown
crashes (NoC/interconnect errors). So we make sure from this
shutdown callback that the ETR is shutdown before SMMU translation
is disabled and device_link in SMMU driver will take care of
ordering of shutdown callbacks such that SMMU shutdown callback
is not called before any of its consumer shutdown callbacks.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
.../hwtracing/coresight/coresight-tmc-etr.c | 2 +-
drivers/hwtracing/coresight/coresight-tmc.c | 23 +++++++++++++++++++
drivers/hwtracing/coresight/coresight-tmc.h | 1 +
3 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 625882bc8b08..b29c2db94d96 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1110,7 +1110,7 @@ static void __tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
}
-static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
+void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
{
__tmc_etr_disable_hw(drvdata);
/* Disable CATU device if this ETR is connected to one */
diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index 39fba1d16e6e..b13ce0daa572 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -538,6 +538,28 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
return ret;
}
+static void tmc_shutdown(struct amba_device *adev)
+{
+ unsigned long flags;
+ struct tmc_drvdata *drvdata = amba_get_drvdata(adev);
+
+ spin_lock_irqsave(&drvdata->spinlock, flags);
+
+ if (drvdata->mode == CS_MODE_DISABLED)
+ goto out;
+
+ if (drvdata->config_type == TMC_CONFIG_TYPE_ETR)
+ tmc_etr_disable_hw(drvdata);
+
+ /*
+ * We do not care about coresight unregister here unlike remove
+ * callback which is required for making coresight modular since
+ * the system is going down after this.
+ */
+out:
+ spin_unlock_irqrestore(&drvdata->spinlock, flags);
+}
+
static const struct amba_id tmc_ids[] = {
CS_AMBA_ID(0x000bb961),
/* Coresight SoC 600 TMC-ETR/ETS */
@@ -556,6 +578,7 @@ static struct amba_driver tmc_driver = {
.suppress_bind_attrs = true,
},
.probe = tmc_probe,
+ .shutdown = tmc_shutdown,
.id_table = tmc_ids,
};
builtin_amba_driver(tmc_driver);
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 71de978575f3..6e8d2dc33d17 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -268,6 +268,7 @@ ssize_t tmc_etb_get_sysfs_trace(struct tmc_drvdata *drvdata,
/* ETR functions */
int tmc_read_prepare_etr(struct tmc_drvdata *drvdata);
int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata);
+void tmc_etr_disable_hw(struct tmc_drvdata *drvdata);
extern const struct coresight_ops tmc_etr_cs_ops;
ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata,
loff_t pos, size_t len, char **bufpp);
--
2.25.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 13/17] coresight: tmc: Fix TMC mode read in tmc_read_unprepare_etb()
2020-07-16 17:57 [PATCH 00/17] coresight: next v5.8-rc5 Mathieu Poirier
` (11 preceding siblings ...)
2020-07-16 17:57 ` [PATCH 12/17] coresight: tmc: Add shutdown callback for TMC ETR Mathieu Poirier
@ 2020-07-16 17:57 ` Mathieu Poirier
2020-07-16 17:57 ` [PATCH 14/17] coresight: Add default sink selection to CoreSight base Mathieu Poirier
` (3 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mathieu Poirier @ 2020-07-16 17:57 UTC (permalink / raw)
To: gregkh
Cc: saiprakash.ranjan, suzuki.poulose, vulab, tingwei,
andriy.shevchenko, linux-arm-kernel, mike.leach
From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reading TMC mode register without proper coresight power
management can lead to exceptions like the one in the call
trace below in tmc_read_unprepare_etb() when the trace data
is read after the sink is disabled. So fix this by having
a check for coresight sysfs mode before reading TMC mode
management register in tmc_read_unprepare_etb() similar to
tmc_read_prepare_etb().
SError Interrupt on CPU6, code 0xbe000411 -- SError
pstate: 80400089 (Nzcv daIf +PAN -UAO)
pc : tmc_read_unprepare_etb+0x74/0x108
lr : tmc_read_unprepare_etb+0x54/0x108
sp : ffffff80d9507c30
x29: ffffff80d9507c30 x28: ffffff80b3569a0c
x27: 0000000000000000 x26: 00000000000a0001
x25: ffffff80cbae9550 x24: 0000000000000010
x23: ffffffd07296b0f0 x22: ffffffd0109ee028
x21: 0000000000000000 x20: ffffff80d19e70e0
x19: ffffff80d19e7080 x18: 0000000000000000
x17: 0000000000000000 x16: 0000000000000000
x15: 0000000000000000 x14: 0000000000000000
x13: 0000000000000000 x12: 0000000000000000
x11: 0000000000000000 x10: dfffffd000000001
x9 : 0000000000000000 x8 : 0000000000000002
x7 : ffffffd071d0fe78 x6 : 0000000000000000
x5 : 0000000000000080 x4 : 0000000000000001
x3 : ffffffd071d0fe98 x2 : 0000000000000000
x1 : 0000000000000004 x0 : 0000000000000001
Kernel panic - not syncing: Asynchronous SError Interrupt
Fixes: 4525412a5046 ("coresight: tmc: making prepare/unprepare functions generic")
Reported-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Tested-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index 36cce2bfb744..6375504ba8b0 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -639,15 +639,14 @@ int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata)
spin_lock_irqsave(&drvdata->spinlock, flags);
- /* There is no point in reading a TMC in HW FIFO mode */
- mode = readl_relaxed(drvdata->base + TMC_MODE);
- if (mode != TMC_MODE_CIRCULAR_BUFFER) {
- spin_unlock_irqrestore(&drvdata->spinlock, flags);
- return -EINVAL;
- }
-
/* Re-enable the TMC if need be */
if (drvdata->mode == CS_MODE_SYSFS) {
+ /* There is no point in reading a TMC in HW FIFO mode */
+ mode = readl_relaxed(drvdata->base + TMC_MODE);
+ if (mode != TMC_MODE_CIRCULAR_BUFFER) {
+ spin_unlock_irqrestore(&drvdata->spinlock, flags);
+ return -EINVAL;
+ }
/*
* The trace run will continue with the same allocated trace
* buffer. As such zero-out the buffer so that we don't end
--
2.25.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 14/17] coresight: Add default sink selection to CoreSight base
2020-07-16 17:57 [PATCH 00/17] coresight: next v5.8-rc5 Mathieu Poirier
` (12 preceding siblings ...)
2020-07-16 17:57 ` [PATCH 13/17] coresight: tmc: Fix TMC mode read in tmc_read_unprepare_etb() Mathieu Poirier
@ 2020-07-16 17:57 ` Mathieu Poirier
2020-07-16 17:57 ` [PATCH 15/17] coresight: tmc: Update sink types for default selection Mathieu Poirier
` (2 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mathieu Poirier @ 2020-07-16 17:57 UTC (permalink / raw)
To: gregkh
Cc: saiprakash.ranjan, suzuki.poulose, vulab, tingwei,
andriy.shevchenko, linux-arm-kernel, mike.leach
From: Mike Leach <mike.leach@linaro.org>
Adds a method to select a suitable sink connected to a given source.
In cases where no sink is defined, the coresight_find_default_sink
routine can search from a given source, through the child connections
until a suitable sink is found.
The suitability is defined in by the sink coresight_dev_subtype on the
CoreSight device, and the distance from the source by counting
connections.
Higher value subtype is preferred - where these are equal, shorter
distance from source is used as a tie-break.
This allows for default sink to be discovered were none is specified
(e.g. perf command line)
Signed-off-by: Mike Leach <mike.leach@linaro.org>
Suggested-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-priv.h | 2 +
drivers/hwtracing/coresight/coresight.c | 166 +++++++++++++++++++
include/linux/coresight.h | 3 +
3 files changed, 171 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
index 36c943ae94d5..f2dc625ea585 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -150,6 +150,8 @@ int coresight_enable_path(struct list_head *path, u32 mode, void *sink_data);
struct coresight_device *coresight_get_sink(struct list_head *path);
struct coresight_device *coresight_get_enabled_sink(bool reset);
struct coresight_device *coresight_get_sink_by_id(u32 id);
+struct coresight_device *
+coresight_find_default_sink(struct coresight_device *csdev);
struct list_head *coresight_build_path(struct coresight_device *csdev,
struct coresight_device *sink);
void coresight_release_path(struct list_head *path);
diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c
index f3efbb3b2b4d..e9c90f2de34a 100644
--- a/drivers/hwtracing/coresight/coresight.c
+++ b/drivers/hwtracing/coresight/coresight.c
@@ -769,6 +769,171 @@ void coresight_release_path(struct list_head *path)
path = NULL;
}
+/* return true if the device is a suitable type for a default sink */
+static inline bool coresight_is_def_sink_type(struct coresight_device *csdev)
+{
+ /* sink & correct subtype */
+ if (((csdev->type == CORESIGHT_DEV_TYPE_SINK) ||
+ (csdev->type == CORESIGHT_DEV_TYPE_LINKSINK)) &&
+ (csdev->subtype.sink_subtype >= CORESIGHT_DEV_SUBTYPE_SINK_BUFFER))
+ return true;
+ return false;
+}
+
+/**
+ * coresight_select_best_sink - return the best sink for use as default from
+ * the two provided.
+ *
+ * @sink: current best sink.
+ * @depth: search depth where current sink was found.
+ * @new_sink: new sink for comparison with current sink.
+ * @new_depth: search depth where new sink was found.
+ *
+ * Sinks prioritised according to coresight_dev_subtype_sink, with only
+ * subtypes CORESIGHT_DEV_SUBTYPE_SINK_BUFFER or higher being used.
+ *
+ * Where two sinks of equal priority are found, the sink closest to the
+ * source is used (smallest search depth).
+ *
+ * return @new_sink & update @depth if better than @sink, else return @sink.
+ */
+static struct coresight_device *
+coresight_select_best_sink(struct coresight_device *sink, int *depth,
+ struct coresight_device *new_sink, int new_depth)
+{
+ bool update = false;
+
+ if (!sink) {
+ /* first found at this level */
+ update = true;
+ } else if (new_sink->subtype.sink_subtype >
+ sink->subtype.sink_subtype) {
+ /* found better sink */
+ update = true;
+ } else if ((new_sink->subtype.sink_subtype ==
+ sink->subtype.sink_subtype) &&
+ (*depth > new_depth)) {
+ /* found same but closer sink */
+ update = true;
+ }
+
+ if (update)
+ *depth = new_depth;
+ return update ? new_sink : sink;
+}
+
+/**
+ * coresight_find_sink - recursive function to walk trace connections from
+ * source to find a suitable default sink.
+ *
+ * @csdev: source / current device to check.
+ * @depth: [in] search depth of calling dev, [out] depth of found sink.
+ *
+ * This will walk the connection path from a source (ETM) till a suitable
+ * sink is encountered and return that sink to the original caller.
+ *
+ * If current device is a plain sink return that & depth, otherwise recursively
+ * call child connections looking for a sink. Select best possible using
+ * coresight_select_best_sink.
+ *
+ * return best sink found, or NULL if not found at this node or child nodes.
+ */
+static struct coresight_device *
+coresight_find_sink(struct coresight_device *csdev, int *depth)
+{
+ int i, curr_depth = *depth + 1, found_depth = 0;
+ struct coresight_device *found_sink = NULL;
+
+ if (coresight_is_def_sink_type(csdev)) {
+ found_depth = curr_depth;
+ found_sink = csdev;
+ if (csdev->type == CORESIGHT_DEV_TYPE_SINK)
+ goto return_def_sink;
+ /* look past LINKSINK for something better */
+ }
+
+ /*
+ * Not a sink we want - or possible child sink may be better.
+ * recursively explore each port found on this element.
+ */
+ for (i = 0; i < csdev->pdata->nr_outport; i++) {
+ struct coresight_device *child_dev, *sink = NULL;
+ int child_depth = curr_depth;
+
+ child_dev = csdev->pdata->conns[i].child_dev;
+ if (child_dev)
+ sink = coresight_find_sink(child_dev, &child_depth);
+
+ if (sink)
+ found_sink = coresight_select_best_sink(found_sink,
+ &found_depth,
+ sink,
+ child_depth);
+ }
+
+return_def_sink:
+ /* return found sink and depth */
+ if (found_sink)
+ *depth = found_depth;
+ return found_sink;
+}
+
+/**
+ * coresight_find_default_sink: Find a sink suitable for use as a
+ * default sink.
+ *
+ * @csdev: starting source to find a connected sink.
+ *
+ * Walks connections graph looking for a suitable sink to enable for the
+ * supplied source. Uses CoreSight device subtypes and distance from source
+ * to select the best sink.
+ *
+ * If a sink is found, then the default sink for this device is set and
+ * will be automatically used in future.
+ *
+ * Used in cases where the CoreSight user (perf / sysfs) has not selected a
+ * sink.
+ */
+struct coresight_device *
+coresight_find_default_sink(struct coresight_device *csdev)
+{
+ int depth = 0;
+
+ /* look for a default sink if we have not found for this device */
+ if (!csdev->def_sink)
+ csdev->def_sink = coresight_find_sink(csdev, &depth);
+ return csdev->def_sink;
+}
+
+static int coresight_remove_sink_ref(struct device *dev, void *data)
+{
+ struct coresight_device *sink = data;
+ struct coresight_device *source = to_coresight_device(dev);
+
+ if (source->def_sink == sink)
+ source->def_sink = NULL;
+ return 0;
+}
+
+/**
+ * coresight_clear_default_sink: Remove all default sink references to the
+ * supplied sink.
+ *
+ * If supplied device is a sink, then check all the bus devices and clear
+ * out all the references to this sink from the coresight_device def_sink
+ * parameter.
+ *
+ * @csdev: coresight sink - remove references to this from all sources.
+ */
+static void coresight_clear_default_sink(struct coresight_device *csdev)
+{
+ if ((csdev->type == CORESIGHT_DEV_TYPE_SINK) ||
+ (csdev->type == CORESIGHT_DEV_TYPE_LINKSINK)) {
+ bus_for_each_dev(&coresight_bustype, NULL, csdev,
+ coresight_remove_sink_ref);
+ }
+}
+
/** coresight_validate_source - make sure a source has the right credentials
* @csdev: the device structure for a source.
* @function: the function this was called from.
@@ -1358,6 +1523,7 @@ void coresight_unregister(struct coresight_device *csdev)
etm_perf_del_symlink_sink(csdev);
/* Remove references of that device in the topology */
coresight_remove_conns(csdev);
+ coresight_clear_default_sink(csdev);
coresight_release_platform_data(csdev, csdev->pdata);
device_unregister(&csdev->dev);
}
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index 84dc695e87d4..58fffdecdbfd 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -48,6 +48,7 @@ enum coresight_dev_subtype_sink {
CORESIGHT_DEV_SUBTYPE_SINK_NONE,
CORESIGHT_DEV_SUBTYPE_SINK_PORT,
CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
+ CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
};
enum coresight_dev_subtype_link {
@@ -182,6 +183,7 @@ struct coresight_sysfs_link {
* happens when a source has been selected and a path is enabled
* from source to that sink.
* @ea: Device attribute for sink representation under PMU directory.
+ * @def_sink: cached reference to default sink found for this device.
* @ect_dev: Associated cross trigger device. Not part of the trace data
* path or connections.
* @nr_links: number of sysfs links created to other components from this
@@ -200,6 +202,7 @@ struct coresight_device {
/* sink specific fields */
bool activated; /* true only if a sink is part of a path */
struct dev_ext_attribute *ea;
+ struct coresight_device *def_sink;
/* cross trigger handling */
struct coresight_device *ect_dev;
/* sysfs links between components */
--
2.25.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 15/17] coresight: tmc: Update sink types for default selection
2020-07-16 17:57 [PATCH 00/17] coresight: next v5.8-rc5 Mathieu Poirier
` (13 preceding siblings ...)
2020-07-16 17:57 ` [PATCH 14/17] coresight: Add default sink selection to CoreSight base Mathieu Poirier
@ 2020-07-16 17:57 ` Mathieu Poirier
2020-07-16 17:57 ` [PATCH 16/17] coresight: etm: perf: Add default sink selection to etm perf Mathieu Poirier
2020-07-16 17:57 ` [PATCH 17/17] coresight: etm4x: Fix save/restore during cpu idle Mathieu Poirier
16 siblings, 0 replies; 18+ messages in thread
From: Mathieu Poirier @ 2020-07-16 17:57 UTC (permalink / raw)
To: gregkh
Cc: saiprakash.ranjan, suzuki.poulose, vulab, tingwei,
andriy.shevchenko, linux-arm-kernel, mike.leach
From: Mike Leach <mike.leach@linaro.org>
An additional sink subtype is added to differentiate ETB/ETF buffer
sinks and ETR type system memory sinks.
This allows the prioritised selection of default sinks.
Signed-off-by: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-tmc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index b13ce0daa572..7040d583bed9 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -484,7 +484,7 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
break;
case TMC_CONFIG_TYPE_ETR:
desc.type = CORESIGHT_DEV_TYPE_SINK;
- desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
+ desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM;
desc.ops = &tmc_etr_cs_ops;
ret = tmc_etr_setup_caps(dev, devid,
coresight_get_uci_data(id));
@@ -496,6 +496,7 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
break;
case TMC_CONFIG_TYPE_ETF:
desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
+ desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
desc.ops = &tmc_etf_cs_ops;
dev_list = &etf_devs;
--
2.25.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 16/17] coresight: etm: perf: Add default sink selection to etm perf
2020-07-16 17:57 [PATCH 00/17] coresight: next v5.8-rc5 Mathieu Poirier
` (14 preceding siblings ...)
2020-07-16 17:57 ` [PATCH 15/17] coresight: tmc: Update sink types for default selection Mathieu Poirier
@ 2020-07-16 17:57 ` Mathieu Poirier
2020-07-16 17:57 ` [PATCH 17/17] coresight: etm4x: Fix save/restore during cpu idle Mathieu Poirier
16 siblings, 0 replies; 18+ messages in thread
From: Mathieu Poirier @ 2020-07-16 17:57 UTC (permalink / raw)
To: gregkh
Cc: saiprakash.ranjan, suzuki.poulose, vulab, tingwei,
andriy.shevchenko, linux-arm-kernel, mike.leach
From: Mike Leach <mike.leach@linaro.org>
Add default sink selection to the perf trace handling in the etm driver.
Uses the select default sink infrastructure to select a sink for the perf
session, if no other sink is specified.
Signed-off-by: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
.../hwtracing/coresight/coresight-etm-perf.c | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
index 84f1dcb69827..1a3169e69bb1 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -226,9 +226,6 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
sink = coresight_get_enabled_sink(true);
}
- if (!sink)
- goto err;
-
mask = &event_data->mask;
/*
@@ -253,6 +250,16 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
continue;
}
+ /*
+ * No sink provided - look for a default sink for one of the
+ * devices. At present we only support topology where all CPUs
+ * use the same sink [N:1], so only need to find one sink. The
+ * coresight_build_path later will remove any CPU that does not
+ * attach to the sink, or if we have not found a sink.
+ */
+ if (!sink)
+ sink = coresight_find_default_sink(csdev);
+
/*
* Building a path doesn't enable it, it simply builds a
* list of devices from source to sink that can be
@@ -267,6 +274,10 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
*etm_event_cpu_path_ptr(event_data, cpu) = path;
}
+ /* no sink found for any CPU - cannot trace */
+ if (!sink)
+ goto err;
+
/* If we don't have any CPUs ready for tracing, abort */
cpu = cpumask_first(mask);
if (cpu >= nr_cpu_ids)
--
2.25.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 17/17] coresight: etm4x: Fix save/restore during cpu idle
2020-07-16 17:57 [PATCH 00/17] coresight: next v5.8-rc5 Mathieu Poirier
` (15 preceding siblings ...)
2020-07-16 17:57 ` [PATCH 16/17] coresight: etm: perf: Add default sink selection to etm perf Mathieu Poirier
@ 2020-07-16 17:57 ` Mathieu Poirier
16 siblings, 0 replies; 18+ messages in thread
From: Mathieu Poirier @ 2020-07-16 17:57 UTC (permalink / raw)
To: gregkh
Cc: saiprakash.ranjan, suzuki.poulose, vulab, tingwei,
andriy.shevchenko, linux-arm-kernel, mike.leach
From: Suzuki K Poulose <suzuki.poulose@arm.com>
The ETM state save/restore incorrectly reads/writes some of the 64bit
registers (e.g, address comparators, vmid/cid comparators etc.) using
32bit accesses. Ensure we use the appropriate width accessors for
the registers.
Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states")
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etm4x.c | 16 ++++++++--------
drivers/hwtracing/coresight/coresight-etm4x.h | 2 +-
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index 2d732af8b3e7..6d7d2169bfb2 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -1206,8 +1206,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
}
for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
- state->trcacvr[i] = readl(drvdata->base + TRCACVRn(i));
- state->trcacatr[i] = readl(drvdata->base + TRCACATRn(i));
+ state->trcacvr[i] = readq(drvdata->base + TRCACVRn(i));
+ state->trcacatr[i] = readq(drvdata->base + TRCACATRn(i));
}
/*
@@ -1218,10 +1218,10 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
*/
for (i = 0; i < drvdata->numcidc; i++)
- state->trccidcvr[i] = readl(drvdata->base + TRCCIDCVRn(i));
+ state->trccidcvr[i] = readq(drvdata->base + TRCCIDCVRn(i));
for (i = 0; i < drvdata->numvmidc; i++)
- state->trcvmidcvr[i] = readl(drvdata->base + TRCVMIDCVRn(i));
+ state->trcvmidcvr[i] = readq(drvdata->base + TRCVMIDCVRn(i));
state->trccidcctlr0 = readl(drvdata->base + TRCCIDCCTLR0);
state->trccidcctlr1 = readl(drvdata->base + TRCCIDCCTLR1);
@@ -1319,18 +1319,18 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
}
for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
- writel_relaxed(state->trcacvr[i],
+ writeq_relaxed(state->trcacvr[i],
drvdata->base + TRCACVRn(i));
- writel_relaxed(state->trcacatr[i],
+ writeq_relaxed(state->trcacatr[i],
drvdata->base + TRCACATRn(i));
}
for (i = 0; i < drvdata->numcidc; i++)
- writel_relaxed(state->trccidcvr[i],
+ writeq_relaxed(state->trccidcvr[i],
drvdata->base + TRCCIDCVRn(i));
for (i = 0; i < drvdata->numvmidc; i++)
- writel_relaxed(state->trcvmidcvr[i],
+ writeq_relaxed(state->trcvmidcvr[i],
drvdata->base + TRCVMIDCVRn(i));
writel_relaxed(state->trccidcctlr0, drvdata->base + TRCCIDCCTLR0);
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 7da022e87218..b8283e1d6d88 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -334,7 +334,7 @@ struct etmv4_save_state {
u64 trcacvr[ETM_MAX_SINGLE_ADDR_CMP];
u64 trcacatr[ETM_MAX_SINGLE_ADDR_CMP];
u64 trccidcvr[ETMv4_MAX_CTXID_CMP];
- u32 trcvmidcvr[ETM_MAX_VMID_CMP];
+ u64 trcvmidcvr[ETM_MAX_VMID_CMP];
u32 trccidcctlr0;
u32 trccidcctlr1;
u32 trcvmidcctlr0;
--
2.25.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread