* [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer
@ 2020-07-22 5:55 Umesh Nerlige Ramappa
2020-07-22 5:55 ` [Intel-gfx] [PATCH 1/4] drm/i915/perf: Ensure observation logic is not clock gated Umesh Nerlige Ramappa
` (5 more replies)
0 siblings, 6 replies; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2020-07-22 5:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
This cover letter is included to trigger "Test-with" an IGT patch.
Tests - https://patchwork.freedesktop.org/series/79745/
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Test-with: 20200722053805.57139-1-umesh.nerlige.ramappa@intel.com
Piotr Maciejewski (4):
drm/i915/perf: Ensure observation logic is not clock gated
drm/i915/perf: Whitelist OA report trigger registers
drm/i915/perf: Whitelist OA counter and buffer registers
drm/i915/perf: Map OA buffer to user space for gen12 performance query
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_mman.h | 2 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 60 +++++
.../gpu/drm/i915/gt/selftest_workarounds.c | 38 ++-
drivers/gpu/drm/i915/i915_perf.c | 239 +++++++++++++++++-
drivers/gpu/drm/i915/i915_perf_types.h | 17 ++
drivers/gpu/drm/i915/i915_reg.h | 12 +
include/uapi/drm/i915_drm.h | 32 +++
8 files changed, 396 insertions(+), 6 deletions(-)
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 1/4] drm/i915/perf: Ensure observation logic is not clock gated
2020-07-22 5:55 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
@ 2020-07-22 5:55 ` Umesh Nerlige Ramappa
2020-07-22 5:55 ` [Intel-gfx] [PATCH 2/4] drm/i915/perf: Whitelist OA report trigger registers Umesh Nerlige Ramappa
` (4 subsequent siblings)
5 siblings, 0 replies; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2020-07-22 5:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
From: Piotr Maciejewski <piotr.maciejewski@intel.com>
A clock gating switch can control if the performance monitoring and
observation logic is enaled or not. Ensure that we enable the clocks.
v2: Separate code from other patches (Lionel)
v3: Reset PMON enable when disabling perf to save power (Lionel)
Fixes: 00a7f0d7155c ("drm/i915/tgl: Add perf support on TGL")
Signed-off-by: Piotr Maciejewski <piotr.maciejewski@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 13 +++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index c6f6370283cf..fe408c327d3c 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2493,6 +2493,14 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
(period_exponent << GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT))
: 0);
+ /*
+ * Initialize Super Queue Internal Cnt Register
+ * Set PMON Enable in order to collect valid metrics.
+ */
+ intel_uncore_write(uncore, GEN12_SQCNT1,
+ intel_uncore_read(uncore, GEN12_SQCNT1) |
+ GEN12_SQCNT1_PMON_ENABLE);
+
/*
* Update all contexts prior writing the mux configurations as we need
* to make sure all slices/subslices are ON before writing to NOA
@@ -2552,6 +2560,11 @@ static void gen12_disable_metric_set(struct i915_perf_stream *stream)
/* Make sure we disable noa to save power. */
intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
+
+ /* Reset PMON Enable to save power. */
+ intel_uncore_write(uncore, GEN12_SQCNT1,
+ intel_uncore_read(uncore, GEN12_SQCNT1) &
+ ~GEN12_SQCNT1_PMON_ENABLE);
}
static void gen7_oa_enable(struct i915_perf_stream *stream)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a0d31f3bf634..9cc3e312b6b7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -696,6 +696,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define OABUFFER_SIZE_16M (7 << 3)
#define GEN12_OA_TLB_INV_CR _MMIO(0xceec)
+#define GEN12_SQCNT1 _MMIO(0x8718)
+#define GEN12_SQCNT1_PMON_ENABLE (1 << 30)
/* Gen12 OAR unit */
#define GEN12_OAR_OACONTROL _MMIO(0x2960)
--
2.20.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 2/4] drm/i915/perf: Whitelist OA report trigger registers
2020-07-22 5:55 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-07-22 5:55 ` [Intel-gfx] [PATCH 1/4] drm/i915/perf: Ensure observation logic is not clock gated Umesh Nerlige Ramappa
@ 2020-07-22 5:55 ` Umesh Nerlige Ramappa
2020-07-22 5:55 ` [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers Umesh Nerlige Ramappa
` (3 subsequent siblings)
5 siblings, 0 replies; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2020-07-22 5:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
From: Piotr Maciejewski <piotr.maciejewski@intel.com>
OA reports can be triggered into the OA buffer by writing into the
OAREPORTTRIG registers. Whitelist the registers to allow user to trigger
reports.
v2:
- Move related change to this patch (Lionel)
- Bump up perf revision (Lionel)
v3: Pardon whitelisted registers for selftest (Umesh)
v4: Document supported gens for the feature (Lionel)
Signed-off-by: Piotr Maciejewski <piotr.maciejewski@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 +++++++++++++++++++
.../gpu/drm/i915/gt/selftest_workarounds.c | 8 ++++++
drivers/gpu/drm/i915/i915_perf.c | 11 +++++---
3 files changed, 42 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index cef1c122696f..a72ebfd115e5 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1387,6 +1387,20 @@ whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
}
+static void gen9_whitelist_build_performance_counters(struct i915_wa_list *w)
+{
+ /* OA buffer trigger report 2/6 used by performance query */
+ whitelist_reg(w, OAREPORTTRIG2);
+ whitelist_reg(w, OAREPORTTRIG6);
+}
+
+static void gen12_whitelist_build_performance_counters(struct i915_wa_list *w)
+{
+ /* OA buffer trigger report 2/6 used by performance query */
+ whitelist_reg(w, GEN12_OAG_OAREPORTTRIG2);
+ whitelist_reg(w, GEN12_OAG_OAREPORTTRIG6);
+}
+
static void gen9_whitelist_build(struct i915_wa_list *w)
{
/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
@@ -1400,6 +1414,9 @@ static void gen9_whitelist_build(struct i915_wa_list *w)
/* WaSendPushConstantsFromMMIO:skl,bxt */
whitelist_reg(w, COMMON_SLICE_CHICKEN2);
+
+ /* Performance counters support */
+ gen9_whitelist_build_performance_counters(w);
}
static void skl_whitelist_build(struct intel_engine_cs *engine)
@@ -1493,6 +1510,9 @@ static void cnl_whitelist_build(struct intel_engine_cs *engine)
/* WaEnablePreemptionGranularityControlByUMD:cnl */
whitelist_reg(w, GEN8_CS_CHICKEN1);
+
+ /* Performance counters support */
+ gen9_whitelist_build_performance_counters(w);
}
static void icl_whitelist_build(struct intel_engine_cs *engine)
@@ -1522,6 +1542,9 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
whitelist_reg_ext(w, PS_INVOCATION_COUNT,
RING_FORCE_TO_NONPRIV_ACCESS_RD |
RING_FORCE_TO_NONPRIV_RANGE_4);
+
+ /* Performance counters support */
+ gen9_whitelist_build_performance_counters(w);
break;
case VIDEO_DECODE_CLASS:
@@ -1572,6 +1595,9 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
/* Wa_1806527549:tgl */
whitelist_reg(w, HIZ_CHICKEN);
+
+ /* Performance counters support */
+ gen12_whitelist_build_performance_counters(w);
break;
default:
whitelist_reg_ext(w,
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index febc9e6692ba..3b1d3dbcd477 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -934,6 +934,10 @@ static bool pardon_reg(struct drm_i915_private *i915, i915_reg_t reg)
static const struct regmask pardon[] = {
{ GEN9_CTX_PREEMPT_REG, INTEL_GEN_MASK(9, 9) },
{ GEN8_L3SQCREG4, INTEL_GEN_MASK(9, 9) },
+ { OAREPORTTRIG2, INTEL_GEN_MASK(8, 11) },
+ { OAREPORTTRIG6, INTEL_GEN_MASK(8, 11) },
+ { GEN12_OAG_OAREPORTTRIG2, INTEL_GEN_MASK(12, 12) },
+ { GEN12_OAG_OAREPORTTRIG6, INTEL_GEN_MASK(12, 12) },
};
return find_reg(i915, reg, pardon, ARRAY_SIZE(pardon));
@@ -956,6 +960,10 @@ static bool writeonly_reg(struct drm_i915_private *i915, i915_reg_t reg)
/* Some registers do not seem to behave and our writes unreadable */
static const struct regmask wo[] = {
{ GEN9_SLICE_COMMON_ECO_CHICKEN1, INTEL_GEN_MASK(9, 9) },
+ { OAREPORTTRIG2, INTEL_GEN_MASK(8, 11) },
+ { OAREPORTTRIG6, INTEL_GEN_MASK(8, 11) },
+ { GEN12_OAG_OAREPORTTRIG2, INTEL_GEN_MASK(12, 12) },
+ { GEN12_OAG_OAREPORTTRIG6, INTEL_GEN_MASK(12, 12) },
};
return find_reg(i915, reg, wo, ARRAY_SIZE(wo));
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index fe408c327d3c..30f6aeb819aa 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1448,7 +1448,8 @@ static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
* bit."
*/
intel_uncore_write(uncore, GEN8_OABUFFER, gtt_offset |
- OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);
+ OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT |
+ GEN7_OABUFFER_EDGE_TRIGGER);
intel_uncore_write(uncore, GEN8_OATAILPTR, gtt_offset & GEN8_OATAILPTR_MASK);
/* Mark that we need updated tail pointers to read from... */
@@ -1501,7 +1502,8 @@ static void gen12_init_oa_buffer(struct i915_perf_stream *stream)
* bit."
*/
intel_uncore_write(uncore, GEN12_OAG_OABUFFER, gtt_offset |
- OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);
+ OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT |
+ GEN7_OABUFFER_EDGE_TRIGGER);
intel_uncore_write(uncore, GEN12_OAG_OATAILPTR,
gtt_offset & GEN12_OAG_OATAILPTR_MASK);
@@ -4445,8 +4447,11 @@ int i915_perf_ioctl_version(void)
*
* 5: Add DRM_I915_PERF_PROP_POLL_OA_PERIOD parameter that controls the
* interval for the hrtimer used to check for OA data.
+ *
+ * 6: Whitelist OATRIGGER registers to allow user to trigger reports
+ * into the OA buffer. This applies only to gen8+.
*/
- return 5;
+ return 6;
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers
2020-07-22 5:55 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-07-22 5:55 ` [Intel-gfx] [PATCH 1/4] drm/i915/perf: Ensure observation logic is not clock gated Umesh Nerlige Ramappa
2020-07-22 5:55 ` [Intel-gfx] [PATCH 2/4] drm/i915/perf: Whitelist OA report trigger registers Umesh Nerlige Ramappa
@ 2020-07-22 5:55 ` Umesh Nerlige Ramappa
2020-07-22 5:55 ` [Intel-gfx] [PATCH 4/4] drm/i915/perf: Map OA buffer to user space for gen12 performance query Umesh Nerlige Ramappa
` (2 subsequent siblings)
5 siblings, 0 replies; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2020-07-22 5:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
From: Piotr Maciejewski <piotr.maciejewski@intel.com>
It is useful to have markers in the OA reports to identify triggered
reports. Whitelist some OA counters that can be used as markers.
A triggered report can be found faster if we can sample the HW tail and
head registers when the report was triggered. Whitelist OA buffer
specific registers.
v2:
- Bump up the perf revision (Lionel)
- Use indexing for counters (Lionel)
- Fix selftest for oa ticking register (Umesh)
v3: Pardon whitelisted registers for selftest (Umesh)
v4:
- Document whitelisted registers (Lionel)
- Fix live isolated whitelist for OA regs (Umesh)
Signed-off-by: Piotr Maciejewski <piotr.maciejewski@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 34 +++++++++++++++++++
.../gpu/drm/i915/gt/selftest_workarounds.c | 30 +++++++++++++++-
drivers/gpu/drm/i915/i915_perf.c | 8 ++++-
drivers/gpu/drm/i915/i915_reg.h | 10 ++++++
4 files changed, 80 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a72ebfd115e5..c950d07beec3 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1392,6 +1392,23 @@ static void gen9_whitelist_build_performance_counters(struct i915_wa_list *w)
/* OA buffer trigger report 2/6 used by performance query */
whitelist_reg(w, OAREPORTTRIG2);
whitelist_reg(w, OAREPORTTRIG6);
+
+ /* Performance counters A18-20 used by tbs marker query */
+ whitelist_reg_ext(w, OA_PERF_COUNTER_A(18),
+ RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
+
+ whitelist_reg(w, OA_PERF_COUNTER_A(20));
+ whitelist_reg(w, OA_PERF_COUNTER_A_UPPER(20));
+
+ /* Read access to gpu ticks */
+ whitelist_reg_ext(w, GEN8_GPU_TICKS,
+ RING_FORCE_TO_NONPRIV_ACCESS_RD);
+
+ /* Read access to: oa status, head, tail, buffer settings */
+ whitelist_reg_ext(w, GEN8_OASTATUS,
+ RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
}
static void gen12_whitelist_build_performance_counters(struct i915_wa_list *w)
@@ -1399,6 +1416,23 @@ static void gen12_whitelist_build_performance_counters(struct i915_wa_list *w)
/* OA buffer trigger report 2/6 used by performance query */
whitelist_reg(w, GEN12_OAG_OAREPORTTRIG2);
whitelist_reg(w, GEN12_OAG_OAREPORTTRIG6);
+
+ /* Performance counters A18-20 used by tbs marker query */
+ whitelist_reg_ext(w, GEN12_OAG_PERF_COUNTER_A(18),
+ RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
+
+ whitelist_reg(w, GEN12_OAG_PERF_COUNTER_A(20));
+ whitelist_reg(w, GEN12_OAG_PERF_COUNTER_A_UPPER(20));
+
+ /* Read access to gpu ticks */
+ whitelist_reg_ext(w, GEN12_OAG_GPU_TICKS,
+ RING_FORCE_TO_NONPRIV_ACCESS_RD);
+
+ /* Read access to: oa status, head, tail, buffer settings */
+ whitelist_reg_ext(w, GEN12_OAG_OASTATUS,
+ RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
}
static void gen9_whitelist_build(struct i915_wa_list *w)
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index 3b1d3dbcd477..7c2c2be8d212 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -431,6 +431,19 @@ static bool timestamp(const struct intel_engine_cs *engine, u32 reg)
}
}
+static bool oa_gpu_ticks(u32 reg)
+{
+ reg = reg & ~RING_FORCE_TO_NONPRIV_ACCESS_MASK;
+ switch (reg) {
+ case 0x2910:
+ case 0xda90:
+ return true;
+
+ default:
+ return false;
+ }
+}
+
static bool ro_register(u32 reg)
{
if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
@@ -511,7 +524,7 @@ static int check_dirty_whitelist(struct intel_context *ce)
if (wo_register(engine, reg))
continue;
- if (timestamp(engine, reg))
+ if (timestamp(engine, reg) || oa_gpu_ticks(reg))
continue; /* timestamps are expected to autoincrement */
ro_reg = ro_register(reg);
@@ -918,6 +931,9 @@ static bool find_reg(struct drm_i915_private *i915,
{
u32 offset = i915_mmio_reg_offset(reg);
+ /* Clear non priv flags */
+ offset &= RING_FORCE_TO_NONPRIV_ADDRESS_MASK;
+
while (count--) {
if (INTEL_INFO(i915)->gen_mask & tbl->gen_mask &&
i915_mmio_reg_offset(tbl->reg) == offset)
@@ -938,6 +954,12 @@ static bool pardon_reg(struct drm_i915_private *i915, i915_reg_t reg)
{ OAREPORTTRIG6, INTEL_GEN_MASK(8, 11) },
{ GEN12_OAG_OAREPORTTRIG2, INTEL_GEN_MASK(12, 12) },
{ GEN12_OAG_OAREPORTTRIG6, INTEL_GEN_MASK(12, 12) },
+ { OA_PERF_COUNTER_A(18), INTEL_GEN_MASK(8, 11) },
+ { OA_PERF_COUNTER_A(20), INTEL_GEN_MASK(8, 11) },
+ { OA_PERF_COUNTER_A_UPPER(20), INTEL_GEN_MASK(8, 11) },
+ { GEN12_OAG_PERF_COUNTER_A(18), INTEL_GEN_MASK(12, 12) },
+ { GEN12_OAG_PERF_COUNTER_A(20), INTEL_GEN_MASK(12, 12) },
+ { GEN12_OAG_PERF_COUNTER_A_UPPER(20), INTEL_GEN_MASK(12, 12) },
};
return find_reg(i915, reg, pardon, ARRAY_SIZE(pardon));
@@ -964,6 +986,12 @@ static bool writeonly_reg(struct drm_i915_private *i915, i915_reg_t reg)
{ OAREPORTTRIG6, INTEL_GEN_MASK(8, 11) },
{ GEN12_OAG_OAREPORTTRIG2, INTEL_GEN_MASK(12, 12) },
{ GEN12_OAG_OAREPORTTRIG6, INTEL_GEN_MASK(12, 12) },
+ { OA_PERF_COUNTER_A(18), INTEL_GEN_MASK(8, 11) },
+ { OA_PERF_COUNTER_A(20), INTEL_GEN_MASK(8, 11) },
+ { OA_PERF_COUNTER_A_UPPER(20), INTEL_GEN_MASK(8, 11) },
+ { GEN12_OAG_PERF_COUNTER_A(18), INTEL_GEN_MASK(12, 12) },
+ { GEN12_OAG_PERF_COUNTER_A(20), INTEL_GEN_MASK(12, 12) },
+ { GEN12_OAG_PERF_COUNTER_A_UPPER(20), INTEL_GEN_MASK(12, 12) },
};
return find_reg(i915, reg, wo, ARRAY_SIZE(wo));
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 30f6aeb819aa..2f23aad12c60 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4450,8 +4450,14 @@ int i915_perf_ioctl_version(void)
*
* 6: Whitelist OATRIGGER registers to allow user to trigger reports
* into the OA buffer. This applies only to gen8+.
+ *
+ * 7: Whitelist below OA registers for user to identify the location of
+ * triggered reports in the OA buffer. This applies only to gen8+.
+ *
+ * - OA buffer head/tail/status/buffer registers for read only
+ * - OA counters A18, A19, A20 for read/write
*/
- return 6;
+ return 7;
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9cc3e312b6b7..c68dc3f39e62 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -675,6 +675,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
#define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
+#define GEN8_GPU_TICKS _MMIO(0x2910)
#define GEN8_OASTATUS _MMIO(0x2b08)
#define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3)
#define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2)
@@ -733,6 +734,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
#define GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
+#define GEN12_OAG_GPU_TICKS _MMIO(0xda90)
#define GEN12_OAG_OASTATUS _MMIO(0xdafc)
#define GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2)
#define GEN12_OAG_OASTATUS_BUFFER_OVERFLOW (1 << 1)
@@ -974,6 +976,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
+/* Performance counters registers */
+#define OA_PERF_COUNTER_A(idx) _MMIO(0x2800 + 8 * (idx))
+#define OA_PERF_COUNTER_A_UPPER(idx) _MMIO(0x2800 + 8 * (idx) + 4)
+
+/* Gen12 Performance counters registers */
+#define GEN12_OAG_PERF_COUNTER_A(idx) _MMIO(0xD980 + 8 * (idx))
+#define GEN12_OAG_PERF_COUNTER_A_UPPER(idx) _MMIO(0xD980 + 8 * (idx) + 4)
+
/* Same layout as OASTARTTRIGX */
#define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
#define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
--
2.20.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 4/4] drm/i915/perf: Map OA buffer to user space for gen12 performance query
2020-07-22 5:55 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
` (2 preceding siblings ...)
2020-07-22 5:55 ` [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers Umesh Nerlige Ramappa
@ 2020-07-22 5:55 ` Umesh Nerlige Ramappa
2020-07-23 9:31 ` Lionel Landwerlin
2020-07-22 6:27 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Allow privileged user to map the OA buffer (rev4) Patchwork
2020-07-22 6:48 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
5 siblings, 1 reply; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2020-07-22 5:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
From: Piotr Maciejewski <piotr.maciejewski@intel.com>
i915 used to support time based sampling mode which is good for overall
system monitoring, but is not enough for query mode used to measure a
single draw call or dispatch. Gen9-Gen11 are using current i915 perf
implementation for query, but Gen12+ requires a new approach for query
based on triggered reports within oa buffer.
Triggering reports into the OA buffer is achieved by writing into a
a trigger register. Optionally an unused counter/register is set with a
marker value such that a triggered report can be identified in the OA
buffer. Reports are usually triggered at the start and end of work that
is measured.
Since OA buffer is large and queries can be frequent, an efficient way
to look for triggered reports is required. By knowing the current head
and tail offsets into the OA buffer, it is easier to determine the
locality of the reports of interest.
Current perf OA interface does not expose head/tail information to the
user and it filters out invalid reports before sending data to user.
Also considering limited size of user buffer used during a query,
creating a 1:1 copy of the OA buffer at the user space added undesired
complexity.
The solution was to map the OA buffer to user space provided
(1) that it is accessed from a privileged user.
(2) OA report filtering is not used.
These 2 conditions would satisfy the safety criteria that the current
perf interface addresses.
To enable the query:
- Add an ioctl to expose head and tail to the user
- Add an ioctl to return size and offset of the OA buffer
- Map the OA buffer to the user space
v2:
- Improve commit message (Chris)
- Do not mmap based on gem object filp. Instead, use perf_fd and support
mmap syscall (Chris)
- Pass non-zero offset in mmap to enforce the right object is
mapped (Chris)
- Do not expose gpu_address (Chris)
- Verify start and length of vma for page alignment (Lionel)
- Move SQNTL config out (Lionel)
v3: (Chris)
- Omit redundant checks
- Return VM_FAULT_SIGBUS is old stream is closed
- Maintain reference counts to stream in vm_open and vm_close
- Use switch to identify object to be mapped
v4: Call kref_put on closing perf fd (Chris)
Signed-off-by: Piotr Maciejewski <piotr.maciejewski@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_mman.h | 2 +
drivers/gpu/drm/i915/i915_perf.c | 211 ++++++++++++++++++++++-
drivers/gpu/drm/i915/i915_perf_types.h | 17 ++
include/uapi/drm/i915_drm.h | 32 ++++
5 files changed, 261 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index b23368529a40..7c4b9b0c334b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -204,7 +204,7 @@ compute_partial_view(const struct drm_i915_gem_object *obj,
return view;
}
-static vm_fault_t i915_error_to_vmf_fault(int err)
+vm_fault_t i915_error_to_vmf_fault(int err)
{
switch (err) {
default:
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.h b/drivers/gpu/drm/i915/gem/i915_gem_mman.h
index efee9e0d2508..1190a3a228ea 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.h
@@ -29,4 +29,6 @@ void i915_gem_object_release_mmap_gtt(struct drm_i915_gem_object *obj);
void i915_gem_object_release_mmap_offset(struct drm_i915_gem_object *obj);
+vm_fault_t i915_error_to_vmf_fault(int err);
+
#endif
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2f23aad12c60..331c3f9c59e2 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -192,10 +192,12 @@
*/
#include <linux/anon_inodes.h>
+#include <linux/mman.h>
#include <linux/sizes.h>
#include <linux/uuid.h>
#include "gem/i915_gem_context.h"
+#include "gem/i915_gem_mman.h"
#include "gt/intel_engine_pm.h"
#include "gt/intel_engine_user.h"
#include "gt/intel_gt.h"
@@ -378,6 +380,24 @@ static struct ctl_table_header *sysctl_header;
static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
+static void free_stream(struct kref *kref)
+{
+ struct i915_perf_stream *stream =
+ container_of(kref, typeof(*stream), refcount);
+
+ kfree(stream);
+}
+
+static void perf_stream_get(struct i915_perf_stream *stream)
+{
+ kref_get(&stream->refcount);
+}
+
+static void perf_stream_put(struct i915_perf_stream *stream)
+{
+ kref_put(&stream->refcount, free_stream);
+}
+
void i915_oa_config_release(struct kref *ref)
{
struct i915_oa_config *oa_config =
@@ -434,6 +454,30 @@ static u32 gen7_oa_hw_tail_read(struct i915_perf_stream *stream)
return oastatus1 & GEN7_OASTATUS1_TAIL_MASK;
}
+static u32 gen12_oa_hw_head_read(struct i915_perf_stream *stream)
+{
+ struct intel_uncore *uncore = stream->uncore;
+
+ return intel_uncore_read(uncore, GEN12_OAG_OAHEADPTR) &
+ GEN12_OAG_OAHEADPTR_MASK;
+}
+
+static u32 gen8_oa_hw_head_read(struct i915_perf_stream *stream)
+{
+ struct intel_uncore *uncore = stream->uncore;
+
+ return intel_uncore_read(uncore, GEN8_OAHEADPTR) &
+ GEN8_OAHEADPTR_MASK;
+}
+
+static u32 gen7_oa_hw_head_read(struct i915_perf_stream *stream)
+{
+ struct intel_uncore *uncore = stream->uncore;
+ u32 oastatus2 = intel_uncore_read(uncore, GEN7_OASTATUS2);
+
+ return oastatus2 & GEN7_OASTATUS2_HEAD_MASK;
+}
+
/**
* oa_buffer_check_unlocked - check for data and update tail ptr state
* @stream: i915 stream instance
@@ -2934,6 +2978,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
stream->poll_check_timer.function = oa_poll_check_timer_cb;
init_waitqueue_head(&stream->poll_wq);
spin_lock_init(&stream->oa_buffer.ptr_lock);
+ kref_init(&stream->refcount);
return 0;
@@ -3214,6 +3259,69 @@ static long i915_perf_config_locked(struct i915_perf_stream *stream,
return ret;
}
+/**
+ * i915_perf_oa_buffer_head_tail_locked - head and tail of the OA buffer
+ * @stream: i915 perf stream
+ * @arg: pointer to oa buffer head and tail filled by this function.
+ */
+static int i915_perf_oa_buffer_head_tail_locked(struct i915_perf_stream *stream,
+ unsigned long arg)
+{
+ struct drm_i915_perf_oa_buffer_head_tail ht;
+ void __user *output = (void __user *)arg;
+ u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
+
+ if (i915_perf_stream_paranoid && !perfmon_capable()) {
+ DRM_DEBUG("Insufficient privileges to access OA buffer info\n");
+ return -EACCES;
+ }
+
+ if (!output)
+ return -EINVAL;
+
+ memset(&ht, 0, sizeof(ht));
+
+ ht.head = stream->perf->ops.oa_hw_head_read(stream) - gtt_offset;
+ ht.tail = stream->perf->ops.oa_hw_tail_read(stream) - gtt_offset;
+
+ if (copy_to_user(output, &ht, sizeof(ht)))
+ return -EFAULT;
+
+ return 0;
+}
+
+#define I915_PERF_OA_BUFFER_MMAP_OFFSET 1
+
+/**
+ * i915_perf_oa_buffer_info_locked - size and offset of the OA buffer
+ * @stream: i915 perf stream
+ * @arg: pointer to oa buffer info filled by this function.
+ */
+static int i915_perf_oa_buffer_info_locked(struct i915_perf_stream *stream,
+ unsigned long arg)
+{
+ struct drm_i915_perf_oa_buffer_info info;
+ void __user *output = (void __user *)arg;
+
+ if (i915_perf_stream_paranoid && !perfmon_capable()) {
+ DRM_DEBUG("Insufficient privileges to access OA buffer info\n");
+ return -EACCES;
+ }
+
+ if (!output)
+ return -EINVAL;
+
+ memset(&info, 0, sizeof(info));
+
+ info.size = stream->oa_buffer.vma->size;
+ info.offset = I915_PERF_OA_BUFFER_MMAP_OFFSET * PAGE_SIZE;
+
+ if (copy_to_user(output, &info, sizeof(info)))
+ return -EFAULT;
+
+ return 0;
+}
+
/**
* i915_perf_ioctl - support ioctl() usage with i915 perf stream FDs
* @stream: An i915 perf stream
@@ -3239,6 +3347,10 @@ static long i915_perf_ioctl_locked(struct i915_perf_stream *stream,
return 0;
case I915_PERF_IOCTL_CONFIG:
return i915_perf_config_locked(stream, arg);
+ case I915_PERF_IOCTL_GET_OA_BUFFER_INFO:
+ return i915_perf_oa_buffer_info_locked(stream, arg);
+ case I915_PERF_IOCTL_GET_OA_BUFFER_HEAD_TAIL:
+ return i915_perf_oa_buffer_head_tail_locked(stream, arg);
}
return -EINVAL;
@@ -3291,7 +3403,8 @@ static void i915_perf_destroy_locked(struct i915_perf_stream *stream)
if (stream->ctx)
i915_gem_context_put(stream->ctx);
- kfree(stream);
+ WRITE_ONCE(stream->closed, true);
+ perf_stream_put(stream);
}
/**
@@ -3314,12 +3427,98 @@ static int i915_perf_release(struct inode *inode, struct file *file)
i915_perf_destroy_locked(stream);
mutex_unlock(&perf->lock);
+ unmap_mapping_range(file->f_mapping, 0, OA_BUFFER_SIZE, 1);
+
/* Release the reference the perf stream kept on the driver. */
drm_dev_put(&perf->i915->drm);
return 0;
}
+static void vm_open_oa(struct vm_area_struct *vma)
+{
+ struct i915_perf_stream *stream = vma->vm_private_data;
+
+ GEM_BUG_ON(!stream);
+ perf_stream_get(stream);
+}
+
+static void vm_close_oa(struct vm_area_struct *vma)
+{
+ struct i915_perf_stream *stream = vma->vm_private_data;
+
+ GEM_BUG_ON(!stream);
+ perf_stream_put(stream);
+}
+
+static vm_fault_t vm_fault_oa(struct vm_fault *vmf)
+{
+ struct vm_area_struct *vma = vmf->vma;
+ struct i915_perf_stream *stream = vma->vm_private_data;
+ struct i915_perf *perf = stream->perf;
+ struct drm_i915_gem_object *obj = stream->oa_buffer.vma->obj;
+ int err;
+ bool closed;
+
+ mutex_lock(&perf->lock);
+ closed = READ_ONCE(stream->closed);
+ mutex_unlock(&perf->lock);
+
+ if (closed)
+ return VM_FAULT_SIGBUS;
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ goto out;
+
+ err = remap_io_sg(vma,
+ vma->vm_start, vma->vm_end - vma->vm_start,
+ obj->mm.pages->sgl, -1);
+
+ i915_gem_object_unpin_pages(obj);
+
+out:
+ return i915_error_to_vmf_fault(err);
+}
+
+static const struct vm_operations_struct vm_ops_oa = {
+ .open = vm_open_oa,
+ .close = vm_close_oa,
+ .fault = vm_fault_oa,
+};
+
+int i915_perf_mmap(struct file *file, struct vm_area_struct *vma)
+{
+ struct i915_perf_stream *stream = file->private_data;
+
+ if (i915_perf_stream_paranoid && !perfmon_capable()) {
+ DRM_DEBUG("Insufficient privileges to map OA buffer\n");
+ return -EACCES;
+ }
+
+ switch (vma->vm_pgoff) {
+ case I915_PERF_OA_BUFFER_MMAP_OFFSET:
+ if (vma->vm_end - vma->vm_start > OA_BUFFER_SIZE)
+ return -EINVAL;
+
+ if (vma->vm_flags & VM_WRITE)
+ return -EINVAL;
+
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ vma->vm_flags &= ~(VM_MAYWRITE | VM_MAYEXEC | VM_MAYSHARE);
+ vma->vm_flags |= VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP;
+ vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
+ vma->vm_private_data = stream;
+ vma->vm_ops = &vm_ops_oa;
+ vm_open_oa(vma);
+
+ return 0;
+}
static const struct file_operations fops = {
.owner = THIS_MODULE,
@@ -3332,6 +3531,7 @@ static const struct file_operations fops = {
* to handle 32bits compatibility.
*/
.compat_ioctl = i915_perf_ioctl,
+ .mmap = i915_perf_mmap,
};
@@ -4260,6 +4460,7 @@ void i915_perf_init(struct drm_i915_private *i915)
perf->ops.oa_disable = gen7_oa_disable;
perf->ops.read = gen7_oa_read;
perf->ops.oa_hw_tail_read = gen7_oa_hw_tail_read;
+ perf->ops.oa_hw_head_read = gen7_oa_hw_head_read;
perf->oa_formats = hsw_oa_formats;
} else if (HAS_LOGICAL_RING_CONTEXTS(i915)) {
@@ -4291,6 +4492,7 @@ void i915_perf_init(struct drm_i915_private *i915)
perf->ops.enable_metric_set = gen8_enable_metric_set;
perf->ops.disable_metric_set = gen8_disable_metric_set;
perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
+ perf->ops.oa_hw_head_read = gen8_oa_hw_head_read;
if (IS_GEN(i915, 8)) {
perf->ctx_oactxctrl_offset = 0x120;
@@ -4318,6 +4520,7 @@ void i915_perf_init(struct drm_i915_private *i915)
perf->ops.enable_metric_set = gen8_enable_metric_set;
perf->ops.disable_metric_set = gen10_disable_metric_set;
perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
+ perf->ops.oa_hw_head_read = gen8_oa_hw_head_read;
if (IS_GEN(i915, 10)) {
perf->ctx_oactxctrl_offset = 0x128;
@@ -4342,6 +4545,7 @@ void i915_perf_init(struct drm_i915_private *i915)
perf->ops.enable_metric_set = gen12_enable_metric_set;
perf->ops.disable_metric_set = gen12_disable_metric_set;
perf->ops.oa_hw_tail_read = gen12_oa_hw_tail_read;
+ perf->ops.oa_hw_head_read = gen12_oa_hw_head_read;
perf->ctx_flexeu0_offset = 0;
perf->ctx_oactxctrl_offset = 0x144;
@@ -4456,8 +4660,11 @@ int i915_perf_ioctl_version(void)
*
* - OA buffer head/tail/status/buffer registers for read only
* - OA counters A18, A19, A20 for read/write
+ *
+ * 8: Added an option to map oa buffer at umd driver level and trigger
+ * oa reports within oa buffer from command buffer.
*/
- return 7;
+ return 8;
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h b/drivers/gpu/drm/i915/i915_perf_types.h
index a36a455ae336..2efbe35c5fa9 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -311,6 +311,18 @@ struct i915_perf_stream {
* buffer should be checked for available data.
*/
u64 poll_oa_period;
+
+ /**
+ * @closed: Open or closed state of the stream.
+ * True if stream is closed.
+ */
+ bool closed;
+
+ /**
+ * @refcount: References to the mapped OA buffer managed by this
+ * stream.
+ */
+ struct kref refcount;
};
/**
@@ -377,6 +389,11 @@ struct i915_oa_ops {
* generations.
*/
u32 (*oa_hw_tail_read)(struct i915_perf_stream *stream);
+
+ /**
+ * @oa_hw_head_read: read the OA head pointer register
+ */
+ u32 (*oa_hw_head_read)(struct i915_perf_stream *stream);
};
struct i915_perf {
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 00546062e023..2042f6339182 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2048,6 +2048,38 @@ struct drm_i915_perf_open_param {
*/
#define I915_PERF_IOCTL_CONFIG _IO('i', 0x2)
+/**
+ * Returns OA buffer properties to be used with mmap.
+ *
+ * This ioctl is available in perf revision 8.
+ */
+#define I915_PERF_IOCTL_GET_OA_BUFFER_INFO _IO('i', 0x3)
+
+/**
+ * OA buffer size and offset.
+ */
+struct drm_i915_perf_oa_buffer_info {
+ __u32 size;
+ __u32 offset;
+ __u64 reserved[4];
+};
+
+/**
+ * Returns current position of OA buffer head and tail.
+ *
+ * This ioctl is available in perf revision 8.
+ */
+#define I915_PERF_IOCTL_GET_OA_BUFFER_HEAD_TAIL _IO('i', 0x4)
+
+/**
+ * OA buffer head and tail.
+ */
+struct drm_i915_perf_oa_buffer_head_tail {
+ __u32 head;
+ __u32 tail;
+ __u64 reserved[4];
+};
+
/**
* Common to all i915 perf records
*/
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Allow privileged user to map the OA buffer (rev4)
2020-07-22 5:55 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
` (3 preceding siblings ...)
2020-07-22 5:55 ` [Intel-gfx] [PATCH 4/4] drm/i915/perf: Map OA buffer to user space for gen12 performance query Umesh Nerlige Ramappa
@ 2020-07-22 6:27 ` Patchwork
2020-07-22 6:48 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
5 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2020-07-22 6:27 UTC (permalink / raw)
To: Umesh Nerlige Ramappa; +Cc: intel-gfx
== Series Details ==
Series: Allow privileged user to map the OA buffer (rev4)
URL : https://patchwork.freedesktop.org/series/79460/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for Allow privileged user to map the OA buffer (rev4)
2020-07-22 5:55 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
` (4 preceding siblings ...)
2020-07-22 6:27 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Allow privileged user to map the OA buffer (rev4) Patchwork
@ 2020-07-22 6:48 ` Patchwork
5 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2020-07-22 6:48 UTC (permalink / raw)
To: Umesh Nerlige Ramappa; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 15041 bytes --]
== Series Details ==
Series: Allow privileged user to map the OA buffer (rev4)
URL : https://patchwork.freedesktop.org/series/79460/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8775 -> Patchwork_18221
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18221 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18221, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18221:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@workarounds:
- fi-skl-6700k2: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-skl-6700k2/igt@i915_selftest@live@workarounds.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-skl-6700k2/igt@i915_selftest@live@workarounds.html
- fi-kbl-x1275: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-kbl-x1275/igt@i915_selftest@live@workarounds.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-kbl-x1275/igt@i915_selftest@live@workarounds.html
- fi-cfl-guc: [PASS][5] -> [DMESG-FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-cfl-guc/igt@i915_selftest@live@workarounds.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-cfl-guc/igt@i915_selftest@live@workarounds.html
- fi-skl-guc: [PASS][7] -> [DMESG-FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-skl-guc/igt@i915_selftest@live@workarounds.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-skl-guc/igt@i915_selftest@live@workarounds.html
- fi-skl-6600u: [PASS][9] -> [DMESG-FAIL][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-skl-6600u/igt@i915_selftest@live@workarounds.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-skl-6600u/igt@i915_selftest@live@workarounds.html
- fi-kbl-8809g: [PASS][11] -> [DMESG-FAIL][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-kbl-8809g/igt@i915_selftest@live@workarounds.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-kbl-8809g/igt@i915_selftest@live@workarounds.html
- fi-cfl-8700k: [PASS][13] -> [DMESG-FAIL][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-cfl-8700k/igt@i915_selftest@live@workarounds.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-cfl-8700k/igt@i915_selftest@live@workarounds.html
- fi-kbl-r: NOTRUN -> [DMESG-FAIL][15]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-kbl-r/igt@i915_selftest@live@workarounds.html
- fi-cfl-8109u: [PASS][16] -> [DMESG-FAIL][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-cfl-8109u/igt@i915_selftest@live@workarounds.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-cfl-8109u/igt@i915_selftest@live@workarounds.html
- fi-skl-lmem: [PASS][18] -> [DMESG-FAIL][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-skl-lmem/igt@i915_selftest@live@workarounds.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-skl-lmem/igt@i915_selftest@live@workarounds.html
- fi-kbl-7500u: [PASS][20] -> [DMESG-FAIL][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-kbl-7500u/igt@i915_selftest@live@workarounds.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-kbl-7500u/igt@i915_selftest@live@workarounds.html
- fi-kbl-guc: [PASS][22] -> [DMESG-FAIL][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-kbl-guc/igt@i915_selftest@live@workarounds.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-kbl-guc/igt@i915_selftest@live@workarounds.html
- fi-kbl-soraka: [PASS][24] -> [DMESG-FAIL][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-kbl-soraka/igt@i915_selftest@live@workarounds.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-kbl-soraka/igt@i915_selftest@live@workarounds.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@workarounds:
- {fi-kbl-7560u}: [PASS][26] -> [DMESG-FAIL][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-kbl-7560u/igt@i915_selftest@live@workarounds.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-kbl-7560u/igt@i915_selftest@live@workarounds.html
Known issues
------------
Here are the changes found in Patchwork_18221 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@read_all_entries:
- fi-bsw-kefka: [PASS][28] -> [DMESG-WARN][29] ([i915#1982]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-bsw-kefka/igt@debugfs_test@read_all_entries.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-bsw-kefka/igt@debugfs_test@read_all_entries.html
* igt@gem_ctx_create@basic:
- fi-tgl-y: [PASS][30] -> [DMESG-WARN][31] ([i915#402]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-tgl-y/igt@gem_ctx_create@basic.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-tgl-y/igt@gem_ctx_create@basic.html
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [PASS][32] -> [DMESG-WARN][33] ([i915#1982])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@workarounds:
- fi-apl-guc: [PASS][34] -> [DMESG-FAIL][35] ([i915#1635])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-apl-guc/igt@i915_selftest@live@workarounds.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-apl-guc/igt@i915_selftest@live@workarounds.html
- fi-bxt-dsi: [PASS][36] -> [DMESG-FAIL][37] ([i915#1635])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-bxt-dsi/igt@i915_selftest@live@workarounds.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-bxt-dsi/igt@i915_selftest@live@workarounds.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-n3050: [PASS][38] -> [DMESG-WARN][39] ([i915#1982]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- fi-icl-u2: [PASS][40] -> [DMESG-WARN][41] ([i915#1982])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
* igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2:
- fi-skl-guc: [PASS][42] -> [DMESG-WARN][43] ([i915#2203])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-skl-guc/igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-skl-guc/igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2.html
#### Possible fixes ####
* igt@i915_module_load@reload:
- {fi-tgl-dsi}: [DMESG-WARN][44] ([i915#1982]) -> [PASS][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-tgl-dsi/igt@i915_module_load@reload.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-tgl-dsi/igt@i915_module_load@reload.html
- fi-apl-guc: [DMESG-WARN][46] ([i915#1635] / [i915#1982]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-apl-guc/igt@i915_module_load@reload.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-apl-guc/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-byt-j1900: [DMESG-WARN][48] ([i915#1982]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-bsw-kefka: [DMESG-WARN][50] ([i915#1982]) -> [PASS][51] +2 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-bsw-kefka/igt@i915_pm_rpm@module-reload.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-bsw-kefka/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@active:
- fi-cfl-8109u: [DMESG-FAIL][52] ([i915#666]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-cfl-8109u/igt@i915_selftest@live@active.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-cfl-8109u/igt@i915_selftest@live@active.html
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [DMESG-WARN][54] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-kbl-x1275/igt@kms_busy@basic@flip.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-kbl-x1275/igt@kms_busy@basic@flip.html
- fi-tgl-y: [DMESG-WARN][56] ([i915#1982]) -> [PASS][57] +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-tgl-y/igt@kms_busy@basic@flip.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-tgl-y/igt@kms_busy@basic@flip.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [DMESG-WARN][58] ([i915#2203]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-tgl-u2: [DMESG-WARN][60] ([i915#402]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-tgl-u2/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-tgl-u2/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
* igt@prime_self_import@basic-with_two_bos:
- fi-tgl-y: [DMESG-WARN][62] ([i915#402]) -> [PASS][63] +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
#### Warnings ####
* igt@i915_module_load@reload:
- fi-icl-u2: [DMESG-WARN][64] ([i915#1982] / [i915#289]) -> [DMESG-WARN][65] ([i915#289])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-icl-u2/igt@i915_module_load@reload.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-icl-u2/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-guc: [SKIP][66] ([fdo#109271]) -> [DMESG-FAIL][67] ([i915#2203])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-x1275: [DMESG-WARN][68] ([i915#62] / [i915#92]) -> [DMESG-WARN][69] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-kbl-x1275/igt@kms_force_connector_basic@force-connector-state.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-kbl-x1275/igt@kms_force_connector_basic@force-connector-state.html
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-x1275: [DMESG-WARN][70] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][71] ([i915#62] / [i915#92]) +3 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8775/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#289]: https://gitlab.freedesktop.org/drm/intel/issues/289
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (47 -> 40)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* IGT: IGT_5742 -> IGTPW_4788
* Linux: CI_DRM_8775 -> Patchwork_18221
CI-20190529: 20190529
CI_DRM_8775: 2dc052ea981f79cb758997ffa762fe4ea18ef9ca @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_4788: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4788/index.html
IGT_5742: 540f9de91ab2816885a9076a4c0835cb3dc67a97 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18221: bab0da323556d2819afea0d012f4ffff7f7410dd @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
bab0da323556 drm/i915/perf: Map OA buffer to user space for gen12 performance query
ef7adc915aec drm/i915/perf: Whitelist OA counter and buffer registers
07511bbc9441 drm/i915/perf: Whitelist OA report trigger registers
ddc28fbf91e1 drm/i915/perf: Ensure observation logic is not clock gated
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18221/index.html
[-- Attachment #1.2: Type: text/html, Size: 18175 bytes --]
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915/perf: Map OA buffer to user space for gen12 performance query
2020-07-22 5:55 ` [Intel-gfx] [PATCH 4/4] drm/i915/perf: Map OA buffer to user space for gen12 performance query Umesh Nerlige Ramappa
@ 2020-07-23 9:31 ` Lionel Landwerlin
2020-07-23 23:48 ` Umesh Nerlige Ramappa
0 siblings, 1 reply; 21+ messages in thread
From: Lionel Landwerlin @ 2020-07-23 9:31 UTC (permalink / raw)
To: Umesh Nerlige Ramappa, intel-gfx; +Cc: Chris Wilson
On 22/07/2020 08:55, Umesh Nerlige Ramappa wrote:
> From: Piotr Maciejewski <piotr.maciejewski@intel.com>
>
> i915 used to support time based sampling mode which is good for overall
> system monitoring, but is not enough for query mode used to measure a
> single draw call or dispatch. Gen9-Gen11 are using current i915 perf
> implementation for query, but Gen12+ requires a new approach for query
> based on triggered reports within oa buffer.
>
> Triggering reports into the OA buffer is achieved by writing into a
> a trigger register. Optionally an unused counter/register is set with a
> marker value such that a triggered report can be identified in the OA
> buffer. Reports are usually triggered at the start and end of work that
> is measured.
>
> Since OA buffer is large and queries can be frequent, an efficient way
> to look for triggered reports is required. By knowing the current head
> and tail offsets into the OA buffer, it is easier to determine the
> locality of the reports of interest.
>
> Current perf OA interface does not expose head/tail information to the
> user and it filters out invalid reports before sending data to user.
> Also considering limited size of user buffer used during a query,
> creating a 1:1 copy of the OA buffer at the user space added undesired
> complexity.
>
> The solution was to map the OA buffer to user space provided
>
> (1) that it is accessed from a privileged user.
> (2) OA report filtering is not used.
>
> These 2 conditions would satisfy the safety criteria that the current
> perf interface addresses.
>
> To enable the query:
> - Add an ioctl to expose head and tail to the user
> - Add an ioctl to return size and offset of the OA buffer
> - Map the OA buffer to the user space
>
> v2:
> - Improve commit message (Chris)
> - Do not mmap based on gem object filp. Instead, use perf_fd and support
> mmap syscall (Chris)
> - Pass non-zero offset in mmap to enforce the right object is
> mapped (Chris)
> - Do not expose gpu_address (Chris)
> - Verify start and length of vma for page alignment (Lionel)
> - Move SQNTL config out (Lionel)
>
> v3: (Chris)
> - Omit redundant checks
> - Return VM_FAULT_SIGBUS is old stream is closed
> - Maintain reference counts to stream in vm_open and vm_close
> - Use switch to identify object to be mapped
>
> v4: Call kref_put on closing perf fd (Chris)
>
> Signed-off-by: Piotr Maciejewski <piotr.maciejewski@intel.com>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
> drivers/gpu/drm/i915/gem/i915_gem_mman.h | 2 +
> drivers/gpu/drm/i915/i915_perf.c | 211 ++++++++++++++++++++++-
> drivers/gpu/drm/i915/i915_perf_types.h | 17 ++
> include/uapi/drm/i915_drm.h | 32 ++++
> 5 files changed, 261 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> index b23368529a40..7c4b9b0c334b 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> @@ -204,7 +204,7 @@ compute_partial_view(const struct drm_i915_gem_object *obj,
> return view;
> }
>
> -static vm_fault_t i915_error_to_vmf_fault(int err)
> +vm_fault_t i915_error_to_vmf_fault(int err)
> {
> switch (err) {
> default:
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.h b/drivers/gpu/drm/i915/gem/i915_gem_mman.h
> index efee9e0d2508..1190a3a228ea 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.h
> @@ -29,4 +29,6 @@ void i915_gem_object_release_mmap_gtt(struct drm_i915_gem_object *obj);
>
> void i915_gem_object_release_mmap_offset(struct drm_i915_gem_object *obj);
>
> +vm_fault_t i915_error_to_vmf_fault(int err);
> +
> #endif
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 2f23aad12c60..331c3f9c59e2 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -192,10 +192,12 @@
> */
>
> #include <linux/anon_inodes.h>
> +#include <linux/mman.h>
> #include <linux/sizes.h>
> #include <linux/uuid.h>
>
> #include "gem/i915_gem_context.h"
> +#include "gem/i915_gem_mman.h"
> #include "gt/intel_engine_pm.h"
> #include "gt/intel_engine_user.h"
> #include "gt/intel_gt.h"
> @@ -378,6 +380,24 @@ static struct ctl_table_header *sysctl_header;
>
> static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
>
> +static void free_stream(struct kref *kref)
> +{
> + struct i915_perf_stream *stream =
> + container_of(kref, typeof(*stream), refcount);
> +
> + kfree(stream);
> +}
> +
> +static void perf_stream_get(struct i915_perf_stream *stream)
> +{
> + kref_get(&stream->refcount);
> +}
> +
> +static void perf_stream_put(struct i915_perf_stream *stream)
> +{
> + kref_put(&stream->refcount, free_stream);
> +}
> +
> void i915_oa_config_release(struct kref *ref)
> {
> struct i915_oa_config *oa_config =
> @@ -434,6 +454,30 @@ static u32 gen7_oa_hw_tail_read(struct i915_perf_stream *stream)
> return oastatus1 & GEN7_OASTATUS1_TAIL_MASK;
> }
>
> +static u32 gen12_oa_hw_head_read(struct i915_perf_stream *stream)
> +{
> + struct intel_uncore *uncore = stream->uncore;
> +
> + return intel_uncore_read(uncore, GEN12_OAG_OAHEADPTR) &
> + GEN12_OAG_OAHEADPTR_MASK;
> +}
> +
> +static u32 gen8_oa_hw_head_read(struct i915_perf_stream *stream)
> +{
> + struct intel_uncore *uncore = stream->uncore;
> +
> + return intel_uncore_read(uncore, GEN8_OAHEADPTR) &
> + GEN8_OAHEADPTR_MASK;
> +}
> +
> +static u32 gen7_oa_hw_head_read(struct i915_perf_stream *stream)
> +{
> + struct intel_uncore *uncore = stream->uncore;
> + u32 oastatus2 = intel_uncore_read(uncore, GEN7_OASTATUS2);
> +
> + return oastatus2 & GEN7_OASTATUS2_HEAD_MASK;
> +}
> +
> /**
> * oa_buffer_check_unlocked - check for data and update tail ptr state
> * @stream: i915 stream instance
> @@ -2934,6 +2978,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
> stream->poll_check_timer.function = oa_poll_check_timer_cb;
> init_waitqueue_head(&stream->poll_wq);
> spin_lock_init(&stream->oa_buffer.ptr_lock);
> + kref_init(&stream->refcount);
>
> return 0;
>
> @@ -3214,6 +3259,69 @@ static long i915_perf_config_locked(struct i915_perf_stream *stream,
> return ret;
> }
>
> +/**
> + * i915_perf_oa_buffer_head_tail_locked - head and tail of the OA buffer
> + * @stream: i915 perf stream
> + * @arg: pointer to oa buffer head and tail filled by this function.
> + */
> +static int i915_perf_oa_buffer_head_tail_locked(struct i915_perf_stream *stream,
> + unsigned long arg)
> +{
> + struct drm_i915_perf_oa_buffer_head_tail ht;
> + void __user *output = (void __user *)arg;
> + u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
> +
> + if (i915_perf_stream_paranoid && !perfmon_capable()) {
> + DRM_DEBUG("Insufficient privileges to access OA buffer info\n");
> + return -EACCES;
> + }
> +
> + if (!output)
> + return -EINVAL;
> +
> + memset(&ht, 0, sizeof(ht));
> +
> + ht.head = stream->perf->ops.oa_hw_head_read(stream) - gtt_offset;
> + ht.tail = stream->perf->ops.oa_hw_tail_read(stream) - gtt_offset;
> +
> + if (copy_to_user(output, &ht, sizeof(ht)))
> + return -EFAULT;
> +
> + return 0;
> +}
> +
> +#define I915_PERF_OA_BUFFER_MMAP_OFFSET 1
> +
> +/**
> + * i915_perf_oa_buffer_info_locked - size and offset of the OA buffer
> + * @stream: i915 perf stream
> + * @arg: pointer to oa buffer info filled by this function.
> + */
> +static int i915_perf_oa_buffer_info_locked(struct i915_perf_stream *stream,
> + unsigned long arg)
> +{
> + struct drm_i915_perf_oa_buffer_info info;
> + void __user *output = (void __user *)arg;
> +
> + if (i915_perf_stream_paranoid && !perfmon_capable()) {
> + DRM_DEBUG("Insufficient privileges to access OA buffer info\n");
> + return -EACCES;
> + }
> +
> + if (!output)
> + return -EINVAL;
> +
> + memset(&info, 0, sizeof(info));
> +
> + info.size = stream->oa_buffer.vma->size;
> + info.offset = I915_PERF_OA_BUFFER_MMAP_OFFSET * PAGE_SIZE;
> +
> + if (copy_to_user(output, &info, sizeof(info)))
> + return -EFAULT;
> +
> + return 0;
> +}
> +
> /**
> * i915_perf_ioctl - support ioctl() usage with i915 perf stream FDs
> * @stream: An i915 perf stream
> @@ -3239,6 +3347,10 @@ static long i915_perf_ioctl_locked(struct i915_perf_stream *stream,
> return 0;
> case I915_PERF_IOCTL_CONFIG:
> return i915_perf_config_locked(stream, arg);
> + case I915_PERF_IOCTL_GET_OA_BUFFER_INFO:
> + return i915_perf_oa_buffer_info_locked(stream, arg);
> + case I915_PERF_IOCTL_GET_OA_BUFFER_HEAD_TAIL:
> + return i915_perf_oa_buffer_head_tail_locked(stream, arg);
> }
>
> return -EINVAL;
> @@ -3291,7 +3403,8 @@ static void i915_perf_destroy_locked(struct i915_perf_stream *stream)
> if (stream->ctx)
> i915_gem_context_put(stream->ctx);
>
> - kfree(stream);
> + WRITE_ONCE(stream->closed, true);
> + perf_stream_put(stream);
> }
>
> /**
> @@ -3314,12 +3427,98 @@ static int i915_perf_release(struct inode *inode, struct file *file)
> i915_perf_destroy_locked(stream);
> mutex_unlock(&perf->lock);
>
> + unmap_mapping_range(file->f_mapping, 0, OA_BUFFER_SIZE, 1);
> +
> /* Release the reference the perf stream kept on the driver. */
> drm_dev_put(&perf->i915->drm);
>
> return 0;
> }
>
> +static void vm_open_oa(struct vm_area_struct *vma)
> +{
> + struct i915_perf_stream *stream = vma->vm_private_data;
> +
> + GEM_BUG_ON(!stream);
> + perf_stream_get(stream);
> +}
> +
> +static void vm_close_oa(struct vm_area_struct *vma)
> +{
> + struct i915_perf_stream *stream = vma->vm_private_data;
> +
> + GEM_BUG_ON(!stream);
> + perf_stream_put(stream);
> +}
> +
> +static vm_fault_t vm_fault_oa(struct vm_fault *vmf)
> +{
> + struct vm_area_struct *vma = vmf->vma;
> + struct i915_perf_stream *stream = vma->vm_private_data;
> + struct i915_perf *perf = stream->perf;
> + struct drm_i915_gem_object *obj = stream->oa_buffer.vma->obj;
I could be wrong because I'm not that knowledgeable on memory mapping stuff.
But it seems if close() is called on the i915-perf stream before this
function is called. stream->oa_buffer.vma might be NULL/freed.
It seems like we need an additional reference on the
stream->oa_buffer.vma->obj taken within the perf->lock in this function.
If you notice the stream->oa_buffer.vaddr is NULL inside the lock, it
means a close() call won the race with the mmap() and you should return
VM_FAULT_SIGBUS.
We should drop that reference taken on stream->oa_buffer.vma->obj when
the memory is unmapped.
Maybe Chris can confirm if that sounds correct.
-Lionel
> + int err;
> + bool closed;
> +
> + mutex_lock(&perf->lock);
> + closed = READ_ONCE(stream->closed);
> + mutex_unlock(&perf->lock);
> +
> + if (closed)
> + return VM_FAULT_SIGBUS;
> +
> + err = i915_gem_object_pin_pages(obj);
> + if (err)
> + goto out;
> +
> + err = remap_io_sg(vma,
> + vma->vm_start, vma->vm_end - vma->vm_start,
> + obj->mm.pages->sgl, -1);
> +
> + i915_gem_object_unpin_pages(obj);
> +
> +out:
> + return i915_error_to_vmf_fault(err);
> +}
> +
> +static const struct vm_operations_struct vm_ops_oa = {
> + .open = vm_open_oa,
> + .close = vm_close_oa,
> + .fault = vm_fault_oa,
> +};
> +
> +int i915_perf_mmap(struct file *file, struct vm_area_struct *vma)
> +{
> + struct i915_perf_stream *stream = file->private_data;
> +
> + if (i915_perf_stream_paranoid && !perfmon_capable()) {
> + DRM_DEBUG("Insufficient privileges to map OA buffer\n");
> + return -EACCES;
> + }
> +
> + switch (vma->vm_pgoff) {
> + case I915_PERF_OA_BUFFER_MMAP_OFFSET:
> + if (vma->vm_end - vma->vm_start > OA_BUFFER_SIZE)
> + return -EINVAL;
> +
> + if (vma->vm_flags & VM_WRITE)
> + return -EINVAL;
> +
> + break;
> +
> + default:
> + return -EINVAL;
> + }
> +
> + vma->vm_flags &= ~(VM_MAYWRITE | VM_MAYEXEC | VM_MAYSHARE);
> + vma->vm_flags |= VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP;
> + vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
> + vma->vm_private_data = stream;
> + vma->vm_ops = &vm_ops_oa;
> + vm_open_oa(vma);
> +
> + return 0;
> +}
>
> static const struct file_operations fops = {
> .owner = THIS_MODULE,
> @@ -3332,6 +3531,7 @@ static const struct file_operations fops = {
> * to handle 32bits compatibility.
> */
> .compat_ioctl = i915_perf_ioctl,
> + .mmap = i915_perf_mmap,
> };
>
>
> @@ -4260,6 +4460,7 @@ void i915_perf_init(struct drm_i915_private *i915)
> perf->ops.oa_disable = gen7_oa_disable;
> perf->ops.read = gen7_oa_read;
> perf->ops.oa_hw_tail_read = gen7_oa_hw_tail_read;
> + perf->ops.oa_hw_head_read = gen7_oa_hw_head_read;
>
> perf->oa_formats = hsw_oa_formats;
> } else if (HAS_LOGICAL_RING_CONTEXTS(i915)) {
> @@ -4291,6 +4492,7 @@ void i915_perf_init(struct drm_i915_private *i915)
> perf->ops.enable_metric_set = gen8_enable_metric_set;
> perf->ops.disable_metric_set = gen8_disable_metric_set;
> perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
> + perf->ops.oa_hw_head_read = gen8_oa_hw_head_read;
>
> if (IS_GEN(i915, 8)) {
> perf->ctx_oactxctrl_offset = 0x120;
> @@ -4318,6 +4520,7 @@ void i915_perf_init(struct drm_i915_private *i915)
> perf->ops.enable_metric_set = gen8_enable_metric_set;
> perf->ops.disable_metric_set = gen10_disable_metric_set;
> perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
> + perf->ops.oa_hw_head_read = gen8_oa_hw_head_read;
>
> if (IS_GEN(i915, 10)) {
> perf->ctx_oactxctrl_offset = 0x128;
> @@ -4342,6 +4545,7 @@ void i915_perf_init(struct drm_i915_private *i915)
> perf->ops.enable_metric_set = gen12_enable_metric_set;
> perf->ops.disable_metric_set = gen12_disable_metric_set;
> perf->ops.oa_hw_tail_read = gen12_oa_hw_tail_read;
> + perf->ops.oa_hw_head_read = gen12_oa_hw_head_read;
>
> perf->ctx_flexeu0_offset = 0;
> perf->ctx_oactxctrl_offset = 0x144;
> @@ -4456,8 +4660,11 @@ int i915_perf_ioctl_version(void)
> *
> * - OA buffer head/tail/status/buffer registers for read only
> * - OA counters A18, A19, A20 for read/write
> + *
> + * 8: Added an option to map oa buffer at umd driver level and trigger
> + * oa reports within oa buffer from command buffer.
> */
> - return 7;
> + return 8;
> }
>
> #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> diff --git a/drivers/gpu/drm/i915/i915_perf_types.h b/drivers/gpu/drm/i915/i915_perf_types.h
> index a36a455ae336..2efbe35c5fa9 100644
> --- a/drivers/gpu/drm/i915/i915_perf_types.h
> +++ b/drivers/gpu/drm/i915/i915_perf_types.h
> @@ -311,6 +311,18 @@ struct i915_perf_stream {
> * buffer should be checked for available data.
> */
> u64 poll_oa_period;
> +
> + /**
> + * @closed: Open or closed state of the stream.
> + * True if stream is closed.
> + */
> + bool closed;
> +
> + /**
> + * @refcount: References to the mapped OA buffer managed by this
> + * stream.
> + */
> + struct kref refcount;
> };
>
> /**
> @@ -377,6 +389,11 @@ struct i915_oa_ops {
> * generations.
> */
> u32 (*oa_hw_tail_read)(struct i915_perf_stream *stream);
> +
> + /**
> + * @oa_hw_head_read: read the OA head pointer register
> + */
> + u32 (*oa_hw_head_read)(struct i915_perf_stream *stream);
> };
>
> struct i915_perf {
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 00546062e023..2042f6339182 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -2048,6 +2048,38 @@ struct drm_i915_perf_open_param {
> */
> #define I915_PERF_IOCTL_CONFIG _IO('i', 0x2)
>
> +/**
> + * Returns OA buffer properties to be used with mmap.
> + *
> + * This ioctl is available in perf revision 8.
> + */
> +#define I915_PERF_IOCTL_GET_OA_BUFFER_INFO _IO('i', 0x3)
> +
> +/**
> + * OA buffer size and offset.
> + */
> +struct drm_i915_perf_oa_buffer_info {
> + __u32 size;
> + __u32 offset;
> + __u64 reserved[4];
> +};
> +
> +/**
> + * Returns current position of OA buffer head and tail.
> + *
> + * This ioctl is available in perf revision 8.
> + */
> +#define I915_PERF_IOCTL_GET_OA_BUFFER_HEAD_TAIL _IO('i', 0x4)
> +
> +/**
> + * OA buffer head and tail.
> + */
> +struct drm_i915_perf_oa_buffer_head_tail {
> + __u32 head;
> + __u32 tail;
> + __u64 reserved[4];
> +};
> +
> /**
> * Common to all i915 perf records
> */
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915/perf: Map OA buffer to user space for gen12 performance query
2020-07-23 9:31 ` Lionel Landwerlin
@ 2020-07-23 23:48 ` Umesh Nerlige Ramappa
0 siblings, 0 replies; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2020-07-23 23:48 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: intel-gfx, Chris Wilson
On Thu, Jul 23, 2020 at 12:31:30PM +0300, Lionel Landwerlin wrote:
>On 22/07/2020 08:55, Umesh Nerlige Ramappa wrote:
>>From: Piotr Maciejewski <piotr.maciejewski@intel.com>
>>
>>i915 used to support time based sampling mode which is good for overall
>>system monitoring, but is not enough for query mode used to measure a
>>single draw call or dispatch. Gen9-Gen11 are using current i915 perf
>>implementation for query, but Gen12+ requires a new approach for query
>>based on triggered reports within oa buffer.
>>
>>Triggering reports into the OA buffer is achieved by writing into a
>>a trigger register. Optionally an unused counter/register is set with a
>>marker value such that a triggered report can be identified in the OA
>>buffer. Reports are usually triggered at the start and end of work that
>>is measured.
>>
>>Since OA buffer is large and queries can be frequent, an efficient way
>>to look for triggered reports is required. By knowing the current head
>>and tail offsets into the OA buffer, it is easier to determine the
>>locality of the reports of interest.
>>
>>Current perf OA interface does not expose head/tail information to the
>>user and it filters out invalid reports before sending data to user.
>>Also considering limited size of user buffer used during a query,
>>creating a 1:1 copy of the OA buffer at the user space added undesired
>>complexity.
>>
>>The solution was to map the OA buffer to user space provided
>>
>>(1) that it is accessed from a privileged user.
>>(2) OA report filtering is not used.
>>
>>These 2 conditions would satisfy the safety criteria that the current
>>perf interface addresses.
>>
>>To enable the query:
>>- Add an ioctl to expose head and tail to the user
>>- Add an ioctl to return size and offset of the OA buffer
>>- Map the OA buffer to the user space
>>
>>v2:
>>- Improve commit message (Chris)
>>- Do not mmap based on gem object filp. Instead, use perf_fd and support
>> mmap syscall (Chris)
>>- Pass non-zero offset in mmap to enforce the right object is
>> mapped (Chris)
>>- Do not expose gpu_address (Chris)
>>- Verify start and length of vma for page alignment (Lionel)
>>- Move SQNTL config out (Lionel)
>>
>>v3: (Chris)
>>- Omit redundant checks
>>- Return VM_FAULT_SIGBUS is old stream is closed
>>- Maintain reference counts to stream in vm_open and vm_close
>>- Use switch to identify object to be mapped
>>
>>v4: Call kref_put on closing perf fd (Chris)
>>
>>Signed-off-by: Piotr Maciejewski <piotr.maciejewski@intel.com>
>>Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>>---
>> drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
>> drivers/gpu/drm/i915/gem/i915_gem_mman.h | 2 +
>> drivers/gpu/drm/i915/i915_perf.c | 211 ++++++++++++++++++++++-
>> drivers/gpu/drm/i915/i915_perf_types.h | 17 ++
>> include/uapi/drm/i915_drm.h | 32 ++++
>> 5 files changed, 261 insertions(+), 3 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
>>index b23368529a40..7c4b9b0c334b 100644
>>--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
>>+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
>>@@ -204,7 +204,7 @@ compute_partial_view(const struct drm_i915_gem_object *obj,
>> return view;
>> }
>>-static vm_fault_t i915_error_to_vmf_fault(int err)
>>+vm_fault_t i915_error_to_vmf_fault(int err)
>> {
>> switch (err) {
>> default:
>>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.h b/drivers/gpu/drm/i915/gem/i915_gem_mman.h
>>index efee9e0d2508..1190a3a228ea 100644
>>--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.h
>>+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.h
>>@@ -29,4 +29,6 @@ void i915_gem_object_release_mmap_gtt(struct drm_i915_gem_object *obj);
>> void i915_gem_object_release_mmap_offset(struct drm_i915_gem_object *obj);
>>+vm_fault_t i915_error_to_vmf_fault(int err);
>>+
>> #endif
>>diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
>>index 2f23aad12c60..331c3f9c59e2 100644
>>--- a/drivers/gpu/drm/i915/i915_perf.c
>>+++ b/drivers/gpu/drm/i915/i915_perf.c
>>@@ -192,10 +192,12 @@
>> */
>> #include <linux/anon_inodes.h>
>>+#include <linux/mman.h>
>> #include <linux/sizes.h>
>> #include <linux/uuid.h>
>> #include "gem/i915_gem_context.h"
>>+#include "gem/i915_gem_mman.h"
>> #include "gt/intel_engine_pm.h"
>> #include "gt/intel_engine_user.h"
>> #include "gt/intel_gt.h"
>>@@ -378,6 +380,24 @@ static struct ctl_table_header *sysctl_header;
>> static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
>>+static void free_stream(struct kref *kref)
>>+{
>>+ struct i915_perf_stream *stream =
>>+ container_of(kref, typeof(*stream), refcount);
>>+
>>+ kfree(stream);
>>+}
>>+
>>+static void perf_stream_get(struct i915_perf_stream *stream)
>>+{
>>+ kref_get(&stream->refcount);
>>+}
>>+
>>+static void perf_stream_put(struct i915_perf_stream *stream)
>>+{
>>+ kref_put(&stream->refcount, free_stream);
>>+}
>>+
>> void i915_oa_config_release(struct kref *ref)
>> {
>> struct i915_oa_config *oa_config =
>>@@ -434,6 +454,30 @@ static u32 gen7_oa_hw_tail_read(struct i915_perf_stream *stream)
>> return oastatus1 & GEN7_OASTATUS1_TAIL_MASK;
>> }
>>+static u32 gen12_oa_hw_head_read(struct i915_perf_stream *stream)
>>+{
>>+ struct intel_uncore *uncore = stream->uncore;
>>+
>>+ return intel_uncore_read(uncore, GEN12_OAG_OAHEADPTR) &
>>+ GEN12_OAG_OAHEADPTR_MASK;
>>+}
>>+
>>+static u32 gen8_oa_hw_head_read(struct i915_perf_stream *stream)
>>+{
>>+ struct intel_uncore *uncore = stream->uncore;
>>+
>>+ return intel_uncore_read(uncore, GEN8_OAHEADPTR) &
>>+ GEN8_OAHEADPTR_MASK;
>>+}
>>+
>>+static u32 gen7_oa_hw_head_read(struct i915_perf_stream *stream)
>>+{
>>+ struct intel_uncore *uncore = stream->uncore;
>>+ u32 oastatus2 = intel_uncore_read(uncore, GEN7_OASTATUS2);
>>+
>>+ return oastatus2 & GEN7_OASTATUS2_HEAD_MASK;
>>+}
>>+
>> /**
>> * oa_buffer_check_unlocked - check for data and update tail ptr state
>> * @stream: i915 stream instance
>>@@ -2934,6 +2978,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
>> stream->poll_check_timer.function = oa_poll_check_timer_cb;
>> init_waitqueue_head(&stream->poll_wq);
>> spin_lock_init(&stream->oa_buffer.ptr_lock);
>>+ kref_init(&stream->refcount);
>> return 0;
>>@@ -3214,6 +3259,69 @@ static long i915_perf_config_locked(struct i915_perf_stream *stream,
>> return ret;
>> }
>>+/**
>>+ * i915_perf_oa_buffer_head_tail_locked - head and tail of the OA buffer
>>+ * @stream: i915 perf stream
>>+ * @arg: pointer to oa buffer head and tail filled by this function.
>>+ */
>>+static int i915_perf_oa_buffer_head_tail_locked(struct i915_perf_stream *stream,
>>+ unsigned long arg)
>>+{
>>+ struct drm_i915_perf_oa_buffer_head_tail ht;
>>+ void __user *output = (void __user *)arg;
>>+ u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
>>+
>>+ if (i915_perf_stream_paranoid && !perfmon_capable()) {
>>+ DRM_DEBUG("Insufficient privileges to access OA buffer info\n");
>>+ return -EACCES;
>>+ }
>>+
>>+ if (!output)
>>+ return -EINVAL;
>>+
>>+ memset(&ht, 0, sizeof(ht));
>>+
>>+ ht.head = stream->perf->ops.oa_hw_head_read(stream) - gtt_offset;
>>+ ht.tail = stream->perf->ops.oa_hw_tail_read(stream) - gtt_offset;
>>+
>>+ if (copy_to_user(output, &ht, sizeof(ht)))
>>+ return -EFAULT;
>>+
>>+ return 0;
>>+}
>>+
>>+#define I915_PERF_OA_BUFFER_MMAP_OFFSET 1
>>+
>>+/**
>>+ * i915_perf_oa_buffer_info_locked - size and offset of the OA buffer
>>+ * @stream: i915 perf stream
>>+ * @arg: pointer to oa buffer info filled by this function.
>>+ */
>>+static int i915_perf_oa_buffer_info_locked(struct i915_perf_stream *stream,
>>+ unsigned long arg)
>>+{
>>+ struct drm_i915_perf_oa_buffer_info info;
>>+ void __user *output = (void __user *)arg;
>>+
>>+ if (i915_perf_stream_paranoid && !perfmon_capable()) {
>>+ DRM_DEBUG("Insufficient privileges to access OA buffer info\n");
>>+ return -EACCES;
>>+ }
>>+
>>+ if (!output)
>>+ return -EINVAL;
>>+
>>+ memset(&info, 0, sizeof(info));
>>+
>>+ info.size = stream->oa_buffer.vma->size;
>>+ info.offset = I915_PERF_OA_BUFFER_MMAP_OFFSET * PAGE_SIZE;
>>+
>>+ if (copy_to_user(output, &info, sizeof(info)))
>>+ return -EFAULT;
>>+
>>+ return 0;
>>+}
>>+
>> /**
>> * i915_perf_ioctl - support ioctl() usage with i915 perf stream FDs
>> * @stream: An i915 perf stream
>>@@ -3239,6 +3347,10 @@ static long i915_perf_ioctl_locked(struct i915_perf_stream *stream,
>> return 0;
>> case I915_PERF_IOCTL_CONFIG:
>> return i915_perf_config_locked(stream, arg);
>>+ case I915_PERF_IOCTL_GET_OA_BUFFER_INFO:
>>+ return i915_perf_oa_buffer_info_locked(stream, arg);
>>+ case I915_PERF_IOCTL_GET_OA_BUFFER_HEAD_TAIL:
>>+ return i915_perf_oa_buffer_head_tail_locked(stream, arg);
>> }
>> return -EINVAL;
>>@@ -3291,7 +3403,8 @@ static void i915_perf_destroy_locked(struct i915_perf_stream *stream)
>> if (stream->ctx)
>> i915_gem_context_put(stream->ctx);
>>- kfree(stream);
>>+ WRITE_ONCE(stream->closed, true);
>>+ perf_stream_put(stream);
>> }
>> /**
>>@@ -3314,12 +3427,98 @@ static int i915_perf_release(struct inode *inode, struct file *file)
>> i915_perf_destroy_locked(stream);
>> mutex_unlock(&perf->lock);
>>+ unmap_mapping_range(file->f_mapping, 0, OA_BUFFER_SIZE, 1);
>>+
>> /* Release the reference the perf stream kept on the driver. */
>> drm_dev_put(&perf->i915->drm);
>> return 0;
>> }
>>+static void vm_open_oa(struct vm_area_struct *vma)
>>+{
>>+ struct i915_perf_stream *stream = vma->vm_private_data;
>>+
>>+ GEM_BUG_ON(!stream);
>>+ perf_stream_get(stream);
>>+}
>>+
>>+static void vm_close_oa(struct vm_area_struct *vma)
>>+{
>>+ struct i915_perf_stream *stream = vma->vm_private_data;
>>+
>>+ GEM_BUG_ON(!stream);
>>+ perf_stream_put(stream);
>>+}
>>+
>>+static vm_fault_t vm_fault_oa(struct vm_fault *vmf)
>>+{
>>+ struct vm_area_struct *vma = vmf->vma;
>>+ struct i915_perf_stream *stream = vma->vm_private_data;
>>+ struct i915_perf *perf = stream->perf;
>>+ struct drm_i915_gem_object *obj = stream->oa_buffer.vma->obj;
>
>I could be wrong because I'm not that knowledgeable on memory mapping stuff.
>
>But it seems if close() is called on the i915-perf stream before this
>function is called. stream->oa_buffer.vma might be NULL/freed.
>
>
>It seems like we need an additional reference on the
>stream->oa_buffer.vma->obj taken within the perf->lock in this
>function. If you notice the stream->oa_buffer.vaddr is NULL inside the
>lock, it means a close() call won the race with the mmap() and you
>should return VM_FAULT_SIGBUS.
>
>We should drop that reference taken on stream->oa_buffer.vma->obj when
>the memory is unmapped.
>
Based on trying to trigger a SIGBUS with igt, this is what I found:
do_mmap (somewhere in mmap_region) takes a reference to the file. If oa
buffer is mapped successfully, close(perf_fd) does not call
i915_perf_release, but close(perf_fd) followed by unmap() or vice-versa
will end up calling i915_perf_release.
forking did not help either because fork itself takes a reference to the
perf_fd.
Once unmap is called, the vma should be gone anyways, so I don't expect
the kernel to call vm_fault. I would say the kernel is really smart and
wouldn't let it happen :), but maybe Chris can confirm.
Thanks,
Umesh
>
>Maybe Chris can confirm if that sounds correct.
>
>
>-Lionel
>
>
>>+ int err;
>>+ bool closed;
>>+
>>+ mutex_lock(&perf->lock);
>>+ closed = READ_ONCE(stream->closed);
>>+ mutex_unlock(&perf->lock);
>>+
>>+ if (closed)
>>+ return VM_FAULT_SIGBUS;
>>+
>>+ err = i915_gem_object_pin_pages(obj);
>>+ if (err)
>>+ goto out;
>>+
>>+ err = remap_io_sg(vma,
>>+ vma->vm_start, vma->vm_end - vma->vm_start,
>>+ obj->mm.pages->sgl, -1);
>>+
>>+ i915_gem_object_unpin_pages(obj);
>>+
>>+out:
>>+ return i915_error_to_vmf_fault(err);
>>+}
>>+
>>+static const struct vm_operations_struct vm_ops_oa = {
>>+ .open = vm_open_oa,
>>+ .close = vm_close_oa,
>>+ .fault = vm_fault_oa,
>>+};
>>+
>>+int i915_perf_mmap(struct file *file, struct vm_area_struct *vma)
>>+{
>>+ struct i915_perf_stream *stream = file->private_data;
>>+
>>+ if (i915_perf_stream_paranoid && !perfmon_capable()) {
>>+ DRM_DEBUG("Insufficient privileges to map OA buffer\n");
>>+ return -EACCES;
>>+ }
>>+
>>+ switch (vma->vm_pgoff) {
>>+ case I915_PERF_OA_BUFFER_MMAP_OFFSET:
>>+ if (vma->vm_end - vma->vm_start > OA_BUFFER_SIZE)
>>+ return -EINVAL;
>>+
>>+ if (vma->vm_flags & VM_WRITE)
>>+ return -EINVAL;
>>+
>>+ break;
>>+
>>+ default:
>>+ return -EINVAL;
>>+ }
>>+
>>+ vma->vm_flags &= ~(VM_MAYWRITE | VM_MAYEXEC | VM_MAYSHARE);
>>+ vma->vm_flags |= VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP;
>>+ vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
>>+ vma->vm_private_data = stream;
>>+ vma->vm_ops = &vm_ops_oa;
>>+ vm_open_oa(vma);
>>+
>>+ return 0;
>>+}
>> static const struct file_operations fops = {
>> .owner = THIS_MODULE,
>>@@ -3332,6 +3531,7 @@ static const struct file_operations fops = {
>> * to handle 32bits compatibility.
>> */
>> .compat_ioctl = i915_perf_ioctl,
>>+ .mmap = i915_perf_mmap,
>> };
>>@@ -4260,6 +4460,7 @@ void i915_perf_init(struct drm_i915_private *i915)
>> perf->ops.oa_disable = gen7_oa_disable;
>> perf->ops.read = gen7_oa_read;
>> perf->ops.oa_hw_tail_read = gen7_oa_hw_tail_read;
>>+ perf->ops.oa_hw_head_read = gen7_oa_hw_head_read;
>> perf->oa_formats = hsw_oa_formats;
>> } else if (HAS_LOGICAL_RING_CONTEXTS(i915)) {
>>@@ -4291,6 +4492,7 @@ void i915_perf_init(struct drm_i915_private *i915)
>> perf->ops.enable_metric_set = gen8_enable_metric_set;
>> perf->ops.disable_metric_set = gen8_disable_metric_set;
>> perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
>>+ perf->ops.oa_hw_head_read = gen8_oa_hw_head_read;
>> if (IS_GEN(i915, 8)) {
>> perf->ctx_oactxctrl_offset = 0x120;
>>@@ -4318,6 +4520,7 @@ void i915_perf_init(struct drm_i915_private *i915)
>> perf->ops.enable_metric_set = gen8_enable_metric_set;
>> perf->ops.disable_metric_set = gen10_disable_metric_set;
>> perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
>>+ perf->ops.oa_hw_head_read = gen8_oa_hw_head_read;
>> if (IS_GEN(i915, 10)) {
>> perf->ctx_oactxctrl_offset = 0x128;
>>@@ -4342,6 +4545,7 @@ void i915_perf_init(struct drm_i915_private *i915)
>> perf->ops.enable_metric_set = gen12_enable_metric_set;
>> perf->ops.disable_metric_set = gen12_disable_metric_set;
>> perf->ops.oa_hw_tail_read = gen12_oa_hw_tail_read;
>>+ perf->ops.oa_hw_head_read = gen12_oa_hw_head_read;
>> perf->ctx_flexeu0_offset = 0;
>> perf->ctx_oactxctrl_offset = 0x144;
>>@@ -4456,8 +4660,11 @@ int i915_perf_ioctl_version(void)
>> *
>> * - OA buffer head/tail/status/buffer registers for read only
>> * - OA counters A18, A19, A20 for read/write
>>+ *
>>+ * 8: Added an option to map oa buffer at umd driver level and trigger
>>+ * oa reports within oa buffer from command buffer.
>> */
>>- return 7;
>>+ return 8;
>> }
>> #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
>>diff --git a/drivers/gpu/drm/i915/i915_perf_types.h b/drivers/gpu/drm/i915/i915_perf_types.h
>>index a36a455ae336..2efbe35c5fa9 100644
>>--- a/drivers/gpu/drm/i915/i915_perf_types.h
>>+++ b/drivers/gpu/drm/i915/i915_perf_types.h
>>@@ -311,6 +311,18 @@ struct i915_perf_stream {
>> * buffer should be checked for available data.
>> */
>> u64 poll_oa_period;
>>+
>>+ /**
>>+ * @closed: Open or closed state of the stream.
>>+ * True if stream is closed.
>>+ */
>>+ bool closed;
>>+
>>+ /**
>>+ * @refcount: References to the mapped OA buffer managed by this
>>+ * stream.
>>+ */
>>+ struct kref refcount;
>> };
>> /**
>>@@ -377,6 +389,11 @@ struct i915_oa_ops {
>> * generations.
>> */
>> u32 (*oa_hw_tail_read)(struct i915_perf_stream *stream);
>>+
>>+ /**
>>+ * @oa_hw_head_read: read the OA head pointer register
>>+ */
>>+ u32 (*oa_hw_head_read)(struct i915_perf_stream *stream);
>> };
>> struct i915_perf {
>>diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
>>index 00546062e023..2042f6339182 100644
>>--- a/include/uapi/drm/i915_drm.h
>>+++ b/include/uapi/drm/i915_drm.h
>>@@ -2048,6 +2048,38 @@ struct drm_i915_perf_open_param {
>> */
>> #define I915_PERF_IOCTL_CONFIG _IO('i', 0x2)
>>+/**
>>+ * Returns OA buffer properties to be used with mmap.
>>+ *
>>+ * This ioctl is available in perf revision 8.
>>+ */
>>+#define I915_PERF_IOCTL_GET_OA_BUFFER_INFO _IO('i', 0x3)
>>+
>>+/**
>>+ * OA buffer size and offset.
>>+ */
>>+struct drm_i915_perf_oa_buffer_info {
>>+ __u32 size;
>>+ __u32 offset;
>>+ __u64 reserved[4];
>>+};
>>+
>>+/**
>>+ * Returns current position of OA buffer head and tail.
>>+ *
>>+ * This ioctl is available in perf revision 8.
>>+ */
>>+#define I915_PERF_IOCTL_GET_OA_BUFFER_HEAD_TAIL _IO('i', 0x4)
>>+
>>+/**
>>+ * OA buffer head and tail.
>>+ */
>>+struct drm_i915_perf_oa_buffer_head_tail {
>>+ __u32 head;
>>+ __u32 tail;
>>+ __u64 reserved[4];
>>+};
>>+
>> /**
>> * Common to all i915 perf records
>> */
>
>
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* [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers
2020-08-20 18:01 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
@ 2020-08-20 18:01 ` Umesh Nerlige Ramappa
0 siblings, 0 replies; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2020-08-20 18:01 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
It is useful to have markers in the OA reports to identify triggered
reports. Whitelist some OA counters that can be used as markers.
A triggered report can be found faster if we can sample the HW tail and
head registers when the report was triggered. Whitelist OA buffer
specific registers.
v2:
- Bump up the perf revision (Lionel)
- Use indexing for counters (Lionel)
- Fix selftest for oa ticking register (Umesh)
v3: Pardon whitelisted registers for selftest (Umesh)
v4:
- Document whitelisted registers (Lionel)
- Fix live isolated whitelist for OA regs (Umesh)
v5:
- Free up whitelist slots. Remove GPU_TICKS and A20 counter (Piotr)
- Whitelist registers only if perf_stream_paranoid is set to 0 (Jon)
v6: Move oa whitelist array to i915_perf (Chris)
Signed-off-by: Piotr Maciejewski <piotr.maciejewski@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 18 +++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 7443654ef842..562154d3fd49 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1350,11 +1350,19 @@ free_noa_wait(struct i915_perf_stream *stream)
static struct i915_whitelist_reg gen9_oa_wl_regs[] = {
{ OAREPORTTRIG2, RING_FORCE_TO_NONPRIV_ACCESS_RW },
{ OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_ACCESS_RW },
+ { OA_PERF_COUNTER_A(18), RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
+ { GEN8_OASTATUS, RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
};
static struct i915_whitelist_reg gen12_oa_wl_regs[] = {
{ GEN12_OAG_OAREPORTTRIG2, RING_FORCE_TO_NONPRIV_ACCESS_RW },
{ GEN12_OAG_OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_ACCESS_RW },
+ { GEN12_OAG_PERF_COUNTER_A(18), RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
+ { GEN12_OAG_OASTATUS, RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
};
static void intel_engine_apply_oa_whitelist(struct i915_perf_stream *stream)
@@ -4511,8 +4519,16 @@ int i915_perf_ioctl_version(void)
* into the OA buffer. This applies only to gen8+. The feature can
* only be accessed if perf_stream_paranoid is set to 0 by privileged
* user.
+ *
+ * 7: Whitelist below OA registers for user to identify the location of
+ * triggered reports in the OA buffer. This applies only to gen8+.
+ * The feature can only be accessed if perf_stream_paranoid is set to
+ * 0 by privileged user.
+ *
+ * - OA buffer head/tail/status/buffer registers for read only
+ * - OA counters A18, A19, A20 for read/write
*/
- return 6;
+ return 7;
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a6a63303d3d5..e40f6fc86a74 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -974,6 +974,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
+/* Performance counters registers */
+#define OA_PERF_COUNTER_A(idx) _MMIO(0x2800 + 8 * (idx))
+#define OA_PERF_COUNTER_A_UPPER(idx) _MMIO(0x2800 + 8 * (idx) + 4)
+
+/* Gen12 Performance counters registers */
+#define GEN12_OAG_PERF_COUNTER_A(idx) _MMIO(0xD980 + 8 * (idx))
+#define GEN12_OAG_PERF_COUNTER_A_UPPER(idx) _MMIO(0xD980 + 8 * (idx) + 4)
+
/* Same layout as OASTARTTRIGX */
#define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
#define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
--
2.20.1
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers
2020-08-04 17:11 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
@ 2020-08-04 17:11 ` Umesh Nerlige Ramappa
0 siblings, 0 replies; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2020-08-04 17:11 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
It is useful to have markers in the OA reports to identify triggered
reports. Whitelist some OA counters that can be used as markers.
A triggered report can be found faster if we can sample the HW tail and
head registers when the report was triggered. Whitelist OA buffer
specific registers.
v2:
- Bump up the perf revision (Lionel)
- Use indexing for counters (Lionel)
- Fix selftest for oa ticking register (Umesh)
v3: Pardon whitelisted registers for selftest (Umesh)
v4:
- Document whitelisted registers (Lionel)
- Fix live isolated whitelist for OA regs (Umesh)
v5:
- Free up whitelist slots. Remove GPU_TICKS and A20 counter (Piotr)
- Whitelist registers only if perf_stream_paranoid is set to 0 (Jon)
v6: Move oa whitelist array to i915_perf (Chris)
Signed-off-by: Piotr Maciejewski <piotr.maciejewski@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 18 +++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 7443654ef842..562154d3fd49 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1350,11 +1350,19 @@ free_noa_wait(struct i915_perf_stream *stream)
static struct i915_whitelist_reg gen9_oa_wl_regs[] = {
{ OAREPORTTRIG2, RING_FORCE_TO_NONPRIV_ACCESS_RW },
{ OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_ACCESS_RW },
+ { OA_PERF_COUNTER_A(18), RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
+ { GEN8_OASTATUS, RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
};
static struct i915_whitelist_reg gen12_oa_wl_regs[] = {
{ GEN12_OAG_OAREPORTTRIG2, RING_FORCE_TO_NONPRIV_ACCESS_RW },
{ GEN12_OAG_OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_ACCESS_RW },
+ { GEN12_OAG_PERF_COUNTER_A(18), RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
+ { GEN12_OAG_OASTATUS, RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
};
static void intel_engine_apply_oa_whitelist(struct i915_perf_stream *stream)
@@ -4511,8 +4519,16 @@ int i915_perf_ioctl_version(void)
* into the OA buffer. This applies only to gen8+. The feature can
* only be accessed if perf_stream_paranoid is set to 0 by privileged
* user.
+ *
+ * 7: Whitelist below OA registers for user to identify the location of
+ * triggered reports in the OA buffer. This applies only to gen8+.
+ * The feature can only be accessed if perf_stream_paranoid is set to
+ * 0 by privileged user.
+ *
+ * - OA buffer head/tail/status/buffer registers for read only
+ * - OA counters A18, A19, A20 for read/write
*/
- return 6;
+ return 7;
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5e09acbd1406..497f75e70f8a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -974,6 +974,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
+/* Performance counters registers */
+#define OA_PERF_COUNTER_A(idx) _MMIO(0x2800 + 8 * (idx))
+#define OA_PERF_COUNTER_A_UPPER(idx) _MMIO(0x2800 + 8 * (idx) + 4)
+
+/* Gen12 Performance counters registers */
+#define GEN12_OAG_PERF_COUNTER_A(idx) _MMIO(0xD980 + 8 * (idx))
+#define GEN12_OAG_PERF_COUNTER_A_UPPER(idx) _MMIO(0xD980 + 8 * (idx) + 4)
+
/* Same layout as OASTARTTRIGX */
#define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
#define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
--
2.20.1
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers
2020-07-31 23:58 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
@ 2020-07-31 23:58 ` Umesh Nerlige Ramappa
0 siblings, 0 replies; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2020-07-31 23:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
It is useful to have markers in the OA reports to identify triggered
reports. Whitelist some OA counters that can be used as markers.
A triggered report can be found faster if we can sample the HW tail and
head registers when the report was triggered. Whitelist OA buffer
specific registers.
v2:
- Bump up the perf revision (Lionel)
- Use indexing for counters (Lionel)
- Fix selftest for oa ticking register (Umesh)
v3: Pardon whitelisted registers for selftest (Umesh)
v4:
- Document whitelisted registers (Lionel)
- Fix live isolated whitelist for OA regs (Umesh)
v5:
- Free up whitelist slots. Remove GPU_TICKS and A20 counter (Piotr)
- Whitelist registers only if perf_stream_paranoid is set to 0 (Jon)
v6: Move oa whitelist array to i915_perf (Chris)
Signed-off-by: Piotr Maciejewski <piotr.maciejewski@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 18 +++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 7443654ef842..562154d3fd49 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1350,11 +1350,19 @@ free_noa_wait(struct i915_perf_stream *stream)
static struct i915_whitelist_reg gen9_oa_wl_regs[] = {
{ OAREPORTTRIG2, RING_FORCE_TO_NONPRIV_ACCESS_RW },
{ OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_ACCESS_RW },
+ { OA_PERF_COUNTER_A(18), RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
+ { GEN8_OASTATUS, RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
};
static struct i915_whitelist_reg gen12_oa_wl_regs[] = {
{ GEN12_OAG_OAREPORTTRIG2, RING_FORCE_TO_NONPRIV_ACCESS_RW },
{ GEN12_OAG_OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_ACCESS_RW },
+ { GEN12_OAG_PERF_COUNTER_A(18), RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
+ { GEN12_OAG_OASTATUS, RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
};
static void intel_engine_apply_oa_whitelist(struct i915_perf_stream *stream)
@@ -4511,8 +4519,16 @@ int i915_perf_ioctl_version(void)
* into the OA buffer. This applies only to gen8+. The feature can
* only be accessed if perf_stream_paranoid is set to 0 by privileged
* user.
+ *
+ * 7: Whitelist below OA registers for user to identify the location of
+ * triggered reports in the OA buffer. This applies only to gen8+.
+ * The feature can only be accessed if perf_stream_paranoid is set to
+ * 0 by privileged user.
+ *
+ * - OA buffer head/tail/status/buffer registers for read only
+ * - OA counters A18, A19, A20 for read/write
*/
- return 6;
+ return 7;
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5e09acbd1406..497f75e70f8a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -974,6 +974,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
+/* Performance counters registers */
+#define OA_PERF_COUNTER_A(idx) _MMIO(0x2800 + 8 * (idx))
+#define OA_PERF_COUNTER_A_UPPER(idx) _MMIO(0x2800 + 8 * (idx) + 4)
+
+/* Gen12 Performance counters registers */
+#define GEN12_OAG_PERF_COUNTER_A(idx) _MMIO(0xD980 + 8 * (idx))
+#define GEN12_OAG_PERF_COUNTER_A_UPPER(idx) _MMIO(0xD980 + 8 * (idx) + 4)
+
/* Same layout as OASTARTTRIGX */
#define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
#define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
--
2.20.1
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers
2020-07-31 14:46 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
@ 2020-07-31 14:46 ` Umesh Nerlige Ramappa
0 siblings, 0 replies; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2020-07-31 14:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
It is useful to have markers in the OA reports to identify triggered
reports. Whitelist some OA counters that can be used as markers.
A triggered report can be found faster if we can sample the HW tail and
head registers when the report was triggered. Whitelist OA buffer
specific registers.
v2:
- Bump up the perf revision (Lionel)
- Use indexing for counters (Lionel)
- Fix selftest for oa ticking register (Umesh)
v3: Pardon whitelisted registers for selftest (Umesh)
v4:
- Document whitelisted registers (Lionel)
- Fix live isolated whitelist for OA regs (Umesh)
v5:
- Free up whitelist slots. Remove GPU_TICKS and A20 counter (Piotr)
- Whitelist registers only if perf_stream_paranoid is set to 0 (Jon)
v6: Move oa whitelist array to i915_perf (Chris)
Signed-off-by: Piotr Maciejewski <piotr.maciejewski@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 18 +++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 7443654ef842..562154d3fd49 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1350,11 +1350,19 @@ free_noa_wait(struct i915_perf_stream *stream)
static struct i915_whitelist_reg gen9_oa_wl_regs[] = {
{ OAREPORTTRIG2, RING_FORCE_TO_NONPRIV_ACCESS_RW },
{ OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_ACCESS_RW },
+ { OA_PERF_COUNTER_A(18), RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
+ { GEN8_OASTATUS, RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
};
static struct i915_whitelist_reg gen12_oa_wl_regs[] = {
{ GEN12_OAG_OAREPORTTRIG2, RING_FORCE_TO_NONPRIV_ACCESS_RW },
{ GEN12_OAG_OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_ACCESS_RW },
+ { GEN12_OAG_PERF_COUNTER_A(18), RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
+ { GEN12_OAG_OASTATUS, RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
};
static void intel_engine_apply_oa_whitelist(struct i915_perf_stream *stream)
@@ -4511,8 +4519,16 @@ int i915_perf_ioctl_version(void)
* into the OA buffer. This applies only to gen8+. The feature can
* only be accessed if perf_stream_paranoid is set to 0 by privileged
* user.
+ *
+ * 7: Whitelist below OA registers for user to identify the location of
+ * triggered reports in the OA buffer. This applies only to gen8+.
+ * The feature can only be accessed if perf_stream_paranoid is set to
+ * 0 by privileged user.
+ *
+ * - OA buffer head/tail/status/buffer registers for read only
+ * - OA counters A18, A19, A20 for read/write
*/
- return 6;
+ return 7;
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5e09acbd1406..497f75e70f8a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -974,6 +974,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
+/* Performance counters registers */
+#define OA_PERF_COUNTER_A(idx) _MMIO(0x2800 + 8 * (idx))
+#define OA_PERF_COUNTER_A_UPPER(idx) _MMIO(0x2800 + 8 * (idx) + 4)
+
+/* Gen12 Performance counters registers */
+#define GEN12_OAG_PERF_COUNTER_A(idx) _MMIO(0xD980 + 8 * (idx))
+#define GEN12_OAG_PERF_COUNTER_A_UPPER(idx) _MMIO(0xD980 + 8 * (idx) + 4)
+
/* Same layout as OASTARTTRIGX */
#define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
#define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
--
2.20.1
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers
2020-07-31 6:07 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
@ 2020-07-31 6:07 ` Umesh Nerlige Ramappa
0 siblings, 0 replies; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2020-07-31 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
It is useful to have markers in the OA reports to identify triggered
reports. Whitelist some OA counters that can be used as markers.
A triggered report can be found faster if we can sample the HW tail and
head registers when the report was triggered. Whitelist OA buffer
specific registers.
v2:
- Bump up the perf revision (Lionel)
- Use indexing for counters (Lionel)
- Fix selftest for oa ticking register (Umesh)
v3: Pardon whitelisted registers for selftest (Umesh)
v4:
- Document whitelisted registers (Lionel)
- Fix live isolated whitelist for OA regs (Umesh)
v5:
- Free up whitelist slots. Remove GPU_TICKS and A20 counter (Piotr)
- Whitelist registers only if perf_stream_paranoid is set to 0 (Jon)
v6: Move oa whitelist array to i915_perf (Chris)
Signed-off-by: Piotr Maciejewski <piotr.maciejewski@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 18 +++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index d644cb5118d6..8ff502719dfd 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1350,11 +1350,19 @@ free_noa_wait(struct i915_perf_stream *stream)
static struct i915_whitelist_reg gen9_oa_wl_regs[] = {
{ OAREPORTTRIG2, RING_FORCE_TO_NONPRIV_ACCESS_RW },
{ OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_ACCESS_RW },
+ { OA_PERF_COUNTER_A(18), RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
+ { GEN8_OASTATUS, RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
};
static struct i915_whitelist_reg gen12_oa_wl_regs[] = {
{ GEN12_OAG_OAREPORTTRIG2, RING_FORCE_TO_NONPRIV_ACCESS_RW },
{ GEN12_OAG_OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_ACCESS_RW },
+ { GEN12_OAG_PERF_COUNTER_A(18), RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
+ { GEN12_OAG_OASTATUS, RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
};
static void intel_engine_apply_oa_whitelist(struct i915_perf_stream *stream)
@@ -4515,8 +4523,16 @@ int i915_perf_ioctl_version(void)
* into the OA buffer. This applies only to gen8+. The feature can
* only be accessed if perf_stream_paranoid is set to 0 by privileged
* user.
+ *
+ * 7: Whitelist below OA registers for user to identify the location of
+ * triggered reports in the OA buffer. This applies only to gen8+.
+ * The feature can only be accessed if perf_stream_paranoid is set to
+ * 0 by privileged user.
+ *
+ * - OA buffer head/tail/status/buffer registers for read only
+ * - OA counters A18, A19, A20 for read/write
*/
- return 6;
+ return 7;
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 377339399458..6b93a5686cba 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -974,6 +974,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
+/* Performance counters registers */
+#define OA_PERF_COUNTER_A(idx) _MMIO(0x2800 + 8 * (idx))
+#define OA_PERF_COUNTER_A_UPPER(idx) _MMIO(0x2800 + 8 * (idx) + 4)
+
+/* Gen12 Performance counters registers */
+#define GEN12_OAG_PERF_COUNTER_A(idx) _MMIO(0xD980 + 8 * (idx))
+#define GEN12_OAG_PERF_COUNTER_A_UPPER(idx) _MMIO(0xD980 + 8 * (idx) + 4)
+
/* Same layout as OASTARTTRIGX */
#define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
#define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
--
2.20.1
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers
2020-07-30 23:02 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
@ 2020-07-30 23:02 ` Umesh Nerlige Ramappa
0 siblings, 0 replies; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2020-07-30 23:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
It is useful to have markers in the OA reports to identify triggered
reports. Whitelist some OA counters that can be used as markers.
A triggered report can be found faster if we can sample the HW tail and
head registers when the report was triggered. Whitelist OA buffer
specific registers.
v2:
- Bump up the perf revision (Lionel)
- Use indexing for counters (Lionel)
- Fix selftest for oa ticking register (Umesh)
v3: Pardon whitelisted registers for selftest (Umesh)
v4:
- Document whitelisted registers (Lionel)
- Fix live isolated whitelist for OA regs (Umesh)
v5:
- Free up whitelist slots. Remove GPU_TICKS and A20 counter (Piotr)
- Whitelist registers only if perf_stream_paranoid is set to 0 (Jon)
v6: Move oa whitelist array to i915_perf (Chris)
Signed-off-by: Piotr Maciejewski <piotr.maciejewski@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 18 +++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index d644cb5118d6..8ff502719dfd 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1350,11 +1350,19 @@ free_noa_wait(struct i915_perf_stream *stream)
static struct i915_whitelist_reg gen9_oa_wl_regs[] = {
{ OAREPORTTRIG2, RING_FORCE_TO_NONPRIV_ACCESS_RW },
{ OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_ACCESS_RW },
+ { OA_PERF_COUNTER_A(18), RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
+ { GEN8_OASTATUS, RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
};
static struct i915_whitelist_reg gen12_oa_wl_regs[] = {
{ GEN12_OAG_OAREPORTTRIG2, RING_FORCE_TO_NONPRIV_ACCESS_RW },
{ GEN12_OAG_OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_ACCESS_RW },
+ { GEN12_OAG_PERF_COUNTER_A(18), RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
+ { GEN12_OAG_OASTATUS, RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
};
static void intel_engine_apply_oa_whitelist(struct i915_perf_stream *stream)
@@ -4515,8 +4523,16 @@ int i915_perf_ioctl_version(void)
* into the OA buffer. This applies only to gen8+. The feature can
* only be accessed if perf_stream_paranoid is set to 0 by privileged
* user.
+ *
+ * 7: Whitelist below OA registers for user to identify the location of
+ * triggered reports in the OA buffer. This applies only to gen8+.
+ * The feature can only be accessed if perf_stream_paranoid is set to
+ * 0 by privileged user.
+ *
+ * - OA buffer head/tail/status/buffer registers for read only
+ * - OA counters A18, A19, A20 for read/write
*/
- return 6;
+ return 7;
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 377339399458..6b93a5686cba 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -974,6 +974,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
+/* Performance counters registers */
+#define OA_PERF_COUNTER_A(idx) _MMIO(0x2800 + 8 * (idx))
+#define OA_PERF_COUNTER_A_UPPER(idx) _MMIO(0x2800 + 8 * (idx) + 4)
+
+/* Gen12 Performance counters registers */
+#define GEN12_OAG_PERF_COUNTER_A(idx) _MMIO(0xD980 + 8 * (idx))
+#define GEN12_OAG_PERF_COUNTER_A_UPPER(idx) _MMIO(0xD980 + 8 * (idx) + 4)
+
/* Same layout as OASTARTTRIGX */
#define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
#define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
--
2.20.1
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers
2020-07-24 8:55 ` Chris Wilson
@ 2020-07-27 19:34 ` Umesh Nerlige Ramappa
0 siblings, 0 replies; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2020-07-27 19:34 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Fri, Jul 24, 2020 at 09:55:35AM +0100, Chris Wilson wrote:
>Quoting Umesh Nerlige Ramappa (2020-07-24 01:19:00)
>> From: Piotr Maciejewski <piotr.maciejewski@intel.com>
>>
>> It is useful to have markers in the OA reports to identify triggered
>> reports. Whitelist some OA counters that can be used as markers.
>>
>> A triggered report can be found faster if we can sample the HW tail and
>> head registers when the report was triggered. Whitelist OA buffer
>> specific registers.
>>
>> v2:
>> - Bump up the perf revision (Lionel)
>> - Use indexing for counters (Lionel)
>> - Fix selftest for oa ticking register (Umesh)
>>
>> v3: Pardon whitelisted registers for selftest (Umesh)
>>
>> v4:
>> - Document whitelisted registers (Lionel)
>> - Fix live isolated whitelist for OA regs (Umesh)
>>
>> Signed-off-by: Piotr Maciejewski <piotr.maciejewski@intel.com>
>> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 34 +++++++++++++++++++
>> .../gpu/drm/i915/gt/selftest_workarounds.c | 30 +++++++++++++++-
>> drivers/gpu/drm/i915/i915_perf.c | 8 ++++-
>> drivers/gpu/drm/i915/i915_reg.h | 10 ++++++
>> 4 files changed, 80 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index a72ebfd115e5..c950d07beec3 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -1392,6 +1392,23 @@ static void gen9_whitelist_build_performance_counters(struct i915_wa_list *w)
>> /* OA buffer trigger report 2/6 used by performance query */
>> whitelist_reg(w, OAREPORTTRIG2);
>> whitelist_reg(w, OAREPORTTRIG6);
>> +
>> + /* Performance counters A18-20 used by tbs marker query */
>> + whitelist_reg_ext(w, OA_PERF_COUNTER_A(18),
>> + RING_FORCE_TO_NONPRIV_ACCESS_RW |
>> + RING_FORCE_TO_NONPRIV_RANGE_4);
>> +
>> + whitelist_reg(w, OA_PERF_COUNTER_A(20));
>> + whitelist_reg(w, OA_PERF_COUNTER_A_UPPER(20));
>> +
>> + /* Read access to gpu ticks */
>> + whitelist_reg_ext(w, GEN8_GPU_TICKS,
>> + RING_FORCE_TO_NONPRIV_ACCESS_RD);
>> +
>> + /* Read access to: oa status, head, tail, buffer settings */
>> + whitelist_reg_ext(w, GEN8_OASTATUS,
>> + RING_FORCE_TO_NONPRIV_ACCESS_RD |
>> + RING_FORCE_TO_NONPRIV_RANGE_4);
>
>Great. This completely fills RING_MAX_NONPRIV_SLOTS, with over half the
>slots going to OA. That does not seem sustainable.
>
>I did not think the extended whitelist settings were available before
>cml.
Looks like we can remove A20, A20_upper and gpu ticks to free up 3
slots. Will post that in the new series. Hoping that will do for now.
Thanks,
Umesh
>-Chris
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers
2020-07-24 0:19 ` [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers Umesh Nerlige Ramappa
@ 2020-07-24 8:55 ` Chris Wilson
2020-07-27 19:34 ` Umesh Nerlige Ramappa
0 siblings, 1 reply; 21+ messages in thread
From: Chris Wilson @ 2020-07-24 8:55 UTC (permalink / raw)
To: Umesh Nerlige Ramappa, intel-gfx
Quoting Umesh Nerlige Ramappa (2020-07-24 01:19:00)
> From: Piotr Maciejewski <piotr.maciejewski@intel.com>
>
> It is useful to have markers in the OA reports to identify triggered
> reports. Whitelist some OA counters that can be used as markers.
>
> A triggered report can be found faster if we can sample the HW tail and
> head registers when the report was triggered. Whitelist OA buffer
> specific registers.
>
> v2:
> - Bump up the perf revision (Lionel)
> - Use indexing for counters (Lionel)
> - Fix selftest for oa ticking register (Umesh)
>
> v3: Pardon whitelisted registers for selftest (Umesh)
>
> v4:
> - Document whitelisted registers (Lionel)
> - Fix live isolated whitelist for OA regs (Umesh)
>
> Signed-off-by: Piotr Maciejewski <piotr.maciejewski@intel.com>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 34 +++++++++++++++++++
> .../gpu/drm/i915/gt/selftest_workarounds.c | 30 +++++++++++++++-
> drivers/gpu/drm/i915/i915_perf.c | 8 ++++-
> drivers/gpu/drm/i915/i915_reg.h | 10 ++++++
> 4 files changed, 80 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index a72ebfd115e5..c950d07beec3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1392,6 +1392,23 @@ static void gen9_whitelist_build_performance_counters(struct i915_wa_list *w)
> /* OA buffer trigger report 2/6 used by performance query */
> whitelist_reg(w, OAREPORTTRIG2);
> whitelist_reg(w, OAREPORTTRIG6);
> +
> + /* Performance counters A18-20 used by tbs marker query */
> + whitelist_reg_ext(w, OA_PERF_COUNTER_A(18),
> + RING_FORCE_TO_NONPRIV_ACCESS_RW |
> + RING_FORCE_TO_NONPRIV_RANGE_4);
> +
> + whitelist_reg(w, OA_PERF_COUNTER_A(20));
> + whitelist_reg(w, OA_PERF_COUNTER_A_UPPER(20));
> +
> + /* Read access to gpu ticks */
> + whitelist_reg_ext(w, GEN8_GPU_TICKS,
> + RING_FORCE_TO_NONPRIV_ACCESS_RD);
> +
> + /* Read access to: oa status, head, tail, buffer settings */
> + whitelist_reg_ext(w, GEN8_OASTATUS,
> + RING_FORCE_TO_NONPRIV_ACCESS_RD |
> + RING_FORCE_TO_NONPRIV_RANGE_4);
Great. This completely fills RING_MAX_NONPRIV_SLOTS, with over half the
slots going to OA. That does not seem sustainable.
I did not think the extended whitelist settings were available before
cml.
-Chris
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^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers
2020-07-24 0:18 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
@ 2020-07-24 0:19 ` Umesh Nerlige Ramappa
2020-07-24 8:55 ` Chris Wilson
0 siblings, 1 reply; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2020-07-24 0:19 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
From: Piotr Maciejewski <piotr.maciejewski@intel.com>
It is useful to have markers in the OA reports to identify triggered
reports. Whitelist some OA counters that can be used as markers.
A triggered report can be found faster if we can sample the HW tail and
head registers when the report was triggered. Whitelist OA buffer
specific registers.
v2:
- Bump up the perf revision (Lionel)
- Use indexing for counters (Lionel)
- Fix selftest for oa ticking register (Umesh)
v3: Pardon whitelisted registers for selftest (Umesh)
v4:
- Document whitelisted registers (Lionel)
- Fix live isolated whitelist for OA regs (Umesh)
Signed-off-by: Piotr Maciejewski <piotr.maciejewski@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 34 +++++++++++++++++++
.../gpu/drm/i915/gt/selftest_workarounds.c | 30 +++++++++++++++-
drivers/gpu/drm/i915/i915_perf.c | 8 ++++-
drivers/gpu/drm/i915/i915_reg.h | 10 ++++++
4 files changed, 80 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a72ebfd115e5..c950d07beec3 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1392,6 +1392,23 @@ static void gen9_whitelist_build_performance_counters(struct i915_wa_list *w)
/* OA buffer trigger report 2/6 used by performance query */
whitelist_reg(w, OAREPORTTRIG2);
whitelist_reg(w, OAREPORTTRIG6);
+
+ /* Performance counters A18-20 used by tbs marker query */
+ whitelist_reg_ext(w, OA_PERF_COUNTER_A(18),
+ RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
+
+ whitelist_reg(w, OA_PERF_COUNTER_A(20));
+ whitelist_reg(w, OA_PERF_COUNTER_A_UPPER(20));
+
+ /* Read access to gpu ticks */
+ whitelist_reg_ext(w, GEN8_GPU_TICKS,
+ RING_FORCE_TO_NONPRIV_ACCESS_RD);
+
+ /* Read access to: oa status, head, tail, buffer settings */
+ whitelist_reg_ext(w, GEN8_OASTATUS,
+ RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
}
static void gen12_whitelist_build_performance_counters(struct i915_wa_list *w)
@@ -1399,6 +1416,23 @@ static void gen12_whitelist_build_performance_counters(struct i915_wa_list *w)
/* OA buffer trigger report 2/6 used by performance query */
whitelist_reg(w, GEN12_OAG_OAREPORTTRIG2);
whitelist_reg(w, GEN12_OAG_OAREPORTTRIG6);
+
+ /* Performance counters A18-20 used by tbs marker query */
+ whitelist_reg_ext(w, GEN12_OAG_PERF_COUNTER_A(18),
+ RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
+
+ whitelist_reg(w, GEN12_OAG_PERF_COUNTER_A(20));
+ whitelist_reg(w, GEN12_OAG_PERF_COUNTER_A_UPPER(20));
+
+ /* Read access to gpu ticks */
+ whitelist_reg_ext(w, GEN12_OAG_GPU_TICKS,
+ RING_FORCE_TO_NONPRIV_ACCESS_RD);
+
+ /* Read access to: oa status, head, tail, buffer settings */
+ whitelist_reg_ext(w, GEN12_OAG_OASTATUS,
+ RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
}
static void gen9_whitelist_build(struct i915_wa_list *w)
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index 3b1d3dbcd477..7c2c2be8d212 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -431,6 +431,19 @@ static bool timestamp(const struct intel_engine_cs *engine, u32 reg)
}
}
+static bool oa_gpu_ticks(u32 reg)
+{
+ reg = reg & ~RING_FORCE_TO_NONPRIV_ACCESS_MASK;
+ switch (reg) {
+ case 0x2910:
+ case 0xda90:
+ return true;
+
+ default:
+ return false;
+ }
+}
+
static bool ro_register(u32 reg)
{
if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
@@ -511,7 +524,7 @@ static int check_dirty_whitelist(struct intel_context *ce)
if (wo_register(engine, reg))
continue;
- if (timestamp(engine, reg))
+ if (timestamp(engine, reg) || oa_gpu_ticks(reg))
continue; /* timestamps are expected to autoincrement */
ro_reg = ro_register(reg);
@@ -918,6 +931,9 @@ static bool find_reg(struct drm_i915_private *i915,
{
u32 offset = i915_mmio_reg_offset(reg);
+ /* Clear non priv flags */
+ offset &= RING_FORCE_TO_NONPRIV_ADDRESS_MASK;
+
while (count--) {
if (INTEL_INFO(i915)->gen_mask & tbl->gen_mask &&
i915_mmio_reg_offset(tbl->reg) == offset)
@@ -938,6 +954,12 @@ static bool pardon_reg(struct drm_i915_private *i915, i915_reg_t reg)
{ OAREPORTTRIG6, INTEL_GEN_MASK(8, 11) },
{ GEN12_OAG_OAREPORTTRIG2, INTEL_GEN_MASK(12, 12) },
{ GEN12_OAG_OAREPORTTRIG6, INTEL_GEN_MASK(12, 12) },
+ { OA_PERF_COUNTER_A(18), INTEL_GEN_MASK(8, 11) },
+ { OA_PERF_COUNTER_A(20), INTEL_GEN_MASK(8, 11) },
+ { OA_PERF_COUNTER_A_UPPER(20), INTEL_GEN_MASK(8, 11) },
+ { GEN12_OAG_PERF_COUNTER_A(18), INTEL_GEN_MASK(12, 12) },
+ { GEN12_OAG_PERF_COUNTER_A(20), INTEL_GEN_MASK(12, 12) },
+ { GEN12_OAG_PERF_COUNTER_A_UPPER(20), INTEL_GEN_MASK(12, 12) },
};
return find_reg(i915, reg, pardon, ARRAY_SIZE(pardon));
@@ -964,6 +986,12 @@ static bool writeonly_reg(struct drm_i915_private *i915, i915_reg_t reg)
{ OAREPORTTRIG6, INTEL_GEN_MASK(8, 11) },
{ GEN12_OAG_OAREPORTTRIG2, INTEL_GEN_MASK(12, 12) },
{ GEN12_OAG_OAREPORTTRIG6, INTEL_GEN_MASK(12, 12) },
+ { OA_PERF_COUNTER_A(18), INTEL_GEN_MASK(8, 11) },
+ { OA_PERF_COUNTER_A(20), INTEL_GEN_MASK(8, 11) },
+ { OA_PERF_COUNTER_A_UPPER(20), INTEL_GEN_MASK(8, 11) },
+ { GEN12_OAG_PERF_COUNTER_A(18), INTEL_GEN_MASK(12, 12) },
+ { GEN12_OAG_PERF_COUNTER_A(20), INTEL_GEN_MASK(12, 12) },
+ { GEN12_OAG_PERF_COUNTER_A_UPPER(20), INTEL_GEN_MASK(12, 12) },
};
return find_reg(i915, reg, wo, ARRAY_SIZE(wo));
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 30f6aeb819aa..2f23aad12c60 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4450,8 +4450,14 @@ int i915_perf_ioctl_version(void)
*
* 6: Whitelist OATRIGGER registers to allow user to trigger reports
* into the OA buffer. This applies only to gen8+.
+ *
+ * 7: Whitelist below OA registers for user to identify the location of
+ * triggered reports in the OA buffer. This applies only to gen8+.
+ *
+ * - OA buffer head/tail/status/buffer registers for read only
+ * - OA counters A18, A19, A20 for read/write
*/
- return 6;
+ return 7;
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9cc3e312b6b7..c68dc3f39e62 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -675,6 +675,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
#define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
+#define GEN8_GPU_TICKS _MMIO(0x2910)
#define GEN8_OASTATUS _MMIO(0x2b08)
#define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3)
#define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2)
@@ -733,6 +734,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
#define GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
+#define GEN12_OAG_GPU_TICKS _MMIO(0xda90)
#define GEN12_OAG_OASTATUS _MMIO(0xdafc)
#define GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2)
#define GEN12_OAG_OASTATUS_BUFFER_OVERFLOW (1 << 1)
@@ -974,6 +976,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
+/* Performance counters registers */
+#define OA_PERF_COUNTER_A(idx) _MMIO(0x2800 + 8 * (idx))
+#define OA_PERF_COUNTER_A_UPPER(idx) _MMIO(0x2800 + 8 * (idx) + 4)
+
+/* Gen12 Performance counters registers */
+#define GEN12_OAG_PERF_COUNTER_A(idx) _MMIO(0xD980 + 8 * (idx))
+#define GEN12_OAG_PERF_COUNTER_A_UPPER(idx) _MMIO(0xD980 + 8 * (idx) + 4)
+
/* Same layout as OASTARTTRIGX */
#define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
#define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
--
2.20.1
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers
2020-07-21 2:00 ` [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers Umesh Nerlige Ramappa
@ 2020-07-21 6:03 ` Lionel Landwerlin
0 siblings, 0 replies; 21+ messages in thread
From: Lionel Landwerlin @ 2020-07-21 6:03 UTC (permalink / raw)
To: Umesh Nerlige Ramappa, intel-gfx; +Cc: Chris Wilson
On 21/07/2020 05:00, Umesh Nerlige Ramappa wrote:
> From: Piotr Maciejewski <piotr.maciejewski@intel.com>
>
> It is useful to have markers in the OA reports to identify triggered
> reports. Whitelist some OA counters that can be used as markers.
>
> A triggered report can be found faster if we can sample the HW tail and
> head registers when the report was triggered. Whitelist OA buffer
> specific registers.
>
> v2:
> - Bump up the perf revision (Lionel)
> - Use indexing for counters (Lionel)
> - Fix selftest for oa ticking register (Umesh)
>
> v3: Pardon whitelisted registers for selftest (Umesh)
>
> Signed-off-by: Piotr Maciejewski <piotr.maciejewski@intel.com>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 34 +++++++++++++++++++
> .../gpu/drm/i915/gt/selftest_workarounds.c | 21 +++++++++++-
> drivers/gpu/drm/i915/i915_perf.c | 5 ++-
> drivers/gpu/drm/i915/i915_reg.h | 10 ++++++
> 4 files changed, 68 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 582a2c8cd219..5dfa3177d216 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1370,6 +1370,23 @@ static void gen9_whitelist_build_performance_counters(struct i915_wa_list *w)
> /* OA buffer trigger report 2/6 used by performance query */
> whitelist_reg(w, OAREPORTTRIG2);
> whitelist_reg(w, OAREPORTTRIG6);
> +
> + /* Performance counters A18-20 used by tbs marker query */
> + whitelist_reg_ext(w, OA_PERF_COUNTER_A(18),
> + RING_FORCE_TO_NONPRIV_ACCESS_RW |
> + RING_FORCE_TO_NONPRIV_RANGE_4);
> +
> + whitelist_reg(w, OA_PERF_COUNTER_A(20));
> + whitelist_reg(w, OA_PERF_COUNTER_A_UPPER(20));
> +
> + /* Read access to gpu ticks */
> + whitelist_reg_ext(w, GEN8_GPU_TICKS,
> + RING_FORCE_TO_NONPRIV_ACCESS_RD);
> +
> + /* Read access to: oa status, head, tail, buffer settings */
> + whitelist_reg_ext(w, GEN8_OASTATUS,
> + RING_FORCE_TO_NONPRIV_ACCESS_RD |
> + RING_FORCE_TO_NONPRIV_RANGE_4);
> }
>
> static void gen12_whitelist_build_performance_counters(struct i915_wa_list *w)
> @@ -1377,6 +1394,23 @@ static void gen12_whitelist_build_performance_counters(struct i915_wa_list *w)
> /* OA buffer trigger report 2/6 used by performance query */
> whitelist_reg(w, GEN12_OAG_OAREPORTTRIG2);
> whitelist_reg(w, GEN12_OAG_OAREPORTTRIG6);
> +
> + /* Performance counters A18-20 used by tbs marker query */
> + whitelist_reg_ext(w, GEN12_OAG_PERF_COUNTER_A(18),
> + RING_FORCE_TO_NONPRIV_ACCESS_RW |
> + RING_FORCE_TO_NONPRIV_RANGE_4);
> +
> + whitelist_reg(w, GEN12_OAG_PERF_COUNTER_A(20));
> + whitelist_reg(w, GEN12_OAG_PERF_COUNTER_A_UPPER(20));
> +
> + /* Read access to gpu ticks */
> + whitelist_reg_ext(w, GEN12_OAG_GPU_TICKS,
> + RING_FORCE_TO_NONPRIV_ACCESS_RD);
> +
> + /* Read access to: oa status, head, tail, buffer settings */
> + whitelist_reg_ext(w, GEN12_OAG_OASTATUS,
> + RING_FORCE_TO_NONPRIV_ACCESS_RD |
> + RING_FORCE_TO_NONPRIV_RANGE_4);
> }
>
> static void gen9_whitelist_build(struct i915_wa_list *w)
> diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> index c7d8af9ee34a..c160483c6ccc 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> @@ -431,6 +431,19 @@ static bool timestamp(const struct intel_engine_cs *engine, u32 reg)
> }
> }
>
> +static bool oa_gpu_ticks(u32 reg)
> +{
> + reg = reg & ~RING_FORCE_TO_NONPRIV_ACCESS_MASK;
> + switch (reg) {
> + case 0x2910:
> + case 0xda90:
> + return true;
> +
> + default:
> + return false;
> + }
> +}
> +
> static bool ro_register(u32 reg)
> {
> if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
> @@ -511,7 +524,7 @@ static int check_dirty_whitelist(struct intel_context *ce)
> if (wo_register(engine, reg))
> continue;
>
> - if (timestamp(engine, reg))
> + if (timestamp(engine, reg) || oa_gpu_ticks(reg))
> continue; /* timestamps are expected to autoincrement */
>
> ro_reg = ro_register(reg);
> @@ -938,6 +951,12 @@ static bool pardon_reg(struct drm_i915_private *i915, i915_reg_t reg)
> { OAREPORTTRIG6, INTEL_GEN_MASK(8, 11) },
> { GEN12_OAG_OAREPORTTRIG2, INTEL_GEN_MASK(12, 12) },
> { GEN12_OAG_OAREPORTTRIG6, INTEL_GEN_MASK(12, 12) },
> + { OA_PERF_COUNTER_A(18), INTEL_GEN_MASK(8, 11) },
> + { OA_PERF_COUNTER_A(20), INTEL_GEN_MASK(8, 11) },
> + { OA_PERF_COUNTER_A_UPPER(20), INTEL_GEN_MASK(8, 11) },
> + { GEN12_OAG_PERF_COUNTER_A(18), INTEL_GEN_MASK(12, 12) },
> + { GEN12_OAG_PERF_COUNTER_A(20), INTEL_GEN_MASK(12, 12) },
> + { GEN12_OAG_PERF_COUNTER_A_UPPER(20), INTEL_GEN_MASK(12, 12) },
> };
>
> return find_reg(i915, reg, pardon, ARRAY_SIZE(pardon));
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 30f6aeb819aa..453afeaee0a7 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -4450,8 +4450,11 @@ int i915_perf_ioctl_version(void)
> *
> * 6: Whitelist OATRIGGER registers to allow user to trigger reports
> * into the OA buffer. This applies only to gen8+.
> + *
> + * 7: Whitelist OA buffer head/tail registers for user to identify the
> + * location of triggered reports into the OA buffer.
You can complete the comment a little with :
* whitelisting on OA buffer head/tail/status/buffer registers for
readonly
* whitelisting of 3 global A counter register in read/write
* only applies to gen8+
With that :
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Thanks!
> */
> - return 6;
> + return 7;
> }
>
> #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1638f1282541..eeb41de84a0f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -675,6 +675,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
> #define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
>
> +#define GEN8_GPU_TICKS _MMIO(0x2910)
> #define GEN8_OASTATUS _MMIO(0x2b08)
> #define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3)
> #define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2)
> @@ -733,6 +734,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
> #define GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
>
> +#define GEN12_OAG_GPU_TICKS _MMIO(0xda90)
> #define GEN12_OAG_OASTATUS _MMIO(0xdafc)
> #define GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2)
> #define GEN12_OAG_OASTATUS_BUFFER_OVERFLOW (1 << 1)
> @@ -974,6 +976,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
> #define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
>
> +/* Performance counters registers */
> +#define OA_PERF_COUNTER_A(idx) _MMIO(0x2800 + 8 * (idx))
> +#define OA_PERF_COUNTER_A_UPPER(idx) _MMIO(0x2800 + 8 * (idx) + 4)
> +
> +/* Gen12 Performance counters registers */
> +#define GEN12_OAG_PERF_COUNTER_A(idx) _MMIO(0xD980 + 8 * (idx))
> +#define GEN12_OAG_PERF_COUNTER_A_UPPER(idx) _MMIO(0xD980 + 8 * (idx) + 4)
> +
> /* Same layout as OASTARTTRIGX */
> #define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
> #define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
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^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers
2020-07-21 2:00 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
@ 2020-07-21 2:00 ` Umesh Nerlige Ramappa
2020-07-21 6:03 ` Lionel Landwerlin
0 siblings, 1 reply; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2020-07-21 2:00 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
From: Piotr Maciejewski <piotr.maciejewski@intel.com>
It is useful to have markers in the OA reports to identify triggered
reports. Whitelist some OA counters that can be used as markers.
A triggered report can be found faster if we can sample the HW tail and
head registers when the report was triggered. Whitelist OA buffer
specific registers.
v2:
- Bump up the perf revision (Lionel)
- Use indexing for counters (Lionel)
- Fix selftest for oa ticking register (Umesh)
v3: Pardon whitelisted registers for selftest (Umesh)
Signed-off-by: Piotr Maciejewski <piotr.maciejewski@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 34 +++++++++++++++++++
.../gpu/drm/i915/gt/selftest_workarounds.c | 21 +++++++++++-
drivers/gpu/drm/i915/i915_perf.c | 5 ++-
drivers/gpu/drm/i915/i915_reg.h | 10 ++++++
4 files changed, 68 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 582a2c8cd219..5dfa3177d216 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1370,6 +1370,23 @@ static void gen9_whitelist_build_performance_counters(struct i915_wa_list *w)
/* OA buffer trigger report 2/6 used by performance query */
whitelist_reg(w, OAREPORTTRIG2);
whitelist_reg(w, OAREPORTTRIG6);
+
+ /* Performance counters A18-20 used by tbs marker query */
+ whitelist_reg_ext(w, OA_PERF_COUNTER_A(18),
+ RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
+
+ whitelist_reg(w, OA_PERF_COUNTER_A(20));
+ whitelist_reg(w, OA_PERF_COUNTER_A_UPPER(20));
+
+ /* Read access to gpu ticks */
+ whitelist_reg_ext(w, GEN8_GPU_TICKS,
+ RING_FORCE_TO_NONPRIV_ACCESS_RD);
+
+ /* Read access to: oa status, head, tail, buffer settings */
+ whitelist_reg_ext(w, GEN8_OASTATUS,
+ RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
}
static void gen12_whitelist_build_performance_counters(struct i915_wa_list *w)
@@ -1377,6 +1394,23 @@ static void gen12_whitelist_build_performance_counters(struct i915_wa_list *w)
/* OA buffer trigger report 2/6 used by performance query */
whitelist_reg(w, GEN12_OAG_OAREPORTTRIG2);
whitelist_reg(w, GEN12_OAG_OAREPORTTRIG6);
+
+ /* Performance counters A18-20 used by tbs marker query */
+ whitelist_reg_ext(w, GEN12_OAG_PERF_COUNTER_A(18),
+ RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
+
+ whitelist_reg(w, GEN12_OAG_PERF_COUNTER_A(20));
+ whitelist_reg(w, GEN12_OAG_PERF_COUNTER_A_UPPER(20));
+
+ /* Read access to gpu ticks */
+ whitelist_reg_ext(w, GEN12_OAG_GPU_TICKS,
+ RING_FORCE_TO_NONPRIV_ACCESS_RD);
+
+ /* Read access to: oa status, head, tail, buffer settings */
+ whitelist_reg_ext(w, GEN12_OAG_OASTATUS,
+ RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
}
static void gen9_whitelist_build(struct i915_wa_list *w)
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index c7d8af9ee34a..c160483c6ccc 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -431,6 +431,19 @@ static bool timestamp(const struct intel_engine_cs *engine, u32 reg)
}
}
+static bool oa_gpu_ticks(u32 reg)
+{
+ reg = reg & ~RING_FORCE_TO_NONPRIV_ACCESS_MASK;
+ switch (reg) {
+ case 0x2910:
+ case 0xda90:
+ return true;
+
+ default:
+ return false;
+ }
+}
+
static bool ro_register(u32 reg)
{
if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
@@ -511,7 +524,7 @@ static int check_dirty_whitelist(struct intel_context *ce)
if (wo_register(engine, reg))
continue;
- if (timestamp(engine, reg))
+ if (timestamp(engine, reg) || oa_gpu_ticks(reg))
continue; /* timestamps are expected to autoincrement */
ro_reg = ro_register(reg);
@@ -938,6 +951,12 @@ static bool pardon_reg(struct drm_i915_private *i915, i915_reg_t reg)
{ OAREPORTTRIG6, INTEL_GEN_MASK(8, 11) },
{ GEN12_OAG_OAREPORTTRIG2, INTEL_GEN_MASK(12, 12) },
{ GEN12_OAG_OAREPORTTRIG6, INTEL_GEN_MASK(12, 12) },
+ { OA_PERF_COUNTER_A(18), INTEL_GEN_MASK(8, 11) },
+ { OA_PERF_COUNTER_A(20), INTEL_GEN_MASK(8, 11) },
+ { OA_PERF_COUNTER_A_UPPER(20), INTEL_GEN_MASK(8, 11) },
+ { GEN12_OAG_PERF_COUNTER_A(18), INTEL_GEN_MASK(12, 12) },
+ { GEN12_OAG_PERF_COUNTER_A(20), INTEL_GEN_MASK(12, 12) },
+ { GEN12_OAG_PERF_COUNTER_A_UPPER(20), INTEL_GEN_MASK(12, 12) },
};
return find_reg(i915, reg, pardon, ARRAY_SIZE(pardon));
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 30f6aeb819aa..453afeaee0a7 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4450,8 +4450,11 @@ int i915_perf_ioctl_version(void)
*
* 6: Whitelist OATRIGGER registers to allow user to trigger reports
* into the OA buffer. This applies only to gen8+.
+ *
+ * 7: Whitelist OA buffer head/tail registers for user to identify the
+ * location of triggered reports into the OA buffer.
*/
- return 6;
+ return 7;
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1638f1282541..eeb41de84a0f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -675,6 +675,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
#define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
+#define GEN8_GPU_TICKS _MMIO(0x2910)
#define GEN8_OASTATUS _MMIO(0x2b08)
#define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3)
#define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2)
@@ -733,6 +734,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
#define GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
+#define GEN12_OAG_GPU_TICKS _MMIO(0xda90)
#define GEN12_OAG_OASTATUS _MMIO(0xdafc)
#define GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2)
#define GEN12_OAG_OASTATUS_BUFFER_OVERFLOW (1 << 1)
@@ -974,6 +976,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
+/* Performance counters registers */
+#define OA_PERF_COUNTER_A(idx) _MMIO(0x2800 + 8 * (idx))
+#define OA_PERF_COUNTER_A_UPPER(idx) _MMIO(0x2800 + 8 * (idx) + 4)
+
+/* Gen12 Performance counters registers */
+#define GEN12_OAG_PERF_COUNTER_A(idx) _MMIO(0xD980 + 8 * (idx))
+#define GEN12_OAG_PERF_COUNTER_A_UPPER(idx) _MMIO(0xD980 + 8 * (idx) + 4)
+
/* Same layout as OASTARTTRIGX */
#define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
#define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers
2020-07-18 0:04 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
@ 2020-07-18 0:04 ` Umesh Nerlige Ramappa
0 siblings, 0 replies; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2020-07-18 0:04 UTC (permalink / raw)
To: intel-gfx
From: Piotr Maciejewski <piotr.maciejewski@intel.com>
It is useful to have markers in the OA reports to identify triggered
reports. Whitelist some OA counters that can be used as markers.
A triggered report can be found faster if we can sample the HW tail and
head registers when the report was triggered. Whitelist OA buffer
specific registers.
v2:
- Bump up the perf revision (Lionel)
- Use indexing for counters (Lionel)
- Fix selftest for oa ticking register (Umesh)
Signed-off-by: Piotr Maciejewski <piotr.maciejewski@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 34 +++++++++++++++++++
.../gpu/drm/i915/gt/selftest_workarounds.c | 15 +++++++-
drivers/gpu/drm/i915/i915_perf.c | 5 ++-
drivers/gpu/drm/i915/i915_reg.h | 10 ++++++
4 files changed, 62 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 582a2c8cd219..5dfa3177d216 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1370,6 +1370,23 @@ static void gen9_whitelist_build_performance_counters(struct i915_wa_list *w)
/* OA buffer trigger report 2/6 used by performance query */
whitelist_reg(w, OAREPORTTRIG2);
whitelist_reg(w, OAREPORTTRIG6);
+
+ /* Performance counters A18-20 used by tbs marker query */
+ whitelist_reg_ext(w, OA_PERF_COUNTER_A(18),
+ RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
+
+ whitelist_reg(w, OA_PERF_COUNTER_A(20));
+ whitelist_reg(w, OA_PERF_COUNTER_A_UPPER(20));
+
+ /* Read access to gpu ticks */
+ whitelist_reg_ext(w, GEN8_GPU_TICKS,
+ RING_FORCE_TO_NONPRIV_ACCESS_RD);
+
+ /* Read access to: oa status, head, tail, buffer settings */
+ whitelist_reg_ext(w, GEN8_OASTATUS,
+ RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
}
static void gen12_whitelist_build_performance_counters(struct i915_wa_list *w)
@@ -1377,6 +1394,23 @@ static void gen12_whitelist_build_performance_counters(struct i915_wa_list *w)
/* OA buffer trigger report 2/6 used by performance query */
whitelist_reg(w, GEN12_OAG_OAREPORTTRIG2);
whitelist_reg(w, GEN12_OAG_OAREPORTTRIG6);
+
+ /* Performance counters A18-20 used by tbs marker query */
+ whitelist_reg_ext(w, GEN12_OAG_PERF_COUNTER_A(18),
+ RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
+
+ whitelist_reg(w, GEN12_OAG_PERF_COUNTER_A(20));
+ whitelist_reg(w, GEN12_OAG_PERF_COUNTER_A_UPPER(20));
+
+ /* Read access to gpu ticks */
+ whitelist_reg_ext(w, GEN12_OAG_GPU_TICKS,
+ RING_FORCE_TO_NONPRIV_ACCESS_RD);
+
+ /* Read access to: oa status, head, tail, buffer settings */
+ whitelist_reg_ext(w, GEN12_OAG_OASTATUS,
+ RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
}
static void gen9_whitelist_build(struct i915_wa_list *w)
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index febc9e6692ba..5e0e839928f9 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -431,6 +431,19 @@ static bool timestamp(const struct intel_engine_cs *engine, u32 reg)
}
}
+static bool oa_gpu_ticks(u32 reg)
+{
+ reg = reg & ~RING_FORCE_TO_NONPRIV_ACCESS_MASK;
+ switch (reg) {
+ case 0x2910:
+ case 0xda90:
+ return true;
+
+ default:
+ return false;
+ }
+}
+
static bool ro_register(u32 reg)
{
if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
@@ -511,7 +524,7 @@ static int check_dirty_whitelist(struct intel_context *ce)
if (wo_register(engine, reg))
continue;
- if (timestamp(engine, reg))
+ if (timestamp(engine, reg) || oa_gpu_ticks(reg))
continue; /* timestamps are expected to autoincrement */
ro_reg = ro_register(reg);
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 1a72565d1928..15f31c250ca9 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4445,8 +4445,11 @@ int i915_perf_ioctl_version(void)
*
* 6: Whitelist OATRIGGER registers to allow user to trigger reports
* into the OA buffer.
+ *
+ * 7: Whitelist OA buffer head/tail registers for user to identify the
+ * location of triggered reports into the OA buffer.
*/
- return 6;
+ return 7;
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1638f1282541..eeb41de84a0f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -675,6 +675,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
#define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
+#define GEN8_GPU_TICKS _MMIO(0x2910)
#define GEN8_OASTATUS _MMIO(0x2b08)
#define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3)
#define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2)
@@ -733,6 +734,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
#define GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
+#define GEN12_OAG_GPU_TICKS _MMIO(0xda90)
#define GEN12_OAG_OASTATUS _MMIO(0xdafc)
#define GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2)
#define GEN12_OAG_OASTATUS_BUFFER_OVERFLOW (1 << 1)
@@ -974,6 +976,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
+/* Performance counters registers */
+#define OA_PERF_COUNTER_A(idx) _MMIO(0x2800 + 8 * (idx))
+#define OA_PERF_COUNTER_A_UPPER(idx) _MMIO(0x2800 + 8 * (idx) + 4)
+
+/* Gen12 Performance counters registers */
+#define GEN12_OAG_PERF_COUNTER_A(idx) _MMIO(0xD980 + 8 * (idx))
+#define GEN12_OAG_PERF_COUNTER_A_UPPER(idx) _MMIO(0xD980 + 8 * (idx) + 4)
+
/* Same layout as OASTARTTRIGX */
#define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
#define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
--
2.20.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
end of thread, other threads:[~2020-08-20 18:02 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-22 5:55 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-07-22 5:55 ` [Intel-gfx] [PATCH 1/4] drm/i915/perf: Ensure observation logic is not clock gated Umesh Nerlige Ramappa
2020-07-22 5:55 ` [Intel-gfx] [PATCH 2/4] drm/i915/perf: Whitelist OA report trigger registers Umesh Nerlige Ramappa
2020-07-22 5:55 ` [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers Umesh Nerlige Ramappa
2020-07-22 5:55 ` [Intel-gfx] [PATCH 4/4] drm/i915/perf: Map OA buffer to user space for gen12 performance query Umesh Nerlige Ramappa
2020-07-23 9:31 ` Lionel Landwerlin
2020-07-23 23:48 ` Umesh Nerlige Ramappa
2020-07-22 6:27 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Allow privileged user to map the OA buffer (rev4) Patchwork
2020-07-22 6:48 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2020-08-20 18:01 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-08-20 18:01 ` [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers Umesh Nerlige Ramappa
2020-08-04 17:11 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-08-04 17:11 ` [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers Umesh Nerlige Ramappa
2020-07-31 23:58 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-07-31 23:58 ` [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers Umesh Nerlige Ramappa
2020-07-31 14:46 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-07-31 14:46 ` [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers Umesh Nerlige Ramappa
2020-07-31 6:07 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-07-31 6:07 ` [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers Umesh Nerlige Ramappa
2020-07-30 23:02 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-07-30 23:02 ` [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers Umesh Nerlige Ramappa
2020-07-24 0:18 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-07-24 0:19 ` [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers Umesh Nerlige Ramappa
2020-07-24 8:55 ` Chris Wilson
2020-07-27 19:34 ` Umesh Nerlige Ramappa
2020-07-21 2:00 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-07-21 2:00 ` [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers Umesh Nerlige Ramappa
2020-07-21 6:03 ` Lionel Landwerlin
2020-07-18 0:04 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-07-18 0:04 ` [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers Umesh Nerlige Ramappa
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