* [PATCH v5 1/4] dt-bindings: USB: Add bindings for new Ingenic SoCs.
2020-07-23 6:12 [PATCH v5 0/4] Add USB PHY support for new Ingenic SoCs 周琰杰 (Zhou Yanjie)
@ 2020-07-23 6:12 ` 周琰杰 (Zhou Yanjie)
2020-07-23 6:12 ` [PATCH v5 2/4] USB: PHY: JZ4770: Unify code style and simplify code 周琰杰 (Zhou Yanjie)
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2020-07-23 6:12 UTC (permalink / raw)
To: balbi, gregkh, robh+dt
Cc: linux-usb, linux-kernel, devicetree, paul, prasannatsmkumar,
dongsheng.qiu, aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou,
zhenwenjin
Add the USB PHY bindings for the JZ4780 SoC, the X1000 SoC and
the X1830 SoC from Ingenic.
Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Notes:
v1->v2:
Add bindings for the JZ4780 SoC.
v2->v3:
No change.
v3->v4:
No change.
v4->v5:
No change.
Documentation/devicetree/bindings/usb/ingenic,jz4770-phy.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/usb/ingenic,jz4770-phy.yaml b/Documentation/devicetree/bindings/usb/ingenic,jz4770-phy.yaml
index a81b0b1a2226..2d61166ea5cf 100644
--- a/Documentation/devicetree/bindings/usb/ingenic,jz4770-phy.yaml
+++ b/Documentation/devicetree/bindings/usb/ingenic,jz4770-phy.yaml
@@ -4,10 +4,11 @@
$id: http://devicetree.org/schemas/usb/ingenic,jz4770-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Ingenic JZ4770 USB PHY devicetree bindings
+title: Ingenic SoCs USB PHY devicetree bindings
maintainers:
- Paul Cercueil <paul@crapouillou.net>
+ - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
properties:
$nodename:
@@ -16,6 +17,9 @@ properties:
compatible:
enum:
- ingenic,jz4770-phy
+ - ingenic,jz4780-phy
+ - ingenic,x1000-phy
+ - ingenic,x1830-phy
reg:
maxItems: 1
--
2.11.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v5 2/4] USB: PHY: JZ4770: Unify code style and simplify code.
2020-07-23 6:12 [PATCH v5 0/4] Add USB PHY support for new Ingenic SoCs 周琰杰 (Zhou Yanjie)
2020-07-23 6:12 ` [PATCH v5 1/4] dt-bindings: USB: Add bindings " 周琰杰 (Zhou Yanjie)
@ 2020-07-23 6:12 ` 周琰杰 (Zhou Yanjie)
2020-07-23 6:13 ` [PATCH v5 3/4] USB: PHY: JZ4770: Add support for new Ingenic SoCs 周琰杰 (Zhou Yanjie)
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2020-07-23 6:12 UTC (permalink / raw)
To: balbi, gregkh, robh+dt
Cc: linux-usb, linux-kernel, devicetree, paul, prasannatsmkumar,
dongsheng.qiu, aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou,
zhenwenjin
1.Modify the macro definition to unify "#define USBPCR_XXXX n"
into the "#define USBPCR_XXXX (n << USBPCR_XXXX_LSB)" style,
so as to unify the code style in the "jz4770_phy_init()" and
simplify the code.
2.Remove unused macro definitions to simplify the code.
Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Suggested-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
Notes:
v5:
New patch.
drivers/usb/phy/phy-jz4770.c | 34 +++++++++++-----------------------
1 file changed, 11 insertions(+), 23 deletions(-)
diff --git a/drivers/usb/phy/phy-jz4770.c b/drivers/usb/phy/phy-jz4770.c
index 8f62dc2a90ff..00209d5469d3 100644
--- a/drivers/usb/phy/phy-jz4770.c
+++ b/drivers/usb/phy/phy-jz4770.c
@@ -20,8 +20,6 @@
/* USBPCR */
#define USBPCR_USB_MODE BIT(31)
#define USBPCR_AVLD_REG BIT(30)
-#define USBPCR_INCRM BIT(27)
-#define USBPCR_CLK12_EN BIT(26)
#define USBPCR_COMMONONN BIT(25)
#define USBPCR_VBUSVLDEXT BIT(24)
#define USBPCR_VBUSVLDEXTSEL BIT(23)
@@ -32,45 +30,39 @@
#define USBPCR_IDPULLUP_LSB 28
#define USBPCR_IDPULLUP_MASK GENMASK(29, USBPCR_IDPULLUP_LSB)
-#define USBPCR_IDPULLUP_ALWAYS (3 << USBPCR_IDPULLUP_LSB)
-#define USBPCR_IDPULLUP_SUSPEND (1 << USBPCR_IDPULLUP_LSB)
-#define USBPCR_IDPULLUP_OTG (0 << USBPCR_IDPULLUP_LSB)
+#define USBPCR_IDPULLUP_ALWAYS (0x2 << USBPCR_IDPULLUP_LSB)
+#define USBPCR_IDPULLUP_SUSPEND (0x1 << USBPCR_IDPULLUP_LSB)
+#define USBPCR_IDPULLUP_OTG (0x0 << USBPCR_IDPULLUP_LSB)
#define USBPCR_COMPDISTUNE_LSB 17
#define USBPCR_COMPDISTUNE_MASK GENMASK(19, USBPCR_COMPDISTUNE_LSB)
-#define USBPCR_COMPDISTUNE_DFT 4
+#define USBPCR_COMPDISTUNE_DFT (0x4 << USBPCR_COMPDISTUNE_LSB)
#define USBPCR_OTGTUNE_LSB 14
#define USBPCR_OTGTUNE_MASK GENMASK(16, USBPCR_OTGTUNE_LSB)
-#define USBPCR_OTGTUNE_DFT 4
+#define USBPCR_OTGTUNE_DFT (0x4 << USBPCR_OTGTUNE_LSB)
#define USBPCR_SQRXTUNE_LSB 11
#define USBPCR_SQRXTUNE_MASK GENMASK(13, USBPCR_SQRXTUNE_LSB)
-#define USBPCR_SQRXTUNE_DFT 3
+#define USBPCR_SQRXTUNE_DFT (0x3 << USBPCR_SQRXTUNE_LSB)
#define USBPCR_TXFSLSTUNE_LSB 7
#define USBPCR_TXFSLSTUNE_MASK GENMASK(10, USBPCR_TXFSLSTUNE_LSB)
-#define USBPCR_TXFSLSTUNE_DFT 3
+#define USBPCR_TXFSLSTUNE_DFT (0x3 << USBPCR_TXFSLSTUNE_LSB)
#define USBPCR_TXRISETUNE_LSB 4
#define USBPCR_TXRISETUNE_MASK GENMASK(5, USBPCR_TXRISETUNE_LSB)
-#define USBPCR_TXRISETUNE_DFT 3
+#define USBPCR_TXRISETUNE_DFT (0x3 << USBPCR_TXRISETUNE_LSB)
#define USBPCR_TXVREFTUNE_LSB 0
#define USBPCR_TXVREFTUNE_MASK GENMASK(3, USBPCR_TXVREFTUNE_LSB)
-#define USBPCR_TXVREFTUNE_DFT 5
+#define USBPCR_TXVREFTUNE_DFT (0x5 << USBPCR_TXVREFTUNE_LSB)
/* USBRDT */
#define USBRDT_VBFIL_LD_EN BIT(25)
#define USBRDT_IDDIG_EN BIT(24)
#define USBRDT_IDDIG_REG BIT(23)
-#define USBRDT_USBRDT_LSB 0
-#define USBRDT_USBRDT_MASK GENMASK(22, USBRDT_USBRDT_LSB)
-
-/* USBPCR1 */
-#define USBPCR1_UHC_POWON BIT(5)
-
struct jz4770_phy {
struct usb_phy phy;
struct usb_otg otg;
@@ -136,12 +128,8 @@ static int jz4770_phy_init(struct usb_phy *phy)
}
reg = USBPCR_AVLD_REG | USBPCR_COMMONONN | USBPCR_IDPULLUP_ALWAYS |
- (USBPCR_COMPDISTUNE_DFT << USBPCR_COMPDISTUNE_LSB) |
- (USBPCR_OTGTUNE_DFT << USBPCR_OTGTUNE_LSB) |
- (USBPCR_SQRXTUNE_DFT << USBPCR_SQRXTUNE_LSB) |
- (USBPCR_TXFSLSTUNE_DFT << USBPCR_TXFSLSTUNE_LSB) |
- (USBPCR_TXRISETUNE_DFT << USBPCR_TXRISETUNE_LSB) |
- (USBPCR_TXVREFTUNE_DFT << USBPCR_TXVREFTUNE_LSB) |
+ USBPCR_COMPDISTUNE_DFT | USBPCR_OTGTUNE_DFT | USBPCR_SQRXTUNE_DFT |
+ USBPCR_TXFSLSTUNE_DFT | USBPCR_TXRISETUNE_DFT | USBPCR_TXVREFTUNE_DFT |
USBPCR_POR;
writel(reg, priv->base + REG_USBPCR_OFFSET);
--
2.11.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v5 3/4] USB: PHY: JZ4770: Add support for new Ingenic SoCs.
2020-07-23 6:12 [PATCH v5 0/4] Add USB PHY support for new Ingenic SoCs 周琰杰 (Zhou Yanjie)
2020-07-23 6:12 ` [PATCH v5 1/4] dt-bindings: USB: Add bindings " 周琰杰 (Zhou Yanjie)
2020-07-23 6:12 ` [PATCH v5 2/4] USB: PHY: JZ4770: Unify code style and simplify code 周琰杰 (Zhou Yanjie)
@ 2020-07-23 6:13 ` 周琰杰 (Zhou Yanjie)
2020-07-24 2:36 ` kernel test robot
2020-07-23 6:13 ` [PATCH v5 4/4] USB: PHY: JZ4770: Reformat the code to align it 周琰杰 (Zhou Yanjie)
2020-07-23 9:19 ` [PATCH v5 0/4] Add USB PHY support for new Ingenic SoCs Felipe Balbi
4 siblings, 1 reply; 8+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2020-07-23 6:13 UTC (permalink / raw)
To: balbi, gregkh, robh+dt
Cc: linux-usb, linux-kernel, devicetree, paul, prasannatsmkumar,
dongsheng.qiu, aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou,
zhenwenjin
Add support for probing the phy-jz4770 driver on the JZ4780 SoC,
the X1000 SoC and the X1830 SoC from Ingenic.
Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Co-developed-by: 漆鹏振 (Qi Pengzhen) <aric.pzqi@ingenic.com>
Signed-off-by: 漆鹏振 (Qi Pengzhen) <aric.pzqi@ingenic.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
Notes:
v1->v2:
Add bindings for the JZ4780 SoC.
v2->v3:
Use "of_device_get_match_data" instead "of_match_device"
to get version information.
v3->v4:
Fix typos.
v4->v5:
1.Modify the help message, make it more future-proof.
2.Drop the unnecessary comment about hardware reset.
3.Create 'soc_info' structures instead having ID_* as platform data.
drivers/usb/phy/Kconfig | 4 +-
drivers/usb/phy/phy-jz4770.c | 192 ++++++++++++++++++++++++++++++++++++-------
2 files changed, 163 insertions(+), 33 deletions(-)
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 4b3fa78995cf..ef4787cd3d37 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -185,11 +185,11 @@ config USB_ULPI_VIEWPORT
controllers with a viewport register (e.g. Chipidea/ARC controllers).
config JZ4770_PHY
- tristate "Ingenic JZ4770 Transceiver Driver"
+ tristate "Ingenic SoCs Transceiver Driver"
depends on MIPS || COMPILE_TEST
select USB_PHY
help
This driver provides PHY support for the USB controller found
- on the JZ4770 SoC from Ingenic.
+ on the JZ-series and X-series SoCs from Ingenic.
endmenu
diff --git a/drivers/usb/phy/phy-jz4770.c b/drivers/usb/phy/phy-jz4770.c
index 00209d5469d3..5c6e5cbb6f30 100644
--- a/drivers/usb/phy/phy-jz4770.c
+++ b/drivers/usb/phy/phy-jz4770.c
@@ -1,7 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Ingenic JZ4770 USB PHY driver
+ * Ingenic SoCs USB PHY driver
* Copyright (c) Paul Cercueil <paul@crapouillou.net>
+ * Copyright (c) 漆鹏振 (Qi Pengzhen) <aric.pzqi@ingenic.com>
+ * Copyright (c) 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
*/
#include <linux/clk.h>
@@ -12,12 +14,13 @@
#include <linux/usb/otg.h>
#include <linux/usb/phy.h>
+/* OTGPHY register offsets */
#define REG_USBPCR_OFFSET 0x00
#define REG_USBRDT_OFFSET 0x04
#define REG_USBVBFIL_OFFSET 0x08
#define REG_USBPCR1_OFFSET 0x0c
-/* USBPCR */
+/* bits within the USBPCR register */
#define USBPCR_USB_MODE BIT(31)
#define USBPCR_AVLD_REG BIT(30)
#define USBPCR_COMMONONN BIT(25)
@@ -44,11 +47,21 @@
#define USBPCR_SQRXTUNE_LSB 11
#define USBPCR_SQRXTUNE_MASK GENMASK(13, USBPCR_SQRXTUNE_LSB)
+#define USBPCR_SQRXTUNE_DCR_20PCT (0x7 << USBPCR_SQRXTUNE_LSB)
#define USBPCR_SQRXTUNE_DFT (0x3 << USBPCR_SQRXTUNE_LSB)
#define USBPCR_TXFSLSTUNE_LSB 7
#define USBPCR_TXFSLSTUNE_MASK GENMASK(10, USBPCR_TXFSLSTUNE_LSB)
+#define USBPCR_TXFSLSTUNE_DCR_50PPT (0xf << USBPCR_TXFSLSTUNE_LSB)
+#define USBPCR_TXFSLSTUNE_DCR_25PPT (0x7 << USBPCR_TXFSLSTUNE_LSB)
#define USBPCR_TXFSLSTUNE_DFT (0x3 << USBPCR_TXFSLSTUNE_LSB)
+#define USBPCR_TXFSLSTUNE_INC_25PPT (0x1 << USBPCR_TXFSLSTUNE_LSB)
+#define USBPCR_TXFSLSTUNE_INC_50PPT (0x0 << USBPCR_TXFSLSTUNE_LSB)
+
+#define USBPCR_TXHSXVTUNE_LSB 4
+#define USBPCR_TXHSXVTUNE_MASK GENMASK(5, USBPCR_TXHSXVTUNE_LSB)
+#define USBPCR_TXHSXVTUNE_DFT (0x3 << USBPCR_TXHSXVTUNE_LSB)
+#define USBPCR_TXHSXVTUNE_DCR_15MV (0x1 << USBPCR_TXHSXVTUNE_LSB)
#define USBPCR_TXRISETUNE_LSB 4
#define USBPCR_TXRISETUNE_MASK GENMASK(5, USBPCR_TXRISETUNE_LSB)
@@ -56,14 +69,40 @@
#define USBPCR_TXVREFTUNE_LSB 0
#define USBPCR_TXVREFTUNE_MASK GENMASK(3, USBPCR_TXVREFTUNE_LSB)
+#define USBPCR_TXVREFTUNE_INC_25PPT (0x7 << USBPCR_TXVREFTUNE_LSB)
#define USBPCR_TXVREFTUNE_DFT (0x5 << USBPCR_TXVREFTUNE_LSB)
-/* USBRDT */
+/* bits within the USBRDTR register */
+#define USBRDT_UTMI_RST BIT(27)
+#define USBRDT_HB_MASK BIT(26)
#define USBRDT_VBFIL_LD_EN BIT(25)
#define USBRDT_IDDIG_EN BIT(24)
#define USBRDT_IDDIG_REG BIT(23)
+#define USBRDT_VBFIL_EN BIT(2)
+
+/* bits within the USBPCR1 register */
+#define USBPCR1_BVLD_REG BIT(31)
+#define USBPCR1_DPPD BIT(29)
+#define USBPCR1_DMPD BIT(28)
+#define USBPCR1_USB_SEL BIT(28)
+#define USBPCR1_WORD_IF_16BIT BIT(19)
+
+enum ingenic_usb_phy_version {
+ ID_JZ4770,
+ ID_JZ4780,
+ ID_X1000,
+ ID_X1830,
+};
+
+struct ingenic_soc_info {
+ enum ingenic_usb_phy_version version;
+
+ void (*usb_phy_init)(struct usb_phy *phy);
+};
struct jz4770_phy {
+ const struct ingenic_soc_info *soc_info;
+
struct usb_phy phy;
struct usb_otg otg;
struct device *dev;
@@ -82,12 +121,18 @@ static inline struct jz4770_phy *phy_to_jz4770_phy(struct usb_phy *phy)
return container_of(phy, struct jz4770_phy, phy);
}
-static int jz4770_phy_set_peripheral(struct usb_otg *otg,
+static int ingenic_usb_phy_set_peripheral(struct usb_otg *otg,
struct usb_gadget *gadget)
{
struct jz4770_phy *priv = otg_to_jz4770_phy(otg);
u32 reg;
+ if (priv->soc_info->version >= ID_X1000) {
+ reg = readl(priv->base + REG_USBPCR1_OFFSET);
+ reg |= USBPCR1_BVLD_REG;
+ writel(reg, priv->base + REG_USBPCR1_OFFSET);
+ }
+
reg = readl(priv->base + REG_USBPCR_OFFSET);
reg &= ~USBPCR_USB_MODE;
reg |= USBPCR_VBUSVLDEXT | USBPCR_VBUSVLDEXTSEL | USBPCR_OTG_DISABLE;
@@ -96,7 +141,7 @@ static int jz4770_phy_set_peripheral(struct usb_otg *otg,
return 0;
}
-static int jz4770_phy_set_host(struct usb_otg *otg, struct usb_bus *host)
+static int ingenic_usb_phy_set_host(struct usb_otg *otg, struct usb_bus *host)
{
struct jz4770_phy *priv = otg_to_jz4770_phy(otg);
u32 reg;
@@ -109,7 +154,7 @@ static int jz4770_phy_set_host(struct usb_otg *otg, struct usb_bus *host)
return 0;
}
-static int jz4770_phy_init(struct usb_phy *phy)
+static int ingenic_usb_phy_init(struct usb_phy *phy)
{
struct jz4770_phy *priv = phy_to_jz4770_phy(phy);
int err;
@@ -127,11 +172,7 @@ static int jz4770_phy_init(struct usb_phy *phy)
return err;
}
- reg = USBPCR_AVLD_REG | USBPCR_COMMONONN | USBPCR_IDPULLUP_ALWAYS |
- USBPCR_COMPDISTUNE_DFT | USBPCR_OTGTUNE_DFT | USBPCR_SQRXTUNE_DFT |
- USBPCR_TXFSLSTUNE_DFT | USBPCR_TXRISETUNE_DFT | USBPCR_TXVREFTUNE_DFT |
- USBPCR_POR;
- writel(reg, priv->base + REG_USBPCR_OFFSET);
+ priv->soc_info->usb_phy_init(phy);
/* Wait for PHY to reset */
usleep_range(30, 300);
@@ -141,7 +182,7 @@ static int jz4770_phy_init(struct usb_phy *phy)
return 0;
}
-static void jz4770_phy_shutdown(struct usb_phy *phy)
+static void ingenic_usb_phy_shutdown(struct usb_phy *phy)
{
struct jz4770_phy *priv = phy_to_jz4770_phy(phy);
@@ -149,11 +190,100 @@ static void jz4770_phy_shutdown(struct usb_phy *phy)
regulator_disable(priv->vcc_supply);
}
-static void jz4770_phy_remove(void *phy)
+static void ingenic_usb_phy_remove(void *phy)
{
usb_remove_phy(phy);
}
+static void jz4770_usb_phy_init(struct usb_phy *phy)
+{
+ struct jz4770_phy *priv = phy_to_jz4770_phy(phy);
+ u32 reg;
+
+ reg = USBPCR_AVLD_REG | USBPCR_COMMONONN | USBPCR_IDPULLUP_ALWAYS |
+ USBPCR_COMPDISTUNE_DFT | USBPCR_OTGTUNE_DFT | USBPCR_SQRXTUNE_DFT |
+ USBPCR_TXFSLSTUNE_DFT | USBPCR_TXRISETUNE_DFT | USBPCR_TXVREFTUNE_DFT |
+ USBPCR_POR;
+ writel(reg, priv->base + REG_USBPCR_OFFSET);
+}
+
+static void jz4780_usb_phy_init(struct usb_phy *phy)
+{
+ struct jz4770_phy *priv = phy_to_jz4770_phy(phy);
+ u32 reg;
+
+ reg = readl(priv->base + REG_USBPCR1_OFFSET) | USBPCR1_USB_SEL |
+ USBPCR1_WORD_IF_16BIT;
+ writel(reg, priv->base + REG_USBPCR1_OFFSET);
+
+ reg = USBPCR_TXPREEMPHTUNE | USBPCR_COMMONONN | USBPCR_POR;
+ writel(reg, priv->base + REG_USBPCR_OFFSET);
+}
+
+static void x1000_usb_phy_init(struct usb_phy *phy)
+{
+ struct jz4770_phy *priv = phy_to_jz4770_phy(phy);
+ u32 reg;
+
+ reg = readl(priv->base + REG_USBPCR1_OFFSET) | USBPCR1_WORD_IF_16BIT;
+ writel(reg, priv->base + REG_USBPCR1_OFFSET);
+
+ reg = USBPCR_SQRXTUNE_DCR_20PCT | USBPCR_TXPREEMPHTUNE |
+ USBPCR_TXHSXVTUNE_DCR_15MV | USBPCR_TXVREFTUNE_INC_25PPT |
+ USBPCR_COMMONONN | USBPCR_POR;
+ writel(reg, priv->base + REG_USBPCR_OFFSET);
+}
+
+static void x1830_usb_phy_init(struct usb_phy *phy)
+{
+ struct jz4770_phy *priv = phy_to_jz4770_phy(phy);
+ u32 reg;
+
+ /* rdt */
+ writel(USBRDT_VBFIL_EN | USBRDT_UTMI_RST, priv->base + REG_USBRDT_OFFSET);
+
+ reg = readl(priv->base + REG_USBPCR1_OFFSET) | USBPCR1_WORD_IF_16BIT |
+ USBPCR1_DMPD | USBPCR1_DPPD;
+ writel(reg, priv->base + REG_USBPCR1_OFFSET);
+
+ reg = USBPCR_IDPULLUP_OTG | USBPCR_VBUSVLDEXT | USBPCR_TXPREEMPHTUNE |
+ USBPCR_COMMONONN | USBPCR_POR;
+ writel(reg, priv->base + REG_USBPCR_OFFSET);
+}
+
+static const struct ingenic_soc_info jz4770_soc_info = {
+ .version = ID_JZ4770,
+
+ .usb_phy_init = jz4770_usb_phy_init,
+};
+
+static const struct ingenic_soc_info jz4780_soc_info = {
+ .version = ID_JZ4780,
+
+ .usb_phy_init = jz4780_usb_phy_init,
+};
+
+static const struct ingenic_soc_info x1000_soc_info = {
+ .version = ID_X1000,
+
+ .usb_phy_init = x1000_usb_phy_init,
+};
+
+static const struct ingenic_soc_info x1830_soc_info = {
+ .version = ID_X1830,
+
+ .usb_phy_init = x1830_usb_phy_init,
+};
+
+static const struct of_device_id ingenic_usb_phy_of_matches[] = {
+ { .compatible = "ingenic,jz4770-phy", .data = &jz4770_soc_info },
+ { .compatible = "ingenic,jz4780-phy", .data = &jz4780_soc_info },
+ { .compatible = "ingenic,x1000-phy", .data = &x1000_soc_info },
+ { .compatible = "ingenic,x1830-phy", .data = &x1830_soc_info },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, ingenic_usb_phy_of_matches);
+
static int jz4770_phy_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -164,18 +294,24 @@ static int jz4770_phy_probe(struct platform_device *pdev)
if (!priv)
return -ENOMEM;
+ priv->soc_info = device_get_match_data(&pdev->dev);
+ if (!priv->soc_info) {
+ dev_err(&pdev->dev, "Error: No device match found\n");
+ return -ENODEV;
+ }
+
platform_set_drvdata(pdev, priv);
priv->dev = dev;
priv->phy.dev = dev;
priv->phy.otg = &priv->otg;
- priv->phy.label = "jz4770-phy";
- priv->phy.init = jz4770_phy_init;
- priv->phy.shutdown = jz4770_phy_shutdown;
+ priv->phy.label = "ingenic-usb-phy";
+ priv->phy.init = ingenic_usb_phy_init;
+ priv->phy.shutdown = ingenic_usb_phy_shutdown;
priv->otg.state = OTG_STATE_UNDEFINED;
priv->otg.usb_phy = &priv->phy;
- priv->otg.set_host = jz4770_phy_set_host;
- priv->otg.set_peripheral = jz4770_phy_set_peripheral;
+ priv->otg.set_host = ingenic_usb_phy_set_host;
+ priv->otg.set_peripheral = ingenic_usb_phy_set_peripheral;
priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base)) {
@@ -206,26 +342,20 @@ static int jz4770_phy_probe(struct platform_device *pdev)
return err;
}
- return devm_add_action_or_reset(dev, jz4770_phy_remove, &priv->phy);
+ return devm_add_action_or_reset(dev, ingenic_usb_phy_remove, &priv->phy);
}
-#ifdef CONFIG_OF
-static const struct of_device_id jz4770_phy_of_matches[] = {
- { .compatible = "ingenic,jz4770-phy" },
- { }
-};
-MODULE_DEVICE_TABLE(of, jz4770_phy_of_matches);
-#endif
-
-static struct platform_driver jz4770_phy_driver = {
+static struct platform_driver ingenic_phy_driver = {
.probe = jz4770_phy_probe,
.driver = {
.name = "jz4770-phy",
- .of_match_table = of_match_ptr(jz4770_phy_of_matches),
+ .of_match_table = of_match_ptr(ingenic_usb_phy_of_matches),
},
};
-module_platform_driver(jz4770_phy_driver);
+module_platform_driver(ingenic_phy_driver);
+MODULE_AUTHOR("周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>");
+MODULE_AUTHOR("漆鹏振 (Qi Pengzhen) <aric.pzqi@ingenic.com>");
MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
-MODULE_DESCRIPTION("Ingenic JZ4770 USB PHY driver");
+MODULE_DESCRIPTION("Ingenic SoCs USB PHY driver");
MODULE_LICENSE("GPL");
--
2.11.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v5 3/4] USB: PHY: JZ4770: Add support for new Ingenic SoCs.
2020-07-23 6:13 ` [PATCH v5 3/4] USB: PHY: JZ4770: Add support for new Ingenic SoCs 周琰杰 (Zhou Yanjie)
@ 2020-07-24 2:36 ` kernel test robot
0 siblings, 0 replies; 8+ messages in thread
From: kernel test robot @ 2020-07-24 2:36 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 4101 bytes --]
Hi "周琰杰,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on balbi-usb/testing/next]
[also build test WARNING on usb/usb-testing robh/for-next v5.8-rc6 next-20200723]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Zhou-Yanjie/Add-USB-PHY-support-for-new-Ingenic-SoCs/20200723-141656
base: https://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git testing/next
config: x86_64-allyesconfig (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project e0ee2288424952e0445f096ae7800472eac11249)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/usb/phy/phy-jz4770.c:179:9: warning: variable 'reg' is uninitialized when used here [-Wuninitialized]
writel(reg & ~USBPCR_POR, priv->base + REG_USBPCR_OFFSET);
^~~
drivers/usb/phy/phy-jz4770.c:161:9: note: initialize the variable 'reg' to silence this warning
u32 reg;
^
= 0
1 warning generated.
vim +/reg +179 drivers/usb/phy/phy-jz4770.c
541368b46b829ea Paul Cercueil 2020-02-29 156
22088346436e0cf 周琰杰 (Zhou Yanjie 2020-07-23 157) static int ingenic_usb_phy_init(struct usb_phy *phy)
541368b46b829ea Paul Cercueil 2020-02-29 158 {
541368b46b829ea Paul Cercueil 2020-02-29 159 struct jz4770_phy *priv = phy_to_jz4770_phy(phy);
541368b46b829ea Paul Cercueil 2020-02-29 160 int err;
541368b46b829ea Paul Cercueil 2020-02-29 161 u32 reg;
541368b46b829ea Paul Cercueil 2020-02-29 162
541368b46b829ea Paul Cercueil 2020-02-29 163 err = regulator_enable(priv->vcc_supply);
541368b46b829ea Paul Cercueil 2020-02-29 164 if (err) {
ab455450fe15f84 Christophe JAILLET 2020-04-11 165 dev_err(priv->dev, "Unable to enable VCC: %d\n", err);
541368b46b829ea Paul Cercueil 2020-02-29 166 return err;
541368b46b829ea Paul Cercueil 2020-02-29 167 }
541368b46b829ea Paul Cercueil 2020-02-29 168
541368b46b829ea Paul Cercueil 2020-02-29 169 err = clk_prepare_enable(priv->clk);
541368b46b829ea Paul Cercueil 2020-02-29 170 if (err) {
ab455450fe15f84 Christophe JAILLET 2020-04-11 171 dev_err(priv->dev, "Unable to start clock: %d\n", err);
541368b46b829ea Paul Cercueil 2020-02-29 172 return err;
541368b46b829ea Paul Cercueil 2020-02-29 173 }
541368b46b829ea Paul Cercueil 2020-02-29 174
22088346436e0cf 周琰杰 (Zhou Yanjie 2020-07-23 175) priv->soc_info->usb_phy_init(phy);
541368b46b829ea Paul Cercueil 2020-02-29 176
541368b46b829ea Paul Cercueil 2020-02-29 177 /* Wait for PHY to reset */
541368b46b829ea Paul Cercueil 2020-02-29 178 usleep_range(30, 300);
541368b46b829ea Paul Cercueil 2020-02-29 @179 writel(reg & ~USBPCR_POR, priv->base + REG_USBPCR_OFFSET);
541368b46b829ea Paul Cercueil 2020-02-29 180 usleep_range(300, 1000);
541368b46b829ea Paul Cercueil 2020-02-29 181
541368b46b829ea Paul Cercueil 2020-02-29 182 return 0;
541368b46b829ea Paul Cercueil 2020-02-29 183 }
541368b46b829ea Paul Cercueil 2020-02-29 184
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 75331 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v5 4/4] USB: PHY: JZ4770: Reformat the code to align it.
2020-07-23 6:12 [PATCH v5 0/4] Add USB PHY support for new Ingenic SoCs 周琰杰 (Zhou Yanjie)
` (2 preceding siblings ...)
2020-07-23 6:13 ` [PATCH v5 3/4] USB: PHY: JZ4770: Add support for new Ingenic SoCs 周琰杰 (Zhou Yanjie)
@ 2020-07-23 6:13 ` 周琰杰 (Zhou Yanjie)
2020-07-23 9:19 ` [PATCH v5 0/4] Add USB PHY support for new Ingenic SoCs Felipe Balbi
4 siblings, 0 replies; 8+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2020-07-23 6:13 UTC (permalink / raw)
To: balbi, gregkh, robh+dt
Cc: linux-usb, linux-kernel, devicetree, paul, prasannatsmkumar,
dongsheng.qiu, aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou,
zhenwenjin
Reformat the code (add one level of indentation before the values),
to align the code in the macro definition section.
Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Co-developed-by: 漆鹏振 (Qi Pengzhen) <aric.pzqi@ingenic.com>
Signed-off-by: 漆鹏振 (Qi Pengzhen) <aric.pzqi@ingenic.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
Notes:
v1->v2:
Add support for the JZ4780 SoC.
v2->v3:
No change.
v3->v4:
No change.
v4->v5:
No change.
drivers/usb/phy/phy-jz4770.c | 74 ++++++++++++++++++++++----------------------
1 file changed, 37 insertions(+), 37 deletions(-)
diff --git a/drivers/usb/phy/phy-jz4770.c b/drivers/usb/phy/phy-jz4770.c
index 5c6e5cbb6f30..40c73c1a8c79 100644
--- a/drivers/usb/phy/phy-jz4770.c
+++ b/drivers/usb/phy/phy-jz4770.c
@@ -15,46 +15,46 @@
#include <linux/usb/phy.h>
/* OTGPHY register offsets */
-#define REG_USBPCR_OFFSET 0x00
-#define REG_USBRDT_OFFSET 0x04
-#define REG_USBVBFIL_OFFSET 0x08
-#define REG_USBPCR1_OFFSET 0x0c
+#define REG_USBPCR_OFFSET 0x00
+#define REG_USBRDT_OFFSET 0x04
+#define REG_USBVBFIL_OFFSET 0x08
+#define REG_USBPCR1_OFFSET 0x0c
/* bits within the USBPCR register */
-#define USBPCR_USB_MODE BIT(31)
-#define USBPCR_AVLD_REG BIT(30)
-#define USBPCR_COMMONONN BIT(25)
-#define USBPCR_VBUSVLDEXT BIT(24)
-#define USBPCR_VBUSVLDEXTSEL BIT(23)
-#define USBPCR_POR BIT(22)
-#define USBPCR_SIDDQ BIT(21)
-#define USBPCR_OTG_DISABLE BIT(20)
-#define USBPCR_TXPREEMPHTUNE BIT(6)
+#define USBPCR_USB_MODE BIT(31)
+#define USBPCR_AVLD_REG BIT(30)
+#define USBPCR_COMMONONN BIT(25)
+#define USBPCR_VBUSVLDEXT BIT(24)
+#define USBPCR_VBUSVLDEXTSEL BIT(23)
+#define USBPCR_POR BIT(22)
+#define USBPCR_SIDDQ BIT(21)
+#define USBPCR_OTG_DISABLE BIT(20)
+#define USBPCR_TXPREEMPHTUNE BIT(6)
#define USBPCR_IDPULLUP_LSB 28
-#define USBPCR_IDPULLUP_MASK GENMASK(29, USBPCR_IDPULLUP_LSB)
-#define USBPCR_IDPULLUP_ALWAYS (0x2 << USBPCR_IDPULLUP_LSB)
-#define USBPCR_IDPULLUP_SUSPEND (0x1 << USBPCR_IDPULLUP_LSB)
-#define USBPCR_IDPULLUP_OTG (0x0 << USBPCR_IDPULLUP_LSB)
+#define USBPCR_IDPULLUP_MASK GENMASK(29, USBPCR_IDPULLUP_LSB)
+#define USBPCR_IDPULLUP_ALWAYS (0x2 << USBPCR_IDPULLUP_LSB)
+#define USBPCR_IDPULLUP_SUSPEND (0x1 << USBPCR_IDPULLUP_LSB)
+#define USBPCR_IDPULLUP_OTG (0x0 << USBPCR_IDPULLUP_LSB)
-#define USBPCR_COMPDISTUNE_LSB 17
-#define USBPCR_COMPDISTUNE_MASK GENMASK(19, USBPCR_COMPDISTUNE_LSB)
-#define USBPCR_COMPDISTUNE_DFT (0x4 << USBPCR_COMPDISTUNE_LSB)
+#define USBPCR_COMPDISTUNE_LSB 17
+#define USBPCR_COMPDISTUNE_MASK GENMASK(19, USBPCR_COMPDISTUNE_LSB)
+#define USBPCR_COMPDISTUNE_DFT (0x4 << USBPCR_COMPDISTUNE_LSB)
-#define USBPCR_OTGTUNE_LSB 14
-#define USBPCR_OTGTUNE_MASK GENMASK(16, USBPCR_OTGTUNE_LSB)
-#define USBPCR_OTGTUNE_DFT (0x4 << USBPCR_OTGTUNE_LSB)
+#define USBPCR_OTGTUNE_LSB 14
+#define USBPCR_OTGTUNE_MASK GENMASK(16, USBPCR_OTGTUNE_LSB)
+#define USBPCR_OTGTUNE_DFT (0x4 << USBPCR_OTGTUNE_LSB)
#define USBPCR_SQRXTUNE_LSB 11
-#define USBPCR_SQRXTUNE_MASK GENMASK(13, USBPCR_SQRXTUNE_LSB)
+#define USBPCR_SQRXTUNE_MASK GENMASK(13, USBPCR_SQRXTUNE_LSB)
#define USBPCR_SQRXTUNE_DCR_20PCT (0x7 << USBPCR_SQRXTUNE_LSB)
-#define USBPCR_SQRXTUNE_DFT (0x3 << USBPCR_SQRXTUNE_LSB)
+#define USBPCR_SQRXTUNE_DFT (0x3 << USBPCR_SQRXTUNE_LSB)
-#define USBPCR_TXFSLSTUNE_LSB 7
-#define USBPCR_TXFSLSTUNE_MASK GENMASK(10, USBPCR_TXFSLSTUNE_LSB)
+#define USBPCR_TXFSLSTUNE_LSB 7
+#define USBPCR_TXFSLSTUNE_MASK GENMASK(10, USBPCR_TXFSLSTUNE_LSB)
#define USBPCR_TXFSLSTUNE_DCR_50PPT (0xf << USBPCR_TXFSLSTUNE_LSB)
#define USBPCR_TXFSLSTUNE_DCR_25PPT (0x7 << USBPCR_TXFSLSTUNE_LSB)
-#define USBPCR_TXFSLSTUNE_DFT (0x3 << USBPCR_TXFSLSTUNE_LSB)
+#define USBPCR_TXFSLSTUNE_DFT (0x3 << USBPCR_TXFSLSTUNE_LSB)
#define USBPCR_TXFSLSTUNE_INC_25PPT (0x1 << USBPCR_TXFSLSTUNE_LSB)
#define USBPCR_TXFSLSTUNE_INC_50PPT (0x0 << USBPCR_TXFSLSTUNE_LSB)
@@ -63,21 +63,21 @@
#define USBPCR_TXHSXVTUNE_DFT (0x3 << USBPCR_TXHSXVTUNE_LSB)
#define USBPCR_TXHSXVTUNE_DCR_15MV (0x1 << USBPCR_TXHSXVTUNE_LSB)
-#define USBPCR_TXRISETUNE_LSB 4
-#define USBPCR_TXRISETUNE_MASK GENMASK(5, USBPCR_TXRISETUNE_LSB)
-#define USBPCR_TXRISETUNE_DFT (0x3 << USBPCR_TXRISETUNE_LSB)
+#define USBPCR_TXRISETUNE_LSB 4
+#define USBPCR_TXRISETUNE_MASK GENMASK(5, USBPCR_TXRISETUNE_LSB)
+#define USBPCR_TXRISETUNE_DFT (0x3 << USBPCR_TXRISETUNE_LSB)
-#define USBPCR_TXVREFTUNE_LSB 0
-#define USBPCR_TXVREFTUNE_MASK GENMASK(3, USBPCR_TXVREFTUNE_LSB)
+#define USBPCR_TXVREFTUNE_LSB 0
+#define USBPCR_TXVREFTUNE_MASK GENMASK(3, USBPCR_TXVREFTUNE_LSB)
#define USBPCR_TXVREFTUNE_INC_25PPT (0x7 << USBPCR_TXVREFTUNE_LSB)
-#define USBPCR_TXVREFTUNE_DFT (0x5 << USBPCR_TXVREFTUNE_LSB)
+#define USBPCR_TXVREFTUNE_DFT (0x5 << USBPCR_TXVREFTUNE_LSB)
/* bits within the USBRDTR register */
#define USBRDT_UTMI_RST BIT(27)
#define USBRDT_HB_MASK BIT(26)
-#define USBRDT_VBFIL_LD_EN BIT(25)
-#define USBRDT_IDDIG_EN BIT(24)
-#define USBRDT_IDDIG_REG BIT(23)
+#define USBRDT_VBFIL_LD_EN BIT(25)
+#define USBRDT_IDDIG_EN BIT(24)
+#define USBRDT_IDDIG_REG BIT(23)
#define USBRDT_VBFIL_EN BIT(2)
/* bits within the USBPCR1 register */
--
2.11.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v5 0/4] Add USB PHY support for new Ingenic SoCs.
2020-07-23 6:12 [PATCH v5 0/4] Add USB PHY support for new Ingenic SoCs 周琰杰 (Zhou Yanjie)
` (3 preceding siblings ...)
2020-07-23 6:13 ` [PATCH v5 4/4] USB: PHY: JZ4770: Reformat the code to align it 周琰杰 (Zhou Yanjie)
@ 2020-07-23 9:19 ` Felipe Balbi
2020-07-25 3:12 ` Zhou Yanjie
4 siblings, 1 reply; 8+ messages in thread
From: Felipe Balbi @ 2020-07-23 9:19 UTC (permalink / raw)
To: 周琰杰 (Zhou Yanjie), gregkh, robh+dt
Cc: linux-usb, linux-kernel, devicetree, paul, prasannatsmkumar,
dongsheng.qiu, aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou,
zhenwenjin
[-- Attachment #1: Type: text/plain, Size: 402 bytes --]
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> writes:
> 1.separate the adjustments to the code style into
> a separate patch.
> 2.Modify the help message, make it more future-proof.
> 3.Drop the unnecessary comment about hardware reset.
> 4.Create 'soc_info' structures instead having ID_* as platform data.
For v5.10, make sure to move your phy driver to drivers/phy.
--
balbi
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 832 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v5 0/4] Add USB PHY support for new Ingenic SoCs.
2020-07-23 9:19 ` [PATCH v5 0/4] Add USB PHY support for new Ingenic SoCs Felipe Balbi
@ 2020-07-25 3:12 ` Zhou Yanjie
0 siblings, 0 replies; 8+ messages in thread
From: Zhou Yanjie @ 2020-07-25 3:12 UTC (permalink / raw)
To: Felipe Balbi, gregkh, robh+dt
Cc: linux-usb, linux-kernel, devicetree, paul, prasannatsmkumar,
dongsheng.qiu, aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou,
zhenwenjin
Hello Felipe,
在 2020/7/23 下午5:19, Felipe Balbi 写道:
> 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> writes:
>
>> 1.separate the adjustments to the code style into
>> a separate patch.
>> 2.Modify the help message, make it more future-proof.
>> 3.Drop the unnecessary comment about hardware reset.
>> 4.Create 'soc_info' structures instead having ID_* as platform data.
> For v5.10, make sure to move your phy driver to drivers/phy.
>
Sure, I will move it to drivers/phy in next version.
Thanks and best regards!
^ permalink raw reply [flat|nested] 8+ messages in thread