From: Anup Patel <anup.patel@wdc.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Rob Herring <robh+dt@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de> Cc: Damien Le Moal <damien.lemoal@wdc.com>, Atish Patra <atish.patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel <anup.patel@wdc.com>, Palmer Dabbelt <palmerdabbelt@google.com>, Emil Renner Berhing <kernel@esmil.dk> Subject: [PATCH v6 4/4] dt-bindings: timer: Add CLINT bindings Date: Fri, 24 Jul 2020 12:48:22 +0530 [thread overview] Message-ID: <20200724071822.126758-5-anup.patel@wdc.com> (raw) In-Reply-To: <20200724071822.126758-1-anup.patel@wdc.com> We add DT bindings documentation for CLINT device. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Tested-by: Emil Renner Berhing <kernel@esmil.dk> --- .../bindings/timer/sifive,clint.yaml | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.yaml diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml new file mode 100644 index 000000000000..2a0e9cd9fbcf --- /dev/null +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/sifive,clint.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive Core Local Interruptor + +maintainers: + - Palmer Dabbelt <palmer@dabbelt.com> + - Anup Patel <anup.patel@wdc.com> + +description: + SiFive (and other RISC-V) SOCs include an implementation of the SiFive + Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor + interrupts. It directly connects to the timer and inter-processor interrupt + lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local + interrupt controller is the parent interrupt controller for CLINT device. + The clock frequency of CLINT is specified via "timebase-frequency" DT + property of "/cpus" DT node. The "timebase-frequency" DT property is + described in Documentation/devicetree/bindings/riscv/cpus.yaml + +properties: + compatible: + items: + - const: sifive,fu540-c000-clint + - const: sifive,clint0 + + description: + Should be "sifive,<chip>-clint" and "sifive,clint<version>". + Supported compatible strings are - + "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated + onto the SiFive FU540 chip, and "sifive,clint0" for the SiFive + CLINT v0 IP block with no chip integration tweaks. + Please refer to sifive-blocks-ip-versioning.txt for details + + reg: + maxItems: 1 + + interrupts-extended: + minItems: 1 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + timer@2000000 { + compatible = "sifive,fu540-c000-clint", "sifive,clint0"; + interrupts-extended = <&cpu1intc 3 &cpu1intc 7 + &cpu2intc 3 &cpu2intc 7 + &cpu3intc 3 &cpu3intc 7 + &cpu4intc 3 &cpu4intc 7>; + reg = <0x2000000 0x10000>; + }; +... -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup.patel@wdc.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Rob Herring <robh+dt@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de> Cc: devicetree@vger.kernel.org, Damien Le Moal <damien.lemoal@wdc.com>, Palmer Dabbelt <palmerdabbelt@google.com>, Emil Renner Berhing <kernel@esmil.dk>, Anup Patel <anup@brainfault.org>, Anup Patel <anup.patel@wdc.com>, linux-kernel@vger.kernel.org, Atish Patra <atish.patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, linux-riscv@lists.infradead.org Subject: [PATCH v6 4/4] dt-bindings: timer: Add CLINT bindings Date: Fri, 24 Jul 2020 12:48:22 +0530 [thread overview] Message-ID: <20200724071822.126758-5-anup.patel@wdc.com> (raw) In-Reply-To: <20200724071822.126758-1-anup.patel@wdc.com> We add DT bindings documentation for CLINT device. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Tested-by: Emil Renner Berhing <kernel@esmil.dk> --- .../bindings/timer/sifive,clint.yaml | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.yaml diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml new file mode 100644 index 000000000000..2a0e9cd9fbcf --- /dev/null +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/sifive,clint.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive Core Local Interruptor + +maintainers: + - Palmer Dabbelt <palmer@dabbelt.com> + - Anup Patel <anup.patel@wdc.com> + +description: + SiFive (and other RISC-V) SOCs include an implementation of the SiFive + Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor + interrupts. It directly connects to the timer and inter-processor interrupt + lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local + interrupt controller is the parent interrupt controller for CLINT device. + The clock frequency of CLINT is specified via "timebase-frequency" DT + property of "/cpus" DT node. The "timebase-frequency" DT property is + described in Documentation/devicetree/bindings/riscv/cpus.yaml + +properties: + compatible: + items: + - const: sifive,fu540-c000-clint + - const: sifive,clint0 + + description: + Should be "sifive,<chip>-clint" and "sifive,clint<version>". + Supported compatible strings are - + "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated + onto the SiFive FU540 chip, and "sifive,clint0" for the SiFive + CLINT v0 IP block with no chip integration tweaks. + Please refer to sifive-blocks-ip-versioning.txt for details + + reg: + maxItems: 1 + + interrupts-extended: + minItems: 1 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + timer@2000000 { + compatible = "sifive,fu540-c000-clint", "sifive,clint0"; + interrupts-extended = <&cpu1intc 3 &cpu1intc 7 + &cpu2intc 3 &cpu2intc 7 + &cpu3intc 3 &cpu3intc 7 + &cpu4intc 3 &cpu4intc 7>; + reg = <0x2000000 0x10000>; + }; +... -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2020-07-24 7:19 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-07-24 7:18 [PATCH v6 0/4] Dedicated CLINT timer driver Anup Patel 2020-07-24 7:18 ` Anup Patel 2020-07-24 7:18 ` [PATCH v6 1/4] RISC-V: Add mechanism to provide custom IPI operations Anup Patel 2020-07-24 7:18 ` Anup Patel 2020-08-05 1:47 ` Palmer Dabbelt 2020-08-05 1:47 ` Palmer Dabbelt 2020-07-24 7:18 ` [PATCH v6 2/4] clocksource/drivers: Add CLINT timer driver Anup Patel 2020-07-24 7:18 ` Anup Patel 2020-07-25 5:02 ` Atish Patra 2020-07-25 5:02 ` Atish Patra 2020-08-05 1:47 ` Palmer Dabbelt 2020-08-05 1:47 ` Palmer Dabbelt 2020-07-24 7:18 ` [PATCH v6 3/4] RISC-V: Remove CLINT related code from timer and arch Anup Patel 2020-07-24 7:18 ` Anup Patel 2020-07-25 5:15 ` Atish Patra 2020-07-25 5:15 ` Atish Patra 2020-07-26 5:15 ` Anup Patel 2020-07-26 5:15 ` Anup Patel 2020-08-05 1:47 ` Palmer Dabbelt 2020-08-05 1:47 ` Palmer Dabbelt 2020-07-24 7:18 ` Anup Patel [this message] 2020-07-24 7:18 ` [PATCH v6 4/4] dt-bindings: timer: Add CLINT bindings Anup Patel 2020-07-25 5:04 ` Atish Patra 2020-07-25 5:04 ` Atish Patra 2020-07-27 19:56 ` Rob Herring 2020-07-27 19:56 ` Rob Herring 2020-08-05 1:47 ` Palmer Dabbelt 2020-08-05 1:47 ` Palmer Dabbelt 2020-08-05 1:47 ` [PATCH v6 0/4] Dedicated CLINT timer driver Palmer Dabbelt 2020-08-05 1:47 ` Palmer Dabbelt 2020-08-05 9:37 ` Anup Patel 2020-08-05 9:37 ` Anup Patel
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