* [PATCH 1/2] drm/amdgpu: add interface amdgpu_gfx_init_spm_golden for Navi1x
@ 2020-07-28 5:27 Tianci Yin
2020-07-28 5:27 ` [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit Tianci Yin
2020-07-28 18:29 ` [PATCH 1/2] drm/amdgpu: add interface amdgpu_gfx_init_spm_golden for Navi1x Luben Tuikov
0 siblings, 2 replies; 10+ messages in thread
From: Tianci Yin @ 2020-07-28 5:27 UTC (permalink / raw)
To: amd-gfx
Cc: Feifei Xu, Tianci Yin, Tuikov Luben, Hesik Christopher,
Deucher Alexander, Swamy Manjunatha, Evan Quan, Feng Kenneth,
Hawking Zhang
From: "Tianci.Yin" <tianci.yin@amd.com>
On Navi1x, the SPM golden settings will be lost after GFXOFF enter/exit,
reconfiguration is needed. Make the configuration code as an interface for
future use.
Change-Id: I172f3dc7f59da69b0364052dcad75a9c9aab019e
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 ++
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 34 ++++++++++++++++++-------
2 files changed, 27 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 1e7a2b0997c5..a611e78dd4ba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -216,6 +216,7 @@ struct amdgpu_gfx_funcs {
int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if);
int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status);
void (*reset_ras_error_count) (struct amdgpu_device *adev);
+ void (*init_spm_golden)(struct amdgpu_device *adev);
};
struct sq_work {
@@ -324,6 +325,7 @@ struct amdgpu_gfx {
#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))
+#define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev))
/**
* amdgpu_gfx_create_bitmask - create a bitmask
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index db9f1e89a0f8..da21ad04ac0f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3307,6 +3307,29 @@ static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
}
+static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
+{
+ switch (adev->asic_type) {
+ case CHIP_NAVI10:
+ soc15_program_register_sequence(adev,
+ golden_settings_gc_rlc_spm_10_0_nv10,
+ (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
+ break;
+ case CHIP_NAVI14:
+ soc15_program_register_sequence(adev,
+ golden_settings_gc_rlc_spm_10_1_nv14,
+ (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
+ break;
+ case CHIP_NAVI12:
+ soc15_program_register_sequence(adev,
+ golden_settings_gc_rlc_spm_10_1_2_nv12,
+ (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
+ break;
+ default:
+ break;
+ }
+}
+
static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
{
switch (adev->asic_type) {
@@ -3317,9 +3340,6 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
soc15_program_register_sequence(adev,
golden_settings_gc_10_0_nv10,
(const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
- soc15_program_register_sequence(adev,
- golden_settings_gc_rlc_spm_10_0_nv10,
- (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
break;
case CHIP_NAVI14:
soc15_program_register_sequence(adev,
@@ -3328,9 +3348,6 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
soc15_program_register_sequence(adev,
golden_settings_gc_10_1_nv14,
(const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
- soc15_program_register_sequence(adev,
- golden_settings_gc_rlc_spm_10_1_nv14,
- (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
break;
case CHIP_NAVI12:
soc15_program_register_sequence(adev,
@@ -3339,9 +3356,6 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
soc15_program_register_sequence(adev,
golden_settings_gc_10_1_2_nv12,
(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
- soc15_program_register_sequence(adev,
- golden_settings_gc_rlc_spm_10_1_2_nv12,
- (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
break;
case CHIP_SIENNA_CICHLID:
soc15_program_register_sequence(adev,
@@ -3360,6 +3374,7 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
default:
break;
}
+ gfx_v10_0_init_spm_golden_registers(adev);
}
static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
@@ -4147,6 +4162,7 @@ static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
.read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
.read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
.select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
+ .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
};
static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
--
2.17.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit
2020-07-28 5:27 [PATCH 1/2] drm/amdgpu: add interface amdgpu_gfx_init_spm_golden for Navi1x Tianci Yin
@ 2020-07-28 5:27 ` Tianci Yin
[not found] ` <CY4PR12MB1623B0A15166F72FF7032C2AFE730@CY4PR12MB1623.namprd12.prod.outlook.com>
` (2 more replies)
2020-07-28 18:29 ` [PATCH 1/2] drm/amdgpu: add interface amdgpu_gfx_init_spm_golden for Navi1x Luben Tuikov
1 sibling, 3 replies; 10+ messages in thread
From: Tianci Yin @ 2020-07-28 5:27 UTC (permalink / raw)
To: amd-gfx
Cc: Feifei Xu, Tianci Yin, Tuikov Luben, Hesik Christopher,
Deucher Alexander, Swamy Manjunatha, Evan Quan, Feng Kenneth,
Hawking Zhang
From: "Tianci.Yin" <tianci.yin@amd.com>
On Navi1x, the SPM golden settings will be lost after GFXOFF enter/exit,
reconfigure the golden settings after GFXOFF exit.
Change-Id: I9358ba9c65f241c36f8a35916170b19535148ee9
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 55463e7a11e2..5da0436d41e0 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1309,6 +1309,7 @@ static int smu_enable_umd_pstate(void *handle,
struct smu_context *smu = (struct smu_context*)(handle);
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+ struct amdgpu_device *adev = smu->adev;
if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
return -EINVAL;
@@ -1324,6 +1325,16 @@ static int smu_enable_umd_pstate(void *handle,
amdgpu_device_ip_set_clockgating_state(smu->adev,
AMD_IP_BLOCK_TYPE_GFX,
AMD_CG_STATE_UNGATE);
+
+ if (adev->asic_type >= CHIP_NAVI10 &&
+ adev->asic_type <= CHIP_NAVI12 &&
+ (adev->pm.pp_feature & PP_GFXOFF_MASK)) {
+ if (adev->gfx.funcs->init_spm_golden) {
+ dev_dbg(adev->dev,"GFXOFF exited, re-init SPM golden settings\n");
+ amdgpu_gfx_init_spm_golden(adev);
+ } else
+ dev_warn(adev->dev,"Callback init_spm_golden is NULL\n");
+ }
}
} else {
/* exit umd pstate, restore level, enable gfx cg*/
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* RE: [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit
[not found] ` <CY4PR12MB1623B0A15166F72FF7032C2AFE730@CY4PR12MB1623.namprd12.prod.outlook.com>
@ 2020-07-28 6:23 ` Yin, Tianci (Rico)
0 siblings, 0 replies; 10+ messages in thread
From: Yin, Tianci (Rico) @ 2020-07-28 6:23 UTC (permalink / raw)
To: Xu, Feifei, amd-gfx
Cc: Tuikov, Luben, Hesik, Christopher, Deucher, Alexander, Swamy,
Manjunatha, Quan, Evan, Feng, Kenneth, Zhang, Hawking
[AMD Official Use Only - Internal Distribution Only]
Thanks Feifei!
Rico
-----Original Message-----
From: Xu, Feifei <Feifei.Xu@amd.com>
Sent: Tuesday, July 28, 2020 2:21 PM
To: Yin, Tianci (Rico) <Tianci.Yin@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Tuikov, Luben <Luben.Tuikov@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Hesik, Christopher <Christopher.Hesik@amd.com>; Swamy, Manjunatha <Manjunatha.Swamy@amd.com>; Quan, Evan <Evan.Quan@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com>; Yin, Tianci (Rico) <Tianci.Yin@amd.com>
Subject: RE: [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit
[AMD Official Use Only - Internal Distribution Only]
Series is Reviewed-by: Feifei Xu <Feifei Xu@amd.com>
-----Original Message-----
From: Tianci Yin <tianci.yin@amd.com>
Sent: Tuesday, July 28, 2020 1:27 PM
To: amd-gfx@lists.freedesktop.org
Cc: Tuikov, Luben <Luben.Tuikov@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Xu, Feifei <Feifei.Xu@amd.com>; Hesik, Christopher <Christopher.Hesik@amd.com>; Swamy, Manjunatha <Manjunatha.Swamy@amd.com>; Quan, Evan <Evan.Quan@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com>; Yin, Tianci (Rico) <Tianci.Yin@amd.com>
Subject: [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit
From: "Tianci.Yin" <tianci.yin@amd.com>
On Navi1x, the SPM golden settings will be lost after GFXOFF enter/exit, reconfigure the golden settings after GFXOFF exit.
Change-Id: I9358ba9c65f241c36f8a35916170b19535148ee9
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 55463e7a11e2..5da0436d41e0 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1309,6 +1309,7 @@ static int smu_enable_umd_pstate(void *handle,
struct smu_context *smu = (struct smu_context*)(handle); struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+struct amdgpu_device *adev = smu->adev;
if (!smu->is_apu && !smu_dpm_ctx->dpm_context) return -EINVAL; @@ -1324,6 +1325,16 @@ static int smu_enable_umd_pstate(void *handle, amdgpu_device_ip_set_clockgating_state(smu->adev,
AMD_IP_BLOCK_TYPE_GFX,
AMD_CG_STATE_UNGATE);
+
+if (adev->asic_type >= CHIP_NAVI10 &&
+ adev->asic_type <= CHIP_NAVI12 &&
+ (adev->pm.pp_feature & PP_GFXOFF_MASK)) { if
+(adev->gfx.funcs->init_spm_golden) { dev_dbg(adev->dev,"GFXOFF exited,
+re-init SPM golden settings\n"); amdgpu_gfx_init_spm_golden(adev); }
+else dev_warn(adev->dev,"Callback init_spm_golden is NULL\n"); }
}
} else {
/* exit umd pstate, restore level, enable gfx cg*/
--
2.17.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* RE: [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit
2020-07-28 5:27 ` [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit Tianci Yin
[not found] ` <CY4PR12MB1623B0A15166F72FF7032C2AFE730@CY4PR12MB1623.namprd12.prod.outlook.com>
@ 2020-07-28 6:26 ` Chen, Guchun
2020-07-28 6:48 ` Yin, Tianci (Rico)
2020-07-28 18:44 ` Luben Tuikov
2 siblings, 1 reply; 10+ messages in thread
From: Chen, Guchun @ 2020-07-28 6:26 UTC (permalink / raw)
To: Yin, Tianci (Rico), amd-gfx
Cc: Xu, Feifei, Yin, Tianci (Rico),
Tuikov, Luben, Hesik, Christopher, Deucher, Alexander, Swamy,
Manjunatha, Quan, Evan, Feng, Kenneth, Zhang, Hawking
[AMD Public Use]
One minor comment.
Regards,
Guchun
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Tianci Yin
Sent: Tuesday, July 28, 2020 1:27 PM
To: amd-gfx@lists.freedesktop.org
Cc: Xu, Feifei <Feifei.Xu@amd.com>; Yin, Tianci (Rico) <Tianci.Yin@amd.com>; Tuikov, Luben <Luben.Tuikov@amd.com>; Hesik, Christopher <Christopher.Hesik@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Swamy, Manjunatha <Manjunatha.Swamy@amd.com>; Quan, Evan <Evan.Quan@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>
Subject: [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit
From: "Tianci.Yin" <tianci.yin@amd.com>
On Navi1x, the SPM golden settings will be lost after GFXOFF enter/exit, reconfigure the golden settings after GFXOFF exit.
Change-Id: I9358ba9c65f241c36f8a35916170b19535148ee9
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 55463e7a11e2..5da0436d41e0 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1309,6 +1309,7 @@ static int smu_enable_umd_pstate(void *handle,
struct smu_context *smu = (struct smu_context*)(handle);
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+ struct amdgpu_device *adev = smu->adev;
if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
return -EINVAL;
@@ -1324,6 +1325,16 @@ static int smu_enable_umd_pstate(void *handle,
amdgpu_device_ip_set_clockgating_state(smu->adev,
[Guchun]Use the local adev instead of smu->adev?
AMD_IP_BLOCK_TYPE_GFX,
AMD_CG_STATE_UNGATE);
+
+ if (adev->asic_type >= CHIP_NAVI10 &&
+ adev->asic_type <= CHIP_NAVI12 &&
+ (adev->pm.pp_feature & PP_GFXOFF_MASK)) {
+ if (adev->gfx.funcs->init_spm_golden) {
+ dev_dbg(adev->dev,"GFXOFF exited, re-init SPM golden settings\n");
+ amdgpu_gfx_init_spm_golden(adev);
+ } else
+ dev_warn(adev->dev,"Callback init_spm_golden is NULL\n");
+ }
}
} else {
/* exit umd pstate, restore level, enable gfx cg*/
--
2.17.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* RE: [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit
2020-07-28 6:26 ` Chen, Guchun
@ 2020-07-28 6:48 ` Yin, Tianci (Rico)
2020-07-28 7:03 ` Chen, Guchun
0 siblings, 1 reply; 10+ messages in thread
From: Yin, Tianci (Rico) @ 2020-07-28 6:48 UTC (permalink / raw)
To: Chen, Guchun, amd-gfx
Cc: Xu, Feifei, Tuikov, Luben, Hesik, Christopher, Deucher,
Alexander, Swamy, Manjunatha, Quan, Evan, Feng, Kenneth, Zhang,
Hawking
Hi Guchun,
Since the adev variable invoked a few times, local adev make the code more concise.
Thanks!
Rico
-----Original Message-----
From: Chen, Guchun <Guchun.Chen@amd.com>
Sent: Tuesday, July 28, 2020 2:26 PM
To: Yin, Tianci (Rico) <Tianci.Yin@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Xu, Feifei <Feifei.Xu@amd.com>; Yin, Tianci (Rico) <Tianci.Yin@amd.com>; Tuikov, Luben <Luben.Tuikov@amd.com>; Hesik, Christopher <Christopher.Hesik@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Swamy, Manjunatha <Manjunatha.Swamy@amd.com>; Quan, Evan <Evan.Quan@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>
Subject: RE: [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit
[AMD Public Use]
One minor comment.
Regards,
Guchun
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Tianci Yin
Sent: Tuesday, July 28, 2020 1:27 PM
To: amd-gfx@lists.freedesktop.org
Cc: Xu, Feifei <Feifei.Xu@amd.com>; Yin, Tianci (Rico) <Tianci.Yin@amd.com>; Tuikov, Luben <Luben.Tuikov@amd.com>; Hesik, Christopher <Christopher.Hesik@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Swamy, Manjunatha <Manjunatha.Swamy@amd.com>; Quan, Evan <Evan.Quan@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>
Subject: [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit
From: "Tianci.Yin" <tianci.yin@amd.com>
On Navi1x, the SPM golden settings will be lost after GFXOFF enter/exit, reconfigure the golden settings after GFXOFF exit.
Change-Id: I9358ba9c65f241c36f8a35916170b19535148ee9
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 55463e7a11e2..5da0436d41e0 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1309,6 +1309,7 @@ static int smu_enable_umd_pstate(void *handle,
struct smu_context *smu = (struct smu_context*)(handle);
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+ struct amdgpu_device *adev = smu->adev;
if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
return -EINVAL;
@@ -1324,6 +1325,16 @@ static int smu_enable_umd_pstate(void *handle,
amdgpu_device_ip_set_clockgating_state(smu->adev,
[Guchun]Use the local adev instead of smu->adev?
AMD_IP_BLOCK_TYPE_GFX,
AMD_CG_STATE_UNGATE);
+
+ if (adev->asic_type >= CHIP_NAVI10 &&
+ adev->asic_type <= CHIP_NAVI12 &&
+ (adev->pm.pp_feature & PP_GFXOFF_MASK)) {
+ if (adev->gfx.funcs->init_spm_golden) {
+ dev_dbg(adev->dev,"GFXOFF exited, re-init SPM golden settings\n");
+ amdgpu_gfx_init_spm_golden(adev);
+ } else
+ dev_warn(adev->dev,"Callback init_spm_golden is NULL\n");
+ }
}
} else {
/* exit umd pstate, restore level, enable gfx cg*/
--
2.17.1
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* RE: [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit
2020-07-28 6:48 ` Yin, Tianci (Rico)
@ 2020-07-28 7:03 ` Chen, Guchun
0 siblings, 0 replies; 10+ messages in thread
From: Chen, Guchun @ 2020-07-28 7:03 UTC (permalink / raw)
To: Yin, Tianci (Rico), amd-gfx
Cc: Xu, Feifei, Tuikov, Luben, Hesik, Christopher, Deucher,
Alexander, Swamy, Manjunatha, Quan, Evan, Feng, Kenneth, Zhang,
Hawking
[AMD Public Use]
Hi Tianci,
My point is, as in the new patch, one new local adev variable is introduced, then in the same function, for others where smu->adev is used should be replace by the new local adev as well.
Otherwise, it looks not perfect from coding style's perspective.
Regards,
Guchun
-----Original Message-----
From: Yin, Tianci (Rico) <Tianci.Yin@amd.com>
Sent: Tuesday, July 28, 2020 2:48 PM
To: Chen, Guchun <Guchun.Chen@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Xu, Feifei <Feifei.Xu@amd.com>; Tuikov, Luben <Luben.Tuikov@amd.com>; Hesik, Christopher <Christopher.Hesik@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Swamy, Manjunatha <Manjunatha.Swamy@amd.com>; Quan, Evan <Evan.Quan@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>
Subject: RE: [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit
Hi Guchun,
Since the adev variable invoked a few times, local adev make the code more concise.
Thanks!
Rico
-----Original Message-----
From: Chen, Guchun <Guchun.Chen@amd.com>
Sent: Tuesday, July 28, 2020 2:26 PM
To: Yin, Tianci (Rico) <Tianci.Yin@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Xu, Feifei <Feifei.Xu@amd.com>; Yin, Tianci (Rico) <Tianci.Yin@amd.com>; Tuikov, Luben <Luben.Tuikov@amd.com>; Hesik, Christopher <Christopher.Hesik@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Swamy, Manjunatha <Manjunatha.Swamy@amd.com>; Quan, Evan <Evan.Quan@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>
Subject: RE: [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit
[AMD Public Use]
One minor comment.
Regards,
Guchun
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Tianci Yin
Sent: Tuesday, July 28, 2020 1:27 PM
To: amd-gfx@lists.freedesktop.org
Cc: Xu, Feifei <Feifei.Xu@amd.com>; Yin, Tianci (Rico) <Tianci.Yin@amd.com>; Tuikov, Luben <Luben.Tuikov@amd.com>; Hesik, Christopher <Christopher.Hesik@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Swamy, Manjunatha <Manjunatha.Swamy@amd.com>; Quan, Evan <Evan.Quan@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>
Subject: [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit
From: "Tianci.Yin" <tianci.yin@amd.com>
On Navi1x, the SPM golden settings will be lost after GFXOFF enter/exit, reconfigure the golden settings after GFXOFF exit.
Change-Id: I9358ba9c65f241c36f8a35916170b19535148ee9
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 55463e7a11e2..5da0436d41e0 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1309,6 +1309,7 @@ static int smu_enable_umd_pstate(void *handle,
struct smu_context *smu = (struct smu_context*)(handle);
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+ struct amdgpu_device *adev = smu->adev;
if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
return -EINVAL;
@@ -1324,6 +1325,16 @@ static int smu_enable_umd_pstate(void *handle,
amdgpu_device_ip_set_clockgating_state(smu->adev,
[Guchun]Use the local adev instead of smu->adev?
AMD_IP_BLOCK_TYPE_GFX,
AMD_CG_STATE_UNGATE);
+
+ if (adev->asic_type >= CHIP_NAVI10 &&
+ adev->asic_type <= CHIP_NAVI12 &&
+ (adev->pm.pp_feature & PP_GFXOFF_MASK)) {
+ if (adev->gfx.funcs->init_spm_golden) {
+ dev_dbg(adev->dev,"GFXOFF exited, re-init SPM golden settings\n");
+ amdgpu_gfx_init_spm_golden(adev);
+ } else
+ dev_warn(adev->dev,"Callback init_spm_golden is NULL\n");
+ }
}
} else {
/* exit umd pstate, restore level, enable gfx cg*/
--
2.17.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu: add interface amdgpu_gfx_init_spm_golden for Navi1x
2020-07-28 5:27 [PATCH 1/2] drm/amdgpu: add interface amdgpu_gfx_init_spm_golden for Navi1x Tianci Yin
2020-07-28 5:27 ` [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit Tianci Yin
@ 2020-07-28 18:29 ` Luben Tuikov
2020-07-29 2:34 ` Yin, Tianci (Rico)
1 sibling, 1 reply; 10+ messages in thread
From: Luben Tuikov @ 2020-07-28 18:29 UTC (permalink / raw)
To: Tianci Yin, amd-gfx
Cc: Feifei Xu, Hesik Christopher, Deucher Alexander,
Swamy Manjunatha, Evan Quan, Feng Kenneth, Hawking Zhang
On 2020-07-28 1:27 a.m., Tianci Yin wrote:
> From: "Tianci.Yin" <tianci.yin@amd.com>
>
> On Navi1x, the SPM golden settings will be lost after GFXOFF enter/exit,
Use present tense:............... " are lost after "
> reconfiguration is needed. Make the configuration code as an interface for
Add "so a reconfiguration is needed. "
> future use.
>
If the lines of your commit message are too long, then "git push" complains
about them. Sixty char wide is perfect, since "git log" indents them when
displaying them.
With this fixed, then Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Regards,
Luben
> Change-Id: I172f3dc7f59da69b0364052dcad75a9c9aab019e
> Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 ++
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 34 ++++++++++++++++++-------
> 2 files changed, 27 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index 1e7a2b0997c5..a611e78dd4ba 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -216,6 +216,7 @@ struct amdgpu_gfx_funcs {
> int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if);
> int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status);
> void (*reset_ras_error_count) (struct amdgpu_device *adev);
> + void (*init_spm_golden)(struct amdgpu_device *adev);
> };
>
> struct sq_work {
> @@ -324,6 +325,7 @@ struct amdgpu_gfx {
> #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
> #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
> #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))
> +#define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev))
>
> /**
> * amdgpu_gfx_create_bitmask - create a bitmask
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index db9f1e89a0f8..da21ad04ac0f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -3307,6 +3307,29 @@ static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
> adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
> }
>
> +static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
> +{
> + switch (adev->asic_type) {
> + case CHIP_NAVI10:
> + soc15_program_register_sequence(adev,
> + golden_settings_gc_rlc_spm_10_0_nv10,
> + (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
> + break;
> + case CHIP_NAVI14:
> + soc15_program_register_sequence(adev,
> + golden_settings_gc_rlc_spm_10_1_nv14,
> + (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
> + break;
> + case CHIP_NAVI12:
> + soc15_program_register_sequence(adev,
> + golden_settings_gc_rlc_spm_10_1_2_nv12,
> + (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
> + break;
> + default:
> + break;
> + }
> +}
> +
> static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
> {
> switch (adev->asic_type) {
> @@ -3317,9 +3340,6 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
> soc15_program_register_sequence(adev,
> golden_settings_gc_10_0_nv10,
> (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
> - soc15_program_register_sequence(adev,
> - golden_settings_gc_rlc_spm_10_0_nv10,
> - (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
> break;
> case CHIP_NAVI14:
> soc15_program_register_sequence(adev,
> @@ -3328,9 +3348,6 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
> soc15_program_register_sequence(adev,
> golden_settings_gc_10_1_nv14,
> (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
> - soc15_program_register_sequence(adev,
> - golden_settings_gc_rlc_spm_10_1_nv14,
> - (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
> break;
> case CHIP_NAVI12:
> soc15_program_register_sequence(adev,
> @@ -3339,9 +3356,6 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
> soc15_program_register_sequence(adev,
> golden_settings_gc_10_1_2_nv12,
> (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
> - soc15_program_register_sequence(adev,
> - golden_settings_gc_rlc_spm_10_1_2_nv12,
> - (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
> break;
> case CHIP_SIENNA_CICHLID:
> soc15_program_register_sequence(adev,
> @@ -3360,6 +3374,7 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
> default:
> break;
> }
> + gfx_v10_0_init_spm_golden_registers(adev);
> }
>
> static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
> @@ -4147,6 +4162,7 @@ static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
> .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
> .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
> .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
> + .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
> };
>
> static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
>
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit
2020-07-28 5:27 ` [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit Tianci Yin
[not found] ` <CY4PR12MB1623B0A15166F72FF7032C2AFE730@CY4PR12MB1623.namprd12.prod.outlook.com>
2020-07-28 6:26 ` Chen, Guchun
@ 2020-07-28 18:44 ` Luben Tuikov
2020-07-29 2:42 ` Yin, Tianci (Rico)
2 siblings, 1 reply; 10+ messages in thread
From: Luben Tuikov @ 2020-07-28 18:44 UTC (permalink / raw)
To: Tianci Yin, amd-gfx
Cc: Feifei Xu, Hesik Christopher, Deucher Alexander,
Swamy Manjunatha, Evan Quan, Feng Kenneth, Hawking Zhang
On 2020-07-28 1:27 a.m., Tianci Yin wrote:
> From: "Tianci.Yin" <tianci.yin@amd.com>
>
> On Navi1x, the SPM golden settings will be lost after GFXOFF enter/exit,
" are lost "
> reconfigure the golden settings after GFXOFF exit.
" so reconfigure ..."
>
> Change-Id: I9358ba9c65f241c36f8a35916170b19535148ee9
> Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 55463e7a11e2..5da0436d41e0 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1309,6 +1309,7 @@ static int smu_enable_umd_pstate(void *handle,
>
> struct smu_context *smu = (struct smu_context*)(handle);
> struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
> + struct amdgpu_device *adev = smu->adev;
>
> if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
> return -EINVAL;
> @@ -1324,6 +1325,16 @@ static int smu_enable_umd_pstate(void *handle,
> amdgpu_device_ip_set_clockgating_state(smu->adev,
> AMD_IP_BLOCK_TYPE_GFX,
> AMD_CG_STATE_UNGATE);
> +
> + if (adev->asic_type >= CHIP_NAVI10 &&
> + adev->asic_type <= CHIP_NAVI12 &&
> + (adev->pm.pp_feature & PP_GFXOFF_MASK)) {
> + if (adev->gfx.funcs->init_spm_golden) {
> + dev_dbg(adev->dev,"GFXOFF exited, re-init SPM golden settings\n");
Space after comma is required.
> + amdgpu_gfx_init_spm_golden(adev);
> + } else
> + dev_warn(adev->dev,"Callback init_spm_golden is NULL\n");
Space after comma is required.
Please add braces to the single statement of the "else". The reason for this
is that it complements the braces of the "if ( ) {" of the multi-line statement
and closes the block. "checkpatch" calls it "unbalanced braces".
With these three fixed, this patch is
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Regards,
Luben
> + }
> }
> } else {
> /* exit umd pstate, restore level, enable gfx cg*/
>
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu: add interface amdgpu_gfx_init_spm_golden for Navi1x
2020-07-28 18:29 ` [PATCH 1/2] drm/amdgpu: add interface amdgpu_gfx_init_spm_golden for Navi1x Luben Tuikov
@ 2020-07-29 2:34 ` Yin, Tianci (Rico)
0 siblings, 0 replies; 10+ messages in thread
From: Yin, Tianci (Rico) @ 2020-07-29 2:34 UTC (permalink / raw)
To: Tuikov, Luben, amd-gfx
Cc: Xu, Feifei, Hesik, Christopher, Deucher, Alexander, Swamy,
Manjunatha, Quan, Evan, Feng, Kenneth, Zhang, Hawking
[-- Attachment #1.1: Type: text/plain, Size: 7226 bytes --]
[AMD Official Use Only - Internal Distribution Only]
Thanks very much Luben!
Regards,
Rico
________________________________
From: Tuikov, Luben <Luben.Tuikov@amd.com>
Sent: Wednesday, July 29, 2020 2:29
To: Yin, Tianci (Rico) <Tianci.Yin@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Xu, Feifei <Feifei.Xu@amd.com>; Hesik, Christopher <Christopher.Hesik@amd.com>; Swamy, Manjunatha <Manjunatha.Swamy@amd.com>; Quan, Evan <Evan.Quan@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com>
Subject: Re: [PATCH 1/2] drm/amdgpu: add interface amdgpu_gfx_init_spm_golden for Navi1x
On 2020-07-28 1:27 a.m., Tianci Yin wrote:
> From: "Tianci.Yin" <tianci.yin@amd.com>
>
> On Navi1x, the SPM golden settings will be lost after GFXOFF enter/exit,
Use present tense:............... " are lost after "
> reconfiguration is needed. Make the configuration code as an interface for
Add "so a reconfiguration is needed. "
> future use.
>
If the lines of your commit message are too long, then "git push" complains
about them. Sixty char wide is perfect, since "git log" indents them when
displaying them.
With this fixed, then Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Regards,
Luben
> Change-Id: I172f3dc7f59da69b0364052dcad75a9c9aab019e
> Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 ++
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 34 ++++++++++++++++++-------
> 2 files changed, 27 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index 1e7a2b0997c5..a611e78dd4ba 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -216,6 +216,7 @@ struct amdgpu_gfx_funcs {
> int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if);
> int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status);
> void (*reset_ras_error_count) (struct amdgpu_device *adev);
> + void (*init_spm_golden)(struct amdgpu_device *adev);
> };
>
> struct sq_work {
> @@ -324,6 +325,7 @@ struct amdgpu_gfx {
> #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
> #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
> #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))
> +#define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev))
>
> /**
> * amdgpu_gfx_create_bitmask - create a bitmask
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index db9f1e89a0f8..da21ad04ac0f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -3307,6 +3307,29 @@ static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
> adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
> }
>
> +static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
> +{
> + switch (adev->asic_type) {
> + case CHIP_NAVI10:
> + soc15_program_register_sequence(adev,
> + golden_settings_gc_rlc_spm_10_0_nv10,
> + (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
> + break;
> + case CHIP_NAVI14:
> + soc15_program_register_sequence(adev,
> + golden_settings_gc_rlc_spm_10_1_nv14,
> + (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
> + break;
> + case CHIP_NAVI12:
> + soc15_program_register_sequence(adev,
> + golden_settings_gc_rlc_spm_10_1_2_nv12,
> + (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
> + break;
> + default:
> + break;
> + }
> +}
> +
> static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
> {
> switch (adev->asic_type) {
> @@ -3317,9 +3340,6 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
> soc15_program_register_sequence(adev,
> golden_settings_gc_10_0_nv10,
> (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
> - soc15_program_register_sequence(adev,
> - golden_settings_gc_rlc_spm_10_0_nv10,
> - (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
> break;
> case CHIP_NAVI14:
> soc15_program_register_sequence(adev,
> @@ -3328,9 +3348,6 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
> soc15_program_register_sequence(adev,
> golden_settings_gc_10_1_nv14,
> (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
> - soc15_program_register_sequence(adev,
> - golden_settings_gc_rlc_spm_10_1_nv14,
> - (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
> break;
> case CHIP_NAVI12:
> soc15_program_register_sequence(adev,
> @@ -3339,9 +3356,6 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
> soc15_program_register_sequence(adev,
> golden_settings_gc_10_1_2_nv12,
> (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
> - soc15_program_register_sequence(adev,
> - golden_settings_gc_rlc_spm_10_1_2_nv12,
> - (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
> break;
> case CHIP_SIENNA_CICHLID:
> soc15_program_register_sequence(adev,
> @@ -3360,6 +3374,7 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
> default:
> break;
> }
> + gfx_v10_0_init_spm_golden_registers(adev);
> }
>
> static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
> @@ -4147,6 +4162,7 @@ static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
> .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
> .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
> .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
> + .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
> };
>
> static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
>
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit
2020-07-28 18:44 ` Luben Tuikov
@ 2020-07-29 2:42 ` Yin, Tianci (Rico)
0 siblings, 0 replies; 10+ messages in thread
From: Yin, Tianci (Rico) @ 2020-07-29 2:42 UTC (permalink / raw)
To: Tuikov, Luben, amd-gfx
Cc: Xu, Feifei, Hesik, Christopher, Deucher, Alexander, Swamy,
Manjunatha, Quan, Evan, Feng, Kenneth, Zhang, Hawking
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[AMD Official Use Only - Internal Distribution Only]
Thanks very much Lunben and Guchun!
Regards,
Rico
________________________________
From: Tuikov, Luben <Luben.Tuikov@amd.com>
Sent: Wednesday, July 29, 2020 2:44
To: Yin, Tianci (Rico) <Tianci.Yin@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Xu, Feifei <Feifei.Xu@amd.com>; Hesik, Christopher <Christopher.Hesik@amd.com>; Swamy, Manjunatha <Manjunatha.Swamy@amd.com>; Quan, Evan <Evan.Quan@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com>
Subject: Re: [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit
On 2020-07-28 1:27 a.m., Tianci Yin wrote:
> From: "Tianci.Yin" <tianci.yin@amd.com>
>
> On Navi1x, the SPM golden settings will be lost after GFXOFF enter/exit,
" are lost "
> reconfigure the golden settings after GFXOFF exit.
" so reconfigure ..."
>
> Change-Id: I9358ba9c65f241c36f8a35916170b19535148ee9
> Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 55463e7a11e2..5da0436d41e0 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1309,6 +1309,7 @@ static int smu_enable_umd_pstate(void *handle,
>
> struct smu_context *smu = (struct smu_context*)(handle);
> struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
> + struct amdgpu_device *adev = smu->adev;
>
> if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
> return -EINVAL;
> @@ -1324,6 +1325,16 @@ static int smu_enable_umd_pstate(void *handle,
> amdgpu_device_ip_set_clockgating_state(smu->adev,
> AMD_IP_BLOCK_TYPE_GFX,
> AMD_CG_STATE_UNGATE);
> +
> + if (adev->asic_type >= CHIP_NAVI10 &&
> + adev->asic_type <= CHIP_NAVI12 &&
> + (adev->pm.pp_feature & PP_GFXOFF_MASK)) {
> + if (adev->gfx.funcs->init_spm_golden) {
> + dev_dbg(adev->dev,"GFXOFF exited, re-init SPM golden settings\n");
Space after comma is required.
> + amdgpu_gfx_init_spm_golden(adev);
> + } else
> + dev_warn(adev->dev,"Callback init_spm_golden is NULL\n");
Space after comma is required.
Please add braces to the single statement of the "else". The reason for this
is that it complements the braces of the "if ( ) {" of the multi-line statement
and closes the block. "checkpatch" calls it "unbalanced braces".
With these three fixed, this patch is
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Regards,
Luben
> + }
> }
> } else {
> /* exit umd pstate, restore level, enable gfx cg*/
>
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^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-07-29 2:42 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-28 5:27 [PATCH 1/2] drm/amdgpu: add interface amdgpu_gfx_init_spm_golden for Navi1x Tianci Yin
2020-07-28 5:27 ` [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit Tianci Yin
[not found] ` <CY4PR12MB1623B0A15166F72FF7032C2AFE730@CY4PR12MB1623.namprd12.prod.outlook.com>
2020-07-28 6:23 ` Yin, Tianci (Rico)
2020-07-28 6:26 ` Chen, Guchun
2020-07-28 6:48 ` Yin, Tianci (Rico)
2020-07-28 7:03 ` Chen, Guchun
2020-07-28 18:44 ` Luben Tuikov
2020-07-29 2:42 ` Yin, Tianci (Rico)
2020-07-28 18:29 ` [PATCH 1/2] drm/amdgpu: add interface amdgpu_gfx_init_spm_golden for Navi1x Luben Tuikov
2020-07-29 2:34 ` Yin, Tianci (Rico)
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