All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH 1/2] drm/amd/powerplay: update swSMU VCN/JPEG PG logics
@ 2020-08-03  4:46 Evan Quan
  2020-08-03  4:46 ` [PATCH 2/2] drm/amd/powerplay: put VCN/JPEG into PG ungate state before dpm table setup Evan Quan
  0 siblings, 1 reply; 5+ messages in thread
From: Evan Quan @ 2020-08-03  4:46 UTC (permalink / raw)
  To: amd-gfx; +Cc: alexander.deucher, mcoffin13, Evan Quan

Add lock protections and avoid unnecessary actions
if the PG state is already the same as required.

Change-Id: I01400b84151d3ac6e3c8b0d7e264f9a68a9c2092
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 57 ++++++++++++++++++-
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c  |  4 --
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  6 +-
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c    |  8 ---
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c    |  8 ---
 .../drm/amd/powerplay/sienna_cichlid_ppt.c    |  9 ---
 drivers/gpu/drm/amd/powerplay/smu_internal.h  |  2 -
 7 files changed, 60 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index cf9c5205ef08..85b04c48bd09 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -133,6 +133,56 @@ int smu_get_dpm_freq_range(struct smu_context *smu,
 	return ret;
 }
 
+static int smu_dpm_set_vcn_enable(struct smu_context *smu,
+				  bool enable)
+{
+	struct smu_power_context *smu_power = &smu->smu_power;
+	struct smu_power_gate *power_gate = &smu_power->power_gate;
+	int ret = 0;
+
+	if (!smu->ppt_funcs->dpm_set_vcn_enable)
+		return 0;
+
+	mutex_lock(&power_gate->vcn_gate_lock);
+
+	if (atomic_read(&power_gate->vcn_gated) ^ enable)
+		goto out;
+
+	ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
+	if (!ret)
+		atomic_set(&power_gate->vcn_gated, !enable);
+
+out:
+	mutex_unlock(&power_gate->vcn_gate_lock);
+
+	return ret;
+}
+
+static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
+				   bool enable)
+{
+	struct smu_power_context *smu_power = &smu->smu_power;
+	struct smu_power_gate *power_gate = &smu_power->power_gate;
+	int ret = 0;
+
+	if (!smu->ppt_funcs->dpm_set_jpeg_enable)
+		return 0;
+
+	mutex_lock(&power_gate->jpeg_gate_lock);
+
+	if (atomic_read(&power_gate->jpeg_gated) ^ enable)
+		goto out;
+
+	ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
+	if (!ret)
+		atomic_set(&power_gate->jpeg_gated, !enable);
+
+out:
+	mutex_unlock(&power_gate->jpeg_gate_lock);
+
+	return ret;
+}
+
 /**
  * smu_dpm_set_power_gate - power gate/ungate the specific IP block
  *
@@ -644,6 +694,11 @@ static int smu_sw_init(void *handle)
 	smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 	smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 
+	atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
+	atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
+	mutex_init(&smu->smu_power.power_gate.vcn_gate_lock);
+	mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock);
+
 	smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 	smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
 	smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
@@ -1974,7 +2029,7 @@ int smu_read_sensor(struct smu_context *smu,
 		*size = 4;
 		break;
 	case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
-		*(uint32_t *)data = smu->smu_power.power_gate.vcn_gated ? 0 : 1;
+		*(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1;
 		*size = 4;
 		break;
 	case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index d678534ddc69..a2ba6633fc21 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -1894,8 +1894,6 @@ static bool arcturus_is_dpm_running(struct smu_context *smu)
 
 static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 {
-	struct smu_power_context *smu_power = &smu->smu_power;
-	struct smu_power_gate *power_gate = &smu_power->power_gate;
 	int ret = 0;
 
 	if (enable) {
@@ -1906,7 +1904,6 @@ static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 				return ret;
 			}
 		}
-		power_gate->vcn_gated = false;
 	} else {
 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 			ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
@@ -1915,7 +1912,6 @@ static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 				return ret;
 			}
 		}
-		power_gate->vcn_gated = true;
 	}
 
 	return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ec2d2aa7f4ec..23c2279bd500 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -295,8 +295,10 @@ struct smu_dpm_context {
 struct smu_power_gate {
 	bool uvd_gated;
 	bool vce_gated;
-	bool vcn_gated;
-	bool jpeg_gated;
+	atomic_t vcn_gated;
+	atomic_t jpeg_gated;
+	struct mutex vcn_gate_lock;
+	struct mutex jpeg_gate_lock;
 };
 
 struct smu_power_context {
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index ee8d938ea3bd..9dfa27de7ef3 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -831,8 +831,6 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
 
 static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 {
-	struct smu_power_context *smu_power = &smu->smu_power;
-	struct smu_power_gate *power_gate = &smu_power->power_gate;
 	int ret = 0;
 
 	if (enable) {
@@ -842,14 +840,12 @@ static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 			if (ret)
 				return ret;
 		}
-		power_gate->vcn_gated = false;
 	} else {
 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
 			if (ret)
 				return ret;
 		}
-		power_gate->vcn_gated = true;
 	}
 
 	return ret;
@@ -857,8 +853,6 @@ static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 
 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 {
-	struct smu_power_context *smu_power = &smu->smu_power;
-	struct smu_power_gate *power_gate = &smu_power->power_gate;
 	int ret = 0;
 
 	if (enable) {
@@ -867,14 +861,12 @@ static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 			if (ret)
 				return ret;
 		}
-		power_gate->jpeg_gated = false;
 	} else {
 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL);
 			if (ret)
 				return ret;
 		}
-		power_gate->jpeg_gated = true;
 	}
 
 	return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 4c1a506c3c17..8a8e6033f71f 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -479,8 +479,6 @@ static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context
 
 static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 {
-	struct smu_power_context *smu_power = &smu->smu_power;
-	struct smu_power_gate *power_gate = &smu_power->power_gate;
 	int ret = 0;
 
 	if (enable) {
@@ -490,14 +488,12 @@ static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 			if (ret)
 				return ret;
 		}
-		power_gate->vcn_gated = false;
 	} else {
 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
 			if (ret)
 				return ret;
 		}
-		power_gate->vcn_gated = true;
 	}
 
 	return ret;
@@ -505,8 +501,6 @@ static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 
 static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 {
-	struct smu_power_context *smu_power = &smu->smu_power;
-	struct smu_power_gate *power_gate = &smu_power->power_gate;
 	int ret = 0;
 
 	if (enable) {
@@ -515,14 +509,12 @@ static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 			if (ret)
 				return ret;
 		}
-		power_gate->jpeg_gated = false;
 	} else {
 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
 			if (ret)
 				return ret;
 		}
-		power_gate->jpeg_gated = true;
 	}
 
 	return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index a95c82a709d8..2c0ebb86f109 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -815,10 +815,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 
 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 {
-	struct smu_power_context *smu_power = &smu->smu_power;
-	struct smu_power_gate *power_gate = &smu_power->power_gate;
 	struct amdgpu_device *adev = smu->adev;
-
 	int ret = 0;
 
 	if (enable) {
@@ -834,7 +831,6 @@ static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enabl
 					return ret;
 			}
 		}
-		power_gate->vcn_gated = false;
 	} else {
 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
@@ -847,7 +843,6 @@ static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enabl
 					return ret;
 			}
 		}
-		power_gate->vcn_gated = true;
 	}
 
 	return ret;
@@ -855,8 +850,6 @@ static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enabl
 
 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 {
-	struct smu_power_context *smu_power = &smu->smu_power;
-	struct smu_power_gate *power_gate = &smu_power->power_gate;
 	int ret = 0;
 
 	if (enable) {
@@ -865,14 +858,12 @@ static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enab
 			if (ret)
 				return ret;
 		}
-		power_gate->jpeg_gated = false;
 	} else {
 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
 			if (ret)
 				return ret;
 		}
-		power_gate->jpeg_gated = true;
 	}
 
 	return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
index d0deaefd3feb..f1d8f247e589 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
@@ -77,8 +77,6 @@
 #define smu_get_dal_power_level(smu, clocks)				smu_ppt_funcs(get_dal_power_level, 0, smu, clocks)
 #define smu_get_perf_level(smu, designation, level)			smu_ppt_funcs(get_perf_level, 0, smu, designation, level)
 #define smu_get_current_shallow_sleep_clocks(smu, clocks)		smu_ppt_funcs(get_current_shallow_sleep_clocks, 0, smu, clocks)
-#define smu_dpm_set_vcn_enable(smu, enable)				smu_ppt_funcs(dpm_set_vcn_enable, 0, smu, enable)
-#define smu_dpm_set_jpeg_enable(smu, enable)				smu_ppt_funcs(dpm_set_jpeg_enable, 0, smu, enable)
 #define smu_set_watermarks_table(smu, clock_ranges)			smu_ppt_funcs(set_watermarks_table, 0, smu, clock_ranges)
 #define smu_thermal_temperature_range_update(smu, range, rw)		smu_ppt_funcs(thermal_temperature_range_update, 0, smu, range, rw)
 #define smu_register_irq_handler(smu)					smu_ppt_funcs(register_irq_handler, 0, smu)
-- 
2.28.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [PATCH 2/2] drm/amd/powerplay: put VCN/JPEG into PG ungate state before dpm table setup
  2020-08-03  4:46 [PATCH 1/2] drm/amd/powerplay: update swSMU VCN/JPEG PG logics Evan Quan
@ 2020-08-03  4:46 ` Evan Quan
  2020-08-03 16:29   ` Matt Coffin
  2020-08-04 19:55   ` Alex Deucher
  0 siblings, 2 replies; 5+ messages in thread
From: Evan Quan @ 2020-08-03  4:46 UTC (permalink / raw)
  To: amd-gfx; +Cc: alexander.deucher, mcoffin13, Evan Quan

As VCN related dpm table setup needs VCN be in PG ungate state. Same logics
applies to JPEG.

Change-Id: I94335efc4e0424cfe0991e984c938998fd8f1287
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 38 +++++++++++++++++-----
 1 file changed, 30 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 85b04c48bd09..1349d05c5f3d 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -134,7 +134,8 @@ int smu_get_dpm_freq_range(struct smu_context *smu,
 }
 
 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
-				  bool enable)
+				  bool enable,
+				  int *previous_pg_state)
 {
 	struct smu_power_context *smu_power = &smu->smu_power;
 	struct smu_power_gate *power_gate = &smu_power->power_gate;
@@ -148,6 +149,9 @@ static int smu_dpm_set_vcn_enable(struct smu_context *smu,
 	if (atomic_read(&power_gate->vcn_gated) ^ enable)
 		goto out;
 
+	if (previous_pg_state)
+		*previous_pg_state = atomic_read(&power_gate->vcn_gated);
+
 	ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
 	if (!ret)
 		atomic_set(&power_gate->vcn_gated, !enable);
@@ -159,7 +163,8 @@ static int smu_dpm_set_vcn_enable(struct smu_context *smu,
 }
 
 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
-				   bool enable)
+				   bool enable,
+				   int *previous_pg_state)
 {
 	struct smu_power_context *smu_power = &smu->smu_power;
 	struct smu_power_gate *power_gate = &smu_power->power_gate;
@@ -173,6 +178,9 @@ static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
 	if (atomic_read(&power_gate->jpeg_gated) ^ enable)
 		goto out;
 
+	if (previous_pg_state)
+		*previous_pg_state = atomic_read(&power_gate->jpeg_gated);
+
 	ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
 	if (!ret)
 		atomic_set(&power_gate->jpeg_gated, !enable);
@@ -212,7 +220,7 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 	 */
 	case AMD_IP_BLOCK_TYPE_UVD:
 	case AMD_IP_BLOCK_TYPE_VCN:
-		ret = smu_dpm_set_vcn_enable(smu, !gate);
+		ret = smu_dpm_set_vcn_enable(smu, !gate, NULL);
 		if (ret)
 			dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
 				gate ? "gate" : "ungate");
@@ -230,7 +238,7 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 				gate ? "gate" : "ungate");
 		break;
 	case AMD_IP_BLOCK_TYPE_JPEG:
-		ret = smu_dpm_set_jpeg_enable(smu, !gate);
+		ret = smu_dpm_set_jpeg_enable(smu, !gate, NULL);
 		if (ret)
 			dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
 				gate ? "gate" : "ungate");
@@ -407,6 +415,7 @@ static int smu_late_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	struct smu_context *smu = &adev->smu;
+	int vcn_gate, jpeg_gate;
 	int ret = 0;
 
 	if (!smu->pm_enabled)
@@ -418,6 +427,14 @@ static int smu_late_init(void *handle)
 		return ret;
 	}
 
+	/*
+	 * 1. Power up VCN/JPEG as the succeeding smu_set_default_dpm_table()
+	 *    needs VCN/JPEG up.
+	 * 2. Save original gate states and then we can restore back afterwards.
+	 */
+	smu_dpm_set_vcn_enable(smu, true, &vcn_gate);
+	smu_dpm_set_jpeg_enable(smu, true, &jpeg_gate);
+
 	/*
 	 * Set initialized values (get from vbios) to dpm tables context such as
 	 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
@@ -429,6 +446,11 @@ static int smu_late_init(void *handle)
 		return ret;
 	}
 
+	/* Restore back to original VCN/JPEG power gate states */
+	smu_dpm_set_vcn_enable(smu, !vcn_gate, NULL);
+	smu_dpm_set_jpeg_enable(smu, !vcn_gate, NULL);
+
+
 	ret = smu_populate_umd_state_clk(smu);
 	if (ret) {
 		dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
@@ -991,8 +1013,8 @@ static int smu_hw_init(void *handle)
 
 	if (smu->is_apu) {
 		smu_powergate_sdma(&adev->smu, false);
-		smu_dpm_set_vcn_enable(smu, true);
-		smu_dpm_set_jpeg_enable(smu, true);
+		smu_dpm_set_vcn_enable(smu, true, NULL);
+		smu_dpm_set_jpeg_enable(smu, true, NULL);
 		smu_set_gfx_cgpg(&adev->smu, true);
 	}
 
@@ -1132,8 +1154,8 @@ static int smu_hw_fini(void *handle)
 
 	if (smu->is_apu) {
 		smu_powergate_sdma(&adev->smu, true);
-		smu_dpm_set_vcn_enable(smu, false);
-		smu_dpm_set_jpeg_enable(smu, false);
+		smu_dpm_set_vcn_enable(smu, false, NULL);
+		smu_dpm_set_jpeg_enable(smu, false, NULL);
 	}
 
 	if (!smu->pm_enabled)
-- 
2.28.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] drm/amd/powerplay: put VCN/JPEG into PG ungate state before dpm table setup
  2020-08-03  4:46 ` [PATCH 2/2] drm/amd/powerplay: put VCN/JPEG into PG ungate state before dpm table setup Evan Quan
@ 2020-08-03 16:29   ` Matt Coffin
  2020-08-04 19:55   ` Alex Deucher
  1 sibling, 0 replies; 5+ messages in thread
From: Matt Coffin @ 2020-08-03 16:29 UTC (permalink / raw)
  To: Evan Quan, amd-gfx; +Cc: alexander.deucher

Thanks Evan! I can confirm that this resolved the following GitLab
issue. Thanks for CC'ing me!

https://gitlab.freedesktop.org/drm/amd/-/issues/1243

Series is Tested-by: Matt Coffin <mcoffin13@gmail.com>

On 8/2/20 10:46 PM, Evan Quan wrote:
> As VCN related dpm table setup needs VCN be in PG ungate state. Same logics
> applies to JPEG.
> 
> Change-Id: I94335efc4e0424cfe0991e984c938998fd8f1287
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 38 +++++++++++++++++-----
>  1 file changed, 30 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 85b04c48bd09..1349d05c5f3d 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -134,7 +134,8 @@ int smu_get_dpm_freq_range(struct smu_context *smu,
>  }
>  
>  static int smu_dpm_set_vcn_enable(struct smu_context *smu,
> -				  bool enable)
> +				  bool enable,
> +				  int *previous_pg_state)
>  {
>  	struct smu_power_context *smu_power = &smu->smu_power;
>  	struct smu_power_gate *power_gate = &smu_power->power_gate;
> @@ -148,6 +149,9 @@ static int smu_dpm_set_vcn_enable(struct smu_context *smu,
>  	if (atomic_read(&power_gate->vcn_gated) ^ enable)
>  		goto out;
>  
> +	if (previous_pg_state)
> +		*previous_pg_state = atomic_read(&power_gate->vcn_gated);
> +
>  	ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
>  	if (!ret)
>  		atomic_set(&power_gate->vcn_gated, !enable);
> @@ -159,7 +163,8 @@ static int smu_dpm_set_vcn_enable(struct smu_context *smu,
>  }
>  
>  static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
> -				   bool enable)
> +				   bool enable,
> +				   int *previous_pg_state)
>  {
>  	struct smu_power_context *smu_power = &smu->smu_power;
>  	struct smu_power_gate *power_gate = &smu_power->power_gate;
> @@ -173,6 +178,9 @@ static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
>  	if (atomic_read(&power_gate->jpeg_gated) ^ enable)
>  		goto out;
>  
> +	if (previous_pg_state)
> +		*previous_pg_state = atomic_read(&power_gate->jpeg_gated);
> +
>  	ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
>  	if (!ret)
>  		atomic_set(&power_gate->jpeg_gated, !enable);
> @@ -212,7 +220,7 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
>  	 */
>  	case AMD_IP_BLOCK_TYPE_UVD:
>  	case AMD_IP_BLOCK_TYPE_VCN:
> -		ret = smu_dpm_set_vcn_enable(smu, !gate);
> +		ret = smu_dpm_set_vcn_enable(smu, !gate, NULL);
>  		if (ret)
>  			dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
>  				gate ? "gate" : "ungate");
> @@ -230,7 +238,7 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
>  				gate ? "gate" : "ungate");
>  		break;
>  	case AMD_IP_BLOCK_TYPE_JPEG:
> -		ret = smu_dpm_set_jpeg_enable(smu, !gate);
> +		ret = smu_dpm_set_jpeg_enable(smu, !gate, NULL);
>  		if (ret)
>  			dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
>  				gate ? "gate" : "ungate");
> @@ -407,6 +415,7 @@ static int smu_late_init(void *handle)
>  {
>  	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>  	struct smu_context *smu = &adev->smu;
> +	int vcn_gate, jpeg_gate;
>  	int ret = 0;
>  
>  	if (!smu->pm_enabled)
> @@ -418,6 +427,14 @@ static int smu_late_init(void *handle)
>  		return ret;
>  	}
>  
> +	/*
> +	 * 1. Power up VCN/JPEG as the succeeding smu_set_default_dpm_table()
> +	 *    needs VCN/JPEG up.
> +	 * 2. Save original gate states and then we can restore back afterwards.
> +	 */
> +	smu_dpm_set_vcn_enable(smu, true, &vcn_gate);
> +	smu_dpm_set_jpeg_enable(smu, true, &jpeg_gate);
> +
>  	/*
>  	 * Set initialized values (get from vbios) to dpm tables context such as
>  	 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
> @@ -429,6 +446,11 @@ static int smu_late_init(void *handle)
>  		return ret;
>  	}
>  
> +	/* Restore back to original VCN/JPEG power gate states */
> +	smu_dpm_set_vcn_enable(smu, !vcn_gate, NULL);
> +	smu_dpm_set_jpeg_enable(smu, !vcn_gate, NULL);
> +
> +
>  	ret = smu_populate_umd_state_clk(smu);
>  	if (ret) {
>  		dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
> @@ -991,8 +1013,8 @@ static int smu_hw_init(void *handle)
>  
>  	if (smu->is_apu) {
>  		smu_powergate_sdma(&adev->smu, false);
> -		smu_dpm_set_vcn_enable(smu, true);
> -		smu_dpm_set_jpeg_enable(smu, true);
> +		smu_dpm_set_vcn_enable(smu, true, NULL);
> +		smu_dpm_set_jpeg_enable(smu, true, NULL);
>  		smu_set_gfx_cgpg(&adev->smu, true);
>  	}
>  
> @@ -1132,8 +1154,8 @@ static int smu_hw_fini(void *handle)
>  
>  	if (smu->is_apu) {
>  		smu_powergate_sdma(&adev->smu, true);
> -		smu_dpm_set_vcn_enable(smu, false);
> -		smu_dpm_set_jpeg_enable(smu, false);
> +		smu_dpm_set_vcn_enable(smu, false, NULL);
> +		smu_dpm_set_jpeg_enable(smu, false, NULL);
>  	}
>  
>  	if (!smu->pm_enabled)
> 
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] drm/amd/powerplay: put VCN/JPEG into PG ungate state before dpm table setup
  2020-08-03  4:46 ` [PATCH 2/2] drm/amd/powerplay: put VCN/JPEG into PG ungate state before dpm table setup Evan Quan
  2020-08-03 16:29   ` Matt Coffin
@ 2020-08-04 19:55   ` Alex Deucher
  1 sibling, 0 replies; 5+ messages in thread
From: Alex Deucher @ 2020-08-04 19:55 UTC (permalink / raw)
  To: Evan Quan; +Cc: Deucher, Alexander, Matt Coffin, amd-gfx list

On Mon, Aug 3, 2020 at 12:47 AM Evan Quan <evan.quan@amd.com> wrote:
>
> As VCN related dpm table setup needs VCN be in PG ungate state. Same logics
> applies to JPEG.
>
> Change-Id: I94335efc4e0424cfe0991e984c938998fd8f1287
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 38 +++++++++++++++++-----
>  1 file changed, 30 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 85b04c48bd09..1349d05c5f3d 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -134,7 +134,8 @@ int smu_get_dpm_freq_range(struct smu_context *smu,
>  }
>
>  static int smu_dpm_set_vcn_enable(struct smu_context *smu,
> -                                 bool enable)
> +                                 bool enable,
> +                                 int *previous_pg_state)
>  {
>         struct smu_power_context *smu_power = &smu->smu_power;
>         struct smu_power_gate *power_gate = &smu_power->power_gate;
> @@ -148,6 +149,9 @@ static int smu_dpm_set_vcn_enable(struct smu_context *smu,
>         if (atomic_read(&power_gate->vcn_gated) ^ enable)
>                 goto out;
>
> +       if (previous_pg_state)
> +               *previous_pg_state = atomic_read(&power_gate->vcn_gated);
> +
>         ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
>         if (!ret)
>                 atomic_set(&power_gate->vcn_gated, !enable);
> @@ -159,7 +163,8 @@ static int smu_dpm_set_vcn_enable(struct smu_context *smu,
>  }
>
>  static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
> -                                  bool enable)
> +                                  bool enable,
> +                                  int *previous_pg_state)
>  {
>         struct smu_power_context *smu_power = &smu->smu_power;
>         struct smu_power_gate *power_gate = &smu_power->power_gate;
> @@ -173,6 +178,9 @@ static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
>         if (atomic_read(&power_gate->jpeg_gated) ^ enable)
>                 goto out;
>
> +       if (previous_pg_state)
> +               *previous_pg_state = atomic_read(&power_gate->jpeg_gated);
> +
>         ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
>         if (!ret)
>                 atomic_set(&power_gate->jpeg_gated, !enable);
> @@ -212,7 +220,7 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
>          */
>         case AMD_IP_BLOCK_TYPE_UVD:
>         case AMD_IP_BLOCK_TYPE_VCN:
> -               ret = smu_dpm_set_vcn_enable(smu, !gate);
> +               ret = smu_dpm_set_vcn_enable(smu, !gate, NULL);
>                 if (ret)
>                         dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
>                                 gate ? "gate" : "ungate");
> @@ -230,7 +238,7 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
>                                 gate ? "gate" : "ungate");
>                 break;
>         case AMD_IP_BLOCK_TYPE_JPEG:
> -               ret = smu_dpm_set_jpeg_enable(smu, !gate);
> +               ret = smu_dpm_set_jpeg_enable(smu, !gate, NULL);
>                 if (ret)
>                         dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
>                                 gate ? "gate" : "ungate");
> @@ -407,6 +415,7 @@ static int smu_late_init(void *handle)
>  {
>         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>         struct smu_context *smu = &adev->smu;
> +       int vcn_gate, jpeg_gate;
>         int ret = 0;
>
>         if (!smu->pm_enabled)
> @@ -418,6 +427,14 @@ static int smu_late_init(void *handle)
>                 return ret;
>         }
>
> +       /*
> +        * 1. Power up VCN/JPEG as the succeeding smu_set_default_dpm_table()
> +        *    needs VCN/JPEG up.
> +        * 2. Save original gate states and then we can restore back afterwards.
> +        */
> +       smu_dpm_set_vcn_enable(smu, true, &vcn_gate);
> +       smu_dpm_set_jpeg_enable(smu, true, &jpeg_gate);
> +
>         /*
>          * Set initialized values (get from vbios) to dpm tables context such as
>          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
> @@ -429,6 +446,11 @@ static int smu_late_init(void *handle)
>                 return ret;
>         }
>
> +       /* Restore back to original VCN/JPEG power gate states */
> +       smu_dpm_set_vcn_enable(smu, !vcn_gate, NULL);
> +       smu_dpm_set_jpeg_enable(smu, !vcn_gate, NULL);

Copy paste typo.  This should be !jpeg_gate.  With that fixed, the series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

Alex

> +
> +
>         ret = smu_populate_umd_state_clk(smu);
>         if (ret) {
>                 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
> @@ -991,8 +1013,8 @@ static int smu_hw_init(void *handle)
>
>         if (smu->is_apu) {
>                 smu_powergate_sdma(&adev->smu, false);
> -               smu_dpm_set_vcn_enable(smu, true);
> -               smu_dpm_set_jpeg_enable(smu, true);
> +               smu_dpm_set_vcn_enable(smu, true, NULL);
> +               smu_dpm_set_jpeg_enable(smu, true, NULL);
>                 smu_set_gfx_cgpg(&adev->smu, true);
>         }
>
> @@ -1132,8 +1154,8 @@ static int smu_hw_fini(void *handle)
>
>         if (smu->is_apu) {
>                 smu_powergate_sdma(&adev->smu, true);
> -               smu_dpm_set_vcn_enable(smu, false);
> -               smu_dpm_set_jpeg_enable(smu, false);
> +               smu_dpm_set_vcn_enable(smu, false, NULL);
> +               smu_dpm_set_jpeg_enable(smu, false, NULL);
>         }
>
>         if (!smu->pm_enabled)
> --
> 2.28.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* [PATCH 1/2] drm/amd/powerplay: update swSMU VCN/JPEG PG logics
@ 2020-08-05  9:37 Evan Quan
  0 siblings, 0 replies; 5+ messages in thread
From: Evan Quan @ 2020-08-05  9:37 UTC (permalink / raw)
  To: amd-gfx; +Cc: alexander.deucher, Matt Coffin, Evan Quan

Add lock protections and avoid unnecessary actions
if the PG state is already the same as required.

Change-Id: I01400b84151d3ac6e3c8b0d7e264f9a68a9c2092
Signed-off-by: Evan Quan <evan.quan@amd.com>
Tested-by: Matt Coffin <mcoffin13@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 57 ++++++++++++++++++-
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c  |  4 --
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  6 +-
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c    |  8 ---
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c    |  8 ---
 .../drm/amd/powerplay/sienna_cichlid_ppt.c    |  9 ---
 drivers/gpu/drm/amd/powerplay/smu_internal.h  |  2 -
 7 files changed, 60 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index f3f50b5add99..1b64ca9ecccb 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -133,6 +133,56 @@ int smu_get_dpm_freq_range(struct smu_context *smu,
 	return ret;
 }
 
+static int smu_dpm_set_vcn_enable(struct smu_context *smu,
+				  bool enable)
+{
+	struct smu_power_context *smu_power = &smu->smu_power;
+	struct smu_power_gate *power_gate = &smu_power->power_gate;
+	int ret = 0;
+
+	if (!smu->ppt_funcs->dpm_set_vcn_enable)
+		return 0;
+
+	mutex_lock(&power_gate->vcn_gate_lock);
+
+	if (atomic_read(&power_gate->vcn_gated) ^ enable)
+		goto out;
+
+	ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
+	if (!ret)
+		atomic_set(&power_gate->vcn_gated, !enable);
+
+out:
+	mutex_unlock(&power_gate->vcn_gate_lock);
+
+	return ret;
+}
+
+static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
+				   bool enable)
+{
+	struct smu_power_context *smu_power = &smu->smu_power;
+	struct smu_power_gate *power_gate = &smu_power->power_gate;
+	int ret = 0;
+
+	if (!smu->ppt_funcs->dpm_set_jpeg_enable)
+		return 0;
+
+	mutex_lock(&power_gate->jpeg_gate_lock);
+
+	if (atomic_read(&power_gate->jpeg_gated) ^ enable)
+		goto out;
+
+	ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
+	if (!ret)
+		atomic_set(&power_gate->jpeg_gated, !enable);
+
+out:
+	mutex_unlock(&power_gate->jpeg_gate_lock);
+
+	return ret;
+}
+
 /**
  * smu_dpm_set_power_gate - power gate/ungate the specific IP block
  *
@@ -650,6 +700,11 @@ static int smu_sw_init(void *handle)
 	smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 	smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 
+	atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
+	atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
+	mutex_init(&smu->smu_power.power_gate.vcn_gate_lock);
+	mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock);
+
 	smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 	smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
 	smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
@@ -1974,7 +2029,7 @@ int smu_read_sensor(struct smu_context *smu,
 		*size = 4;
 		break;
 	case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
-		*(uint32_t *)data = smu->smu_power.power_gate.vcn_gated ? 0 : 1;
+		*(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1;
 		*size = 4;
 		break;
 	case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index e3a2d7f0aba1..e59e6fb6f0a8 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -1896,8 +1896,6 @@ static bool arcturus_is_dpm_running(struct smu_context *smu)
 
 static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 {
-	struct smu_power_context *smu_power = &smu->smu_power;
-	struct smu_power_gate *power_gate = &smu_power->power_gate;
 	int ret = 0;
 
 	if (enable) {
@@ -1908,7 +1906,6 @@ static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 				return ret;
 			}
 		}
-		power_gate->vcn_gated = false;
 	} else {
 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 			ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
@@ -1917,7 +1914,6 @@ static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 				return ret;
 			}
 		}
-		power_gate->vcn_gated = true;
 	}
 
 	return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ec2d2aa7f4ec..23c2279bd500 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -295,8 +295,10 @@ struct smu_dpm_context {
 struct smu_power_gate {
 	bool uvd_gated;
 	bool vce_gated;
-	bool vcn_gated;
-	bool jpeg_gated;
+	atomic_t vcn_gated;
+	atomic_t jpeg_gated;
+	struct mutex vcn_gate_lock;
+	struct mutex jpeg_gate_lock;
 };
 
 struct smu_power_context {
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 8c45c472f7f2..82659b781f05 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -831,8 +831,6 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
 
 static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 {
-	struct smu_power_context *smu_power = &smu->smu_power;
-	struct smu_power_gate *power_gate = &smu_power->power_gate;
 	int ret = 0;
 
 	if (enable) {
@@ -842,14 +840,12 @@ static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 			if (ret)
 				return ret;
 		}
-		power_gate->vcn_gated = false;
 	} else {
 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
 			if (ret)
 				return ret;
 		}
-		power_gate->vcn_gated = true;
 	}
 
 	return ret;
@@ -857,8 +853,6 @@ static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 
 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 {
-	struct smu_power_context *smu_power = &smu->smu_power;
-	struct smu_power_gate *power_gate = &smu_power->power_gate;
 	int ret = 0;
 
 	if (enable) {
@@ -867,14 +861,12 @@ static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 			if (ret)
 				return ret;
 		}
-		power_gate->jpeg_gated = false;
 	} else {
 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL);
 			if (ret)
 				return ret;
 		}
-		power_gate->jpeg_gated = true;
 	}
 
 	return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 4c1a506c3c17..8a8e6033f71f 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -479,8 +479,6 @@ static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context
 
 static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 {
-	struct smu_power_context *smu_power = &smu->smu_power;
-	struct smu_power_gate *power_gate = &smu_power->power_gate;
 	int ret = 0;
 
 	if (enable) {
@@ -490,14 +488,12 @@ static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 			if (ret)
 				return ret;
 		}
-		power_gate->vcn_gated = false;
 	} else {
 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
 			if (ret)
 				return ret;
 		}
-		power_gate->vcn_gated = true;
 	}
 
 	return ret;
@@ -505,8 +501,6 @@ static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 
 static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 {
-	struct smu_power_context *smu_power = &smu->smu_power;
-	struct smu_power_gate *power_gate = &smu_power->power_gate;
 	int ret = 0;
 
 	if (enable) {
@@ -515,14 +509,12 @@ static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 			if (ret)
 				return ret;
 		}
-		power_gate->jpeg_gated = false;
 	} else {
 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
 			if (ret)
 				return ret;
 		}
-		power_gate->jpeg_gated = true;
 	}
 
 	return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 2566ae5df64b..bb756b4c284e 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -815,10 +815,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 
 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 {
-	struct smu_power_context *smu_power = &smu->smu_power;
-	struct smu_power_gate *power_gate = &smu_power->power_gate;
 	struct amdgpu_device *adev = smu->adev;
-
 	int ret = 0;
 
 	if (enable) {
@@ -834,7 +831,6 @@ static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enabl
 					return ret;
 			}
 		}
-		power_gate->vcn_gated = false;
 	} else {
 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
@@ -847,7 +843,6 @@ static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enabl
 					return ret;
 			}
 		}
-		power_gate->vcn_gated = true;
 	}
 
 	return ret;
@@ -855,8 +850,6 @@ static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enabl
 
 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 {
-	struct smu_power_context *smu_power = &smu->smu_power;
-	struct smu_power_gate *power_gate = &smu_power->power_gate;
 	int ret = 0;
 
 	if (enable) {
@@ -865,14 +858,12 @@ static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enab
 			if (ret)
 				return ret;
 		}
-		power_gate->jpeg_gated = false;
 	} else {
 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
 			if (ret)
 				return ret;
 		}
-		power_gate->jpeg_gated = true;
 	}
 
 	return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
index d0deaefd3feb..f1d8f247e589 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
@@ -77,8 +77,6 @@
 #define smu_get_dal_power_level(smu, clocks)				smu_ppt_funcs(get_dal_power_level, 0, smu, clocks)
 #define smu_get_perf_level(smu, designation, level)			smu_ppt_funcs(get_perf_level, 0, smu, designation, level)
 #define smu_get_current_shallow_sleep_clocks(smu, clocks)		smu_ppt_funcs(get_current_shallow_sleep_clocks, 0, smu, clocks)
-#define smu_dpm_set_vcn_enable(smu, enable)				smu_ppt_funcs(dpm_set_vcn_enable, 0, smu, enable)
-#define smu_dpm_set_jpeg_enable(smu, enable)				smu_ppt_funcs(dpm_set_jpeg_enable, 0, smu, enable)
 #define smu_set_watermarks_table(smu, clock_ranges)			smu_ppt_funcs(set_watermarks_table, 0, smu, clock_ranges)
 #define smu_thermal_temperature_range_update(smu, range, rw)		smu_ppt_funcs(thermal_temperature_range_update, 0, smu, range, rw)
 #define smu_register_irq_handler(smu)					smu_ppt_funcs(register_irq_handler, 0, smu)
-- 
2.28.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-08-05  9:38 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-03  4:46 [PATCH 1/2] drm/amd/powerplay: update swSMU VCN/JPEG PG logics Evan Quan
2020-08-03  4:46 ` [PATCH 2/2] drm/amd/powerplay: put VCN/JPEG into PG ungate state before dpm table setup Evan Quan
2020-08-03 16:29   ` Matt Coffin
2020-08-04 19:55   ` Alex Deucher
2020-08-05  9:37 [PATCH 1/2] drm/amd/powerplay: update swSMU VCN/JPEG PG logics Evan Quan

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.