* [igt-dev] [PATCH 1/2] HAX i915/perf: add tests for triggered OA reports
@ 2020-08-04 18:00 Umesh Nerlige Ramappa
2020-08-04 18:00 ` [igt-dev] [PATCH 2/2] HAX i915/perf: Add tests for mapped OA buffer Umesh Nerlige Ramappa
2020-08-04 18:27 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [1/2] HAX i915/perf: add tests for triggered OA reports Patchwork
0 siblings, 2 replies; 3+ messages in thread
From: Umesh Nerlige Ramappa @ 2020-08-04 18:00 UTC (permalink / raw)
To: igt-dev
From: Lionel G Landwerlin <lionel.g.landwerlin@intel.com>
By whitelisting a couple of registers we can allow an application
batch to trigger OA reports in the OA buffer by switching back & forth
an inverter on the condition logic.
v2: Wait before sampling the timestamp used to end the OA buffer search
v3:
- Ensure OA regs are whitelisted and reports are triggered only when
perf_stream_paranoid is set to 0.
- Drop root to trigger reports.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
tests/i915/perf.c | 449 ++++++++++++++++++++++++--
tests/intel-ci/fast-feedback.testlist | 165 +---------
2 files changed, 434 insertions(+), 180 deletions(-)
diff --git a/tests/i915/perf.c b/tests/i915/perf.c
index 92edc9f1..b030cfad 100644
--- a/tests/i915/perf.c
+++ b/tests/i915/perf.c
@@ -53,6 +53,8 @@ IGT_TEST_DESCRIPTION("Test the i915 perf metrics streaming interface");
#define OAREPORT_REASON_SHIFT 19
#define OAREPORT_REASON_TIMER (1<<0)
#define OAREPORT_REASON_INTERNAL (3<<1)
+#define OAREPORT_REASON_TRIGGER1 (1<<1)
+#define OAREPORT_REASON_TRIGGER2 (1<<2)
#define OAREPORT_REASON_CTX_SWITCH (1<<3)
#define OAREPORT_REASON_GO (1<<4)
#define OAREPORT_REASON_CLK_RATIO (1<<5)
@@ -204,6 +206,7 @@ static struct intel_perf *intel_perf = NULL;
static struct intel_perf_metric_set *test_set = NULL;
static bool *undefined_a_counters;
static uint64_t oa_exp_1_millisec;
+struct intel_mmio_data mmio_data;
static igt_render_copyfunc_t render_copy = NULL;
static uint32_t (*read_report_ticks)(uint32_t *report,
@@ -293,6 +296,23 @@ __perf_open(int fd, struct drm_i915_perf_open_param *param, bool prevent_pm)
return ret;
}
+static int i915_perf_revision(int fd)
+{
+ drm_i915_getparam_t gp;
+ int value = 1, ret;
+
+ gp.param = I915_PARAM_PERF_REVISION;
+ gp.value = &value;
+ ret = igt_ioctl(drm_fd, DRM_IOCTL_I915_GETPARAM, &gp);
+ if (ret == -1) {
+ /* If the param is missing, consider version 1. */
+ igt_assert_eq(errno, EINVAL);
+ return 1;
+ }
+
+ return value;
+}
+
static int
lookup_format(int i915_perf_fmt_id)
{
@@ -383,11 +403,17 @@ gen8_read_report_clock_ratios(uint32_t *report,
*unslice_freq_mhz = (unslice_freq * 16666) / 1000;
}
+static uint32_t
+gen8_report_reason(const uint32_t *report)
+{
+ return ((report[0] >> OAREPORT_REASON_SHIFT) &
+ OAREPORT_REASON_MASK);
+}
+
static const char *
gen8_read_report_reason(const uint32_t *report)
{
- uint32_t reason = ((report[0] >> OAREPORT_REASON_SHIFT) &
- OAREPORT_REASON_MASK);
+ uint32_t reason = gen8_report_reason(report);
if (reason & (1<<0))
return "timer";
@@ -3118,6 +3144,268 @@ emit_stall_timestamp_and_rpc(struct intel_batchbuffer *batch,
emit_report_perf_count(batch, dst, report_dst_offset, report_id);
}
+/* The following register all have the same layout. */
+#define OAREPORTTRIG2 (0x2744)
+#define OAREPORTTRIG2_INVERT_A_0 (1 << 0)
+#define OAREPORTTRIG2_INVERT_A_1 (1 << 1)
+#define OAREPORTTRIG2_INVERT_A_2 (1 << 2)
+#define OAREPORTTRIG2_INVERT_A_3 (1 << 3)
+#define OAREPORTTRIG2_INVERT_A_4 (1 << 4)
+#define OAREPORTTRIG2_INVERT_A_5 (1 << 5)
+#define OAREPORTTRIG2_INVERT_A_6 (1 << 6)
+#define OAREPORTTRIG2_INVERT_A_7 (1 << 7)
+#define OAREPORTTRIG2_INVERT_A_8 (1 << 8)
+#define OAREPORTTRIG2_INVERT_A_9 (1 << 9)
+#define OAREPORTTRIG2_INVERT_A_10 (1 << 10)
+#define OAREPORTTRIG2_INVERT_A_11 (1 << 11)
+#define OAREPORTTRIG2_INVERT_A_12 (1 << 12)
+#define OAREPORTTRIG2_INVERT_A_13 (1 << 13)
+#define OAREPORTTRIG2_INVERT_A_14 (1 << 14)
+#define OAREPORTTRIG2_INVERT_A_15 (1 << 15)
+#define OAREPORTTRIG2_INVERT_B_0 (1 << 16)
+#define OAREPORTTRIG2_INVERT_B_1 (1 << 17)
+#define OAREPORTTRIG2_INVERT_B_2 (1 << 18)
+#define OAREPORTTRIG2_INVERT_B_3 (1 << 19)
+#define OAREPORTTRIG2_INVERT_C_0 (1 << 20)
+#define OAREPORTTRIG2_INVERT_C_1 (1 << 21)
+#define OAREPORTTRIG2_INVERT_D_0 (1 << 22)
+#define OAREPORTTRIG2_THRESHOLD_ENABLE (1 << 23)
+#define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31)
+#define OAREPORTTRIG6 (0x2754)
+#define OA_PERF_COUNTER_A(idx) (0x2800 + 8 * (idx))
+#define GEN8_OASTATUS (0x2b08)
+
+#define GEN12_OAREPORTTRIG2 (0xd924)
+#define GEN12_OAREPORTTRIG6 (0xd934)
+#define GEN12_OAG_PERF_COUNTER_A(idx) (0xD980 + 8 * (idx))
+#define GEN12_OAG_OASTATUS (0xdafc)
+
+/*
+ * We have 2 trigger registers that each generate a different
+ * report reason.
+ */
+static const uint32_t gen8_oa_wl[] = {
+ OAREPORTTRIG2,
+ OAREPORTTRIG6,
+ OA_PERF_COUNTER_A(18),
+ GEN8_OASTATUS,
+};
+static const uint32_t gen12_oa_wl[] = {
+ GEN12_OAREPORTTRIG2,
+ GEN12_OAREPORTTRIG6,
+ GEN12_OAG_PERF_COUNTER_A(18),
+ GEN12_OAG_OASTATUS,
+};
+
+static void
+emit_triggered_oa_report(struct intel_batchbuffer *batch,
+ uint32_t trigger)
+{
+ const uint32_t *triggers = intel_gen(devid) >= 12 ? gen12_oa_wl: gen8_oa_wl;
+
+ assert(trigger <= 1);
+
+ BEGIN_BATCH(6, 0);
+ OUT_BATCH(MI_LOAD_REGISTER_IMM);
+ OUT_BATCH(triggers[trigger]);
+ OUT_BATCH(OAREPORTTRIG2_INVERT_C_1 |
+ OAREPORTTRIG2_REPORT_TRIGGER_ENABLE);
+ OUT_BATCH(MI_LOAD_REGISTER_IMM);
+ OUT_BATCH(triggers[trigger]);
+ OUT_BATCH(OAREPORTTRIG2_INVERT_C_1 |
+ OAREPORTTRIG2_INVERT_D_0 |
+ OAREPORTTRIG2_REPORT_TRIGGER_ENABLE);
+ ADVANCE_BATCH();
+}
+
+static uint64_t
+rcs_timestmap_reg_read(int fd)
+{
+ struct drm_i915_reg_read rr = {
+ .offset = 0x2358 | I915_REG_READ_8B_WA, /* render ring timestamp */
+ };
+
+ do_ioctl(fd, DRM_IOCTL_I915_REG_READ, &rr);
+
+ return rr.val;
+}
+
+/*
+ * Verify that we can trigger OA reports into the OA buffer using
+ * MI_LRI.
+ */
+static void
+test_triggered_oa_reports(int paranoid)
+{
+ int oa_exponent = max_oa_exponent_for_period_lte(1000000);
+ uint64_t properties[] = {
+ DRM_I915_PERF_PROP_CTX_HANDLE, UINT64_MAX, /* updated below */
+
+ /* Note: we have to specify at least one sample property even
+ * though we aren't interested in samples in this case
+ */
+ DRM_I915_PERF_PROP_SAMPLE_OA, true,
+
+ /* OA unit configuration */
+ DRM_I915_PERF_PROP_OA_METRICS_SET, test_set->perf_oa_metrics_set,
+ DRM_I915_PERF_PROP_OA_FORMAT, test_set->perf_oa_format,
+ DRM_I915_PERF_PROP_OA_EXPONENT, oa_exponent,
+
+ /* Note: no OA exponent specified in this case */
+ };
+ struct drm_i915_perf_open_param param = {
+ .flags = I915_PERF_FLAG_FD_CLOEXEC,
+ .num_properties = ARRAY_SIZE(properties) / 2,
+ .properties_ptr = to_user_pointer(properties),
+ };
+ struct drm_i915_perf_record_header *header;
+ drm_intel_bufmgr *bufmgr;
+ drm_intel_context *context;
+ struct igt_helper_process child = {};
+ struct intel_batchbuffer *batch;
+ struct igt_buf src[2], dst[2];
+ uint64_t timestamp32_mask = (1ull << 32) - 1;
+ uint64_t timestamps[2];
+ uint32_t buf_size = 16 * 1024 * 1024;
+ uint8_t *buf = malloc(buf_size);
+ uint32_t ctx_id;
+ int width = 800;
+ int height = 600;
+ uint32_t trigger_counts[2] = { 0, };
+ int ret;
+
+ write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", paranoid);
+
+ do {
+ igt_fork_helper(&child) {
+ if (!paranoid)
+ igt_drop_root();
+
+ bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
+ drm_intel_bufmgr_gem_enable_reuse(bufmgr);
+
+ scratch_buf_init(bufmgr, &src[0], width, height, 0xff0000ff);
+ scratch_buf_init(bufmgr, &dst[0], width, height, 0x00ff00ff);
+ scratch_buf_init(bufmgr, &src[1], 2 * width, height, 0xff0000ff);
+ scratch_buf_init(bufmgr, &dst[1], 2 * width, height, 0x00ff00ff);
+
+ batch = intel_batchbuffer_alloc(bufmgr, devid);
+
+ context = drm_intel_gem_context_create(bufmgr);
+ igt_assert(context);
+
+ ret = drm_intel_gem_context_get_id(context, &ctx_id);
+ properties[1] = ctx_id;
+
+
+ timestamps[0] = rcs_timestmap_reg_read(drm_fd);
+
+ stream_fd = __perf_open(drm_fd, ¶m, false);
+
+ emit_triggered_oa_report(batch, 0);
+
+ render_copy(batch,
+ context,
+ &src[0], 0, 0, width, height,
+ &dst[0], 0, 0);
+
+ emit_triggered_oa_report(batch, 0);
+
+ emit_triggered_oa_report(batch, 1);
+
+ render_copy(batch,
+ context,
+ &src[1], 0, 0, 2 * width, height,
+ &dst[1], 0, 0);
+
+ emit_triggered_oa_report(batch, 1);
+
+ intel_batchbuffer_flush_with_context(batch, context);
+
+ /* On some failures, this timestamp is too early as in
+ * we bail out before seeing the triggered report. Wait
+ * a little more and then check.
+ */
+ usleep(50000);
+
+ timestamps[1] = rcs_timestmap_reg_read(drm_fd);
+
+ if (timestamps[1] < timestamps[0] ||
+ (timestamps[1] & timestamp32_mask) < (timestamps[1] & timestamp32_mask)) {
+ igt_debug("Timestamp rollover, trying again\n");
+ exit(EAGAIN);
+ }
+
+ ret = i915_read_reports_until_timestamp(test_set->perf_oa_format,
+ buf, buf_size,
+ timestamps[0] & timestamp32_mask,
+ timestamps[1] & timestamp32_mask);
+
+ for (size_t offset = 0; offset < ret; offset += header->size) {
+ uint32_t *report;
+
+ header = (void *)(buf + offset);
+
+ igt_assert_eq(header->pad, 0); /* Reserved */
+
+ igt_assert_neq(header->type, DRM_I915_PERF_RECORD_OA_BUFFER_LOST);
+
+ if (header->type == DRM_I915_PERF_RECORD_OA_REPORT_LOST)
+ continue;
+
+ /* Currently the only other record type expected is a
+ * _SAMPLE. Notably this test will need updating if
+ * i915-perf is extended in the future with additional
+ * record types.
+ */
+ igt_assert_eq(header->type, DRM_I915_PERF_RECORD_SAMPLE);
+
+ report = (void *)(header + 1);
+
+ igt_debug("report ts=0x%08x hw_id=0x%08x reason=%s\n",
+ report[1], report[2],
+ gen8_read_report_reason(report));
+
+ if (gen8_report_reason(report) & OAREPORT_REASON_TRIGGER1) {
+ igt_assert_eq(trigger_counts[1], 0);
+ trigger_counts[0]++;
+ }
+ if (gen8_report_reason(report) & OAREPORT_REASON_TRIGGER2) {
+ igt_assert_eq(trigger_counts[0], 2);
+ trigger_counts[1]++;
+ }
+ }
+
+ if (paranoid) {
+ igt_assert_eq(trigger_counts[0], 0);
+ igt_assert_eq(trigger_counts[1], 0);
+ } else {
+ igt_assert_eq(trigger_counts[0], 2);
+ igt_assert_eq(trigger_counts[1], 2);
+ }
+
+ for (int i = 0; i < ARRAY_SIZE(src); i++) {
+ drm_intel_bo_unreference(src[i].bo);
+ drm_intel_bo_unreference(dst[i].bo);
+ }
+
+ intel_batchbuffer_free(batch);
+ drm_intel_gem_context_destroy(context);
+ drm_intel_bufmgr_destroy(bufmgr);
+ __perf_close(stream_fd);
+ }
+
+
+ ret = igt_wait_helper(&child);
+
+ igt_assert(WEXITSTATUS(ret) == EAGAIN ||
+ WEXITSTATUS(ret) == 0);
+
+ } while (WEXITSTATUS(ret) == EAGAIN);
+
+ free(buf);
+}
+
/* Tests the INTEL_performance_query use case where an unprivileged process
* should be able to configure the OA unit for per-context metrics (for a
* context associated with that process' drm file descriptor) and the counters
@@ -4768,6 +5056,122 @@ test_whitelisted_registers_userspace_config(void)
i915_perf_remove_config(drm_fd, config_id);
}
+#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK 0x03fffffc
+
+static uint32_t gen12_wl_slots[] = {
+ 0x24d0, 0x24d4, 0x24d8, 0x24dc, 0x24e0, 0x24e4, 0x24e8, 0x24ec,
+ 0x24f0, 0x24f4, 0x24f8, 0x24fc, 0x2010, 0x2014, 0x2018, 0x201c,
+ 0x21e0, 0x21e4, 0x21e8, 0x21ec,
+};
+
+static uint32_t gen9_wl_slots[] = {
+ 0x24d0, 0x24d4, 0x24d8, 0x24dc, 0x24e0, 0x24e4, 0x24e8, 0x24ec,
+ 0x24f0, 0x24f4, 0x24f8, 0x24fc,
+};
+
+static void dump_wl(uint32_t *slots, uint32_t count)
+{
+ int i;
+
+ for (i = 0; i < count; i++)
+ igt_debug("LOCAL: FORCE_TO_NON_PRIV_%02d = %08x\n",
+ i, intel_register_read(&mmio_data, slots[i]));
+}
+
+static void dump_whitelist(const char *msg)
+{
+ igt_debug("%s\n", msg);
+
+ if (intel_gen(devid) >= 12)
+ dump_wl(gen12_wl_slots, ARRAY_SIZE(gen12_wl_slots));
+ else if (intel_gen(devid) > 8)
+ dump_wl(gen9_wl_slots, ARRAY_SIZE(gen9_wl_slots));
+ else
+ return;
+}
+
+static bool in_whitelist(uint32_t reg)
+{
+ uint32_t *slots, count;
+ int i;
+
+ if (intel_gen(devid) >= 12) {
+ slots = gen12_wl_slots;
+ count = ARRAY_SIZE(gen12_wl_slots);
+ } else {
+ slots = gen9_wl_slots;
+ count = ARRAY_SIZE(gen9_wl_slots);
+ }
+
+ for (i = 0; i < count; i++) {
+ uint32_t fpriv = intel_register_read(&mmio_data, slots[i]);
+
+ if ((fpriv & RING_FORCE_TO_NONPRIV_ADDRESS_MASK) == reg)
+ return true;
+ }
+
+ return false;
+}
+
+static void oa_regs_in_whitelist(bool are_present)
+{
+ const uint32_t *regs;
+ uint32_t count;
+ int i;
+
+ if (intel_gen(devid) >= 12) {
+ regs = gen12_oa_wl;
+ count = i915_perf_revision(drm_fd) >= 7 ?
+ ARRAY_SIZE(gen12_oa_wl) : 2;
+ } else {
+ regs = gen8_oa_wl;
+ count = i915_perf_revision(drm_fd) >= 7 ?
+ ARRAY_SIZE(gen8_oa_wl) : 2;
+ }
+
+ for (i = 0; i < count; i++)
+ if (are_present)
+ igt_assert(in_whitelist(regs[i]));
+ else
+ igt_assert(!in_whitelist(regs[i]));
+}
+
+static void test_oa_regs_whitelist(int paranoid)
+{
+ uint64_t properties[] = {
+ DRM_I915_PERF_PROP_SAMPLE_OA, true,
+ DRM_I915_PERF_PROP_OA_METRICS_SET, test_set->perf_oa_metrics_set,
+ DRM_I915_PERF_PROP_OA_FORMAT, test_set->perf_oa_format,
+ DRM_I915_PERF_PROP_OA_EXPONENT, oa_exp_1_millisec,
+
+ };
+ struct drm_i915_perf_open_param param = {
+ .flags = I915_PERF_FLAG_FD_CLOEXEC,
+ .num_properties = sizeof(properties) / 16,
+ .properties_ptr = to_user_pointer(properties),
+ };
+ write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", paranoid);
+ intel_register_access_init(&mmio_data, intel_get_pci_device(),
+ 0, drm_fd);
+ stream_fd = __perf_open(drm_fd, ¶m, false);
+
+ dump_whitelist("oa whitelisted");
+
+ if (paranoid)
+ oa_regs_in_whitelist(false);
+ else
+ oa_regs_in_whitelist(true);
+
+ __perf_close(stream_fd);
+
+ dump_whitelist("oa remove whitelist");
+
+ /* after perf close, whitelist should be removed */
+ oa_regs_in_whitelist(false);
+
+ intel_register_access_fini(&mmio_data);
+}
+
static unsigned
read_i915_module_ref(void)
{
@@ -4880,23 +5284,6 @@ test_sysctl_defaults(void)
igt_assert_eq(max_freq, 100000);
}
-static int i915_perf_revision(int fd)
-{
- drm_i915_getparam_t gp;
- int value = 1, ret;
-
- gp.param = I915_PARAM_PERF_REVISION;
- gp.value = &value;
- ret = igt_ioctl(drm_fd, DRM_IOCTL_I915_GETPARAM, &gp);
- if (ret == -1) {
- /* If the param is missing, consider version 1. */
- igt_assert_eq(errno, EINVAL);
- return 1;
- }
-
- return value;
-}
-
igt_main
{
igt_fixture {
@@ -5096,6 +5483,30 @@ igt_main
igt_subtest("whitelisted-registers-userspace-config")
test_whitelisted_registers_userspace_config();
+
+ igt_subtest_group {
+ igt_fixture {
+ igt_require(intel_gen(devid) > 8);
+ igt_require(i915_perf_revision(drm_fd) >= 6);
+ }
+
+ igt_describe("Verify that OA registers are whitelisted for paranoid 0");
+ igt_subtest("oa-regs-whitelisted")
+ test_oa_regs_whitelist(0);
+
+ igt_describe("Verify that OA registers are not whitelisted for paranoid 1");
+ igt_subtest("oa-regs-not-whitelisted")
+ test_oa_regs_whitelist(1);
+
+ igt_describe("Verify reports triggered when perf_stream_paranoid is 0");
+ igt_subtest("triggered-oa-reports-paranoid-0")
+ test_triggered_oa_reports(0);
+
+ igt_describe("Verify reports not triggered when perf_stream_paranoid is 1");
+ igt_subtest("triggered-oa-reports-paranoid-1")
+ test_triggered_oa_reports(1);
+ }
+
igt_fixture {
/* leave sysctl options in their default state... */
write_u64_file("/proc/sys/dev/i915/oa_max_sample_rate", 100000);
diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-feedback.testlist
index b796b264..262f8d1c 100644
--- a/tests/intel-ci/fast-feedback.testlist
+++ b/tests/intel-ci/fast-feedback.testlist
@@ -1,163 +1,6 @@
# Keep alphabetically sorted by default
-igt@core_auth@basic-auth
-igt@debugfs_test@read_all_entries
-igt@fbdev@mmap
-igt@gem_basic@bad-close
-igt@gem_basic@create-close
-igt@gem_basic@create-fd-close
-igt@gem_busy@busy@all
-igt@gem_close_race@basic-process
-igt@gem_close_race@basic-threads
-igt@gem_ctx_create@basic
-igt@gem_ctx_create@basic-files
-igt@gem_ctx_exec@basic
-igt@gem_exec_basic@basic
-igt@gem_exec_create@basic
-igt@gem_exec_fence@basic-busy
-igt@gem_exec_fence@basic-wait
-igt@gem_exec_fence@basic-await
-igt@gem_exec_fence@nb-await
-igt@gem_exec_gttfill@basic
-igt@gem_exec_parallel@engines
-igt@gem_exec_store@basic
-igt@gem_exec_suspend@basic-s0
-igt@gem_exec_suspend@basic-s3
-igt@gem_flink_basic@bad-flink
-igt@gem_flink_basic@bad-open
-igt@gem_flink_basic@basic
-igt@gem_flink_basic@double-flink
-igt@gem_flink_basic@flink-lifetime
-igt@gem_huc_copy@huc-copy
-igt@gem_linear_blits@basic
-igt@gem_mmap@basic
-igt@gem_mmap_gtt@basic
-igt@gem_render_linear_blits@basic
-igt@gem_render_tiled_blits@basic
-igt@gem_ringfill@basic-all
-igt@gem_sync@basic-all
-igt@gem_sync@basic-each
-igt@gem_tiled_blits@basic
-igt@gem_tiled_fence_blits@basic
-igt@gem_tiled_pread_basic
-igt@gem_wait@busy@all
-igt@gem_wait@wait@all
-igt@i915_getparams_basic@basic-eu-total
-igt@i915_getparams_basic@basic-subslice-total
-igt@i915_hangman@error-state-basic
-igt@kms_addfb_basic@addfb25-bad-modifier
-igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling
-igt@kms_addfb_basic@addfb25-modifier-no-flag
-igt@kms_addfb_basic@addfb25-x-tiled
-igt@kms_addfb_basic@addfb25-x-tiled-mismatch
-igt@kms_addfb_basic@addfb25-yf-tiled
-igt@kms_addfb_basic@addfb25-y-tiled
-igt@kms_addfb_basic@addfb25-y-tiled-small
-igt@kms_addfb_basic@bad-pitch-0
-igt@kms_addfb_basic@bad-pitch-1024
-igt@kms_addfb_basic@bad-pitch-128
-igt@kms_addfb_basic@bad-pitch-256
-igt@kms_addfb_basic@bad-pitch-32
-igt@kms_addfb_basic@bad-pitch-63
-igt@kms_addfb_basic@bad-pitch-65536
-igt@kms_addfb_basic@bad-pitch-999
-igt@kms_addfb_basic@basic
-igt@kms_addfb_basic@basic-x-tiled
-igt@kms_addfb_basic@basic-y-tiled
-igt@kms_addfb_basic@bo-too-small
-igt@kms_addfb_basic@bo-too-small-due-to-tiling
-igt@kms_addfb_basic@clobberred-modifier
-igt@kms_addfb_basic@framebuffer-vs-set-tiling
-igt@kms_addfb_basic@invalid-get-prop
-igt@kms_addfb_basic@invalid-get-prop-any
-igt@kms_addfb_basic@invalid-set-prop
-igt@kms_addfb_basic@invalid-set-prop-any
-igt@kms_addfb_basic@no-handle
-igt@kms_addfb_basic@size-max
-igt@kms_addfb_basic@small-bo
-igt@kms_addfb_basic@tile-pitch-mismatch
-igt@kms_addfb_basic@too-high
-igt@kms_addfb_basic@too-wide
-igt@kms_addfb_basic@unused-handle
-igt@kms_addfb_basic@unused-modifier
-igt@kms_addfb_basic@unused-offsets
-igt@kms_addfb_basic@unused-pitches
-igt@kms_busy@basic
-igt@kms_chamelium@dp-hpd-fast
-igt@kms_chamelium@dp-edid-read
-igt@kms_chamelium@dp-crc-fast
-igt@kms_chamelium@hdmi-hpd-fast
-igt@kms_chamelium@hdmi-edid-read
-igt@kms_chamelium@hdmi-crc-fast
-igt@kms_chamelium@vga-hpd-fast
-igt@kms_chamelium@vga-edid-read
-igt@kms_chamelium@common-hpd-after-suspend
-igt@kms_prop_blob@basic
-igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic
-igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy
-igt@kms_cursor_legacy@basic-flip-after-cursor-atomic
-igt@kms_cursor_legacy@basic-flip-after-cursor-legacy
-igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size
-igt@kms_cursor_legacy@basic-flip-before-cursor-atomic
-igt@kms_cursor_legacy@basic-flip-before-cursor-legacy
-igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size
-igt@kms_flip@basic-flip-vs-dpms
-igt@kms_flip@basic-flip-vs-modeset
-igt@kms_flip@basic-flip-vs-wf_vblank
-igt@kms_flip@basic-plain-flip
-igt@kms_force_connector_basic@force-connector-state
-igt@kms_force_connector_basic@force-edid
-igt@kms_force_connector_basic@force-load-detect
-igt@kms_force_connector_basic@prune-stale-modes
-igt@kms_frontbuffer_tracking@basic
-igt@kms_pipe_crc_basic@hang-read-crc-pipe-a
-igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a
-igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence
-igt@kms_pipe_crc_basic@read-crc-pipe-a
-igt@kms_pipe_crc_basic@read-crc-pipe-b
-igt@kms_pipe_crc_basic@read-crc-pipe-c
-igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence
-igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a
-igt@kms_psr@primary_page_flip
-igt@kms_psr@cursor_plane_move
-igt@kms_psr@sprite_plane_onoff
-igt@kms_psr@primary_mmap_gtt
-igt@kms_setmode@basic-clone-single-crtc
-igt@i915_pm_backlight@basic-brightness
-igt@i915_pm_rpm@basic-pci-d3-state
-igt@i915_pm_rpm@basic-rte
-igt@i915_pm_rps@basic-api
-igt@prime_self_import@basic-llseek-bad
-igt@prime_self_import@basic-llseek-size
-igt@prime_self_import@basic-with_fd_dup
-igt@prime_self_import@basic-with_one_bo
-igt@prime_self_import@basic-with_one_bo_two_files
-igt@prime_self_import@basic-with_two_bos
-igt@prime_vgem@basic-fence-flip
-igt@prime_vgem@basic-fence-mmap
-igt@prime_vgem@basic-fence-read
-igt@prime_vgem@basic-gtt
-igt@prime_vgem@basic-read
-igt@prime_vgem@basic-write
-igt@vgem_basic@setversion
-igt@vgem_basic@create
-igt@vgem_basic@debugfs
-igt@vgem_basic@dmabuf-export
-igt@vgem_basic@dmabuf-fence
-igt@vgem_basic@dmabuf-fence-before
-igt@vgem_basic@dmabuf-mmap
-igt@vgem_basic@mmap
-igt@vgem_basic@second-client
-igt@vgem_basic@sysfs
-
-# All tests that do module unloading and reloading are executed last.
-# They will sometimes reveal issues of earlier tests leaving the
-# driver in a broken state that is not otherwise noticed in that test.
-
-igt@vgem_basic@unload
-igt@i915_module_load@reload
-igt@i915_pm_rpm@module-reload
-
-# Kernel selftests
-igt@i915_selftest@live
-igt@dmabuf@all
+igt@perf@oa-regs-whitelisted
+igt@perf@oa-regs-not-whitelisted
+igt@perf@triggered-oa-reports-paranoid-0
+igt@perf@triggered-oa-reports-paranoid-1
--
2.20.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [igt-dev] [PATCH 2/2] HAX i915/perf: Add tests for mapped OA buffer
2020-08-04 18:00 [igt-dev] [PATCH 1/2] HAX i915/perf: add tests for triggered OA reports Umesh Nerlige Ramappa
@ 2020-08-04 18:00 ` Umesh Nerlige Ramappa
2020-08-04 18:27 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [1/2] HAX i915/perf: add tests for triggered OA reports Patchwork
1 sibling, 0 replies; 3+ messages in thread
From: Umesh Nerlige Ramappa @ 2020-08-04 18:00 UTC (permalink / raw)
To: igt-dev
For applications that need a faster way to access reports in the OA
buffer, i915 now provides a way to map the OA buffer to privileged user
space. Validate the mapped OA buffer.
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
include/drm-uapi/i915_drm.h | 18 ++
tests/i915/perf.c | 276 ++++++++++++++++++++++++++
tests/intel-ci/fast-feedback.testlist | 6 +
3 files changed, 300 insertions(+)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 2b55af13..e948a81c 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -2048,6 +2048,24 @@ struct drm_i915_perf_open_param {
*/
#define I915_PERF_IOCTL_CONFIG _IO('i', 0x2)
+/**
+ * Returns OA buffer properties to be used with mmap.
+ *
+ * This ioctl is available in perf revision 8.
+ */
+#define I915_PERF_IOCTL_GET_OA_BUFFER_INFO _IOWR('i', 0x3, struct drm_i915_perf_oa_buffer_info)
+
+/**
+ * OA buffer size and offset.
+ */
+struct drm_i915_perf_oa_buffer_info {
+ __u32 type; /* in */
+ __u32 flags; /* in */
+ __u64 size; /* out */
+ __u64 offset; /* out */
+ __u64 rsvd; /* mbz */
+};
+
/**
* Common to all i915 perf records
*/
diff --git a/tests/i915/perf.c b/tests/i915/perf.c
index b030cfad..fe94e163 100644
--- a/tests/i915/perf.c
+++ b/tests/i915/perf.c
@@ -5172,6 +5172,256 @@ static void test_oa_regs_whitelist(int paranoid)
intel_register_access_fini(&mmio_data);
}
+#define OA_BUFFER_DATA(tail, head, oa_buffer_size) \
+ (((tail) - (head)) & ((oa_buffer_size) - 1))
+
+#ifndef MAP_FAILED
+#define MAP_FAILED ((void *)-1)
+#endif
+
+static uint32_t oa_status_reg(void)
+{
+ uint32_t status;
+
+ intel_register_access_init(&mmio_data, intel_get_pci_device(),
+ 0, drm_fd);
+ if (IS_HASWELL(devid))
+ status = intel_register_read(&mmio_data, 0x2346) & 0x7;
+ else if (IS_GEN12(devid))
+ status = intel_register_read(&mmio_data, 0xdafc) & 0x7;
+ else
+ status = intel_register_read(&mmio_data, 0x2b08) & 0xf;
+
+ intel_register_access_fini(&mmio_data);
+
+ return status;
+}
+
+static jmp_buf jmp;
+static void __attribute__((noreturn)) sigtrap(int sig)
+{
+ siglongjmp(jmp, sig);
+}
+
+static void try_invalid_access(void *vaddr)
+{
+ sighandler_t old_sigsegv;
+ uint32_t dummy;
+
+ old_sigsegv = signal(SIGSEGV, sigtrap);
+ switch (sigsetjmp(jmp, SIGSEGV)) {
+ case SIGSEGV:
+ break;
+ case 0:
+ dummy = READ_ONCE(*((uint32_t *)vaddr + 1));
+ (void) dummy;
+ default:
+ igt_assert(!"reached");
+ break;
+ }
+ signal(SIGSEGV, old_sigsegv);
+}
+
+static void invalid_param_map_oa_buffer(void)
+{
+ struct drm_i915_perf_oa_buffer_info oa_buffer = { 0 };
+ void *oa_vaddr = NULL;
+
+ do_ioctl(stream_fd, I915_PERF_IOCTL_GET_OA_BUFFER_INFO, &oa_buffer);
+
+ igt_debug("size = %llu\n", oa_buffer.size);
+ igt_debug("offset = %llx\n", oa_buffer.offset);
+
+ igt_assert_eq(oa_buffer.size & (oa_buffer.size - 1), 0);
+
+ /* try a couple invalid mmaps */
+ /* bad prots */
+ oa_vaddr = mmap(0, oa_buffer.size, PROT_WRITE, MAP_PRIVATE, stream_fd, oa_buffer.offset);
+ igt_assert(oa_vaddr == MAP_FAILED);
+
+ oa_vaddr = mmap(0, oa_buffer.size, PROT_EXEC, MAP_PRIVATE, stream_fd, oa_buffer.offset);
+ igt_assert(oa_vaddr == MAP_FAILED);
+
+ /* bad MAPs */
+ oa_vaddr = mmap(0, oa_buffer.size, PROT_READ, MAP_SHARED, stream_fd, oa_buffer.offset);
+ igt_assert(oa_vaddr == MAP_FAILED);
+
+ /* bad offsets */
+ oa_vaddr = mmap(0, oa_buffer.size, PROT_READ, MAP_PRIVATE, stream_fd, 0);
+ igt_assert(oa_vaddr == MAP_FAILED);
+
+ oa_vaddr = mmap(0, oa_buffer.size, PROT_READ, MAP_PRIVATE, stream_fd, 8192);
+ igt_assert(oa_vaddr == MAP_FAILED);
+
+ oa_vaddr = mmap(0, oa_buffer.size, PROT_READ, MAP_PRIVATE, stream_fd, 11);
+ igt_assert(oa_vaddr == MAP_FAILED);
+
+ /* bad size */
+ oa_vaddr = mmap(0, oa_buffer.size + 1, PROT_READ, MAP_PRIVATE, stream_fd, oa_buffer.offset);
+ igt_assert(oa_vaddr == MAP_FAILED);
+
+ /* do the right thing */
+ oa_vaddr = mmap(0, oa_buffer.size, PROT_READ, MAP_PRIVATE, stream_fd, oa_buffer.offset);
+ igt_assert(oa_vaddr != MAP_FAILED && oa_vaddr != NULL);
+
+ munmap(oa_vaddr, oa_buffer.size);
+}
+
+static void *map_oa_buffer(uint32_t *size)
+{
+ struct drm_i915_perf_oa_buffer_info oa_buffer = { 0 };
+ void *vaddr;
+
+ do_ioctl(stream_fd, I915_PERF_IOCTL_GET_OA_BUFFER_INFO, &oa_buffer);
+
+ igt_debug("size = %llu\n", oa_buffer.size);
+ igt_debug("offset = %llx\n", oa_buffer.offset);
+
+ igt_assert_eq(oa_buffer.size & (oa_buffer.size - 1), 0);
+ igt_assert_eq(oa_status_reg(), 0);
+
+ vaddr = mmap(0, oa_buffer.size, PROT_READ, MAP_PRIVATE, stream_fd, oa_buffer.offset);
+ igt_assert(vaddr != NULL);
+
+ *size = oa_buffer.size;
+
+ return vaddr;
+}
+
+static void unmap_oa_buffer(void *addr, uint32_t size)
+{
+ munmap(addr, size);
+}
+
+static void check_reports(void *oa_vaddr, uint32_t oa_size)
+{
+ struct oa_format format = get_oa_format(test_set->perf_oa_format);
+ size_t report_words = format.size >> 2;
+ uint32_t *reports;
+ uint32_t timer_reports = 0;
+
+ for (reports = (uint32_t *)oa_vaddr;
+ timer_reports < 20 && reports[0] && reports[1];
+ reports += report_words) {
+ if (!oa_report_is_periodic(oa_exp_1_millisec, reports))
+ continue;
+
+ timer_reports++;
+ if (timer_reports >= 3)
+ sanity_check_reports(reports - 2 * report_words,
+ reports - report_words,
+ test_set->perf_oa_format);
+ }
+
+ igt_assert(timer_reports >= 3);
+}
+
+static void check_reports_from_mapped_buffer(void)
+{
+ void *vaddr;
+ uint32_t size;
+ uint32_t period_us = oa_exponent_to_ns(oa_exp_1_millisec) / 1000;
+
+ vaddr = map_oa_buffer(&size);
+
+ /* wait for approx 100 reports */
+ usleep(100 * period_us);
+ check_reports(vaddr, size);
+
+ unmap_oa_buffer(vaddr, size);
+}
+
+static void unprivileged_try_to_map_oa_buffer(void)
+{
+ struct drm_i915_perf_oa_buffer_info oa_buffer = { 0 };
+ void *oa_vaddr;
+
+ do_ioctl_err(stream_fd, I915_PERF_IOCTL_GET_OA_BUFFER_INFO,
+ &oa_buffer, EACCES);
+
+ oa_vaddr = mmap(0, 4096, PROT_READ, MAP_PRIVATE, stream_fd, 4096);
+ igt_assert(oa_vaddr == MAP_FAILED);
+ igt_assert_eq(errno, EACCES);
+}
+
+static void unprivileged_map_oa_buffer(void)
+{
+ igt_fork(child, 1) {
+ igt_drop_root();
+ unprivileged_try_to_map_oa_buffer();
+ }
+ igt_waitchildren();
+}
+
+static void map_oa_buffer_unprivilege_access(void)
+{
+ void *vaddr;
+ uint32_t size;
+
+ vaddr = map_oa_buffer(&size);
+
+ igt_fork(child, 1) {
+ igt_drop_root();
+ try_invalid_access(vaddr);
+ }
+ igt_waitchildren();
+
+ unmap_oa_buffer(vaddr, size);
+}
+
+static void test_mapped_oa_buffer(void (*test_with_fd_open)(void))
+{
+ uint64_t properties[] = {
+ DRM_I915_PERF_PROP_SAMPLE_OA, true,
+ DRM_I915_PERF_PROP_OA_METRICS_SET, test_set->perf_oa_metrics_set,
+ DRM_I915_PERF_PROP_OA_FORMAT, test_set->perf_oa_format,
+ DRM_I915_PERF_PROP_OA_EXPONENT, oa_exp_1_millisec,
+
+ };
+ struct drm_i915_perf_open_param param = {
+ .flags = I915_PERF_FLAG_FD_CLOEXEC,
+ .num_properties = sizeof(properties) / 16,
+ .properties_ptr = to_user_pointer(properties),
+ };
+
+ stream_fd = __perf_open(drm_fd, ¶m, false);
+
+ igt_assert(test_with_fd_open);
+ test_with_fd_open();
+
+ __perf_close(stream_fd);
+}
+
+static void closed_fd_and_unmapped_access(void)
+{
+ uint64_t properties[] = {
+ DRM_I915_PERF_PROP_SAMPLE_OA, true,
+ DRM_I915_PERF_PROP_OA_METRICS_SET, test_set->perf_oa_metrics_set,
+ DRM_I915_PERF_PROP_OA_FORMAT, test_set->perf_oa_format,
+ DRM_I915_PERF_PROP_OA_EXPONENT, oa_exp_1_millisec,
+
+ };
+ struct drm_i915_perf_open_param param = {
+ .flags = I915_PERF_FLAG_FD_CLOEXEC,
+ .num_properties = sizeof(properties) / 16,
+ .properties_ptr = to_user_pointer(properties),
+ };
+ void *vaddr;
+ uint32_t size;
+ uint32_t period_us = oa_exponent_to_ns(oa_exp_1_millisec) / 1000;
+
+ stream_fd = __perf_open(drm_fd, ¶m, false);
+ vaddr = map_oa_buffer(&size);
+
+ usleep(100 * period_us);
+ check_reports(vaddr, size);
+
+ unmap_oa_buffer(vaddr, size);
+ __perf_close(stream_fd);
+
+ try_invalid_access(vaddr);
+}
+
static unsigned
read_i915_module_ref(void)
{
@@ -5507,6 +5757,32 @@ igt_main
test_triggered_oa_reports(1);
}
+ igt_subtest_group {
+ igt_fixture {
+ igt_require(i915_perf_revision(drm_fd) >= 8);
+ }
+
+ igt_describe("Verify mapping of oa buffer");
+ igt_subtest("map-oa-buffer")
+ test_mapped_oa_buffer(check_reports_from_mapped_buffer);
+
+ igt_describe("Verify invalid mappings of oa buffer");
+ igt_subtest("invalid-map-oa-buffer")
+ test_mapped_oa_buffer(invalid_param_map_oa_buffer);
+
+ igt_describe("Verify if non-privileged user can map oa buffer");
+ igt_subtest("non-privileged-map-oa-buffer")
+ test_mapped_oa_buffer(unprivileged_map_oa_buffer);
+
+ igt_describe("Verify if non-privileged user can map oa buffer");
+ igt_subtest("non-privileged-access-vaddr")
+ test_mapped_oa_buffer(map_oa_buffer_unprivilege_access);
+
+ igt_describe("Unmap buffer, close fd and try to access");
+ igt_subtest("closed-fd-and-unmapped-access")
+ closed_fd_and_unmapped_access();
+ }
+
igt_fixture {
/* leave sysctl options in their default state... */
write_u64_file("/proc/sys/dev/i915/oa_max_sample_rate", 100000);
diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-feedback.testlist
index 262f8d1c..adb8050a 100644
--- a/tests/intel-ci/fast-feedback.testlist
+++ b/tests/intel-ci/fast-feedback.testlist
@@ -4,3 +4,9 @@ igt@perf@oa-regs-whitelisted
igt@perf@oa-regs-not-whitelisted
igt@perf@triggered-oa-reports-paranoid-0
igt@perf@triggered-oa-reports-paranoid-1
+
+igt@perf@map-oa-buffer
+igt@perf@invalid-map-oa-buffer
+igt@perf@non-privileged-map-oa-buffer
+igt@perf@non-privileged-access-vaddr
+igt@perf@closed-fd-and-unmapped-access
--
2.20.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for series starting with [1/2] HAX i915/perf: add tests for triggered OA reports
2020-08-04 18:00 [igt-dev] [PATCH 1/2] HAX i915/perf: add tests for triggered OA reports Umesh Nerlige Ramappa
2020-08-04 18:00 ` [igt-dev] [PATCH 2/2] HAX i915/perf: Add tests for mapped OA buffer Umesh Nerlige Ramappa
@ 2020-08-04 18:27 ` Patchwork
1 sibling, 0 replies; 3+ messages in thread
From: Patchwork @ 2020-08-04 18:27 UTC (permalink / raw)
To: Umesh Nerlige Ramappa; +Cc: igt-dev
[-- Attachment #1.1: Type: text/plain, Size: 4439 bytes --]
== Series Details ==
Series: series starting with [1/2] HAX i915/perf: add tests for triggered OA reports
URL : https://patchwork.freedesktop.org/series/80253/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8841 -> IGTPW_4851
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4851/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_4851:
### IGT changes ###
#### Possible regressions ####
* {igt@perf@closed-fd-and-unmapped-access} (NEW):
- {fi-tgl-dsi}: NOTRUN -> [SKIP][1] +8 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4851/fi-tgl-dsi/igt@perf@closed-fd-and-unmapped-access.html
* {igt@perf@map-oa-buffer} (NEW):
- fi-icl-y: NOTRUN -> [SKIP][2] +8 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4851/fi-icl-y/igt@perf@map-oa-buffer.html
* {igt@perf@non-privileged-access-vaddr} (NEW):
- fi-icl-u2: NOTRUN -> [SKIP][3] +8 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4851/fi-icl-u2/igt@perf@non-privileged-access-vaddr.html
- fi-tgl-y: NOTRUN -> [SKIP][4] +8 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4851/fi-tgl-y/igt@perf@non-privileged-access-vaddr.html
* {igt@perf@non-privileged-map-oa-buffer} (NEW):
- fi-tgl-u2: NOTRUN -> [SKIP][5] +8 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4851/fi-tgl-u2/igt@perf@non-privileged-map-oa-buffer.html
* {igt@perf@oa-regs-not-whitelisted} (NEW):
- fi-cml-s: NOTRUN -> [SKIP][6] +8 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4851/fi-cml-s/igt@perf@oa-regs-not-whitelisted.html
- fi-cml-u2: NOTRUN -> [SKIP][7] +8 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4851/fi-cml-u2/igt@perf@oa-regs-not-whitelisted.html
* {igt@perf@triggered-oa-reports-paranoid-1} (NEW):
- {fi-ehl-1}: NOTRUN -> [SKIP][8] +8 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4851/fi-ehl-1/igt@perf@triggered-oa-reports-paranoid-1.html
New tests
---------
New tests have been introduced between CI_DRM_8841 and IGTPW_4851:
### New IGT tests (9) ###
* igt@perf@closed-fd-and-unmapped-access:
- Statuses : 38 skip(s)
- Exec time: [0.0] s
* igt@perf@invalid-map-oa-buffer:
- Statuses : 38 skip(s)
- Exec time: [0.0] s
* igt@perf@map-oa-buffer:
- Statuses : 38 skip(s)
- Exec time: [0.0] s
* igt@perf@non-privileged-access-vaddr:
- Statuses : 38 skip(s)
- Exec time: [0.0] s
* igt@perf@non-privileged-map-oa-buffer:
- Statuses : 38 skip(s)
- Exec time: [0.0] s
* igt@perf@oa-regs-not-whitelisted:
- Statuses : 38 skip(s)
- Exec time: [0.0] s
* igt@perf@oa-regs-whitelisted:
- Statuses : 38 skip(s)
- Exec time: [0.0] s
* igt@perf@triggered-oa-reports-paranoid-0:
- Statuses : 38 skip(s)
- Exec time: [0.0] s
* igt@perf@triggered-oa-reports-paranoid-1:
- Statuses : 38 skip(s)
- Exec time: [0.0] s
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
Participating hosts (45 -> 38)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5757 -> IGTPW_4851
CI-20190529: 20190529
CI_DRM_8841: 7530f9dbf9161936dd90afe68d6627515347e5b8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_4851: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4851/index.html
IGT_5757: d78c7fd293cb228fe03ccff730202b033e25ff18 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@perf@closed-fd-and-unmapped-access
+igt@perf@invalid-map-oa-buffer
+igt@perf@map-oa-buffer
+igt@perf@non-privileged-access-vaddr
+igt@perf@non-privileged-map-oa-buffer
+igt@perf@oa-regs-not-whitelisted
+igt@perf@oa-regs-whitelisted
+igt@perf@triggered-oa-reports-paranoid-0
+igt@perf@triggered-oa-reports-paranoid-1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4851/index.html
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2020-08-04 18:00 [igt-dev] [PATCH 1/2] HAX i915/perf: add tests for triggered OA reports Umesh Nerlige Ramappa
2020-08-04 18:00 ` [igt-dev] [PATCH 2/2] HAX i915/perf: Add tests for mapped OA buffer Umesh Nerlige Ramappa
2020-08-04 18:27 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [1/2] HAX i915/perf: add tests for triggered OA reports Patchwork
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