[PATCH 1/3] dt-bindings: Bindings for reserved memory for BPMP mail

[PATCH 1/3] dt-bindings: Bindings for reserved memory for BPMP mail

[Peter De Schrijver]

Tegra234 will use DRAM to store the messages exchanged between Linux and
BPMP firmware rather than sysram as used in Tegra186 and Tegra194. The
kernel will be informed about the size and location of the DRAM area to
be used using the DT reserved memory bindings.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
 .../firmware/nvidia,tegra186-bpmp.txt         | 38 ++++++++++++++++++-
 .../reserved-memory/tegra234-bpmp-shmem.txt   | 33 ++++++++++++++++
 2 files changed, 69 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/reserved-memory/tegra234-bpmp-shmem.txt

diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt
index ff380dadb5f9..ff8fc4b6816d 100644
--- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt
+++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt
@@ -13,12 +13,18 @@ Required properties:
     One of:
     - "nvidia,tegra186-bpmp"
 - mboxes : The phandle of mailbox controller and the mailbox specifier.
-- shmem : List of the phandle of the TX and RX shared memory area that
-	  the IPC between CPU and BPMP is based on.
 - #clock-cells : Should be 1.
 - #power-domain-cells : Should be 1.
 - #reset-cells : Should be 1.
 
+Optinal properties:
+- shmem : List of the phandle of the TX and RX shared memory area that
+	  the IPC between CPU and BPMP is based on.
+- memory-region : phandle to reserved memory region used for IPC between
+	  CPU-NS and BPMP.
+One 1 of the above 2 properties must be present. In case both are present
+memory-region will take precedence and shmem will be ignored.
+
 This node is a mailbox consumer. See the following files for details of
 the mailbox subsystem, and the specifiers implemented by the relevant
 provider(s):
@@ -105,3 +111,31 @@ bpmp {
 		...
 	};
 };
+
+memory-region binding for BPMP
+------------------------------
+
+The shared memory area for the IPC TX and RX between CPU-NS and BPMP
+resides in normal SDRAM and is defined using a sub-node of the reserved-memory
+node. See ../reserved-memory/nvidia,tegra234-bpmp-shmem.txt for binding.
+
+Example:
+
+hsp_top: hsp@3c00000 {
+	...
+	#mbox-cells = <2>;
+};
+
+bpmp: bpmp {
+	compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
+	mboxes = <&hsp_top TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>;
+	memory-region = <&dram_cpu_bpmp_mail>;
+	#clock-cells = <1>;
+	#reset-cells = <1>;
+	#power-domain-cells = <1>;
+
+	i2c {
+		compatible = "...";
+		...
+	};
+};
diff --git a/Documentation/devicetree/bindings/reserved-memory/tegra234-bpmp-shmem.txt b/Documentation/devicetree/bindings/reserved-memory/tegra234-bpmp-shmem.txt
new file mode 100644
index 000000000000..44338184d94b
--- /dev/null
+++ b/Documentation/devicetree/bindings/reserved-memory/tegra234-bpmp-shmem.txt
@@ -0,0 +1,33 @@
+* Tegra CPU-NS - BPMP IPC reserved memory binding
+
+Define a memory region used for communication between CPU-NS and BPMP.
+Typically this node is created by the bootloader as the physical address
+has to be known to both CPU-NS and BPMP for correct IPC operation.
+
+The memory region is defined using a child node under /reserved-memory.
+The sub-node is named shmem@<address> and has the following properties:
+
+- compatible:
+	compatible = "nvidia,tegra234-bpmp-shmem";
+
+- reg:
+	The physical address and size of the shared SDRAM region
+
+- no-map:
+	To prevent the OS from creating a virtual mapping for this region.
+	(See reserved-memory.txt for deatils on the no-map property)
+
+Example:
+
+/ {
+	reserved-memory {
+		...
+		dram_cpu_bpmp_mail: shmem@0xf1be0000  {
+			compatible = "nvidia,tegra234-bpmp-shmem";
+			reg = <0x0 0xf1be0000 0x0 0x2000>;
+			no-map;
+		};
+
+		...
+	};
+};
-- 
2.17.1